CN117118443A

CN117118443A - Multichannel signal acquisition circuit

Info

Publication number: CN117118443A
Application number: CN202311024406.9A
Authority: CN
Inventors: 卫梦昭
Original assignee: Hangzhou Shenlian Microelectronics Technology Co ltd
Current assignee: Hangzhou Shenlian Microelectronics Technology Co ltd
Priority date: 2023-08-15
Filing date: 2023-08-15
Publication date: 2023-11-24

Abstract

Embodiments of the present disclosure provide a multi-channel signal acquisition circuit, comprising: the circuit comprises a first input circuit, a second input circuit, a first amplifying circuit, a second amplifying circuit, a selecting circuit, a first sampling circuit, a second sampling circuit and a storage circuit. During a first sampling period, the acquisition circuit samples a first voltage difference between two voltage terminals coupled to the first input circuit. The first sampling circuit samples the second amplified signal to generate a second digital signal. During a second sampling period, the acquisition circuit samples a second voltage difference between two voltage terminals coupled to the second input circuit. The first sampling circuit samples the third amplified signal to generate a first digital signal. The second sampling circuit samples the first amplified signal during a first sampling period to generate a first codeword and a target codeword from the first codeword and the first digital signal, and samples the fourth amplified signal during a second sampling period to generate a second codeword and a target codeword from the second codeword and the second digital signal.

Description

Multichannel signal acquisition circuit

Technical Field

Embodiments of the present disclosure relate to the field of circuit technology, and in particular, to a multichannel signal acquisition circuit.

Background

The multichannel signal acquisition circuit typically includes one or more analog-to-digital converters (ADCs) and a multiplexer. The ADC converts the input analog signal into a digital signal for subsequent processing. The multiplexer is used for selecting the sampled and converted channels. Depending on the strength of the input signal, the amplifier may also be a necessary component in the multi-channel signal acquisition circuit to pre-process the signal before it enters the ADC. The amplifier in the multi-channel signal acquisition circuit needs to have a low input offset voltage (input offset voltage) and sufficient output capability to drive the ADC. To ensure that the ADC has good noise performance and is not affected by signal Aliasing (Aliasing), the input signal typically requires a filter before entering the ADC. In some applications, such as Battery Management Systems (BMS) and industrial grade measurement systems, where the observed signal is at a direct current or very low frequency, the filter must use resistors and capacitors of large value. Due to the high cost of integrating large resistors and large capacitors on a single chip, these passive components are typically arranged outside the chip. Because these off-chip large resistors are between the input signal and the ADC, this type of multi-channel signal acquisition circuit needs to have very low input current to ensure that the overall sampling accuracy does not cause additional voltage drops due to the input current flowing through the filter resistor.

Disclosure of Invention

Embodiments described herein provide a multi-channel signal acquisition circuit.

According to a first aspect of the present disclosure, a multi-channel signal acquisition circuit is provided. The multichannel signal acquisition circuit includes: the first input circuit, the second input circuit, the first amplifying circuit, the second amplifying circuit, the selecting circuit, the first sampling circuit, the second sampling circuit, and the storage circuit. The first input circuit is coupled to the initial voltage terminal and the first to nth voltage terminals. The second input circuit is coupled to the n-th voltage terminal to the 2 n-th voltage terminal. During a first sampling period, the multi-channel signal acquisition circuit samples a first voltage difference between two of the voltage terminals coupled to a first input circuit, the first input circuit configured to provide the first voltage difference to a first amplification circuit, the second input circuit configured to provide a reference voltage difference to a second amplification circuit, the first amplification circuit configured to amplify the first voltage difference, the second amplification circuit configured to amplify the reference voltage difference, the selection circuit configured to provide a first amplified signal to the second sampling circuit and a second amplified signal to the first sampling circuit, the first amplified signal being equal to a sum of the amplified first voltage difference and a offset voltage of the first amplification circuit, the second amplified signal being equal to a sum of the amplified reference voltage difference and an offset voltage of the second amplification circuit, the first sampling circuit configured to sample the second amplified signal to generate a second digital signal. During a second sampling period, the multi-channel signal acquisition circuit samples a second voltage difference between two of the voltage terminals coupled to the second input circuit, the first input circuit configured to provide a reference voltage difference to the first amplification circuit, the second input circuit configured to provide the second voltage difference to the second amplification circuit, the first amplification circuit configured to amplify the reference voltage difference, the second amplification circuit configured to amplify the second voltage difference, the selection circuit configured to provide a third amplified signal to the first sampling circuit and a fourth amplified signal to the second sampling circuit, the third amplified signal being equal to a sum of the amplified reference voltage difference and a offset voltage of the first amplification circuit, the fourth amplified signal being equal to a sum of the amplified second voltage difference and an offset voltage of the second amplification circuit, the first sampling circuit configured to sample the third amplified signal to generate the first digital signal. The memory circuit is configured to: the first digital signal and the second digital signal are stored. The second sampling circuit is configured to: during a first sampling period, sampling the first amplified signal to generate a first codeword, and generating a target codeword from the first codeword and the first digital signal; during the second sampling period, the fourth amplified signal is sampled to generate a second codeword, and a target codeword is generated from the second codeword and the second digital signal.

In some embodiments of the present disclosure, during the first sampling, the second amplifying circuit is further configured to: a negative reference voltage difference is generated and amplified. The selection circuit is further configured to provide a negative second amplified signal to the first sampling circuit. The negative second amplified signal is equal to the sum of the amplified negative reference voltage difference and the negative offset voltage of the second amplifying circuit. The first sampling circuit is configured to: half of the difference between the negative second amplified signal and the second amplified signal is sampled to generate a second digital signal. During the second sampling, the first amplification circuit is further configured to: a negative reference voltage difference is generated and amplified. The selection circuit is further configured to provide a negative third amplified signal to the first sampling circuit. The negative third amplified signal is equal to the sum of the amplified negative reference voltage difference and the negative offset voltage of the first amplifying circuit. The first sampling circuit is configured to: half of the difference between the negative third amplified signal and the third amplified signal is sampled to generate a first digital signal.

In some embodiments of the present disclosure, the reference voltage difference is zero.

In some embodiments of the present disclosure, the first input circuit includes: a first multiplexer, a second multiplexer, a plurality of filter resistors and a plurality of filter capacitors. The first multiplexer is coupled to even voltage terminals, a start voltage terminal and a reference voltage terminal among the first voltage terminal to the n-th voltage terminal. The second multiplexer is coupled to the odd voltage terminal and the reference voltage terminal among the first voltage terminal to the n voltage terminal. A filter resistor is coupled between each of the even voltage terminals and the start voltage terminal and the first multiplexer. A filter resistor is coupled between each odd voltage terminal and the second multiplexer. A filter capacitor is coupled between any adjacent two of the start voltage terminal and the even voltage terminal. A filter capacitor is coupled between any two adjacent odd voltage terminals. The first multiplexer is configured to: sequentially outputting voltages from one of the start voltage terminal and the even voltage terminal during the first sampling period; during the second sampling period, a reference voltage from the reference voltage terminal is output. The second multiplexer is configured to: sequentially outputting voltages from one of the odd voltage terminals during the first sampling period; during the second sampling period, a reference voltage from the reference voltage terminal is output. The voltage difference between the output end of the first multiplexer and the output end of the second multiplexer is a first voltage difference. The voltages from the start voltage terminal and the n-th voltage terminal are outputted for one clock period. The voltage from the other voltage terminal is output for two clock cycles. The other voltage terminals are voltage terminals other than the start voltage terminal and the nth voltage terminal.

In some embodiments of the present disclosure, the second input circuit includes: a third multiplexer, a fourth multiplexer, a plurality of filter resistors and a plurality of filter capacitors. The third multiplexer is coupled to the even voltage terminal and the reference voltage terminal among the n-th voltage terminal to the 2 n-th voltage terminal. The fourth multiplexer is coupled to the odd voltage terminal and the reference voltage terminal among the n voltage terminals 2. A filter resistor is coupled between each even voltage terminal and the third multiplexer. A filter resistor is coupled between each odd voltage terminal and the fourth multiplexer. A filter capacitor is coupled between any two adjacent voltage terminals of the even number of voltage terminals. A filter capacitor is coupled between any two adjacent odd voltage terminals. The third multiplexer is configured to: outputting a reference voltage from a reference voltage terminal during a first sampling period; during the second sampling period, voltages from one of the even-numbered voltage terminals are sequentially output. The fourth multiplexer is configured to: outputting a reference voltage from a reference voltage terminal during a first sampling period; during the second sampling period, voltages from one of the odd voltage terminals are sequentially output. The voltage difference between the output end of the third multiplexer and the output end of the fourth multiplexer is the second voltage difference. The voltages from the n-th voltage terminal and the 2 n-th voltage terminal are output for one clock cycle. The voltage from the other voltage terminal is output for two clock cycles. The other voltage terminals are voltage terminals other than the nth voltage terminal and the 2 nd voltage terminal.

In some embodiments of the present disclosure, the first amplifying circuit includes: the first switching circuit to the fourth switching circuit, the first transconductance unit, the first fully differential amplifier, the first resistor, and the second resistor. The first input end of the first switching circuit is coupled with the first output end of the first input circuit. The second input end of the first switching circuit is coupled with the second output end of the first input circuit. The first output end of the first switching circuit is coupled to the first input end of the first transconductance unit. The second output end of the first switching circuit is coupled to the second input end of the first transconductance unit. The first switching circuit is configured to: the first input end and the second input end of the first switching circuit are respectively coupled with the second output end and the first output end of the first switching circuit when the first switching indication signal is at a first level, and the first input end and the second input end of the first switching circuit are respectively coupled with the first output end and the second output end of the first switching circuit when the first switching indication signal is at a second level. The first transconductance unit is configured to: a first differential voltage between a first output terminal and a second output terminal of the first switching circuit is converted into a first differential current. The first input end of the second switching circuit is coupled to the first output end of the first transconductance unit. The second input end of the second switching circuit is coupled to the second output end of the first transconductance unit. The first output end of the second switching circuit is coupled with the first input end of the third switching circuit and the first end of the first resistor. The second output end of the second switching circuit is coupled with the second input end of the third switching circuit and the first end of the second resistor. The second switching circuit is configured to: the first input end and the second input end of the second switching circuit are respectively coupled with the second output end and the first output end of the second switching circuit when the first switching indication signal is at the first level, and the first input end and the second input end of the second switching circuit are respectively coupled with the first output end and the second output end of the second switching circuit when the first switching indication signal is at the second level. The first output end of the third switching circuit is coupled with the first input end of the first fully-differential amplifier. The second output end of the third switching circuit is coupled with the second input end of the first fully-differential amplifier. The third switching circuit is configured to: the first input end and the second input end of the third switching circuit are respectively coupled with the second output end and the first output end of the third switching circuit when the first switching indication signal is at the first level, and the first input end and the second input end of the third switching circuit are respectively coupled with the first output end and the second output end of the third switching circuit when the first switching indication signal is at the second level. The first output end of the first fully differential amplifier is coupled with the first input end of the fourth switching circuit. The second output end of the first fully differential amplifier is coupled with the second input end of the fourth switching circuit. The first output end of the fourth switching circuit is coupled to the second end of the first resistor and the first input end of the selection circuit. The second output end of the fourth switching circuit is coupled with the second end of the second resistor and the second input end of the selection circuit. The fourth switching circuit is configured to: the first input end and the second input end of the fourth switching circuit are respectively coupled with the second output end and the first output end of the fourth switching circuit when the first switching indication signal is at the first level, and the first input end and the second input end of the fourth switching circuit are respectively coupled with the first output end and the second output end of the fourth switching circuit when the first switching indication signal is at the second level. Wherein, during the first sampling period, the voltage difference between the first output end and the second output end of the fourth switching circuit is equal to the first amplified signal, and during the second sampling period, the voltage difference between the first output end and the second output end of the fourth switching circuit is equal to the third amplified signal. A first offset voltage exists between the first input end and the second input end of the first transconductance unit. A second offset voltage exists between the first input terminal and the second input terminal of the first fully differential amplifier. The offset voltage of the first amplifying circuit is the difference between the first offset voltage and the second offset voltage.

In some embodiments of the present disclosure, the second amplifying circuit includes: the fifth to eighth switching circuits, the second transconductance cell, the second fully differential amplifier, the third resistor, and the fourth resistor. The first input end of the fifth switching circuit is coupled to the first output end of the second input circuit. The second input end of the fifth switching circuit is coupled to the second output end of the second input circuit. The first output end of the fifth switching circuit is coupled to the first input end of the second transconductance unit. The second output end of the fifth switching circuit is coupled to the second input end of the second transconductance unit. The fifth switching circuit is configured to: the first input end and the second input end of the fifth switching circuit are respectively coupled with the second output end and the first output end of the fifth switching circuit when the second switching indication signal is at the first level, and the first input end and the second input end of the fifth switching circuit are respectively coupled with the first output end and the second output end of the fifth switching circuit when the second switching indication signal is at the second level. The second transconductance cell is configured to: the second differential voltage between the first output terminal and the second output terminal of the fifth switching circuit is converted into a second differential current. The first input end of the sixth switching circuit is coupled to the first output end of the second transconductance unit. The second input end of the sixth switching circuit is coupled to the second output end of the second transconductance unit. The first output terminal of the sixth switching circuit is coupled to the first input terminal of the seventh switching circuit and the first terminal of the third resistor. The second output terminal of the sixth switching circuit is coupled to the second input terminal of the seventh switching circuit and the first terminal of the fourth resistor. The sixth switching circuit is configured to: the first input end and the second input end of the sixth switching circuit are respectively coupled with the second output end and the first output end of the sixth switching circuit when the second switching indication signal is at the first level, and the first input end and the second input end of the sixth switching circuit are respectively coupled with the first output end and the second output end of the sixth switching circuit when the second switching indication signal is at the second level. The first output end of the seventh switching circuit is coupled to the first input end of the second fully differential amplifier. The second output end of the seventh switching circuit is coupled to the second input end of the second fully differential amplifier. The seventh switching circuit is configured to: the first input end and the second input end of the seventh switching circuit are respectively coupled with the second output end and the first output end of the seventh switching circuit when the second switching indication signal is at the first level, and the first input end and the second input end of the seventh switching circuit are respectively coupled with the first output end and the second output end of the seventh switching circuit when the second switching indication signal is at the second level. The first output end of the second full differential amplifier is coupled to the first input end of the eighth switching circuit. The second output end of the second full differential amplifier is coupled to the second input end of the eighth switching circuit. The first output terminal of the eighth switching circuit is coupled to the second terminal of the third resistor and the third input terminal of the selection circuit. The second output terminal of the eighth switching circuit is coupled to the second terminal of the fourth resistor and the fourth input terminal of the selection circuit. The eighth switching circuit is configured to: the first input end and the second input end of the eighth switching circuit are respectively coupled with the second output end and the first output end of the eighth switching circuit when the second switching indication signal is at the first level, and the first input end and the second input end of the eighth switching circuit are respectively coupled with the first output end and the second output end of the eighth switching circuit when the second switching indication signal is at the second level. Wherein, during the first sampling period, a voltage difference between the first output terminal and the second output terminal of the eighth switching circuit is equal to the second amplified signal. During the second sampling period, a voltage difference between the first output terminal and the second output terminal of the eighth switching circuit is equal to the fourth amplified signal. A third offset voltage exists between the first input terminal and the second input terminal of the second transconductance unit. A fourth offset voltage is present between the first input and the second input of the second fully differential amplifier. The offset voltage of the second amplifying circuit is the difference between the third offset voltage and the fourth offset voltage.

In some embodiments of the present disclosure, the selection circuit includes: the first voltage-controlled switch to the eighth voltage-controlled switch. The first end of the first voltage-controlled switch is coupled to the first input end of the selection circuit. The second end of the first voltage-controlled switch is coupled to the first input end of the second sampling circuit. The controlled terminal of the first voltage-controlled switch is coupled to the first selection signal terminal. The first end of the second voltage-controlled switch is coupled to the second input end of the selection circuit. The second end of the second voltage-controlled switch is coupled to the second input end of the second sampling circuit. The controlled end of the second voltage-controlled switch is coupled to the first selection signal end. The first end of the third voltage-controlled switch is coupled to the first input end of the selection circuit. The second end of the third voltage-controlled switch is coupled to the first input end of the first sampling circuit. The controlled end of the third voltage-controlled switch is coupled to the second selection signal end. The first end of the fourth voltage-controlled switch is coupled to the second input end of the selection circuit. The second end of the fourth voltage-controlled switch is coupled to the second input end of the first sampling circuit. The controlled terminal of the fourth voltage-controlled switch is coupled to the second selection signal terminal. The first end of the fifth voltage-controlled switch is coupled to the third input end of the selection circuit. The second end of the fifth voltage-controlled switch is coupled to the first input end of the second sampling circuit. The controlled terminal of the fifth voltage-controlled switch is coupled to the second selection signal terminal. The first end of the sixth voltage-controlled switch is coupled to the fourth input end of the selection circuit. The second end of the sixth voltage-controlled switch is coupled to the second input end of the second sampling circuit. The controlled terminal of the sixth voltage-controlled switch is coupled to the second selection signal terminal. The first end of the seventh voltage-controlled switch is coupled to the third input end of the selection circuit. The second end of the seventh voltage-controlled switch is coupled to the first input end of the first sampling circuit. The controlled terminal of the seventh voltage-controlled switch is coupled to the first selection signal terminal. The first end of the eighth voltage-controlled switch is coupled to the fourth input end of the selection circuit. The second end of the eighth voltage-controlled switch is coupled to the second input end of the first sampling circuit. The controlled terminal of the eighth voltage-controlled switch is coupled to the first selection signal terminal. During the first sampling period, the first selection signal from the first selection signal terminal is at an active level, and the second selection signal from the second selection signal terminal is at an inactive level. During the second sampling period, the first selection signal is at an inactive level and the second selection signal is at an active level.

In some embodiments of the present disclosure, the memory circuit is further configured to: the first gain error of the first amplifying circuit, the second gain error of the second amplifying circuit and the offset voltage value of the second sampling circuit are stored.

In some embodiments of the present disclosure, during the first sample, the target codeword is calculated as:

Dout＝(Dcode1+DVos1)×(1+GE1)+DVos6，

during the second sample, the target codeword is calculated as:

Dout＝(Dcode2+DVos2)×(1+GE2)+DVos6，

wherein Dout denotes a target codeword, dcode1 denotes a first codeword, DVos1 denotes a first digital signal, GE1 denotes a first gain error of the first amplifying circuit, dcode2 denotes a second codeword, DVos2 denotes a second digital signal, GE2 denotes a second gain error of the second amplifying circuit, DVos6 denotes an offset voltage value of the second sampling circuit, odd denotes sampling of a voltage difference between an Odd voltage terminal and an even voltage terminal or a start voltage terminal when Odd is 1, and Odd denotes sampling of a voltage difference between an even voltage terminal and an Odd voltage terminal when Odd is 0.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

FIG. 1 is an exemplary circuit diagram of a multi-channel signal acquisition circuit;

FIG. 2 is an exemplary circuit diagram of another multi-channel signal acquisition circuit;

FIG. 3 is a schematic block diagram of a multi-channel signal acquisition circuit according to an embodiment of the present disclosure;

FIG. 4 is an exemplary circuit diagram of a multi-channel signal acquisition circuit according to an embodiment of the present disclosure;

fig. 5 is a timing diagram of some of the signals used in the multi-channel signal acquisition circuit shown in fig. 4.

In the drawings, the last two digits are identical to the elements. It is noted that the elements in the drawings are schematic and are not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

Fig. 1 shows an exemplary circuit diagram of a multi-channel signal acquisition circuit 100. The multi-channel signal acquisition circuit 100 can sample all channels simultaneously, but can only output one channel of data from the multiplexer MUX as the target codeword Dout at any one time. The number of analog-to-digital converters (ADCs) required by the multi-channel signal acquisition circuit 100 is equal to the number of channels. As shown in fig. 1, in the first channel, a voltage difference between the voltage terminals V1 and V0 is input to the first analog-to-digital converter ADC1. In the second channel, the voltage difference between the voltage terminals V2 and V1 is input to the second analog-to-digital converter ADC2. In the third channel, the voltage difference between the voltage terminals V3 and V2 is input to the third analog-to-digital converter ADC3. With this, the voltage difference between the voltage terminals V (n) and V (n-1) is inputted to the n-th analog-to-digital converter ADCn in the n-th channel. A filter resistor Rf is coupled between each voltage terminal and the input terminal of the ADC. A filter capacitor Cf is coupled between two adjacent voltage terminals. Since each ADC requires separate calibration, the chip area of the multichannel signal acquisition circuit 100 is greatly increased and the time required for calibration is also increased, resulting in increased costs. Since these ADCs have no pre-amplification circuit, the resolution required by the ADC is determined by the input signal amplitude. If the input signal is weaker, the resolution required by the ADCs is higher, and the design difficulty of the ADCs is increased. Also, since a non-zero current is required to drive the ADC, the multi-channel signal acquisition circuit 100 may cause additional errors due to the input current of the ADC flowing through the filter resistor Rf.

Fig. 2 shows an exemplary circuit diagram of another multi-channel signal acquisition circuit 200. The multi-channel signal acquisition circuit 200 employs a pair of multiplexers MUX1 and MUX2 to select the acquisition signals and a fully differential amplifier A1 to drive the analog-to-digital converter ADC. A filter resistor Rf is coupled between each of the voltage terminals V0, V1, V2, V3, V4, V5, … … V (2 n-1) and V (2 n) and the input of the multiplexer. The gain of the fully differential amplifier A1 is- (r1+r2)/(r3+r4). Where R1 represents the resistance value of the resistor R1, R2 represents the resistance value of the resistor R2, R3 represents the resistance value of the resistor R3, and R4 represents the resistance value of the resistor R4. The multi-channel signal acquisition circuit 200 requires only one ADC, reducing cost. With the help of choppers Ch1 and Ch2, the fully differential amplifier A1 uses chopping technology (chopping) to reduce its offset voltage so that it does not affect the overall accuracy. The control signal Chop is used to control the operation of the choppers Ch1 and Ch 2. The control signal Odd of the chopper Ch3 varies with switching of the sampling channel, and thus the chopper Ch3 operates as a selector or a switching circuit. The control signal Odd of the chopper Ch3 determines the output polarity of the fully differential amplifier A1. In one example, when the control signal Odd is at a low level, the ADC samples an even channel (e.g., V (2 n) -V (2 n-1), V4-V3, V2-V1). When the control signal Odd is at a high level, the ADC samples Odd channels (e.g., V5-V4, V3-V2, V1-V0). By changing the output polarity of the fully differential amplifier A1 by the chopper Ch3, each of the multiplexers MUX1 and MUX2 does not need to be coupled to all of the voltage terminals, and the number of input terminals required for each of the multiplexers MUX1 and MUX2 can be reduced by 50%, contributing to a reduction in the area occupied by the multiplexers MUX1 and MUX 2. However, due to the resistive feedback network employed by the fully differential amplifier A1, the input impedance of the multi-channel signal acquisition circuit 200 is limited, and still causes an additional voltage drop for the input current Iin to flow through the filter resistor Rf. And since the input current Iin varies with the input common mode voltage, the multi-channel signal acquisition circuit 200 cannot compensate for this additional error with a single calibration.

The embodiment of the disclosure provides a multichannel signal acquisition circuit capable of simultaneously ensuring low input offset voltage, low input current and low drift. Fig. 3 shows a schematic block diagram of a multi-channel signal acquisition circuit 300 according to an embodiment of the present disclosure. The multi-channel signal acquisition circuit 300 includes: the first input circuit 310, the second input circuit 320, the first amplifying circuit 330, the second amplifying circuit 340, the selecting circuit 350, the first sampling circuit ADC1, the second sampling circuit ADC2, and the storage circuit 360.

The first input circuit 310 includes a plurality of input terminals respectively coupled to the start voltage terminal V0 and one of the first to nth voltage terminals V1 to Vn. One input of the first input circuit 310 may also be coupled to a reference voltage terminal Vref. The reference voltage terminal Vref can provide a reference voltage Vref. A first output of the first input circuit 310 is coupled to a first input of the first amplifying circuit 330. A second output terminal of the first input circuit 310 is coupled to a second input terminal of the first amplifying circuit 330. The voltage at the first output of the first input circuit 310 is equal to Va. The voltage at the second output of the first input circuit 310 is equal to Vb. The first output terminal of the first amplifying circuit 330 is coupled to the first input terminal InP1 of the selecting circuit 350. The second output terminal of the first amplifying circuit 330 is coupled to the second input terminal InP2 of the selecting circuit 350.

The second input circuit 320 includes a plurality of input terminals respectively coupled to one of the n-th voltage terminal Vn to the 2 n-th voltage terminal V2 n. One input of the second input circuit 330 may also be coupled to a reference voltage terminal Vref. The first output terminal of the second input circuit 320 is coupled to the first input terminal of the second amplifying circuit 340. A second output of the second input circuit 320 is coupled to a second input of the second amplifying circuit 340. The voltage at the first output of the second input circuit 320 is equal to Vc. The voltage at the second output of the second input circuit 320 is equal to Vd. The first output terminal of the second amplifying circuit 340 is coupled to the third input terminal InP3 of the selecting circuit 350. The second output terminal of the second amplifying circuit 340 is coupled to the fourth input terminal InP4 of the selecting circuit 350.

The first output terminal OtP1 of the selection circuit 350 is coupled to the first input terminal of the first sampling circuit ADC 1. The second output terminal OtP2 of the selection circuit 350 is coupled to the second input terminal of the first sampling circuit ADC 1. The third output terminal OtP3 of the selection circuit 350 is coupled to the first input terminal of the second sampling circuit ADC2. The fourth output terminal OtP4 of the selection circuit 350 is coupled to the second input terminal of the second sampling circuit ADC2. The output terminal of the first sampling circuit ADC1 is coupled to the memory circuit 360. The storage circuit 360 is coupled to the second sampling circuit ADC2. The output terminal of the second sampling circuit ADC2 is coupled to the output terminal of the multi-channel signal acquisition circuit 300.

During a first sampling period, the multichannel signal acquisition circuit 300 samples a first voltage difference between two of the voltage terminals coupled to the first input circuit 310. The first input circuit 310 is configured to provide a first voltage difference to the first amplifying circuit 330. The second input circuit 320 is configured to provide a reference voltage difference to the second amplifying circuit 340. In the example of FIG. 3, during the first sample, the first voltage difference is equal to Va-Vb. The reference voltage difference is equal to Vc-Vd. The first amplifying circuit 330 is configured to amplify the first voltage difference. The second amplifying circuit 340 is configured to amplify the reference voltage difference. The selection circuit 350 is configured to supply the first amplified signal to the second sampling circuit ADC2 and to supply the second amplified signal to the first sampling circuit ADC 1. The first amplified signal is equal to the sum of the amplified first voltage difference and the offset voltage of the first amplifying circuit 330. The second amplified signal is equal to the sum of the amplified reference voltage difference and the offset voltage of the second amplifying circuit 340. In the example of fig. 3, during the first sample, the first amplified signal is equal to Vout1. The second amplified signal is equal to Vout2. The first sampling circuit ADC1 is configured to sample the second amplified signal to generate a second digital signal.

During a second sampling period, the multi-channel signal acquisition circuit 300 samples a second voltage difference between two of the voltage terminals coupled to the second input circuit 320. The first input circuit 310 is configured to provide a reference voltage difference to the first amplifying circuit 330. The second input circuit 320 is configured to provide a second voltage difference to the second amplifying circuit 340. In the example of FIG. 3, during the second sample, the reference voltage difference is equal to Va-Vb. The second voltage difference is equal to Vc-Vd. The first amplifying circuit 330 is configured to amplify the reference voltage difference. The second amplifying circuit 340 is configured to amplify the second voltage difference. The selection circuit 350 is configured to supply the third amplified signal to the first sampling circuit ADC1 and the fourth amplified signal to the second sampling circuit ADC 2. The third amplified signal is equal to the sum of the amplified reference voltage difference and the offset voltage of the first amplifying circuit 330. The fourth amplified signal is equal to the sum of the amplified second voltage difference and the offset voltage of the second amplifying circuit 340. In the example of fig. 3, during the second sampling, the third amplified signal is equal to Vout1. The fourth amplified signal is equal to Vout2. The first sampling circuit ADC1 is configured to sample the third amplified signal to generate a first digital signal.

The memory circuit 360 is configured to: the first digital signal and the second digital signal are stored.

The second sampling circuit ADC2 is configured to: during a first sampling period, sampling the first amplified signal to generate a first codeword, and generating a target codeword Dout according to the first codeword and the first digital signal; during the second sampling period, the fourth amplified signal is sampled to generate a second codeword, and a target codeword Dout is generated from the second codeword and the second digital signal.

In some embodiments of the present disclosure, the reference voltage difference is set to zero, which facilitates subsequent calculations. The reference voltage difference is, for example, a voltage difference between two reference voltages Vref, so that the reference voltage difference is set to zero. Since the first digital signal includes the information of the offset voltage of the first amplifying circuit 330, the influence of the offset voltage of the first amplifying circuit 330 can be removed from the first codeword by the first digital signal when the first amplifying signal is sampled, so that the generated target codeword Dout is more accurate. Also, since the second digital signal includes information of the offset voltage of the second amplifying circuit 340, the influence of the offset voltage of the second amplifying circuit 340 can be removed from the second codeword by the second digital signal when the second amplifying signal is sampled, so that the generated target codeword Dout is more accurate.

Embodiments of the present disclosure further contemplate offset voltages in the first sampling circuit ADC 1. The influence of the offset voltage in the first sampling circuit ADC1 on the second digital signal can be removed by acquiring the second amplified signal twice during the first sampling and subtracting the results of the two acquisitions. Similarly, the influence of the offset voltage in the first sampling circuit ADC1 on the first digital signal can be removed by acquiring the third amplified signal twice during the second sampling and subtracting the results of the two acquisitions.

In the above embodiment, during the first sampling, the second amplifying circuit 340 is further configured to: a negative reference voltage difference is generated and amplified. The selection circuit 350 is further configured to provide a negative second amplified signal to the first sampling circuit ADC 1. The negative second amplified signal is equal to the sum of the amplified negative reference voltage difference and the negative offset voltage of the second amplifying circuit 340. The negative second amplified signal is equal in absolute value but opposite in sign to the second amplified signal. The first sampling circuit ADC1 is configured to: half of the difference between the negative second amplified signal and the second amplified signal is sampled to generate a second digital signal. During the second sampling, the first amplification circuit 330 is further configured to: a negative reference voltage difference is generated and amplified. The selection circuit 350 is further configured to provide a negative third amplified signal to the first sampling circuit ADC 1. The negative third amplified signal is equal to the sum of the amplified negative reference voltage difference and the negative offset voltage of the first amplifying circuit 330. The negative third amplified signal is equal in absolute value but opposite in sign to the third amplified signal. The first sampling circuit ADC1 is configured to: half of the difference between the negative third amplified signal and the third amplified signal is sampled to generate a first digital signal.

Fig. 4 shows an exemplary circuit diagram of a multi-channel signal acquisition circuit 400 according to an embodiment of the present disclosure. The first input circuit 410 includes: a first multiplexer MUX1, a second multiplexer MUX2, a plurality of filter resistors Rf and a plurality of filter capacitors Cf. The first multiplexer MUX1 is coupled to even voltage terminals V2, … …, vn, the start voltage terminal V0 and the reference voltage terminal Vref among the first voltage terminal V1 to the n-th voltage terminal Vn. The second multiplexer MUX2 is coupled to the odd voltage terminal V1, V3, … … V (n-1) among the first through nth voltage terminals V1 through Vn and the reference voltage terminal Vref. A filter resistor Rf is coupled between each of the even voltage terminal and the start voltage terminal V0 and the first multiplexer MUX 1. A filter resistor Rf is coupled between each odd voltage terminal and the second multiplexer MUX 2. A filter capacitor Cf is coupled between any two adjacent voltage terminals of the start voltage terminal V0 and the even voltage terminal. A filter capacitor Cf is coupled between any adjacent two of the odd voltage terminals. Herein, "even voltage terminals" refers to voltage terminals numbered even, and "odd voltage terminals" refers to voltage terminals numbered odd,

The first multiplexer MUX1 is configured to: sequentially outputting voltages from one of the start voltage terminal V0 and the even voltage terminal during the first sampling period; during the second sampling period, the reference voltage from the reference voltage terminal Vref is output. The second multiplexer MUX2 is configured to: sequentially outputting voltages from one of the odd voltage terminals during the first sampling period; during the second sampling period, the reference voltage from the reference voltage terminal Vref is output.

Wherein the voltage difference between the output terminal of the first multiplexer MUX1 and the output terminal of the second multiplexer MUX2 is the first voltage difference (equal to Va-Vb). The voltages from the start voltage terminal V0 and the n-th voltage terminal Vn are outputted for one clock period. The voltage from the other voltage terminal is output for two clock cycles. The other voltage terminals are voltage terminals other than the start voltage terminal V0 and the nth voltage terminal Vn.

The second input circuit 420 includes: a third multiplexer MUX3, a fourth multiplexer MUX4, a plurality of filter resistors Rf and a plurality of filter capacitors Cf. The third multiplexer MUX3 is coupled to the even voltage terminal and the reference voltage terminal Vref among the n-th voltage terminals Vn to 2 n-th voltage terminal V2 n. The fourth multiplexer MUX4 is coupled to the odd voltage terminal and the reference voltage terminal Vref among the n-th voltage terminal Vn to the 2 n-th voltage terminal V2 n. A filter resistor Rf is coupled between each even voltage terminal and the third multiplexer MUX 3. A filter resistor Rf is coupled between each odd voltage terminal and the fourth multiplexer MUX 4. A filter capacitor Cf is coupled between any two adjacent ones of the even voltage terminals. A filter capacitor Cf is coupled between any adjacent two of the odd voltage terminals.

The third multiplexer MUX3 is configured to: during a first sampling period, outputting a reference voltage Vref from a reference voltage terminal Vref; during the second sampling period, voltages from one of the even-numbered voltage terminals are sequentially output. The fourth multiplexer MUX4 is configured to: during a first sampling period, outputting a reference voltage Vref from a reference voltage terminal Vref; during the second sampling period, voltages from one of the odd voltage terminals are sequentially output. Wherein the voltage difference between the output terminal of the third multiplexer MUX3 and the output terminal of the fourth multiplexer MUX4 is the second voltage difference. The voltages from the n-th voltage terminal Vn and the 2 n-th voltage terminal V2n are output for one clock period. The voltage from the other voltage terminal is output for two clock cycles. The other voltage terminals are voltage terminals other than the nth voltage terminal Vn and the 2 nd voltage terminal V2 n.

The first amplification circuit 430 includes: the first to fourth switching circuits CH1 to CH4, the first transconductance cell Gm1, the first fully differential amplifier A1, the first resistor R1, and the second resistor R2. The first input terminal of the first switching circuit CH1 is coupled to the first output terminal of the first input circuit 410. The second input terminal of the first switching circuit CH1 is coupled to the second output terminal of the first input circuit 410. The first output terminal of the first switching circuit CH1 is coupled to the first input terminal of the first transconductance unit Gm 1. The second output terminal of the first switching circuit CH1 is coupled to the second input terminal of the first transconductance unit Gm 1. The first switching circuit CH1 is configured to: the first input terminal and the second input terminal of the first switching circuit CH1 are respectively coupled to the second output terminal and the first output terminal of the first switching circuit CH1 when the first switching indication signal Odd1 is at a first level (e.g., a high level), and the first input terminal and the second input terminal of the first switching circuit CH1 are respectively coupled to the first output terminal and the second output terminal of the first switching circuit CH1 when the first switching indication signal Odd1 is at a second level (e.g., a low level). The first transconductance unit Gm1 is configured to: the first differential voltage between the first output terminal and the second output terminal of the first switching circuit CH1 is converted into a first differential current. The first input terminal of the second switching circuit CH2 is coupled to the first output terminal of the first transconductance unit Gm 1. The second input terminal of the second switching circuit CH2 is coupled to the second output terminal of the first transconductance unit Gm 1. The first output terminal of the second switching circuit CH2 is coupled to the first input terminal of the third switching circuit CH3 and the first terminal of the first resistor R1. The second output terminal of the second switching circuit CH2 is coupled to the second input terminal of the third switching circuit CH3 and the first terminal of the second resistor R2. The second switching circuit CH2 is configured to: the first input terminal and the second input terminal of the second switching circuit CH2 are respectively coupled to the second output terminal and the first output terminal of the second switching circuit CH2 when the first switching indication signal Odd1 is at a first level (e.g., a high level), and the first input terminal and the second input terminal of the second switching circuit CH2 are respectively coupled to the first output terminal and the second output terminal of the second switching circuit CH2 when the first switching indication signal Odd1 is at a second level (e.g., a low level). The first output terminal of the third switching circuit CH3 is coupled to the first input terminal of the first fully differential amplifier A1. The second output terminal of the third switching circuit CH3 is coupled to the second input terminal of the first fully differential amplifier A1. The third switching circuit CH3 is configured to: the first input terminal and the second input terminal of the third switching circuit CH3 are respectively coupled to the second output terminal and the first output terminal of the third switching circuit CH3 when the first switching indication signal Odd1 is at a first level (e.g., a high level), and the first input terminal and the second input terminal of the third switching circuit CH3 are respectively coupled to the first output terminal and the second output terminal of the third switching circuit CH3 when the first switching indication signal Odd1 is at a second level (e.g., a low level). The first output terminal of the first fully differential amplifier A1 is coupled to the first input terminal of the fourth switching circuit CH 4. The second output terminal of the first fully differential amplifier A1 is coupled to the second input terminal of the fourth switching circuit CH 4. The first output terminal of the fourth switching circuit CH4 is coupled to the second terminal of the first resistor R1 and the first input terminal InP1 of the selection circuit 450. The second output terminal of the fourth switching circuit CH4 is coupled to the second terminal of the second resistor R2 and the second input terminal InP2 of the selection circuit 450. The fourth switching circuit CH4 is configured to: the first input terminal and the second input terminal of the fourth switching circuit CH4 are respectively coupled to the second output terminal and the first output terminal of the fourth switching circuit CH4 when the first switching indication signal Odd1 is at a first level (e.g., a high level), and the first input terminal and the second input terminal of the fourth switching circuit CH4 are respectively coupled to the first output terminal and the second output terminal of the fourth switching circuit CH4 when the first switching indication signal Odd1 is at a second level (e.g., a low level). Wherein, during the first sampling period, the voltage difference between the first output terminal and the second output terminal of the fourth switching circuit CH4 is equal to the first amplified signal, and during the second sampling period, the voltage difference between the first output terminal and the second output terminal of the fourth switching circuit CH4 is equal to the third amplified signal. A first offset voltage Vos1 exists between the first input terminal and the second input terminal of the first transconductance unit Gm 1. A second offset voltage Vos2 exists between the first input terminal and the second input terminal of the first fully differential amplifier A1. The offset voltage of the first amplifying circuit 430 is the difference between the first offset voltage Vos1 and the second offset voltage Vos2.

The second amplification circuit 440 includes: fifth to eighth switching circuits CH5 to CH8, a second transconductance cell Gm2, a second fully differential amplifier A2, a third resistor R3, and a fourth resistor R4. The first input terminal of the fifth switching circuit CH5 is coupled to the first output terminal of the second input circuit 420. The second input terminal of the fifth switching circuit CH5 is coupled to the second output terminal of the second input circuit 420. The first output terminal of the fifth switching circuit CH5 is coupled to the first input terminal of the second transconductance unit Gm 2. The second output terminal of the fifth switching circuit CH5 is coupled to the second input terminal of the second transconductance unit Gm 2. The fifth switching circuit CH5 is configured to: the first input terminal and the second input terminal of the fifth switching circuit CH5 are respectively coupled to the second output terminal and the first output terminal of the fifth switching circuit CH5 when the second switching indication signal Odd2 is at a first level (e.g., a high level), and the first input terminal and the second input terminal of the fifth switching circuit CH5 are respectively coupled to the first output terminal and the second output terminal of the fifth switching circuit CH5 when the second switching indication signal Odd2 is at a second level (e.g., a low level). The second transconductance cell Gm2 is configured to: the second differential voltage between the first output terminal and the second output terminal of the fifth switching circuit CH5 is converted into a second differential current. The first input terminal of the sixth switching circuit CH6 is coupled to the first output terminal of the second transconductance unit Gm 2. The second input terminal of the sixth switching circuit CH6 is coupled to the second output terminal of the second transconductance unit Gm 2. The first output terminal of the sixth switching circuit CH6 is coupled to the first input terminal of the seventh switching circuit CH7 and the first terminal of the third resistor R3. The second output terminal of the sixth switching circuit CH6 is coupled to the second input terminal of the seventh switching circuit CH7 and the first terminal of the fourth resistor R4. The sixth switching circuit CH6 is configured to: the first input terminal and the second input terminal of the sixth switching circuit CH6 are respectively coupled to the second output terminal and the first output terminal of the sixth switching circuit CH6 when the second switching indication signal Odd2 is at a first level (e.g., a high level), and the first input terminal and the second input terminal of the sixth switching circuit CH6 are respectively coupled to the first output terminal and the second output terminal of the sixth switching circuit CH6 when the second switching indication signal Odd2 is at a second level (e.g., a low level). The first output terminal of the seventh switching circuit CH7 is coupled to the first input terminal of the second fully differential amplifier A2. The second output terminal of the seventh switching circuit CH7 is coupled to the second input terminal of the second fully differential amplifier A2. The seventh switching circuit CH7 is configured to: the first input terminal and the second input terminal of the seventh switching circuit CH7 are coupled to the second output terminal and the first output terminal of the seventh switching circuit CH7, respectively, when the second switching indication signal Odd2 is at a first level (e.g., a high level), and the first input terminal and the second input terminal of the seventh switching circuit CH7 are coupled to the first output terminal and the second output terminal of the seventh switching circuit CH7, respectively, when the second switching indication signal Odd2 is at a second level (e.g., a low level). The first output terminal of the second fully differential amplifier A2 is coupled to the first input terminal of the eighth switching circuit CH 8. The second output terminal of the second fully differential amplifier A2 is coupled to the second input terminal of the eighth switching circuit CH 8. The first output terminal of the eighth switching circuit CH8 is coupled to the second terminal of the third resistor R3 and the third input terminal InP3 of the selection circuit 450. The second output terminal of the eighth switching circuit CH8 is coupled to the second terminal of the fourth resistor R4 and the fourth input terminal InP4 of the selection circuit 450. The eighth switching circuit CH8 is configured to: the first input terminal and the second input terminal of the eighth switching circuit CH8 are respectively coupled to the second output terminal and the first output terminal of the eighth switching circuit CH8 when the second switching indication signal Odd2 is at a first level (e.g., a high level), and the first input terminal and the second input terminal of the eighth switching circuit CH8 are respectively coupled to the first output terminal and the second output terminal of the eighth switching circuit CH8 when the second switching indication signal Odd2 is at a second level (e.g., a low level). Wherein, during the first sampling period, a voltage difference between the first output terminal and the second output terminal of the eighth switching circuit CH8 is equal to the second amplified signal. During the second sampling period, the voltage difference between the first output terminal and the second output terminal of the eighth switching circuit CH8 is equal to the fourth amplified signal. A third offset voltage Vos3 exists between the first input terminal and the second input terminal of the second transconductance unit Gm 2. A fourth offset voltage Vos4 exists between the first input terminal and the second input terminal of the second fully differential amplifier A2. The offset voltage of the second amplifying circuit 440 is the difference between the third offset voltage Vos3 and the fourth offset voltage Vos4.

In some embodiments of the present disclosure, the first to eighth switching circuits CH1 to CH8 may be implemented by choppers. The resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2. The resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4. Transconductance gm1=1/2R of the first transconductance cell Gm1, where R represents the resistance values of the first resistor R1 and the second resistor R2. Transconductance gm2=1/2R of the second transconductance cell Gm2, where R represents the resistance values of the third resistor R3 and the fourth resistor R4. The gain of the first amplifying circuit 430 is-2 gm1×r= -1. The gain of the second amplifying circuit 440 is-2 gm2xr= -1.

The selection circuit 450 includes: the first voltage-controlled switch S1 to the eighth voltage-controlled switch S8. The first end of the first voltage-controlled switch S1 is coupled to the first input InP1 of the selection circuit 450. A second terminal of the first voltage-controlled switch S1 is coupled to a first input terminal of the second sampling circuit ADC 2. The controlled terminal of the first voltage-controlled switch S1 is coupled to the first selection signal terminal SEL1. The first terminal of the second voltage-controlled switch S2 is coupled to the second input terminal InP2 of the selection circuit 450. A second terminal of the second voltage-controlled switch S2 is coupled to a second input terminal of the second sampling circuit ADC 2. The controlled terminal of the second voltage-controlled switch S2 is coupled to the first selection signal terminal SEL1. The first terminal of the third voltage-controlled switch S3 is coupled to the first input InP1 of the selection circuit 450. The second terminal of the third voltage-controlled switch S3 is coupled to the first input terminal of the first sampling circuit ADC 1. The controlled terminal of the third voltage-controlled switch S3 is coupled to the second selection signal terminal SEL2. The first terminal of the fourth voltage-controlled switch S4 is coupled to the second input terminal InP2 of the selection circuit 450. A second terminal of the fourth voltage-controlled switch S4 is coupled to the second input terminal of the first sampling circuit ADC 1. The controlled terminal of the fourth voltage-controlled switch S4 is coupled to the second selection signal terminal SEL2. The first end of the fifth voltage-controlled switch S5 is coupled to the third input InP3 of the selection circuit 450. A second terminal of the fifth voltage-controlled switch S5 is coupled to the first input terminal of the second sampling circuit ADC 2. The controlled terminal of the fifth voltage-controlled switch S5 is coupled to the second selection signal terminal SEL2. The first terminal of the sixth voltage-controlled switch S6 is coupled to the fourth input InP4 of the selection circuit 450. A second terminal of the sixth voltage-controlled switch S6 is coupled to the second input terminal of the second sampling circuit ADC 2. The controlled terminal of the sixth voltage-controlled switch S6 is coupled to the second selection signal terminal SEL2. The first end of the seventh voltage-controlled switch S7 is coupled to the third input InP3 of the selection circuit 450. A second terminal of the seventh voltage-controlled switch S7 is coupled to the first input terminal of the first sampling circuit ADC 1. The controlled terminal of the seventh voltage-controlled switch S7 is coupled to the first selection signal terminal SEL1. The first terminal of the eighth voltage-controlled switch S8 is coupled to the fourth input InP4 of the selection circuit 450. A second terminal of the eighth voltage-controlled switch S8 is coupled to the second input terminal of the first sampling circuit ADC 1. The controlled terminal of the eighth voltage-controlled switch S8 is coupled to the first selection signal terminal SEL1. Wherein, during the first sampling period, the first selection signal SEL1 from the first selection signal terminal SEL1 is at an active level (e.g., a high level), and the second selection signal SEL2 from the second selection signal terminal SEL2 is at an inactive level (e.g., a low level). During the second sampling period, the first selection signal SEL1 is at an inactive level (e.g., a low level), and the second selection signal SEL2 is at an active level (e.g., a high level).

In some embodiments of the present disclosure, the storage circuit 460 is configured to: the first digital signal, the second digital signal, the first gain error of the first amplifying circuit 430, the second gain error of the second amplifying circuit 440, and the offset voltage value of the second sampling circuit ADC2 are stored. The first gain error of the first amplifying circuit 430, the second gain error of the second amplifying circuit 440, and the offset voltage value of the second sampling circuit ADC2 may be measured in advance and stored in the nonvolatile memory device of the memory circuit 460.

In some embodiments of the present disclosure, during the first sample, the target codeword Dout is calculated as:

Dout＝ (Dcode1+DVos1)×(1+ GE1)+ DVos6 (1)

during the second sample, the target codeword Dout is calculated as:

Dout＝ (Dcode2+DVos2)×(1+ GE2)+ DVos6 (2)

where Dout denotes a target codeword Dout, dcode1 denotes a first codeword, DVos1 denotes a first digital signal, GE1 denotes a first gain error of the first amplifying circuit 430, dcode2 denotes a second codeword, DVos2 denotes a second digital signal, GE2 denotes a second gain error of the second amplifying circuit 440, DVos6 denotes an offset voltage value of the second sampling circuit ADC2, and Odd is a voltage difference (Odd channel) between the Odd voltage terminal and the even voltage terminal or the start voltage terminal V0, and Odd is a voltage difference (even channel) between the even voltage terminal and the Odd voltage terminal.

In the example of fig. 4, the reference voltage terminal Vref is grounded. The first input of the first transconductance cell Gm1 is a non-inverting input. The second input of the first transconductance cell Gm1 is an inverting input. The first output of the first transconductance cell Gm1 is an inverting output. The second output of the first transconductance cell Gm1 is an in-phase output. The first input of the second transconductance cell Gm2 is a non-inverting input. The second input of the second transconductance cell Gm2 is an inverting input. The first output of the second transconductance cell Gm2 is an inverting output. The second output of the second transconductance cell Gm2 is an in-phase output. The first input of the first fully differential amplifier A1 is a non-inverting input. The second input of the first fully differential amplifier A1 is an inverting input. The first output of the first fully differential amplifier A1 is an inverting output. The second output of the first fully differential amplifier A1 is an in-phase output. The first input of the second fully differential amplifier A2 is a non-inverting input. The second input of the second fully differential amplifier A2 is an inverting input. The first output of the second fully differential amplifier A2 is an inverting output. The second output of the second fully differential amplifier A2 is an in-phase output. The first input of the first sampling circuit ADC1 is a non-inverting input. The second input of the first sampling circuit ADC1 is an inverting input. The first input of the second sampling circuit ADC2 is a non-inverting input. The second input of the second sampling circuit ADC2 is an inverting input. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 4 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described components and voltage terminals may also have different arrangements from the example shown in fig. 4.

Fig. 5 shows a timing diagram of some of the signals used in the multi-channel signal acquisition circuit 400 shown in fig. 4. The operation of the multi-channel signal acquisition circuit 400 according to an embodiment of the present disclosure is described below in conjunction with the example of fig. 5.

Fig. 5 illustrates 16 channels. All sampled channels are divided into two parts, the lower part containing V0 to V8 and the upper part containing V8 to V16. In addition, the first multiplexer MUX1 and the second multiplexer MUX2 contain a set of reference voltage Vref (0V) inputs for calibration of offset voltages of the first amplifying circuit 430. The third multiplexer MUX3 and the fourth multiplexer MUX4 contain a set of reference voltage Vref (0V) inputs for calibration of offset voltages of the second amplification circuit 440. To simplify the analysis, r1=r2=r3=r4=r, gm1=gm2=1/2R may be set. The gains of the first amplification circuit 430 and the second amplification circuit 440 are-2 gm×r= -1. The polarity of the first switching indication signal Odd1 and the second switching indication signal Odd2 determines whether the corresponding signal paths sample Odd channels or even channels (where the Odd channels are defined as V (2i+1) -V (2 i), e.g. V7-V6, and the even channels are defined as V (2 i) -V (2 i-1), e.g. V6-V5, i being a positive integer).

During a first sampling period (from time T1 to time T3), the first selection signal SEL1 is at an active level (high level), and the multi-channel signal acquisition circuit 400 samples a first voltage difference between two of the voltage terminals coupled to the first input circuit 410. The first multiplexer MUX1 sequentially outputs V0, V2, V4, V6 and V8, and the second multiplexer MUX2 sequentially outputs V1, V3, V5 and V7. The length of time between time T1 and time T2 is equal to one clock cycle. The output times of V0 and V8 are one clock cycle. The output time of V1 to V7 is two clock cycles. The third multiplexer MUX3 and the fourth multiplexer MUX4 output 0V at time T1 such that the differential voltages input to the second transconductance cell Gm2 and the second fully differential amplifier A2 are both 0V. The second switch instruction signal Odd2 is at a high level (logic "1") at time T1, so that the second amplified signal is equal to Vout 2=gm2× (r3+r4) ×vos3—vos4=vos3—vos4 at this time. The second switching indication signal Odd2 is at a low level (logic "0") at time T2, so that the negative second amplified signal at this time is equal to Vout2 = -Gm2× (r3+r4) ×vos3+vos4= -vos3+vos4. The first sampling circuit ADC1 may read the difference of the two conversions: vos3+vos4- (Vos 3-Vos 4) =2× (-vos3+vos4), i.e. twice the offset voltage. Here, the offset voltage Vos5 of the first sampling circuit ADC1 itself does not affect the conversion. Since Vos5 remains unchanged during the transition, the effect of Vos5 has been eliminated during the subtraction of the two transitions. At this time, offset voltages Vos3-Vos4 (when odd2=1) and-vos3+vos4 (when odd2=0) of the second amplifying circuit 440 have been calculated and may be stored in the storage circuit 360. The memory circuit 360 is controlled by the control signal Odd, and when odd=0, the memory circuit 360 transmits an offset voltage (-vos3+vos4) to the second sampling circuit ADC 2. When odd=1, the storage circuit 360 sends offset voltages (Vos 3 to Vos 4) to the second sampling circuit ADC 2.

During the second sampling period (from time T3 to time T5), the second selection signal SEL2 is at an active level (high level), and the multi-channel signal acquisition circuit 400 samples a second voltage difference between two of the voltage terminals coupled to the second input circuit 420. The third multiplexer MUX1 sequentially outputs V8, V10, V12, V14 and V16, and the fourth multiplexer MUX4 sequentially outputs V9, V11, V13 and V15. The length of time between time T3 and time T4 is equal to one clock cycle. The output times of V8 and V16 are one clock cycle. The output time of V9 to V15 is two clock cycles. The first multiplexer MUX1 and the second multiplexer MUX2 output 0V at time T3 such that the differential voltages input to the first transconductance cell Gm1 and the first fully differential amplifier A1 are both 0V. The first switching instruction signal Odd1 is at a high level (logic "1") at a time T3 such that the third amplified signal is equal to Vout 1=gm1× (r1+r2) ×vos1-vos2=vos1-Vos 2 at this time. The first switching instruction signal Odd1 is at a low level (logic "0") at a time T4 such that the negative third amplified signal at this time is equal to Vout1 = -Gm1× (r1+r2) ×vos1+vos2= -vos1+vos2. The first sampling circuit ADC1 may read the difference of the two conversions: vos1+vos2- (Vos 1-Vos 2) =2× (-vos1+vos2), i.e. twice the offset voltage. Here, the offset voltage Vos5 of the first sampling circuit ADC1 itself does not affect the conversion. Since Vos5 remains unchanged during the transition, the effect of Vos5 has been eliminated during the subtraction of the two transitions. At this time, offset voltages Vos1-Vos2 (when odd1=1) and-vos1+vos2 (when odd1=0) of the first amplifying circuit 430 have been calculated and may be stored in the storage circuit 360. The memory circuit 360 is controlled by the control signal Odd, and when odd=0, the memory circuit 360 transmits an offset voltage (-vos1+vos2) to the second sampling circuit ADC 2. When odd=1, the storage circuit 360 transmits offset voltages (Vos 1 to Vos 2) to the second sampling circuit ADC 2.

During the first sampling, the first channel (V1-V0) is sampled at time T1, the second channel (V2-V1) is sampled at time T2, and so on. When odd1=0, vout 1= - [ V (2 i) -V (2 i-1) -vos1+vos2]. The second sampling circuit ADC2 converts Vout1 into Dcode1. At this time, odd is also equal to 0, and the storage circuit 360 sends an offset voltage (-vos1+vos2) to the second sampling circuit ADC 2. Dout= (Dcode 1+dvos1) × (1+ge1) +dvos6 according to formula (1). Wherein DVos1 represents the first digital signal into which (-vos1+vos2) is converted. In this way, dout can remove the influence of the offset voltage (-vos1+vos2) of the first amplifying circuit 430. When odd1=1, vout 1= - [ V (2 i-1) -V (2 i-2) - (-vos1+vos2) ]. The second sampling circuit ADC2 converts Vout1 into Dcode1. At this time, odd is also equal to 1, and the storage circuit 360 sends offset voltages (Vos 1 to Vos 2) to the second sampling circuit ADC 2. Dout= (Dcode 1+dvos1) × (1+ge1) +dvos6 according to formula (1). Where DVos1 represents the first digital signal into which Vos1-Vos2 are converted. In this way, dout removes the influence of the offset voltages Vos1-Vos2 of the first amplifying circuit 430. Here, i is a positive integer.

Similarly, during the second sampling, the 9 th channel (V9-V8) is sampled at time T3, the 10 th channel (V10-V9) is sampled at time T4, and so on. When odd2=0, vout 2= - [ V (2 i) -V (2 i-1) -vos3+vos4]. The second sampling circuit ADC2 converts Vout2 into Dcode2. At this time, odd is also equal to 0, and the storage circuit 360 sends an offset voltage (-Vos 3+ Vos 4) to the second sampling circuit ADC 2. Dout= (Dcode 2+dvos2) × (1+ge2) +dvos6 according to formula (2). Wherein DVos2 represents the second digital signal into which (-vos3+vos4) is converted. In this way, dout can remove the influence of the offset voltage (-vos3+vos4) of the second amplifying circuit 440. When odd1=1, vout 2= - [ V (2 i-1) -V (2 i-2) - (-vos3+vos4) ]. The second sampling circuit ADC2 converts Vout2 into Dcode2. At this time, odd is also equal to 1, and the storage circuit 360 sends offset voltages (Vos 3 to Vos 4) to the second sampling circuit ADC 2. Dout= (Dcode 2+dvos2) × (1+ge2) +dvos6 according to formula (2). Wherein DVos2 represents the second digital signal into which Vos3-Vos4 is converted. In this way, dout removes the influence of the offset voltages Vos3-Vos4 of the second amplifying circuit 440. Here, i is a positive integer.

The process shown in fig. 5 may be performed in multiple cycles. In this way, all offset voltages of the multichannel signal acquisition circuit 400 can be continuously updated and offset with the cycling of the voltage acquisition without concern for drift over time.

The embodiment of the disclosure also provides a chip. The chip includes a multichannel signal acquisition circuit according to embodiments of the present disclosure. The chip is, for example, a chip for performing high-precision multichannel analog-digital signal conversion.

The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. Such as battery management devices and industrial-scale measurement devices.

In summary, according to the multi-channel signal acquisition circuit disclosed by the embodiment of the disclosure, the offset voltage is alternately operated and calculated by arranging two signal acquisition lines, and the offset voltage which changes along with the environment and the temperature can be continuously updated and counteracted, so that the multi-channel signal acquisition with low input offset voltage and low drift is realized. Further, the multichannel signal acquisition circuit according to the embodiment of the disclosure enables input current to be low by setting the transconductance unit with high input impedance, so that multichannel signal acquisition with low input current is realized. Because the multichannel signal acquisition circuit according to the embodiment of the disclosure can adaptively offset voltage, offset voltage of the transconductance unit can be offset together, so that sampling precision of the multichannel signal acquisition circuit is not affected. In addition, the multichannel signal acquisition circuit according to the embodiments of the present disclosure does not require the use of chopping techniques, reducing the technical challenges of voltage ripple to eliminate chopping.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope of applicability will become apparent from the description provided herein. It is to be understood that various aspects of the application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A multi-channel signal acquisition circuit comprising: a first input circuit, a second input circuit, a first amplifying circuit, a second amplifying circuit, a selecting circuit, a first sampling circuit, a second sampling circuit, and a memory circuit,

the first input circuit is coupled with the initial voltage end and the first to nth voltage ends, and the second input circuit is coupled with the nth voltage end to the 2 nd voltage end;

during a first sampling period, the multi-channel signal acquisition circuit samples a first voltage difference between two of the voltage terminals coupled to the first input circuit, the first input circuit configured to provide the first voltage difference to the first amplification circuit, the second input circuit configured to provide a reference voltage difference to the second amplification circuit, the first amplification circuit configured to amplify the first voltage difference, the second amplification circuit configured to amplify the reference voltage difference, the selection circuit configured to provide a first amplified signal to the second sampling circuit and a second amplified signal to the first sampling circuit, the first amplified signal being equal to a sum of the amplified first voltage difference and an offset voltage of the first amplification circuit, the second amplified signal being equal to a sum of the amplified reference voltage difference and an offset voltage of the second amplification circuit, the first sampling circuit configured to sample the second amplified signal to generate a second digital signal;

During a second sampling period, the multi-channel signal acquisition circuit samples a second voltage difference between two of the voltage terminals coupled to the second input circuit, the first input circuit configured to provide the reference voltage difference to the first amplification circuit, the second input circuit configured to provide the second voltage difference to the second amplification circuit, the first amplification circuit configured to amplify the reference voltage difference, the second amplification circuit configured to amplify the second voltage difference, the selection circuit configured to provide a third amplified signal to the first sampling circuit and a fourth amplified signal to the second sampling circuit, the third amplified signal being equal to a sum of the amplified reference voltage difference and a offset voltage of the first amplification circuit, the fourth amplified signal being equal to a sum of the amplified second voltage difference and an offset voltage of the second amplification circuit, the first sampling circuit configured to sample the third amplified signal to generate a first digital signal;

the memory circuit is configured to: storing the first digital signal and the second digital signal;

The second sampling circuit is configured to: during the first sampling period, sampling the first amplified signal to generate a first codeword, and generating a target codeword from the first codeword and the first digital signal; during the second sampling, the fourth amplified signal is sampled to generate a second codeword, and the target codeword is generated from the second codeword and the second digital signal.

2. The multi-channel signal acquisition circuit of claim 1, wherein during the first sampling, the second amplification circuit is further configured to: generating a negative reference voltage difference and amplifying the negative reference voltage difference, the selection circuit being further configured to provide a negative second amplified signal to the first sampling circuit, the negative second amplified signal being equal to a sum of the amplified negative reference voltage difference and a negative offset voltage of the second amplifying circuit, the first sampling circuit being configured to: sampling half of the difference between the negative second amplified signal and the second amplified signal to generate the second digital signal;

during the second sampling, the first amplification circuit is further configured to: generating a negative reference voltage difference and amplifying the negative reference voltage difference, the selection circuit further configured to provide a negative third amplified signal to the first sampling circuit, the negative third amplified signal being equal to a sum of the amplified negative reference voltage difference and a negative offset voltage of the first amplifying circuit, the first sampling circuit configured to: half of the difference between the negative third amplified signal and the third amplified signal is sampled to generate the first digital signal.

3. The multi-channel signal acquisition circuit of claim 1 or 2, wherein the reference voltage difference is zero.

4. The multi-channel signal acquisition circuit of claim 1 or 2, wherein the first input circuit comprises: a first multiplexer, a second multiplexer, a plurality of filter resistors and a plurality of filter capacitors,

the first multiplexer is coupled to even voltage ends, the initial voltage ends and the reference voltage ends in the first voltage ends to the n voltage ends, the second multiplexer is coupled to odd voltage ends and the reference voltage ends in the first voltage ends to the n voltage ends, each even voltage end and each initial voltage end are respectively coupled to a filter resistor with the first multiplexer, each odd voltage end and the second multiplexer are respectively coupled to a filter resistor, each filter capacitor is coupled between any two adjacent voltage ends in the initial voltage ends and the even voltage ends, and each filter capacitor is coupled between any two adjacent voltage ends in the odd voltage ends;

the first multiplexer is configured to: sequentially outputting voltages from one of the start voltage terminal and the even voltage terminal during the first sampling period; outputting a reference voltage from the reference voltage terminal during the second sampling period;

The second multiplexer is configured to: sequentially outputting voltages from one of the odd voltage terminals during the first sampling period; outputting a reference voltage from the reference voltage terminal during the second sampling period;

the voltage difference between the output terminal of the first multiplexer and the output terminal of the second multiplexer is the first voltage difference, the time when the voltages from the start voltage terminal and the n-th voltage terminal are output is one clock period, the time when the voltages from other voltage terminals are output is two clock periods, and the other voltage terminals are other voltage terminals except the start voltage terminal and the n-th voltage terminal.

5. The multi-channel signal acquisition circuit of claim 1 or 2, wherein the second input circuit comprises: a third multiplexer, a fourth multiplexer, a plurality of filter resistors and a plurality of filter capacitors,

the third multiplexer is coupled to even voltage ends and reference voltage ends in the nth voltage ends to the 2 nd voltage ends, the fourth multiplexer is coupled to odd voltage ends and reference voltage ends in the nth voltage ends to the 2 nd voltage ends, a filter resistor is respectively coupled between each even voltage end and the third multiplexer, a filter resistor is respectively coupled between each odd voltage end and the fourth multiplexer, a filter capacitor is coupled between any two adjacent voltage ends in the even voltage ends, and a filter capacitor is coupled between any two adjacent voltage ends in the odd voltage ends;

The third multiplexer is configured to: outputting a reference voltage from the reference voltage terminal during the first sampling period; sequentially outputting voltages from one of the even voltage terminals during the second sampling period;

the fourth multiplexer is configured to: outputting a reference voltage from the reference voltage terminal during the first sampling period; sequentially outputting voltages from one of the odd voltage terminals during the second sampling period;

the voltage difference between the output terminal of the third multiplexer and the output terminal of the fourth multiplexer is the second voltage difference, the time when the voltages from the nth voltage terminal and the 2 nd voltage terminal are output is one clock period, the time when the voltages from other voltage terminals are output is two clock periods, and the other voltage terminals are other voltage terminals except the nth voltage terminal and the 2 nd voltage terminal.

6. The multi-channel signal acquisition circuit of claim 1 or 2, wherein the first amplification circuit comprises: first to fourth switching circuits, a first transconductance unit, a first fully differential amplifier, a first resistor, and a second resistor,

Wherein a first input terminal of the first switching circuit is coupled to a first output terminal of the first input circuit, a second input terminal of the first switching circuit is coupled to a second output terminal of the first input circuit, a first output terminal of the first switching circuit is coupled to a first input terminal of the first transconductance unit, a second output terminal of the first switching circuit is coupled to a second input terminal of the first transconductance unit, and the first switching circuit is configured to: coupling the first and second inputs of the first switching circuit to the second and first outputs of the first switching circuit, respectively, when the first switching indication signal is at a first level, and coupling the first and second inputs of the first switching circuit to the first and second outputs of the first switching circuit, respectively, when the first switching indication signal is at a second level;

the first transconductance unit is configured to: converting a first differential voltage between the first output terminal and the second output terminal of the first switching circuit into a first differential current;

a first input of a second switching circuit is coupled to the first output of the first transconductance cell, a second input of the second switching circuit is coupled to the second output of the first transconductance cell, the first output of the second switching circuit is coupled to the first input of a third switching circuit and the first end of the first resistor, and the second output of the second switching circuit is coupled to the second input of the third switching circuit and the first end of the second resistor, the second switching circuit being configured to: coupling the first and second inputs of the second switching circuit to the second and first outputs of the second switching circuit, respectively, when the first switching indication signal is at the first level, and coupling the first and second inputs of the second switching circuit to the first and second outputs of the second switching circuit, respectively, when the first switching indication signal is at the second level;

The first output terminal of the third switching circuit is coupled to the first input terminal of the first fully differential amplifier, the second output terminal of the third switching circuit is coupled to the second input terminal of the first fully differential amplifier, and the third switching circuit is configured to: coupling the first and second inputs of the third switching circuit to the second and first outputs of the third switching circuit, respectively, when the first switching indication signal is at the first level, and coupling the first and second inputs of the third switching circuit to the first and second outputs of the third switching circuit, respectively, when the first switching indication signal is at the second level;

the first output end of the first full differential amplifier is coupled with the first input end of the fourth switching circuit, and the second output end of the first full differential amplifier is coupled with the second input end of the fourth switching circuit;

a first output of the fourth switching circuit is coupled to the second end of the first resistor and the first input of the selection circuit, a second output of the fourth switching circuit is coupled to the second end of the second resistor and the second input of the selection circuit, the fourth switching circuit is configured to: coupling the first and second inputs of the fourth switching circuit to the second and first outputs of the fourth switching circuit, respectively, when the first switching indication signal is at the first level, and coupling the first and second inputs of the fourth switching circuit to the first and second outputs of the fourth switching circuit, respectively, when the first switching indication signal is at the second level;

Wherein, during the first sampling, a voltage difference between the first output terminal and the second output terminal of the fourth switching circuit is equal to the first amplified signal, and during the second sampling, a voltage difference between the first output terminal and the second output terminal of the fourth switching circuit is equal to the third amplified signal; a first offset voltage exists between the first input end and the second input end of the first transconductance unit, a second offset voltage exists between the first input end and the second input end of the first fully differential amplifier, and the offset voltage of the first amplifying circuit is the difference between the first offset voltage and the second offset voltage.

7. The multi-channel signal acquisition circuit of claim 1 or 2, wherein the second amplification circuit comprises: a fifth switching circuit to an eighth switching circuit, a second transconductance cell, a second fully differential amplifier, a third resistor, and a fourth resistor,

wherein a first input terminal of the fifth switching circuit is coupled to a first output terminal of the second input circuit, a second input terminal of the fifth switching circuit is coupled to a second output terminal of the second input circuit, a first output terminal of the fifth switching circuit is coupled to a first input terminal of the second transconductance unit, a second output terminal of the fifth switching circuit is coupled to a second input terminal of the second transconductance unit, and the fifth switching circuit is configured to: coupling the first and second inputs of the fifth switching circuit to the second and first outputs of the fifth switching circuit, respectively, when the second switching indication signal is at a first level, and coupling the first and second inputs of the fifth switching circuit to the first and second outputs of the fifth switching circuit, respectively, when the second switching indication signal is at a second level;

The second transconductance unit is configured to: converting a second differential voltage between the first output terminal and the second output terminal of the fifth switching circuit into a second differential current;

a first input of a sixth switching circuit is coupled to the first output of the second transconductance cell, a second input of the sixth switching circuit is coupled to the second output of the second transconductance cell, the first output of the sixth switching circuit is coupled to the first input of the seventh switching circuit and the first end of the third resistor, and a second output of the sixth switching circuit is coupled to the second input of the seventh switching circuit and the first end of the fourth resistor, the sixth switching circuit being configured to: coupling the first and second inputs of the sixth switching circuit to the second and first outputs of the sixth switching circuit, respectively, when the second switching indication signal is at the first level, and coupling the first and second inputs of the sixth switching circuit to the first and second outputs of the sixth switching circuit, respectively, when the second switching indication signal is at the second level;

The first output terminal of the seventh switching circuit is coupled to the first input terminal of the second fully differential amplifier, the second output terminal of the seventh switching circuit is coupled to the second input terminal of the second fully differential amplifier, and the seventh switching circuit is configured to: coupling the first and second inputs of the seventh switching circuit to the second and first outputs of the seventh switching circuit, respectively, when the second switching indication signal is at the first level, and coupling the first and second inputs of the seventh switching circuit to the first and second outputs of the seventh switching circuit, respectively, when the second switching indication signal is at the second level;

the first output end of the second full differential amplifier is coupled with the first input end of the eighth switching circuit, and the second output end of the second full differential amplifier is coupled with the second input end of the eighth switching circuit;

a first output of the eighth switching circuit is coupled to the second end of the third resistor and the third input of the selection circuit, a second output of the eighth switching circuit is coupled to the second end of the fourth resistor and the fourth input of the selection circuit, and the eighth switching circuit is configured to: coupling the first and second inputs of the eighth switching circuit to the second and first outputs of the eighth switching circuit, respectively, when the second switching indication signal is at the first level, and coupling the first and second inputs of the eighth switching circuit to the first and second outputs of the eighth switching circuit, respectively, when the second switching indication signal is at the second level;

Wherein, during the first sampling, a voltage difference between the first output terminal and the second output terminal of the eighth switching circuit is equal to the second amplified signal, and during the second sampling, a voltage difference between the first output terminal and the second output terminal of the eighth switching circuit is equal to the fourth amplified signal; a third offset voltage exists between the first input end and the second input end of the second transconductance unit, a fourth offset voltage exists between the first input end and the second input end of the second fully differential amplifier, and the offset voltage of the second amplifying circuit is the difference between the third offset voltage and the fourth offset voltage.

8. The multi-channel signal acquisition circuit of claim 1 or 2, wherein the selection circuit comprises: the first voltage-controlled switch to the eighth voltage-controlled switch,

the first end of the first voltage-controlled switch is coupled with the first input end of the selection circuit, the second end of the first voltage-controlled switch is coupled with the first input end of the second sampling circuit, and the controlled end of the first voltage-controlled switch is coupled with the first selection signal end;

a first end of a second voltage-controlled switch is coupled to the second input end of the selection circuit, a second end of the second voltage-controlled switch is coupled to the second input end of the second sampling circuit, and a controlled end of the second voltage-controlled switch is coupled to the first selection signal end;

A first end of a third voltage-controlled switch is coupled with the first input end of the selection circuit, a second end of the third voltage-controlled switch is coupled with the first input end of the first sampling circuit, and a controlled end of the third voltage-controlled switch is coupled with a second selection signal end;

a first end of a fourth voltage-controlled switch is coupled to the second input end of the selection circuit, a second end of the fourth voltage-controlled switch is coupled to the second input end of the first sampling circuit, and a controlled end of the fourth voltage-controlled switch is coupled to the second selection signal end;

a first end of a fifth voltage-controlled switch is coupled to the third input end of the selection circuit, a second end of the fifth voltage-controlled switch is coupled to the first input end of the second sampling circuit, and a controlled end of the fifth voltage-controlled switch is coupled to the second selection signal end;

a first end of a sixth voltage-controlled switch is coupled to the fourth input end of the selection circuit, a second end of the sixth voltage-controlled switch is coupled to the second input end of the second sampling circuit, and a controlled end of the sixth voltage-controlled switch is coupled to the second selection signal end;

a first end of a seventh voltage-controlled switch is coupled to the third input end of the selection circuit, a second end of the seventh voltage-controlled switch is coupled to the first input end of the first sampling circuit, and a controlled end of the seventh voltage-controlled switch is coupled to the first selection signal end;

The first end of the eighth voltage-controlled switch is coupled to the fourth input end of the selection circuit, the second end of the eighth voltage-controlled switch is coupled to the second input end of the first sampling circuit, and the controlled end of the eighth voltage-controlled switch is coupled to the first selection signal end;

wherein during the first sampling period, a first selection signal from the first selection signal terminal is at an active level, and a second selection signal from the second selection signal terminal is at an inactive level; during the second sampling period, the first selection signal is at an inactive level and the second selection signal is at an active level.

9. The multi-channel signal acquisition circuit of claim 1 or 2, wherein the storage circuit is further configured to: and storing a first gain error of the first amplifying circuit, a second gain error of the second amplifying circuit and an offset voltage value of the second sampling circuit.

10. The multi-channel signal acquisition circuit of claim 9, wherein during the first sampling, the target codeword is calculated as:

Dout＝(Dcode1+DVos1)×(1+GE1)+DVos6，

during the second sampling, the target codeword is calculated as:

Dout＝(Dcode2+DVos2)×(1+GE2)+DVos6，

wherein Dout represents the target codeword, dcode1 represents the first codeword, DVos1 represents the first digital signal, GE1 represents the first gain error of the first amplifying circuit, dcode2 represents the second codeword, DVos2 represents the second digital signal, GE2 represents the second gain error of the second amplifying circuit, and DVos6 represents the offset voltage value of the second sampling circuit.