CN117118435B - Digital circuit clock signal generation system and method - Google Patents
Digital circuit clock signal generation system and method Download PDFInfo
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- CN117118435B CN117118435B CN202310922316.5A CN202310922316A CN117118435B CN 117118435 B CN117118435 B CN 117118435B CN 202310922316 A CN202310922316 A CN 202310922316A CN 117118435 B CN117118435 B CN 117118435B
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 title description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention relates to the technical field of electronics, in particular to a system and a method for generating a digital circuit clock signal, comprising a frequency control module, an oscillator and a high-frequency counter, wherein the frequency control module configures corresponding counting window time and a target count value according to the frequency of a reference clock signal; the high-frequency counter counts the digital clock signals in the counting window time to obtain a high-frequency counting result; the frequency control module calculates the error of the target count value and the high-frequency count result, and adjusts the frequency control word according to the error condition; the frequency of the digital clock signal output by the oscillator based on the frequency control word reaches the required frequency, and the invention has the advantages of simple structure, small occupied area and simple and convenient application; and the clock signal with any frequency can be generated by setting the counting window time and the target counting value without any additional circuit, is insensitive to environmental changes such as temperature and voltage, and has the advantages of good working stability and the like.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a system and a method for generating a clock signal of a digital circuit.
Background
Most of the digital clock schemes now use conventional phase locked loops to generate the clock schemes required for digital circuits. The phase-locked loop comprises a plurality of circuit modules, the circuit structure is complex, and the occupied area is large. On the other hand, the pll is actually a negative feedback control loop, and the problem of loop stability of the pll must be considered when the pll is used, and each module inside the pll needs to be designed carefully, so that the loop filter is a great difficulty in designing the pll, which increases the difficulty in applying the pll.
Disclosure of Invention
The invention aims to provide a system and a method for generating a digital circuit clock signal, which aim to solve the problem of difficult application of a phase-locked loop.
In order to achieve the above object, in a first aspect, the present invention provides a system for generating a digital circuit clock signal, including a frequency control module, an oscillator, and a high frequency counter, where the frequency control module, the oscillator, and the high frequency counter are sequentially connected, and the frequency control module and the high frequency counter are sequentially connected;
The frequency control module is used for configuring corresponding counting window time and a target count value according to the frequency of the reference clock signal;
the high-frequency counter is used for counting the digital clock signals in the counting window time to obtain a high-frequency counting result;
The frequency control module is also used for calculating the errors of the target count value and the high-frequency count result and adjusting a frequency control word according to the error condition;
The oscillator outputs a digital clock signal of a corresponding frequency based on the frequency control word.
The high-frequency counter is further used for detecting the frequency of the oscillator at preset time intervals to obtain detection frequency;
The frequency control module adjusts the frequency of the digital clock signal output by the oscillator based on the detection frequency adjustment frequency control word. .
Wherein the oscillator comprises any one of a numerical control oscillator and a voltage-controlled oscillator.
The voltage-controlled oscillator comprises a digital-to-analog converter and a voltage-controlled oscillator body.
In a second aspect, the present invention provides a method for generating a clock signal of a digital circuit, when an oscillator is a digitally controlled oscillator, comprising the steps of:
Initializing, and configuring counting window time and a target count value;
Updating a frequency control word and changing the frequency of the numerical control oscillator;
controlling the high-frequency counter to reset and restore an initial value, opening a counting window, and counting the digital clock signals output by the digital controlled oscillator by the high-frequency counter; when the counting window is closed, stopping counting by the high-frequency counter, and keeping a counting result to obtain a high-frequency counting result;
the frequency control module reads the high-frequency counting result and calculates an error between the high-frequency counting result and the target counting value;
When the error is larger than the threshold value, the frequency control module updates the frequency control word by using a dichotomy, and changes the output frequency of the numerical control oscillator; when the error is equal to or less than the threshold, it is indicated that the output frequency has reached the desired frequency.
Wherein the method further comprises:
Updating the judgment threshold value;
Maintaining the frequency control word unchanged, updating the judgment threshold value, and maintaining the output frequency stable;
Resetting the high-frequency counter to restore an initial value;
since the frequency of the numerically controlled oscillator is changed due to the change of external factors, waiting for a preset time is required;
After a preset time interval, a counting window is opened, so that the high-frequency counter counts digital clock signals output by the digital controlled oscillator; when the window is closed, the high-frequency counter stops counting, and the counting result is kept;
The frequency control module reads the high-frequency counting result and calculates an error between the counting result and the target counting value;
When the error is greater than the threshold value, the frequency control module adjusts the frequency control word; when the error is smaller than or equal to the threshold value, the output frequency is unchanged, the frequency control word is kept unchanged, the judgment threshold value is updated, and the output frequency is kept stable.
Wherein, the frequency control module adjusts a frequency control word, comprising:
The frequency control module adds 1 or subtracts 1 according to the error condition, finely tunes the frequency of the numerical control oscillator, corrects the frequency deviation caused by external factors, then resets the high-frequency counter to reset and restore the initial value, and carries out the next frequency correction.
According to the system for generating the digital circuit clock signal, the frequency control module configures corresponding counting window time and target counting value according to the frequency of the reference clock signal; the high-frequency counter counts the digital clock signals in the counting window time to obtain a high-frequency counting result; the frequency control module calculates the errors of the target count value and the high-frequency count result, and adjusts a frequency control word according to the error condition; the frequency of the digital clock signal output by the oscillator based on the frequency control word reaches the required frequency, and the invention has the advantages of simple structure, small occupied area and simple and convenient application; the clock signal with any frequency can be generated by setting the counting window time and the target counting value without any additional circuit, is insensitive to environmental changes such as temperature and voltage, has the advantages of good working stability and the like, and solves the problem of difficult application of the phase-locked loop.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an oscillator of a digital control oscillator of a digital circuit clock signal generating system according to the present invention.
Fig. 2 is a schematic diagram of an oscillator of a digital circuit clock signal generating system according to the present invention.
Fig. 3 is a control timing diagram.
Fig. 4 is a step diagram of a method for generating a digital circuit clock signal according to the present invention.
Fig. 5 is a schematic diagram of an embodiment for generating an 800MHz clock signal.
Fig. 6 is a flowchart of a method for generating a digital circuit clock signal according to the present invention.
The device comprises a 1-frequency control module, a 2-high frequency counter, a 3-numerical control oscillator, a 4-digital-analog converter and a 5-voltage-controlled oscillator body.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
Referring to fig. 1 to 2, in a first aspect, the present invention provides a system for generating a digital circuit clock signal, which includes a frequency control module 1, an oscillator and a high frequency counter 2, wherein the frequency control module 1, the oscillator and the high frequency counter 2 are sequentially connected, and the frequency control module 1 and the high frequency counter 2 are sequentially connected;
The frequency control module 1 is configured to configure corresponding counting window time and a target count value according to the frequency of the reference clock signal;
the high-frequency counter 2 is used for counting the digital clock signals in the counting window time to obtain a high-frequency counting result;
The frequency control module 1 is further configured to calculate an error between the target count value and the high-frequency count result, and adjust a frequency control word according to an error condition;
The oscillator outputs a digital clock signal of a corresponding frequency based on the frequency control word.
Specifically, where the reference clock signal ref_clk is an accurate clock signal, typically given by a crystal, signal source, etc., the frequency is hardly affected by the external environment. First, the frequency of the required clock signal dig_clk is determined, and corresponding count window time and target count value are configured in the frequency control module 1 according to the frequency of the reference clock ref_clk. The high-frequency counter 2 counts the digital clock dig_clk in the counting window time; after counting, the frequency control module 1 calculates the error of the target count value and the high-frequency count result, adjusts the frequency control word FCW according to the error condition, and enables the frequency of the digital clock signal dig_clk output by the numerically controlled oscillator 3 to reach the required frequency. Compared with the traditional scheme of generating clock signals based on phase-locked loops, the invention has the advantages of simple structure, small occupied area and simple and convenient application; and the clock signal with any frequency can be generated by setting the counting window time and the target counting value without any additional circuit, is insensitive to environmental changes such as temperature and voltage, and has the advantages of good working stability and the like.
Further, the high-frequency counter 2 is further configured to detect the frequency of the oscillator every preset time interval, so as to obtain a detected frequency;
the frequency control module 1 adjusts the frequency of the digital clock signal output by the oscillator based on the detection frequency adjustment frequency control word. .
Specifically, after the above frequency adjustment, the frequency of the digital clock signal dig_clk reaches the desired frequency, so that in order to avoid the influence of external environments such as voltage and temperature on the frequency of the digitally controlled oscillator 3, the frequency is detected by the high frequency counter 2 at intervals, and the frequency control word FCW is adjusted according to the frequency control module 1, so that the frequency of the digital clock signal dig_clk output by the digitally controlled oscillator 3 is kept unchanged.
Further, the oscillator includes any one of a numerically controlled oscillator 3 and a voltage controlled oscillator. The voltage controlled oscillator comprises a digital to analog converter 4 and a voltage controlled oscillator body 5.
Specifically, if a voltage-controlled oscillator body 5 is used in the circuit, a digital-to-analog converter 4 (DAC) may be connected before the voltage-controlled oscillator body 5 to replace the digital-controlled oscillator 3.
Referring to fig. 3 to 6, in a second aspect, the present invention provides a method for generating a digital clock signal, when the oscillator is a digitally controlled oscillator 3, the method is used to generate the digital clock signal, an accurate reference clock signal ref_clk is required to be provided externally, the count window time, the target count value and the judgment threshold are configured according to the desired digital clock frequency, and the digital clock signal with the desired frequency can be output after being adjusted by the frequency control module 1. The whole process is divided into two stages, and the specific steps are as follows:
stage one: according to the configured values, the output frequency of the digitally controlled oscillator 3 is searched and controlled to a desired frequency.
S1, initializing, and configuring counting window time and a target count value;
S2, updating a frequency control word and changing the frequency of the numerical control oscillator 3;
S3, controlling the high-frequency counter 2 to reset and restore an initial value, opening a counting window, and enabling the high-frequency counter 2 to count a digital clock signal output by the digital controlled oscillator 3; when the counting window is closed, the high-frequency counter 2 stops counting and keeps the counting result to obtain a high-frequency counting result;
S4, the frequency control module 1 reads the high-frequency counting result and calculates an error between the high-frequency counting result and the target counting value;
s5, when the error is larger than a threshold value, the frequency control module 1 updates a frequency control word by using a dichotomy, and changes the output frequency of the numerical control oscillator 3; when the error is equal to or less than the threshold, it is indicated that the output frequency has reached the desired frequency.
Stage two: after the above steps are completed, the device is already able to provide a clock signal around the desired frequency. The frequency of the digitally controlled oscillator 3 may also be changed due to the change of external factors such as voltage and temperature, and this stage is to correct the influence of various factors on the frequency, so that the clock signal frequency reaches the desired frequency, and maintain the output clock signal frequency unchanged.
S6, updating a judgment threshold;
S7, keeping the frequency control word unchanged, updating the judgment threshold value, and keeping the output frequency stable;
S8, resetting the high-frequency counter 2 to reset and restore an initial value;
s9, the frequency of the numerical control oscillator 3 is changed due to the change of external factors, so that the preset time is required to wait;
s10, after a preset time interval, opening a counting window to enable the high-frequency counter 2 to count digital clock signals output by the digital controlled oscillator 3; when the window is closed, the high-frequency counter 2 stops counting, and the counting result is kept;
S11, the frequency control module 1 reads the high-frequency counting result and calculates an error between the counting result and a target counting value;
S12, when the error is larger than a threshold value, the frequency control module 1 adjusts a frequency control word; when the error is smaller than or equal to the threshold value, the output frequency is unchanged, the frequency control word is kept unchanged, the judgment threshold value is updated, and the output frequency is kept stable.
Specifically, the frequency control module 1 adjusts a frequency control word, including:
the frequency control module 1 adds 1 or subtracts 1 according to the error condition, finely adjusts the frequency of the numerical control oscillator 3, corrects the frequency deviation caused by external factors, and then resets the high-frequency counter 2 to reset and restore the initial value to carry out the next frequency correction.
One embodiment of the present invention is to generate a 800MHz clock signal, and the block diagram is shown in fig. 5. The external reference signal REF_CLK with the frequency of 50MHz is provided, the internal numerical control oscillator 3 has the frequency range of 750M-850 MHz, and the frequency control word FCW is 8 bits.
1. The count window is configured to 2us, the target count value is configured to 1600, and the waiting interval time is set to 0.5s.
2. After initializing the configured parameters, the frequency control word FCW is set to 1000_0000 from step S2, and then steps S3 to S5 are performed, and it is determined whether the step S2 needs to be performed for looping according to the error. In this embodiment, the FCW is 8 bits, and according to the principle of the binary method, the value of the frequency control word FCW can be completely determined to meet the requirement of the judgment threshold at most 8 times in the first stage, and the process proceeds to the second stage step S6.
3. After the above-described process, the output frequency of the digitally controlled oscillator 3 was around 800MHz. After updating the threshold value according to the application condition, the steps S7 to S12 of the second stage are circularly executed every 0.5S. That is, the frequency deviation caused by various factors is checked every 0.5s and corrected, so that the output frequency is stabilized at 800MHz.
The foregoing disclosure is only illustrative of a preferred embodiment of a system and method for generating a clock signal for a digital circuit, and it is to be understood that the invention is not limited thereto, and that all or part of the process for implementing the embodiment is understood by those skilled in the art and that equivalent changes may be made thereto while remaining within the scope of the invention as defined in the appended claims.
Claims (6)
1. A system for generating a clock signal for a digital circuit is characterized in that,
The device comprises a frequency control module, an oscillator and a high-frequency counter, wherein the frequency control module, the oscillator and the high-frequency counter are sequentially connected;
The frequency control module is used for configuring corresponding counting window time and a target count value according to the frequency of the reference clock signal;
the high-frequency counter is used for counting the digital clock signals in the counting window time to obtain a high-frequency counting result;
The frequency control module is also used for calculating the errors of the target count value and the high-frequency count result and adjusting a frequency control word according to the error condition;
the oscillator is used for controlling the frequency of the digital clock signal output by the word to reach the required frequency;
the generation method of the generation system suitable for the digital circuit clock signal comprises the following steps:
When the oscillator is a numerically controlled oscillator, the method comprises the following steps:
Initializing, and configuring counting window time and a target count value;
Updating a frequency control word and changing the frequency of the numerical control oscillator;
controlling the high-frequency counter to reset and restore an initial value, opening a counting window, and counting the digital clock signals output by the digital controlled oscillator by the high-frequency counter; when the counting window is closed, stopping counting by the high-frequency counter, and keeping a counting result to obtain a high-frequency counting result;
the frequency control module reads the high-frequency counting result and calculates an error between the high-frequency counting result and the target counting value;
When the error is larger than the threshold value, the frequency control module updates the frequency control word by using a dichotomy, and changes the output frequency of the numerical control oscillator; when the error is equal to or less than the threshold, it is indicated that the output frequency has reached the desired frequency.
2. The system for generating a digital circuit clock signal according to claim 1,
The system for generating the digital circuit clock signal further comprises a detection result frequency control module, wherein the detection result frequency control module is connected with the high-frequency counter;
the high-frequency counter is also used for detecting the frequency of the oscillator at preset time intervals to obtain detection frequency;
and the detection result frequency control module adjusts a frequency control word based on the detection frequency, and the frequency of the digital clock signal output by the oscillator is kept unchanged.
3. The system for generating a digital circuit clock signal according to claim 2,
The oscillator includes any one of a numerically controlled oscillator and a voltage controlled oscillator.
4. The system for generating a digital circuit clock signal according to claim 3,
The voltage controlled oscillator includes a digital-to-analog converter and a voltage controlled oscillator body.
5. The system for generating a digital circuit clock signal according to claim 1,
The method further comprises the steps of:
Updating the judgment threshold value;
Maintaining the frequency control word unchanged, updating the judgment threshold value, and maintaining the output frequency stable;
Resetting the high-frequency counter to restore an initial value;
since the frequency of the numerically controlled oscillator is changed due to the change of external factors, waiting for a preset time is required;
After a preset time interval, a counting window is opened, so that the high-frequency counter counts digital clock signals output by the digital controlled oscillator; when the window is closed, the high-frequency counter stops counting, and the counting result is kept;
The frequency control module reads the high-frequency counting result and calculates an error between the counting result and the target counting value;
When the error is greater than the threshold value, the frequency control module adjusts the frequency control word; when the error is smaller than or equal to the threshold value, the output frequency is unchanged, the frequency control word is kept unchanged, the judgment threshold value is updated, and the output frequency is kept stable.
6. The system for generating a digital circuit clock signal according to claim 5,
The frequency control module adjusts a frequency control word, comprising:
The frequency control module adds 1 or subtracts 1 according to the error condition, finely tunes the frequency of the numerical control oscillator, corrects the frequency deviation caused by external factors, then resets the high-frequency counter to reset and restore the initial value, and carries out the next frequency correction.
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| CN101640534A (en) * | 2009-08-14 | 2010-02-03 | 东南大学 | Full digital phase-locked loop applying rapid frequency capture method |
| US7860205B1 (en) * | 2001-09-18 | 2010-12-28 | Ciena Corporation | Clock synchronization using a weighted least squares error filtering technique |
| CN102369665A (en) * | 2009-04-03 | 2012-03-07 | Nxp股份有限公司 | Frequency synthesiser |
| CN115483926A (en) * | 2022-10-08 | 2022-12-16 | 东南大学 | All-digital phase-locked loop framework based on phase discrimination algorithm |
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- 2023-07-25 CN CN202310922316.5A patent/CN117118435B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7860205B1 (en) * | 2001-09-18 | 2010-12-28 | Ciena Corporation | Clock synchronization using a weighted least squares error filtering technique |
| CN102369665A (en) * | 2009-04-03 | 2012-03-07 | Nxp股份有限公司 | Frequency synthesiser |
| CN101640534A (en) * | 2009-08-14 | 2010-02-03 | 东南大学 | Full digital phase-locked loop applying rapid frequency capture method |
| CN115483926A (en) * | 2022-10-08 | 2022-12-16 | 东南大学 | All-digital phase-locked loop framework based on phase discrimination algorithm |
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