CN117118217A - Soft start cycle time control circuit applied to DC/DC converter - Google Patents

Soft start cycle time control circuit applied to DC/DC converter Download PDF

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Publication number
CN117118217A
CN117118217A CN202310980845.0A CN202310980845A CN117118217A CN 117118217 A CN117118217 A CN 117118217A CN 202310980845 A CN202310980845 A CN 202310980845A CN 117118217 A CN117118217 A CN 117118217A
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China
Prior art keywords
tube
pmos tube
nmos
drain electrode
source
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CN202310980845.0A
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Chinese (zh)
Inventor
卢启军
胡鑫源
陈波
朱樟明
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Chongqing Institute Of Integrated Circuit Innovation Xi'an University Of Electronic Science And Technology
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Chongqing Institute Of Integrated Circuit Innovation Xi'an University Of Electronic Science And Technology
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Priority to CN202310980845.0A priority Critical patent/CN117118217A/en
Publication of CN117118217A publication Critical patent/CN117118217A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a soft start cycle time control circuit applied to a DC/DC converter, which comprises: a clock signal generation circuit for generating a first clock signal; the clock period expanding circuit is used for expanding the period of the first clock signal to obtain a second clock signal; the soft start circuit is used for continuously outputting a fixed voltage in T; a step voltage generating circuit for generating a step voltage within T according to a fixed voltage; in the soft start time, the DC/DC converter responds to the first PWM signal to control the on and off of the power tube to realize soft start; after the soft start time, the DC/DC converter responds to the second PWM signal to control the on and off of the power tube to realize voltage conversion; the first PWM signal is generated according to a comparison result of the feedback voltage and the step voltage. The soft start cycle time control circuit is easy to integrate, the soft start process is effective and stable, and the voltage switching process is stable after the soft start is finished.

Description

Soft start cycle time control circuit applied to DC/DC converter
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a soft start cycle time control circuit applied to a DC/DC converter.
Background
The schematic diagram of a PWM (pulse width modulation ) boost converter in the classical peak current mode is shown in fig. 1, and is mainly composed of energy storage elements (inductance and capacitance), power switching tubes, loads and driving circuits. The basic working principle is as follows: load R L The voltage at both ends is taken as a feedback voltage V FB Applied to the inverting input of the error amplifier EA and a reference voltage V REF Is added at the non-inverting input end of the error amplifier EA, the difference value between the two is processed by the error amplifier to obtain an error amplified signal VEA, and the signal is connected into the PWM comparator COMP and the sampling resistor R S Finally generates a PWM control signal capable of controlling the on or off of the power tubes Mn and MP, and adjusts the duty ratio of the PWM control signal to output voltage V OUT And (5) adjusting.
However, the converter has a low output voltage at the moment of circuit start-up and a low voltage across the load, so that when this voltage is fed back to the input of the error amplifier, it is due to V FB Far less than V REF The error amplifier is in an unbalanced state, the VEA outputs a high level, and the VEA is higher than the maximum value of the sampling voltage, and the loop is in a 100% duty cycle working state. The loop is always on, resulting in a large inductor current flowing through the power piping into the output capacitor, resulting in inrush current and overshoot voltage, which can damage the entire system for portable electronic devices.
In order to avoid the occurrence of the abnormal conditions, the prior art introduces a design idea of soft start. A common conventional soft start circuit is shown in fig. 2, and the basic working principle thereof is as follows: through a small current source I soft For soft start capacitor C SS Charging to obtain a V rising in a slope from 0 soft This level replaces V ref And feedback voltage V FB Comparing, the duty ratio of the PWM control signal is gradually increased, and the final output voltage of the DC/DC converter is gradually increasedAnd the aim of soft start is fulfilled. Such a soft start scheme, while simple to implement, requires a large capacitor or a relatively small charge current to generate a gently rising ramp voltage in order to achieve a longer soft start time. However, the large capacitor is not easy to integrate in the chip, and if the large capacitor is integrated outside, extra chip pins are added, so that the cost is increased; while small charging currents have the disadvantage of poor anti-jamming capability. In addition, the soft start scheme has poor linearity in the voltage switching process after the soft start is finished, and the overshoot phenomenon of the inductance current and the output voltage can also occur. Therefore, there is an urgent need for a soft start scheme that is easy to integrate, has an efficient and stable soft start process, and has a stable voltage switching process after the soft start is completed.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a soft start cycle time control circuit applied to a DC/DC converter.
The technical problems to be solved by the invention are realized by the following technical scheme:
a soft start cycle time control circuit for a DC/DC converter, comprising: a clock signal generating circuit, a clock period expanding circuit, a soft start circuit and a step voltage generating circuit;
the clock signal generation circuit is used for generating a first clock signal;
the clock period expanding circuit is used for expanding the period of the first clock signal to obtain a second clock signal; the time length of the signal level of the second clock signal in the clock period is T, and T is equal to the soft start time of the DC/DC converter;
the soft start circuit is electrically connected with the clock period expansion circuit and is used for continuously outputting a fixed voltage in T;
the step voltage generation circuit is used for generating a step voltage in T according to the fixed voltage;
in the soft start time, the DC/DC converter responds to a first PWM signal to control the on and off of a power tube of the DC/DC converter to realize soft start; after the soft start time, the DC/DC converter responds to a second PWM signal to control the on and off of a power tube of the DC/DC converter to realize voltage conversion; the first PWM signal is generated according to a comparison result of the feedback voltage of the output voltage of the DC/DC converter and the step voltage, and the second PWM signal is generated according to a comparison result of the feedback voltage and a reference voltage.
In one embodiment, the clock signal generation circuit includes: PMOS tube P 1 PMOS tube P 2 PMOS tube P 3 PMOS tube P 4 NMOS tube N 1 NMOS tube N 2 Capacitance C 1 Inverter INV 1 Inverter INV 2 ；
Wherein, PMOS tube P 1 Source stage of (P) PMOS tube P 2 Source stage of (d) and PMOS transistor P 3 The source stages of the voltage transformer are connected with the power supply voltage; PMOS tube P 1 The grid electrode and the drain electrode of the transistor are connected with the PMOS tube P 2 A gate electrode of (a); PMOS tube P 1 The drain electrode of the transistor is connected with bias current; PMOS tube P 2 The drain electrode of (C) is connected with the PMOS tube P 4 Is a source of (1); PMOS tube P 4 Gate and NMOS transistor N of (2) 1 The grid electrodes of the (C) are connected with the inverter INV 2 Output end of PMOS tube P 4 The drain electrode of (C) is connected with the PMOS tube P 3 Drain electrode of NMOS transistor N 1 Drain electrode of NMOS transistor N 2 Drain electrode of (C) and capacitor (C) 1 One end of (a) and inverter INV 1 Capacitance C at the input end of (2) 1 The other end of the first electrode is grounded; inverter INV 1 The output end of the (E) is connected with the inverter INV 2 Is of the input end of NMOS tube N 2 Gate of (c) and PMOS tube P 3 A gate electrode of (a); NMOS tube N 1 Source of (N) NMOS transistor N 2 Source stage of (a) is grounded, inverter INV 2 Outputs the first clock signal.
In one embodiment, the clock signal generation circuit includes: PMOS tube P 31 PMOS tube P 32 PMOS tube P 33 PMOS tube P 34 PMOS tube P 35 PMOS tube P 36 PMOS tube P 37 NMOS tube N 31 NMOS tube N 32 NMOS tube N 33 NMOS tube N 34 NMOS tube N 35 Capacitance C 31 Inverter INV 31 Inverter INV 32 ；
Wherein, PMOS tube P 31 Source stage of (P) PMOS tube P 32 Source stage of (P) PMOS tube P 33 Source stage of (d) and PMOS transistor P 34 The source stages of the voltage transformer are connected with the power supply voltage; PMOS tube P 31 Grid electrode, drain electrode and PMOS tube P 32 Grid electrode of PMOS tube P 33 Gate of (d) and PMOS transistor P 35 Are connected with each other; PMOS tube P 35 Grid electrode, drain electrode and PMOS tube P 36 Gate of (d) and NMOS transistor N 31 The drains of the two are connected; NMOS tube N 31 Gate enable signal ENP 0 The enable signal ENP 0 High level is effective in the soft start time; NMOS tube N 31 Is connected with the bias current; PMOS tube P 32 The drain electrode of (C) is connected with the PMOS tube P 36 Is a source of (1); PMOS tube P 36 Drain electrode of NMOS transistor N 32 Drain and gate of (a) and NMOS transistor N 33 The grid electrodes of the two are connected; PMOS tube P 33 The drain electrode of (C) is connected with the PMOS tube P 37 Is a source of (1); PMOS tube P 37 Gate and NMOS transistor N of (2) 34 The grid electrodes of the (C) are connected with the inverter INV 32 An output terminal of (a); PMOS tube P 37 Drain electrode of NMOS transistor N 34 Drain electrode of PMOS tube P 34 Drain electrode of (d) and NMOS transistor N 35 Drain electrodes of (a) are connected to the inverter INV 31 Is provided; capacitor C 31 One end of (a) is connected to the inverter INV 31 The other end of the input end is grounded; inverter INV 31 The output end of (a) is connected with the inverter INV 32 Is provided; PMOS tube P 34 Gate and NMOS transistor N of (2) 35 The grid electrodes of the (C) are connected with the inverter INV 32 Is provided; NMOS tube N 32 Source of (N) NMOS transistor N 33 Source of (2) and NMOS transistor N 35 Is grounded; NMOS tube N 33 The drain electrode of (a) is connected with NMOS tube N 34 Is a source of (1); inverter INV 32 Outputs the first clock signal.
In one embodiment, the clock cycle extension circuit includes: n cascaded T flip-flops;
the VS end of each T trigger is connected with a power supply voltage, the CP end of the 1 st T trigger is connected with the first clock signal, and the QN end of the n= [1,2, …, N-1] T trigger is connected with the CP end of the n+1th T trigger; the CD ends of the N T triggers are all connected with low level; and the QN end of the Nth T trigger outputs the second clock signal.
In one embodiment, the clock cycle extension circuit includes: the system comprises an AND gate, a NOR gate, a first inverter, a second inverter, N cascaded T flip-flops and N-1 NAND gates, wherein the N-1 NAND gates are in one-to-one correspondence with the first N-1T flip-flops;
wherein the VS end of each T trigger is connected with the power supply voltage, the CP end of the 1 st T trigger is connected with the first clock signal, and the nth= [1,2, …, N-1]]The QN ends of the T triggers are connected with the first input ends of the corresponding NAND gates, and the output ends of the NAND gates are connected with the CP ends of the n+1th T triggers; the CD ends of the N T triggers are connected with an enabling signal RSTX; the enable signal RSTX is the enable signal ENP 0 And the enabling signal RST is obtained by NAND operation; the enable signal RST is active high in the soft start time; the Q end of the N T trigger is connected with one input end of the AND gate, and the other input end of the AND gate is connected with an enable signal ENP 1 The enable signal ENP 1 High level is effective in the soft start time; the output end of the AND gate is connected with one input end of the NOR gate, and the enable signal ENP 0 The second inverter is connected with the other input end of the NOR gate, and the output end of the NOR gate outputs a third clock signal; the QN end of the Nth T trigger outputs the second clock signal through the first phase inverter, and the signal level of the third clock signal is opposite to that of the second clock signal; the third clock signal is connected to the second input of each NAND gate.
In one embodiment, the soft start circuit includes: PMOS tube P 11 PMOS tube P 12 PMOS tube P 13 PMOS tube P 14 PMOS tube P 15 PMOS tube P 16 PMOS tube P 17 NMOS tube N 11 NMOS tube N 12 NMOS tube N 13 NMOS tube N 14 NMOS tube N 15 NMOS tube N 16 NMOS tube N 17 NMOS tube N 18 NMOS tube N 19 Resistance R 1 Resistor R 2 ；
Wherein, PMOS tube P 11 Is connected with bias current, PMOS tube P 11 The grid electrode of the PMOS tube P is connected with the second clock signal 11 The drain electrode of (a) is connected with NMOS tube N 11 Drain electrode of NMOS tube N 11 The grid electrode of (C) is connected with NMOS tube N 11 Drain electrode of NMOS transistor N 13 Gate of (2), NMOS transistor N 15 Gate and NMOS transistor N of (2) 17 A gate electrode of (a); NMOS tube N 11 Source-connected NMOS transistor N 12 Drain electrode of NMOS tube N 12 The grid electrode of (C) is connected with NMOS tube N 12 Drain electrode of NMOS transistor N 14 Gate of (2), NMOS transistor N 16 Gate and NMOS transistor N of (2) 18 A gate electrode of (a); NMOS tube N 12 Source of (N) NMOS transistor N 14 Source of (N) NMOS transistor N 16 Source of (2) and NMOS transistor N 18 Is grounded; NMOS tube N 14 The drain electrode of (a) is connected with NMOS tube N 13 Source of NMOS transistor N 13 Is connected with PMOS tube P by the drain electrode 12 A drain electrode of (2); PMOS tube P 12 Source stage of (P) PMOS tube P 13 Source stage of (P) PMOS tube P 14 Source PMOS tube P 15 Source of (d) and resistor R 1 One end of each of the resistors R is connected with a power supply voltage 1 Is connected with the other end of the NMOS tube N 19 A drain electrode of (2); PMOS tube P 12 The grid electrode of (C) is connected with the PMOS tube P 12 Drain electrode of (C) and PMOS tube P 13 A gate electrode of (a); PMOS tube P 13 The drain electrode of (C) is connected with the PMOS tube P 16 Source stage and PMOS tube P of (2) 17 Source stage of PMOS tube P 16 The grid electrode of the PMOS tube is connected with the voltage division of the reference voltage 16 The drain electrode of (a) is connected with NMOS tube N 17 Source and NMOS transistor N 18 Drain electrode of PMOS tube P 17 The grid electrode of (C) is connected with NMOS tube N 19 Source electrode of PMOS tube P 17 The drain electrode of (a) is connected with NMOS tube N 15 Source and NMOS transistor N 16 Drain electrode of NMOS tube N 15 The drain electrode of (C) is connected with the PMOS tube P 14 Drain electrode of PMOS tube P 14 The grid electrode of (C) is connected with the PMOS tube P 14 Drain electrode of (C) and PMOS tube P 15 Grid electrode of PMOS tube P 15 The drain electrode of (a) is connected with NMOS tube N 17 Drain electrode of (d) and NMOS transistor N 19 A gate electrode of (a); NMOS tubeN 19 Source pass resistance R of (2) 2 And the connection part is grounded and outputs the fixed voltage.
In one embodiment, the step voltage generating circuit includes: module 1-Module N, N-1 resistors R d NMOS tube N SW Resistance R e Resistance R f NMOS tube N E ；
The module 1 comprises: NMOS tube N 21 Resistance R a1 Resistance R b1 Resistance R c1 NMOS tube N 31 Resistor R g The method comprises the steps of carrying out a first treatment on the surface of the Wherein, NMOS tube N 21 The drain electrode of the first T trigger is connected with the fixed voltage, the grid electrode of the first T trigger is connected with the Q end of the 1 st T trigger in the clock period expansion circuit, and the source electrode sequentially passes through a resistor R a1 Resistance R c1 Resistor R g Grounding; resistor R b1 Is connected to resistor R a1 And resistance R c1 The other end is connected with an NMOS tube N 31 A drain electrode of (2); NMOS tube N 31 The grid electrode is connected with the QN end of the 1 st T trigger in the clock period expansion circuit; resistor R c1 And resistance R g The connecting node between the two is an output node of the module 1;
module m= [2,3, …, N]Comprising the following steps: NMOS tube N 2m Resistance R am Resistance R bm Resistance R cm NMOS tube N 3m The method comprises the steps of carrying out a first treatment on the surface of the Wherein, NMOS tube N 2m The drain electrode of the (E) is connected with the fixed voltage, the grid electrode is connected with the Q end of the mth T trigger in the clock period expansion circuit, and the source electrode sequentially passes through a resistor R am And resistance R cm Then the output node of the module m is used as an output node of the module m; resistor R bm Is connected to resistor R am And resistance R cm The other end is connected with an NMOS tube N 3m A drain electrode of (2); NMOS tube N 3m The grid electrode is connected with the QN end of an mth T trigger in the clock period expansion circuit;
the output node of the module 1 and the output node of the module 2, the output node of the module m and the output node of the module m+1 pass through a resistor R d Realizing connection;
NMOS tube N SW Is connected with the DC/D by the grid electrodeThe SW node voltage of the C converter and the source electrode are connected with the output node of the module N; NMOS tube N SW The drain electrode of (a) sequentially passes through a resistor R e And resistance R f Connected to NMOS tube N E The step voltage is output from the junction of the drain electrode of the transistor; NMOS tube N E The gate of (a) is connected with an enable signal ENN, the source is grounded, and the enable signal ENN is an enable signal ENP 0 And enable signal ENP 1 And a NAND output of both; enable signal ENP 0 And enable signal ENP 1 Are active high during the soft start time.
The invention provides a soft start period time control circuit applied to a DC/DC converter, wherein a clock signal generating circuit generates a first clock signal; the clock period expansion circuit expands the period of the first clock signal to obtain a second clock signal, so that the time length of which the signal level is high is the soft start time of the DC/DC converter, and the soft start circuit is caused to continuously output a fixed voltage in T; the step voltage generating circuit generates a step voltage in T according to the fixed voltage; in this way, when the DC/DC converter is in soft start, the step voltage is compared with the feedback voltage of the output voltage of the DC/DC converter, and the first PWM signal is generated according to the comparison result to control the on and off of the power tube, so that an effective and stable soft start process is realized. And, after the soft start, the DC/DC converter uses the second PWM signal to perform normal operation irrespective of the output of the soft start cycle time control circuit, so that the voltage switching process is stable after the soft start is finished. In addition, the soft start cycle time control circuit provided by the invention is not dependent on large capacitance implementation, so that the soft start cycle time control circuit is easy to integrate.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of a PWM boost converter in a classical peak current mode;
FIG. 2 is a schematic diagram of a conventional soft start circuit as is common in the prior art;
fig. 3 is a block diagram of a soft start cycle time control circuit applied to a DC/DC converter according to an embodiment of the present invention;
FIG. 4 (a) is a circuit diagram of a clock signal generation circuit applied to the soft start cycle time control circuit of FIG. 3;
FIG. 4 (b) is a circuit diagram of another clock signal generation circuit applied to the soft start cycle time control circuit of FIG. 3
FIG. 4 (c) is a circuit diagram of a further clock signal generation circuit applied to the soft start cycle time control circuit of FIG. 3
FIG. 5 (a) is a schematic diagram of a T flip-flop;
FIG. 5 (b) is a circuit diagram of another clock cycle expansion circuit applied to the soft start cycle time control circuit of FIG. 3;
FIG. 6 is a circuit diagram of a soft start circuit applied to the soft start cycle time control circuit of FIG. 3;
FIG. 7 is a circuit diagram of a step voltage generation circuit applied to the soft start cycle time control circuit of FIG. 3;
Fig. 8 is a waveform of a key control signal applied to a soft start cycle time control circuit of a DC/DC converter according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
In order to realize a soft start scheme that is easy to integrate, has an effective and stable soft start process, and has a stable voltage switching process after soft start, an embodiment of the present invention provides a soft start cycle time control circuit applied to a DC/DC converter, as shown in fig. 3, the circuit includes: a clock signal generating circuit, a clock period expanding circuit, a soft start circuit and a ladder voltage generating circuit.
Wherein the clock signal generating circuit is used for generating a first clock signal CLK 1 ；
A clock period expanding circuit for generating a first clock signal CLK 1 Is extended to obtain a second clock signal CLK 2 The method comprises the steps of carrying out a first treatment on the surface of the The second clock signal CLK 2 Its signal power in clock period of (2)The flat-high duration is T, and T is equal to the soft start time of the DC/DC converter; that is, the second clock signal CLK 2 Is twice the soft start time of the DC/DC converter, such that when the second clock signal toggles from a high level to a low level, i.e. it represents the end of the soft start process.
The soft start circuit is electrically connected with the clock period expansion circuit and is used for continuously outputting a fixed voltage V in T 0 。
A step voltage generating circuit for generating a fixed voltage V 0 Generating a step voltage within T; the voltage value of the step voltage rises slowly, as V in FIG. 3 1 。
In the soft start time, the DC/DC converter responds to the first PWM signal to control the on and off of the power tube to realize soft start; after the soft start time, the DC/DC converter responds to the second PWM signal to control the on and off of the power tube to realize voltage conversion; the first PWM signal is generated according to the comparison result of the feedback voltage and the step voltage of the output voltage of the DC/DC converter, and the second PWM signal is generated according to the comparison result of the feedback voltage and the reference voltage.
Here, the feedback voltage is compared with a voltage, so that a specific circuit for generating the PWM signal according to the comparison result can refer to an existing DC/DC converter, and the embodiments of the present invention are not described herein again.
As can be seen from the soft start cycle time control circuit shown in fig. 3, in the soft start cycle time control circuit, the clock signal generating circuit generates the first clock signal; the clock period expansion circuit expands the period of the first clock signal to obtain a second clock signal, so that the time length of which the signal level is high is the soft start time of the DC/DC converter, and the soft start circuit is caused to continuously output a fixed voltage in T; the step voltage generating circuit generates a step voltage in T according to the fixed voltage; in this way, when the DC/DC converter is in soft start, the step voltage is compared with the feedback voltage of the output voltage of the DC/DC converter, and the first PWM signal is generated according to the comparison result to control the on and off of the power tube, so that an effective and stable soft start process is realized. And, after the soft start, the DC/DC converter uses the second PWM signal to perform normal operation irrespective of the output of the soft start cycle time control circuit, so that the voltage switching process is stable after the soft start is finished. In addition, the soft start cycle time control circuit provided by the embodiment of the invention is not dependent on large capacitance implementation, so that the soft start cycle time control circuit is easy to integrate.
In one embodiment, as shown in fig. 4 (a), the clock signal generating circuit may include: PMOS tube P 1 PMOS tube P 2 PMOS tube P 3 PMOS tube P 4 NMOS tube N 1 NMOS tube N 2 Capacitance C 1 Inverter INV 1 Inverter INV 2 ；
Wherein, PMOS tube P 1 Source stage of (P) PMOS tube P 2 Source stage of (d) and PMOS transistor P 3 The source stages of (a) are connected with the power supply voltage V CC The method comprises the steps of carrying out a first treatment on the surface of the PMOS tube P 1 The grid electrode and the drain electrode of the transistor are connected with the PMOS tube P 2 A gate electrode of (a); PMOS tube P 1 The drain electrode of the transistor is connected with bias current; PMOS tube P 2 The drain electrode of (C) is connected with the PMOS tube P 4 Is a source of (1); PMOS tube P 4 Gate and NMOS transistor N of (2) 1 The grid electrodes of the (C) are connected with the inverter INV 2 Output end of PMOS tube P 4 The drain electrode of (C) is connected with the PMOS tube P 3 Drain electrode of NMOS transistor N 1 Drain electrode of NMOS transistor N 2 Drain electrode of (C) and capacitor (C) 1 One end of (a) and inverter INV 1 Capacitance C at the input end of (2) 1 The other end of the first circuit is grounded to GND; inverter INV 1 The output end of the (E) is connected with the inverter INV 2 Is of the input end of NMOS tube N 2 Gate of (c) and PMOS tube P 3 A gate electrode of (a); NMOS tube N 1 Source of (N) NMOS transistor N 2 Source stage of (a) is grounded, inverter INV 2 Outputs a first clock signal CLK 1 。
In another embodiment, as shown in fig. 4 (b), the clock signal generating circuit may include: PMOS tube P 31 PMOS tube P 32 PMOS tube P 33 PMOS tube P 34 PMOS tube P 35 PMOS tube P 36 PMOS tube P 37 NMOS tube N 31 NMOS tube N 32 NMOS tube N 33 NMOS tube N 34 NMOS tube N 35 Capacitance C 31 Inverter INV 31 Inverter INV 32 ；
Wherein, PMOS tube P 31 Source stage of (P) PMOS tube P 32 Source stage of (P) PMOS tube P 33 Source stage of (d) and PMOS transistor P 34 The source stages of (a) are connected with the power supply voltage V CC The method comprises the steps of carrying out a first treatment on the surface of the PMOS tube P 31 Grid electrode, drain electrode and PMOS tube P 32 Grid electrode of PMOS tube P 33 Gate of (d) and PMOS transistor P 35 Are connected with each other; PMOS tube P 35 Grid electrode, drain electrode and PMOS tube P 36 Gate of (d) and NMOS transistor N 31 The drains of the two are connected;
NMOS tube N 31 Gate enable signal ENP 0 The enable signal ENP 0 High level is effective in soft start time; NMOS tube N 31 Is connected with the bias current; PMOS tube P 32 The drain electrode of (C) is connected with the PMOS tube P 36 Is a source of (1); PMOS tube P 36 Drain electrode of NMOS transistor N 32 Drain and gate of (a) and NMOS transistor N 33 The grid electrodes of the two are connected; PMOS tube P 33 The drain electrode of (C) is connected with the PMOS tube P 37 Is a source of (1); PMOS tube P 37 Gate and NMOS transistor N of (2) 34 The grid electrodes of the (C) are connected with the inverter INV 32 An output terminal of (a); PMOS tube P 37 Drain electrode of NMOS transistor N 34 Drain electrode of PMOS tube P 34 Drain electrode of (d) and NMOS transistor N 35 Drain electrodes of (a) are connected to the inverter INV 31 Is provided; capacitor C 31 One end of (a) is connected to the inverter INV 31 The other end of the input end is grounded; inverter INV 31 The output end of (a) is connected with the inverter INV 32 Is provided; PMOS tube P 34 Gate and NMOS transistor N of (2) 35 The grid electrodes of the (C) are connected with the inverter INV 32 Is provided; NMOS tube N 32 Source of (N) NMOS transistor N 33 Source of (2) and NMOS transistor N 35 Is grounded; NMOS tube N 33 The drain electrode of (a) is connected with NMOS tube N 34 Is a source of (1); inverter INV 32 Outputs a first clock signal CLK 1 。
In yet another embodiment, the clock signal generation circuit shown in FIG. 4 (b) may be implemented in a PMOS transistor P 33 And PMOS tube P 37 A PMOS tube is connected in series between the two transistors, and an NMOS tube N is connected in series between the two transistors 34 And NMOS tube N 33 And an NMOS tube is connected in series between the two MOS tubes, so that the driving voltage required by the circuit is reduced, the current is also reduced, the power consumption is reduced, and more applications are satisfied.
In one embodiment, the clock cycle expansion circuit may include: n cascaded T flip-flop TFFs;
wherein, the terminal structure of the T trigger is shown in fig. 5 (a); the VS end of each T trigger is connected with the power supply voltage, the CP end of the 1 st T trigger is connected with the first clock signal, and the nth= [1,2, …, N-1 ]]The QN end of each T trigger is connected with the CP end of the n+1th T trigger; the CD ends of the N T triggers are all connected with low-level enabling; q ends of the N T triggers are respectively connected to the step voltage generating circuit; the QN end of the N-th T flip-flop outputs the second clock signal CLK 2 In addition, the Q end of the N T flip-flop also outputs a third clock signal CLK 3 The third clock signal CLK 3 And a second clock signal CLK 2 Is opposite to the signal level of (a).
In another embodiment, the clock cycle expansion circuit may include: comprising the following steps: AND gate AND 1 NOR gate NOR 1 First inverter INV x Second inverter INV y N cascaded T flip-flops TFF and N-1 NAND gates in one-to-one correspondence with the first N-1T flip-flops 2 ；
In fig. 5 (b), a circuit structure of a clock period expansion circuit formed by cascading two T flip-flops is shown, and it can be understood that in practice, the number of T flip-flops is more than two, for example, 11, which are all configurable.
As shown in FIG. 5 (b), the VS end of each T flip-flop is connected to the power supply voltage, and the CP end of the 1 st T flip-flop is connected to the first clock signal CLK 1 N= [1,2, …, N-1 ]]QN end of each T trigger is connected with corresponding NAND gate NAND 2 Is a NAND gate 2 The output end of the (n+1) th T trigger is connected with the CP end of the (n+1) th T trigger; the CD ends of the N T triggers are connected with an enabling signal RSTX; the enable signal RSTX is the enable signal ENP 0 And enable signalRST is obtained by NAND operation; the enable signal RST is active high during the soft start time; in practical application, enable signal ENP 0 Enable signal ENP 1 The enabling signal RST is a digital signal under the same condition, namely, in the soft start time, when the input voltage, the enabling voltage, the internal power supply voltage and the temperature of the circuit are all in normal conditions, the three signal outputs are all in an effective high level; the Q end of the N T trigger is connected with an AND gate AND 1 The other input of the AND gate is connected with an enable signal ENP 1 The enable signal ENP 1 High level is effective in soft start time; AND gate AND 1 Is connected with the NOR gate NOR 1 Enable signal ENP 0 Through the second inverter INV y Is connected with the NOR gate NOR 1 Is not equal to the other input of the NOR gate NOR 1 Outputs a third clock signal CLK 3 The method comprises the steps of carrying out a first treatment on the surface of the QN end of the Nth T trigger passes through the first inverter INV x Outputting the second clock signal CLK 2 Third clock signal CLK 3 And a second clock signal CLK 2 Is opposite to the signal level of the third clock signal CLK 3 Connect each NAND gate NAND 2 Is provided.
In one embodiment, as shown in fig. 6, the soft start circuit includes: PMOS tube P 11 PMOS tube P 12 PMOS tube P 13 PMOS tube P 14 PMOS tube P 15 PMOS tube P 16 PMOS tube P 17 NMOS tube N 11 NMOS tube N 12 NMOS tube N 13 NMOS tube N 14 NMOS tube N 15 NMOS tube N 16 NMOS tube N 17 NMOS tube N 18 NMOS tube N 19 Resistance R 1 Resistor R 2 ；
Wherein, PMOS tube P 11 Is connected with bias current, PMOS tube P 11 The gate of (2) is connected to the second clock signal CLK 2 PMOS tube P 11 The drain electrode of (a) is connected with NMOS tube N 11 Drain electrode of NMOS tube N 11 The grid electrode of (C) is connected with NMOS tube N 11 Drain electrode of NMOS transistor N 13 Grid electrode and NMOS tube of (a)N 15 Gate and NMOS transistor N of (2) 17 A gate electrode of (a); NMOS tube N 11 Source-connected NMOS transistor N 12 Drain electrode of NMOS tube N 12 The grid electrode of (C) is connected with NMOS tube N 12 Drain electrode of NMOS transistor N 14 Gate of (2), NMOS transistor N 16 Gate and NMOS transistor N of (2) 18 A gate electrode of (a); NMOS tube N 12 Source of (N) NMOS transistor N 14 Source of (N) NMOS transistor N 16 Source of (2) and NMOS transistor N 18 Is grounded; NMOS tube N 14 The drain electrode of (a) is connected with NMOS tube N 13 Source of NMOS transistor N 13 Is connected with PMOS tube P by the drain electrode 12 A drain electrode of (2); PMOS tube P 12 Source stage of (P) PMOS tube P 13 Source stage of (P) PMOS tube P 14 Source PMOS tube P 15 Source of (d) and resistor R 1 One end of each of the resistors R is connected with a power supply voltage 1 Is connected with the other end of the NMOS tube N 19 A drain electrode of (2); PMOS tube P 12 The grid electrode of (C) is connected with the PMOS tube P 12 Drain electrode of (C) and PMOS tube P 13 A gate electrode of (a); PMOS tube P 13 The drain electrode of (C) is connected with the PMOS tube P 16 Source stage and PMOS tube P of (2) 17 Source stage of PMOS tube P 16 The grid electrode of (2) is connected with the voltage division V of the reference voltage I PMOS tube P 16 The drain electrode of (a) is connected with NMOS tube N 17 Source and NMOS transistor N 18 Drain electrode of PMOS tube P 17 The grid electrode of (C) is connected with NMOS tube N 19 Source electrode of PMOS tube P 17 The drain electrode of (a) is connected with NMOS tube N 15 Source and NMOS transistor N 16 Drain electrode of NMOS tube N 15 The drain electrode of (C) is connected with the PMOS tube P 14 Drain electrode of PMOS tube P 14 The grid electrode of (C) is connected with the PMOS tube P 14 Drain electrode of (C) and PMOS tube P 15 Grid electrode of PMOS tube P 15 The drain electrode of (a) is connected with NMOS tube N 17 Drain electrode of (d) and NMOS transistor N 19 A gate electrode of (a); NMOS tube N 19 Source pass resistance R of (2) 2 Grounded, the junction outputs a fixed voltage V 0 。
In one embodiment, the step voltage generating circuit includes: module 1-Module N, N-1 resistors R d NMOS tube N SW Resistance R e Resistance R f NMOS tube N E ；
A step voltage generation involving n=8 is shown in fig. 7A circuit; referring to fig. 7, the module 1 includes: NMOS tube N 21 Resistance R a1 Resistance R b1 Resistance R c1 NMOS tube N 31 Resistor R g The method comprises the steps of carrying out a first treatment on the surface of the Wherein, NMOS tube N 21 The drain electrode of (2) is connected with a fixed voltage V 0 The grid electrode is connected with the Q end of the 1 st T trigger in the clock period expansion circuit, and the source electrode sequentially passes through the resistor R a1 Resistance R c1 Resistor R g Grounding; resistor R b1 Is connected to resistor R a1 And resistance R c1 The other end is connected with an NMOS tube N 31 A drain electrode of (2); NMOS tube N 31 The grid electrode is connected with the QN end of the 1 st T trigger in the clock period expansion circuit; resistor R c1 And resistance R g The connecting node between the two is an output node of the module 1;
module m= [2,3, …, N]Comprising the following steps: NMOS tube N 2m Resistance R am Resistance R bm Resistance R cm NMOS tube N 3m The method comprises the steps of carrying out a first treatment on the surface of the Wherein, NMOS tube N 2m The drain electrode of (2) is connected with a fixed voltage V 0 The grid electrode is connected with the Q end of the mth T trigger in the clock period expansion circuit, and the source electrode sequentially passes through the resistor R am And resistance R cm Then the output node of the module m is used as an output node of the module m; resistor R bm Is connected to resistor R am And resistance R cm The other end is connected with an NMOS tube N 3m A drain electrode of (2); NMOS tube N 3m The grid electrode is connected with the QN end of an mth T trigger in the clock period expansion circuit;
the output node of the module 1 and the output node of the module 2, the output node of the module m and the output node of the module m+1 pass through a resistor R d Realizing connection;
NMOS tube N SW The grid electrode of the (a) is connected with the SW node voltage of the DC/DC converter, and the source electrode is connected with the output node of the module N; NMOS tube N SW The drain electrode of (a) sequentially passes through a resistor R e And resistance R f Connected to NMOS tube N E The drain electrode of (2) is connected with the output step voltage V 1 The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube N E The gate of (a) is connected with an enable signal ENN, the source is grounded, and the enable signal ENN is an enable signal ENP 0 And enable letterNumber ENP 1 And a NAND output of both; enable signal ENP 0 And enable signal ENP 1 Are active high during the soft start time.
Next, the operation principle of the soft start cycle time control circuit applied to the DC/DC converter according to the embodiment of the present invention will be described based on each circuit module shown in fig. 4 (b), 5 (b), 6 and 7, wherein the number of T flip-flops in fig. 5 (b) is set to 11, and the operation principle is described as follows:
the working principle of the embodiment 1 of the invention is as follows:
for the clock signal generation circuit shown in FIG. 4 (b), when the enable signal ENP 0 At low level, NMOS transistor N 31 Failure to conduct, the circuit fails to operate normally, and the output signal CLK is output 1 Is low. When ENP 0 At a high level, N 31 The tube is turned on and the circuit begins to operate due to CLK at the beginning 1 Is low level, so that the PMOS tube P 37 Tube conduction, NMOS tube N 4 Tube cut-off, capacitance C 31 Charging is started. At capacitor C 31 During charging, inverter INV 31 Outputting high level, at this time, PMOS tube P 34 Turn-off NMOS tube N 35 Conducting, CLK 1 Is low. When the capacitor C 31 After the charging reaches the voltage peak value, the inverter INV 31 The output of the PMOS transistor P is turned to low level 34 Conduction NMOS tube N 35 Turn off and CLK 1 The signal level of (2) is also inverted to high level, NMOS tube N 34 Conduction and capacitance C 31 Start to discharge when discharging to capacitor C 31 Inverter INV when the voltage between both ends is 0 31 The output of (2) is toggled high again to continue the next cycle to form a fixed periodic signal CLK 1 。
The capacitance charging formula can be obtained according to the following formula:
wherein V is C The voltage peak value for charging the capacitor, C is the capacitance value of the capacitor, I is the charging current value, t c The time required to fill the capacitor.
Based on the capacitance charging formula, the capacitance C can be changed in the embodiment of the invention 31 Flexibly adjusting the capacitance value of the first clock signal CLK 1 Thereby flexibly adjusting the soft start time.
For a clock cycle spread circuit including 11T flip-flops, due to the enable signal RST and the enable signal ENP 0 The enable signal RSTX obtained after the nand operation is opposite to the signal level of the enable signal RST, and thus RSTX is a low level signal. The T flip-flop acts as a doubling of the cycle time. A periodic signal CLK formed by a clock signal generating circuit 1 After doubling of 11T triggers, CLK is obtained after inverting the QN end of the 11 th T trigger 2 Cycle times CLK 1 Cycle time 2 11 Multiple, i.e., 2048. The Q-terminal output of 11 th and last T flip-flop is enabled to signal ENP 1 After AND operation, the operation result is summed with ENP 0 The signal obtained through the first inverter is passed through a NOR gate to obtain an output CLK 3 Due to CLK 3 Q from the last T flip-flop, thus CLK 3 Is also CLK 1 2048 times the cycle time. Due to CLK 2 Is twice the soft start time, so only by modifying CLK 1 The soft start time can be adjusted by the cycle time of (a), and the soft start time T is:
therefore, in the embodiment of the invention, the soft start time can be flexibly adjusted by modifying the number of the T triggers, and the corresponding NMOS tube number in the step voltage generating circuit is also required to be correspondingly adjusted. When the soft start is finished, enable signal ENP 0 To a low level at which time the clock cycle extension circuit stops operating.
For the soft start circuit shown in FIG. 6, whenCLK 2 At low level, the circuit starts to operate, I 0 Through PMOS tube P 11 Is input into a circuit and passes through an NMOS tube N 11 Mirror image to NMOS tube N 13 The branch is then passed through PMOS tube P 12 Mirror image to PMOS tube P 13 At this time, PMOS tube P 13 As PMOS tube P 16 And PMOS tube P 17 Tail current source of V I Is from reference voltage V BG The voltage obtained by voltage division has higher voltage stability; PMOS tube P 14 PMOS tube P 15 PMOS tube P 16 PMOS tube P 17 NMOS tube N 15 NMOS tube N 16 NMOS tube N 17 NMOS tube N 18 NMOS tube N 19 Forms a folding type cascade operational amplifier which can lead the fixed voltage V output by the soft start circuit 0 And voltage V I Equality to form a fixed voltage V 0 Input to the step voltage generating circuit.
For the step voltage generating circuit shown in FIG. 7, which is an 8-bit resistor-divider DAC circuit, and the input signal is 8 multiple frequency signals generated by 8T flip-flops, the Q is output when the Q terminals of the 8T flip-flops<1:8>When the voltage is at a low level, the output of the step voltage generating circuit is 0; when Q is<1:8>At high level, the output of the step voltage generating circuit is V 0 The method comprises the steps of carrying out a first treatment on the surface of the When the Q end output Q1 of the 1 st T trigger is high, the NMOS transistor N 21 Conduction NMOS tube N 31 Turn off, let the circuit divide R g 、R e 、R f All resistors except the resistor have the resistance of R g The resistance value at the left end of the A point is R, which is obtained by the method of (2R) a1 R of the connection d The series connection is a resistor 2R, and then is connected with the resistor R a2 +R c2 The parallel resistance value is R, and the voltage is output at the point B in a circulating way, so that the voltage at the point B is stepped up, and the voltage amplitude V of each stepped up can be calculated ref The method comprises the following steps:
due to NMOS tube N 21 And NMOS tube N 31 Correspondingly input opposite signals, so when the NMOS tube N 21 When turned off, NMOS tube N 31 On, at this time R b1 Instead of R a1 And carrying out resistor voltage division, and completing the whole voltage step-up process with the same subsequent structure. When the SW node voltage is high, ENN is the enable signal ENP 0 And enable signal ENP 1 And the NAND outputs of the two, so ENN is low level, the right end circuit of the point B is conducted, and the stepped voltage is output outwards. When the soft start process is finished, enable signal ENP 0 And enable signal ENP 1 All become low level, the corresponding ENN terminal becomes high level, NMOS tube N E Conducting, thereby V 1 The output is 0.
The key control signal waveforms for the circuitry used in the description of the principles of operation described above are shown in fig. 8.
In practical application, the more the number of steps is, the slower the voltage rising speed is, and the better the soft start effect is, but the occupied area of the circuit is increased, so the number of steps when the voltage rising is set by comprehensively considering the relation between the two steps when the voltage rising is designed.
In summary, the soft start cycle time control circuit applied to the DC/DC converter provided by the embodiment of the invention has the characteristics of simple structure, easiness in integration, arbitrary adjustment of the soft start cycle time and stable switching process after the soft start is finished.
It should be noted that the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the disclosed embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects of the present disclosure.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings and the disclosure. In the description of the present application, the word "comprising" does not exclude other elements or steps, the "a" or "an" does not exclude a plurality, and the "a" or "an" means two or more, unless specifically defined otherwise. Moreover, some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.
The foregoing is a further detailed description of the application in connection with the preferred embodiments, and it is not intended that the application be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.

Claims (7)

1. A soft start cycle time control circuit for a DC/DC converter, comprising: a clock signal generating circuit, a clock period expanding circuit, a soft start circuit and a step voltage generating circuit;
The clock signal generation circuit is used for generating a first clock signal;
the clock period expanding circuit is used for expanding the period of the first clock signal to obtain a second clock signal; the time length of the signal level of the second clock signal in the clock period is T, and T is equal to the soft start time of the DC/DC converter;
the soft start circuit is electrically connected with the clock period expansion circuit and is used for continuously outputting a fixed voltage in T;
the step voltage generation circuit is used for generating a step voltage in T according to the fixed voltage;
in the soft start time, the DC/DC converter responds to a first PWM signal to control the on and off of a power tube of the DC/DC converter to realize soft start; after the soft start time, the DC/DC converter responds to a second PWM signal to control the on and off of a power tube of the DC/DC converter to realize voltage conversion; the first PWM signal is generated according to a comparison result of the feedback voltage of the output voltage of the DC/DC converter and the step voltage, and the second PWM signal is generated according to a comparison result of the feedback voltage and a reference voltage.
2. The soft start cycle time control circuit for a DC/DC converter according to claim 1, wherein the clock signal generating circuit comprises: PMOS tube P 1 PMOS tube P 2 PMOS tube P 3 PMOS tube P 4 NMOS tube N 1 NMOS tube N 2 Capacitance C 1 Inverter INV 1 Inverter INV 2 ；
Wherein, PMOS tube P 1 Source stage of (P) PMOS tube P 2 Source stage of (d) and PMOS transistor P 3 The source stages of the voltage transformer are connected with the power supply voltage; PMOS tube P 1 The grid electrode and the drain electrode of the transistor are connected with the PMOS tube P 2 A gate electrode of (a); PMOS tube P 1 The drain electrode of the transistor is connected with bias current; PMOS tube P 2 The drain electrode of (C) is connected with the PMOS tube P 4 Is a source of (1); PMOS tube P 4 Gate and NMOS transistor N of (2) 1 The grid electrodes of the (C) are connected with the inverter INV 2 Output end of PMOS tube P 4 The drain electrode of (C) is connected with the PMOS tube P 3 Drain electrode of NMOS transistor N 1 Drain electrode of NMOS transistor N 2 Drain electrode of (C) and capacitor (C) 1 One end of (a) and inverter INV 1 Capacitance C at the input end of (2) 1 The other end of the first electrode is grounded; inverter INV 1 The output end of the (E) is connected with the inverter INV 2 Is of the input end of NMOS tube N 2 Gate of (c) and PMOS tube P 3 A gate electrode of (a); NMOS tube N 1 Source of (N) NMOS transistor N 2 Source stage of (a) is grounded, inverter INV 2 Outputs the first clock signal.
3. The soft start cycle time control circuit for a DC/DC converter according to claim 1, wherein the clock signal generating circuit comprises: PMOS tube P 31 PMOS tube P 32 PMOS tube P 33 PMOS tube P 34 PMOS tube P 35 PMOS tube P 36 PMOS tube P 37 NMOS tube N 31 NMOS tube N 32 NMOS tube N 33 NMOS tube N 34 NMOS tube N 35 Capacitance C 31 Inverter INV 31 Inverter INV 32 ；
Wherein, PMOS tube P 31 Source stage of (P) PMOS tube P 32 Source stage of (P) PMOS tube P 33 Source stage of (d) and PMOS transistor P 34 The source stages of the voltage transformer are connected with the power supply voltage; PMOS tube P 31 Grid electrode, drain electrode and PMOS tube P 32 Grid electrode of PMOS tube P 33 Gate of (d) and PMOS transistor P 35 Are connected with each other; PMOS tube P 35 Grid electrode, drain electrode and PMOS tube P 36 Gate of (d) and NMOS transistor N 31 The drains of the two are connected; NMOS tube N 31 Gate enable signal ENP 0 The enable signal ENP 0 High level is effective in the soft start time; NMOS tube N 31 Is connected with the bias current; PMOS tube P 32 The drain electrode of (C) is connected with the PMOS tube P 36 Is a source of (1); PMOS tube P 36 Drain electrode of NMOS transistor N 32 Drain and gate of (a) and NMOS transistor N 33 The grid electrodes of the two are connected; PMOS tube P 33 The drain electrode of (C) is connected with the PMOS tube P 37 Is a source of (1); PMOS tube P 37 Gate and NMOS transistor N of (2) 34 The grid electrodes of the (C) are connected with the inverter INV 32 An output terminal of (a); PMOS tube P 37 Drain electrode of NMOS transistor N 34 Drain electrode of PMOS tube P 34 Drain electrode of (d) and NMOS transistor N 35 Drain electrodes of (a) are connected to the inverter INV 31 Is provided; capacitor C 31 One end of (a) is connected to the inverter INV 31 The other end of the input end is grounded; inverter INV 31 The output end of (a) is connected with the inverter INV 32 Is provided; PMOS tube P 34 Gate and NMOS transistor N of (2) 35 The grid electrodes of the (C) are connected with the inverter INV 32 Is provided; NMOS tube N 32 Source of (N) NMOS transistor N 33 Source of (2) and NMOS transistor N 35 Is grounded; NMOS tube N 33 The drain electrode of (a) is connected with NMOS tube N 34 Is a source of (1); inverter INV 32 Outputs the first clock signal.
4. The soft start cycle time control circuit for a DC/DC converter of claim 1, wherein the clock cycle expansion circuit comprises: n cascaded T flip-flops;
the VS end of each T trigger is connected with a power supply voltage, the CP end of the 1 st T trigger is connected with the first clock signal, and the QN end of the n= [1,2, …, N-1] T trigger is connected with the CP end of the n+1th T trigger; the CD ends of the N T triggers are all connected with low level; and the QN end of the Nth T trigger outputs the second clock signal.
5. A soft start cycle time control circuit for a DC/DC converter according to claim 3, wherein the clock cycle expansion circuit comprises: the system comprises an AND gate, a NOR gate, a first inverter, a second inverter, N cascaded T flip-flops and N-1 NAND gates, wherein the N-1 NAND gates are in one-to-one correspondence with the first N-1T flip-flops;
wherein the VS end of each T trigger is connected with the power supply voltage, the CP end of the 1 st T trigger is connected with the first clock signal, and the nth= [1,2, …, N-1] ]The QN ends of the T triggers are connected with the first input ends of the corresponding NAND gates, and the output ends of the NAND gates are connected with the CP ends of the n+1th T triggers; the CD ends of the N T triggers are connected with an enabling signal RSTX; the enable signal RSTX is the enable signal ENP 0 And enable signal RST is obtained by NAND operationThe method comprises the steps of carrying out a first treatment on the surface of the The enable signal RST is active high in the soft start time; the Q end of the N T trigger is connected with one input end of the AND gate, and the other input end of the AND gate is connected with an enable signal ENP 1 The enable signal ENP 1 High level is effective in the soft start time; the output end of the AND gate is connected with one input end of the NOR gate, and the enable signal ENP 0 The second inverter is connected with the other input end of the NOR gate, and the output end of the NOR gate outputs a third clock signal; the QN end of the Nth T trigger outputs the second clock signal through the first phase inverter, and the signal level of the third clock signal is opposite to that of the second clock signal; the third clock signal is connected to the second input of each NAND gate.
6. The soft start cycle time control circuit for a DC/DC converter of claim 4 or 5, wherein the soft start circuit comprises: PMOS tube P 11 PMOS tube P 12 PMOS tube P 13 PMOS tube P 14 PMOS tube P 15 PMOS tube P 16 PMOS tube P 17 NMOS tube N 11 NMOS tube N 12 NMOS tube N 13 NMOS tube N 14 NMOS tube N 15 NMOS tube N 16 NMOS tube N 17 NMOS tube N 18 NMOS tube N 19 Resistance R 1 Resistor R 2 ；
Wherein, PMOS tube P 11 Is connected with bias current, PMOS tube P 11 The grid electrode of the PMOS tube P is connected with the second clock signal 11 The drain electrode of (a) is connected with NMOS tube N 11 Drain electrode of NMOS tube N 11 The grid electrode of (C) is connected with NMOS tube N 11 Drain electrode of NMOS transistor N 13 Gate of (2), NMOS transistor N 15 Gate and NMOS transistor N of (2) 17 A gate electrode of (a); NMOS tube N 11 Source-connected NMOS transistor N 12 Drain electrode of NMOS tube N 12 The grid electrode of (C) is connected with NMOS tube N 12 Drain electrode of NMOS transistor N 14 Gate of (2), NMOS transistor N 16 Gate and NMOS transistor N of (2) 18 A gate electrode of (a); NMOS tube N 12 Source of (N) NMOS transistor N 14 Is a source of (a)Stage NMOS tube N 16 Source of (2) and NMOS transistor N 18 Is grounded; NMOS tube N 14 The drain electrode of (a) is connected with NMOS tube N 13 Source of NMOS transistor N 13 Is connected with PMOS tube P by the drain electrode 12 A drain electrode of (2); PMOS tube P 12 Source stage of (P) PMOS tube P 13 Source stage of (P) PMOS tube P 14 Source PMOS tube P 15 Source of (d) and resistor R 1 One end of each of the resistors R is connected with a power supply voltage 1 Is connected with the other end of the NMOS tube N 19 A drain electrode of (2); PMOS tube P 12 The grid electrode of (C) is connected with the PMOS tube P 12 Drain electrode of (C) and PMOS tube P 13 A gate electrode of (a); PMOS tube P 13 The drain electrode of (C) is connected with the PMOS tube P 16 Source stage and PMOS tube P of (2) 17 Source stage of PMOS tube P 16 The grid electrode of the PMOS tube is connected with the voltage division of the reference voltage 16 The drain electrode of (a) is connected with NMOS tube N 17 Source and NMOS transistor N 18 Drain electrode of PMOS tube P 17 The grid electrode of (C) is connected with NMOS tube N 19 Source electrode of PMOS tube P 17 The drain electrode of (a) is connected with NMOS tube N 15 Source and NMOS transistor N 16 Drain electrode of NMOS tube N 15 The drain electrode of (C) is connected with the PMOS tube P 14 Drain electrode of PMOS tube P 14 The grid electrode of (C) is connected with the PMOS tube P 14 Drain electrode of (C) and PMOS tube P 15 Grid electrode of PMOS tube P 15 The drain electrode of (a) is connected with NMOS tube N 17 Drain electrode of (d) and NMOS transistor N 19 A gate electrode of (a); NMOS tube N 19 Source pass resistance R of (2) 2 And the connection part is grounded and outputs the fixed voltage.
7. The soft start cycle time control circuit for a DC/DC converter according to claim 1, wherein the step voltage generating circuit comprises: module 1-Module N, N-1 resistors R d NMOS tube N SW Resistance R e Resistance R f NMOS tube N E ；
The module 1 comprises: NMOS tube N 21 Resistance R a1 Resistance R b1 Resistance R c1 NMOS tube N 31 Resistor R g The method comprises the steps of carrying out a first treatment on the surface of the Wherein, NMOS tube N 21 The drain electrode of the (B) is connected with the fixed voltage, the grid electrode is connected with Q of the 1 st T trigger in the clock period expanding circuitThe source electrode sequentially passes through the resistor R a1 Resistance R c1 Resistor R g Grounding; resistor R b1 Is connected to resistor R a1 And resistance R c1 The other end is connected with an NMOS tube N 31 A drain electrode of (2); NMOS tube N 31 The grid electrode is connected with the QN end of the 1 st T trigger in the clock period expansion circuit; resistor R c1 And resistance R g The connecting node between the two is an output node of the module 1;
module m= [2,3, …, N]Comprising the following steps: NMOS tube N 2m Resistance R am Resistance R bm Resistance R cm NMOS tube N 3m The method comprises the steps of carrying out a first treatment on the surface of the Wherein, NMOS tube N 2m The drain electrode of the (E) is connected with the fixed voltage, the grid electrode is connected with the Q end of the mth T trigger in the clock period expansion circuit, and the source electrode sequentially passes through a resistor R am And resistance R cm Then the output node of the module m is used as an output node of the module m; resistor R bm Is connected to resistor R am And resistance R cm The other end is connected with an NMOS tube N 3m A drain electrode of (2); NMOS tube N 3m The grid electrode is connected with the QN end of an mth T trigger in the clock period expansion circuit;
the output node of the module 1 and the output node of the module 2, the output node of the module m and the output node of the module m+1 pass through a resistor R d Realizing connection;
NMOS tube N SW The grid electrode of the source electrode is connected with the SW node voltage of the DC/DC converter, and the source electrode is connected with the output node of the module N; NMOS tube N SW The drain electrode of (a) sequentially passes through a resistor R e And resistance R f Connected to NMOS tube N E The step voltage is output from the junction of the drain electrode of the transistor; NMOS tube N E The gate of (a) is connected with an enable signal ENN, the source is grounded, and the enable signal ENN is an enable signal ENP 0 And enable signal ENP 1 And a NAND output of both; enable signal ENP 0 And enable signal ENP 1 Are active high during the soft start time.
CN202310980845.0A 2023-08-04 2023-08-04 Soft start cycle time control circuit applied to DC/DC converter Pending CN117118217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310980845.0A CN117118217A (en) 2023-08-04 2023-08-04 Soft start cycle time control circuit applied to DC/DC converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310980845.0A CN117118217A (en) 2023-08-04 2023-08-04 Soft start cycle time control circuit applied to DC/DC converter

Publications (1)

Publication Number Publication Date
CN117118217A true CN117118217A (en) 2023-11-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310980845.0A Pending CN117118217A (en) 2023-08-04 2023-08-04 Soft start cycle time control circuit applied to DC/DC converter

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