CN117116181A - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN117116181A
CN117116181A CN202311076298.XA CN202311076298A CN117116181A CN 117116181 A CN117116181 A CN 117116181A CN 202311076298 A CN202311076298 A CN 202311076298A CN 117116181 A CN117116181 A CN 117116181A
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CN
China
Prior art keywords
line
data line
display panel
data
load compensation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311076298.XA
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Chinese (zh)
Inventor
李曼曼
陈方
杨萌
那璇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Priority to CN202311076298.XA priority Critical patent/CN117116181A/en
Publication of CN117116181A publication Critical patent/CN117116181A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Abstract

The invention discloses a display panel and a display device, the display panel includes: the array arrangement comprises sub-pixels and a plurality of data lines; the plurality of data lines includes a first data line and a second data line; the load on the first data line is greater than the load on the second data line; the load compensation line is positioned in the display area of the display panel, the first end of the load compensation line is connected with one end of the corresponding second data line, and the load compensation line is used for compensating the load of the second data line connected with the load compensation line so that the difference value between the total load of the second data line and the total load of the first data line is smaller than a preset value. The invention reduces the frame width of the display panel while meeting the requirement of matching the loads on different data lines.

Description

Display panel and display device
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of display technology, people have increasingly high requirements on a comprehensive display screen.
When the conventional organic light emitting display panel displays a picture, a corresponding data voltage needs to be provided to each sub-pixel through a data line. For data lines of different lengths, the loads on the data lines are different; the load of the data lines needs to be compensated, and the requirements of matching the loads on different data lines are met.
However, the load of the data line is usually compensated in the frame area of the display panel in the prior art, which is not beneficial to the development requirement of the narrow frame of the display panel.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for reducing the frame width of the display panel while meeting the requirement of matching the total loads on different data lines.
According to an aspect of the present invention, there is provided a display panel including:
the array arrangement comprises sub-pixels and a plurality of data lines; each data line is connected with a corresponding sub-pixel; wherein the plurality of data lines includes at least one first data line and at least one second data line; the load of the first data line is greater than the load of the second data line;
at least one load compensation line located in a display area of the display panel; the first end of the load compensation line is connected with one end of a corresponding second data line, and the load compensation line is used for compensating the load of the second data line connected with the load compensation line so that the difference value between the total load of the second data line and the total load of the first data line is smaller than a preset value.
Optionally, the length of at least one of the load compensation lines is smaller than the length of a second data line connected to the load compensation line;
optionally, the display panel further includes:
at least one functional auxiliary line arranged in the same layer as the load compensation line; each functional auxiliary line is correspondingly arranged on an extension line with the length smaller than that of the load compensation line; the functional auxiliary line is electrically isolated from the corresponding load compensation line; the function auxiliary line is used for being connected with a function signal line in the display panel so as to reduce the voltage drop on the function signal line;
preferably, the length of the second data line connected to the load compensation line is equal to the sum of the length of the load compensation line, the length of the functional auxiliary line on the extension line of the load compensation line, and the distance therebetween.
Optionally, the functional auxiliary line is connected with a power signal line in the display panel through a through hole;
alternatively, the function auxiliary line is connected to an initialization signal line in the display panel through a via hole.
Optionally, the subpixels are uniformly spaced in the column direction; the length of the second data line is smaller than that of the first data line;
the difference value between the total resistance of the line resistance of the second data line and the line resistance of the load compensation line connected with the second data line and the line resistance of the first data line is smaller than a first preset value;
and the sum of the parasitic capacitance formed by the second data line and the parasitic compensation capacitance formed by the load compensation line connected with the second data line is smaller than a second preset value.
Optionally, the first end of each load compensation line is connected with the corresponding second data line in the frame area of the display panel;
optionally, the first end of each load compensation line is connected to the corresponding second data line in the top frame region of the display panel, or the first end of each load compensation line is connected to the corresponding second data line in the bottom frame region of the display panel.
Optionally, the at least one second data line includes a plurality of second data lines;
at least part of the second data lines have different lengths, and the lengths of the load compensation lines connected to the second data lines having different lengths are different.
Optionally, a plurality of the second data lines are distributed on two sides of the at least one first data line; and the length of the second data line gradually decreases and the length of the load compensation line gradually increases along a direction away from the at least one first data line;
preferably, the shape of the display area of the display panel includes a circle, an ellipse, or a racetrack shape.
Optionally, the display panel includes:
the light-emitting device comprises a substrate, a driving circuit layer arranged on the substrate and a light-emitting structure layer arranged on one side of the driving circuit layer away from the substrate; the driving circuit layer comprises pixel driving units and a plurality of data lines which are arranged in an array manner; the light emitting structure layer includes a plurality of light emitting structures; each pixel driving unit and a corresponding light-emitting structure are used for forming one sub-pixel;
each data line is connected with a corresponding column of pixel driving units, and each data line is used for forming parasitic capacitance with a first electrode plate of a storage capacitor in the corresponding connected column of pixel driving units;
each load compensation line and a first electrode plate of a storage capacitor in at least one pixel driving unit form a parasitic compensation capacitor;
preferably, the load compensation line and the data line are arranged in the same layer; the metal layer where the first electrode plate is located at one side, close to the substrate, of the metal layer where the data line is located.
Optionally, the driving circuit layer further includes a plurality of power signal lines, each power signal line being connected to a corresponding sub-pixel;
at least part of interval sections of each power signal line and the first electrode plate are arranged on the same layer; each load compensation line forms the parasitic compensation capacitance with a first electrode plate of a storage capacitor in at least one pixel driving unit and the power signal line arranged on the same layer with the first electrode plate.
According to another aspect of the present invention, there is provided a display device including: the display panel of any embodiment of the present invention.
According to the technical scheme provided by the embodiment of the invention, the load compensation line is arranged in the display area of the display panel; one end of the load compensation line is connected with one end of the corresponding second data line, wherein the load compensation line is connected with the second data line, so that the line resistance of the second data line can be compensated, and the load compensation line can form parasitic compensation capacitance with an original conductive film layer in the display panel in the extending process; and enabling the difference value between the total load of the second data line and the total load of the first data line to be smaller than a preset value, so that the total load of the second data line is matched with the total load of the first data line. The load compensation line is arranged in the display area of the display panel, and the frame area of the display panel can be not occupied, so that the frame width of the display panel is reduced while the total load on different data lines is matched, and the development of a narrow frame of the display panel is facilitated.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a connection between a second data line and a load compensation line according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the structure of the driving circuit unit in the region 1 in the structure shown in FIG. 1;
fig. 4 is a schematic layout diagram of a load compensation line and a functional auxiliary line according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a driving circuit unit in a region 2 of the structure shown in FIG. 1;
FIG. 6 is a schematic diagram of another driving circuit unit in the region 2 of the structure shown in FIG. 1;
fig. 7 is a circuit diagram of a driving circuit unit according to an embodiment of the present invention;
FIG. 8 is a schematic structural view of the active structure in region 1 or region 2 of FIG. 1;
FIG. 9 is a schematic view of the structure of the active structure and the first metal layer in region 1 or region 2 of FIG. 1;
FIG. 10 is a schematic view of the structure of the active structure, the first metal layer and the second metal layer in region 1 or region 2 of FIG. 1;
fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
In order to meet the higher and higher experience demands of consumers on electronic products, the display device adopts an organic light-emitting comprehensive display screen with higher screen occupation ratio. In the conventional organic light emitting display panel, a plurality of sub-pixels and a plurality of data lines are included; each data line is connected with a corresponding sub-pixel. When the picture is displayed, the corresponding data voltage is required to be provided for each sub-pixel so as to realize the display of different gray scales. The load of the data line is related to the line resistance of the data line itself and the parasitic capacitance generated by the data line and other metal films (i.e., conductive films). Similarly, the line load is also related to the resistance of the line and the parasitic capacitance generated by the line and the conductive film layer.
The data lines extend along the column direction, and in the extending process, overlapping areas exist between the data lines and the conductive film layers in the display panel, so that parasitic capacitances of the data lines are formed. For non-rectangular displays such as circular, oval or racetrack screens, which have arcuate areas, the data lines have different lengths. For the data lines with different lengths, the area of the overlapping area formed by the data line with longer length and the conductive film layer in the display panel in the extending process is larger, the parasitic capacitance formed by the data line with shorter length is larger, the area of the overlapping area formed by the data line with shorter length and the conductive film layer in the display panel in the extending process is smaller, and the parasitic capacitance formed by the data line with longer length and the conductive film layer in the display panel is smaller. And, the data line of different length, the line resistance of the longer data line of length is great, and the line resistance of the shorter data line of length is less.
In other words, the data lines of different lengths have a longer load than the shorter data lines. The different loads of the data lines may cause different charging capacities and/or voltage drops of the data lines to data voltages, so that when the same data voltages are provided, the data voltages obtained on the data lines with different lengths are different, and the brightness of the sub-pixels on the data lines with different lengths is different. To ensure that the load on all data lines is the same or less different, the less loaded data lines are typically compensated. At present, a load compensation capacitor of a data line is generally arranged in a frame area of a display panel, so that the space required by the load compensation capacitor is large, and the development of a narrow frame of the display panel is not facilitated.
In view of this, an embodiment of the present invention provides a display panel, fig. 1 is a schematic structural diagram of the display panel provided by the embodiment of the present invention, fig. 2 is a schematic connecting diagram of a second data line and a load compensation line provided by the embodiment of the present invention, and referring to fig. 1 and 2, the display panel includes:
the array arrangement comprises sub-pixels and a plurality of data lines; each data line is connected with a corresponding sub-pixel; wherein the plurality of data lines includes at least one first data line 10 and at least one second data line 20; the load of the first data line 10 is greater than the load of the second data line 20;
at least one load compensation line 30 located in a display area of the display panel; the first end of the load compensation line 30 is connected to one end of a corresponding second data line 20, and the load compensation line 30 is used for compensating the load of the second data line 20 connected to the load compensation line 30, so that the difference between the total load of the second data line 20 and the total load of the first data line 10 is smaller than a preset value. It should be noted that the total load of the second data line 20 includes the load of the second data line 20, and the load of the load compensation line 30; since the first data line 10 is not additionally provided with the compensation line, the total load of the first data line 10 is equal to the load of the first data line 10.
Specifically, the display panel includes a display area and a non-display area. Wherein the non-display area includes the scan driver 100 and the light emitting driver 200, the data driver 300, the timing controller 400, and the like as shown in fig. 1. The display area comprises an array substrate and a light-emitting structure layer arranged on the array substrate. The array substrate is a film layer structure capable of providing driving signals for the display panel and playing roles of buffering, protecting or supporting, and the like, and comprises a substrate and a driving circuit layer arranged on the substrate. The driving circuit layer includes a plurality of driving circuit units, a plurality of data lines (D1 to Dn), a plurality of scan lines (S1 to Sm), a plurality of light emission control signal lines (E1 to Eo), and a plurality of power supply wirings. The data driver 300 is connected to a plurality of data lines (D1 to Dn), the scan driver 100 is connected to a plurality of scan lines (S1 to Sm), and the light emission driver 200 is connected to a plurality of light emission control signal lines (E1 to Eo).
The light emitting structure layer includes a plurality of light emitting structures, the driving circuit unit and the light emitting structure connected to the driving circuit unit constitute one sub-pixel, and the display area may include a plurality of sub-pixels Pxij, i and j may be natural numbers other than zero. The driving circuit unit may include at least a pixel driving circuit connected to the scan line, the light emission control signal line, and the data line, respectively. The data line is configured to supply a data signal to the pixel driving circuit, the scanning line is configured to supply a scanning signal to the pixel driving circuit, and the light emission control signal line is configured to supply a light emission control signal to the pixel driving circuit, thereby realizing light emission control of the light emission structure.
The timing controller 400 may provide gray values and control signals suitable for the specification of the data driver 300 to the data driver 300, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver 100 to the scan driver 100, may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver 200 to the light emitting driver 200. The data driver 300 may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray values and the control signals received from the timing controller 400. For example, the data driver 300 may sample the gray value with a clock signal and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, and n may be a natural number other than zero. The scan driver 100 may generate the scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller 400, and m may be a natural number other than zero. The light emission driver 200 may generate the light emission control signals to be supplied to the light emission control signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, a emission stop signal, and the like from the timing controller, and o may be a natural number other than zero.
Wherein the plurality of data lines includes at least one first data line 10 and at least one second data line 20 as shown in fig. 2. The load of the first data line 10 is greater than the load of the second data line 20. That is, the area of the overlapping region formed by the first data line 10 and the conductive film layer in the display panel during the extension is larger than the area of the overlapping region formed by the second data line 20 and the conductive film layer in the display panel during the extension, and/or the line resistance of the first data line 10 is larger than the line resistance of the second data line 20. The first data line 10 may be understood as the most loaded data line in the display panel. The reason why the area of the overlapping region formed by the first data line 10 and the conductive film layer in the display panel in the extending process is larger than the area of the overlapping region formed by the second data line 20 and the conductive film layer in the display panel in the extending process at least includes that the number of sub-pixels connected to the first data line 10 is larger than the number of sub-pixels connected to the second data line 20, so that the number of driving circuit units through which the first data line 10 passes is larger than the number of driving circuit units through which the second data line 20 passes. The reason why the line resistance of the first data line 10 is greater than that of the second data line 20 includes at least that the length of the first data line 10 is greater than that of the second data line.
A load compensation line 30 is provided in the display area of the display panel. One end of the load compensation line 30 is connected to one end of a corresponding second data line 20. Each of the second data lines 20 may be connected to one load compensation line 30 or may be connected to a plurality of load compensation lines 30. However, it should be noted that, when one load compensation line 30 is correspondingly connected to one second data line 20, the data voltages on the plurality of second data lines 20 are prevented from interfering with each other when one load compensation line 30 is connected to the plurality of second data lines 20. When the second data lines 20 are connected to the plurality of load compensation lines 30, one load compensation line 30 is correspondingly connected to one second data line 20, so that the data voltages on the plurality of second data lines 20 are prevented from interfering with each other when one load compensation line 30 is connected to the plurality of second data lines 20.
The second data line 20 is connected in series with the load compensation line 30, and the line resistance of the second data line 20 can be compensated, thereby realizing the compensation of the load of the second data line 20. In addition, fig. 3 is a schematic structural diagram of the driving circuit unit in the region 1 in the structure shown in fig. 1, and referring to fig. 3 and 1, the load compensation line 30 may form a parasitic compensation capacitor C3 with the original conductive film layer in the display panel during the extension process. And one end of the load compensation line 30 is connected to one end of the corresponding second data line 20, so that the second data line 20 and the load compensation line 30 are connected in series, thereby increasing the parasitic capacitance formed by the second data line 20, and realizing the compensation of the parasitic capacitance formed by the second data line 20 connected with the load compensation line 30 by the parasitic compensation capacitance C3 formed by the load compensation line 30. Thereby further enabling compensation of the load of the second data line 20.
By compensating the load of the second data line 20 connected to the load compensation line 30 by the load compensation line 30, the difference between the total load of the second data line 20 and the total load of the first data line 10 is smaller than a preset value, and the magnitude of the preset value can be set according to the actual situation. It is achieved that the total load on the second data line 20 matches the total load on the first data line 10. The load compensation line 30 is additionally arranged in the original area of the display area, the load compensation line 30 can be arranged by utilizing the space of the display area, and the frame area of the display panel is not occupied, so that the development of the narrow frame of the display panel is facilitated while the matching of the total loads on the data lines with different lengths is satisfied.
The load compensation line 30 and the second data line 20 may be disposed in the same layer or may be disposed in different layers. The length of the load compensation line 30 may be smaller than the length of the second data line 20 connected to the load compensation line 30, and the length of the load compensation line 30 may be equal to the length of the second data line 20 connected to the load compensation line 30. The load compensation line 30 may be located at one side of the second data line 20 and may or may not extend along an edge of the second data line 20. The total load of the load compensation line 30 and the second data line 20 correspondingly connected with the load compensation line is satisfied, and the difference value between the total load and the total load on the first data line 10 is smaller than a preset value.
The display panel provided by the embodiment of the invention comprises sub-pixels and a plurality of data lines which are arranged in an array; each data line is connected with a corresponding sub-pixel; wherein the plurality of data lines includes at least one first data line and at least one second data line; the load of the first data line is greater than the load of the second data line; at least one load compensation line located in the display area of the display panel; the first end of the load compensation line is connected with one end of the corresponding second data line, and the load compensation line is used for compensating the load of the second data line connected with the load compensation line so that the difference value between the total load of the second data line and the total load of the first data line is smaller than a preset value. The load compensation line is arranged in the display area of the display panel and can not occupy the frame area of the display panel, so that the frame width of the display panel is reduced while the total load phase matching of different data lines is met, and the development of a narrow frame of the display panel is facilitated.
In an embodiment of the present invention, fig. 4 is a schematic layout diagram of a load compensation line and a functional auxiliary line according to an embodiment of the present invention, and referring to fig. 4, at least one load compensation line 30 has a length smaller than a length of a second data line connected to the load compensation line 30.
In other embodiments, the display panel further includes:
at least one function auxiliary line 40 provided in the same layer as the load compensation line 30; each function auxiliary line 40 is correspondingly arranged on an extension line of the load compensation line 30 with a length smaller than that of the second data line; the functional auxiliary line 40 is electrically isolated from the corresponding load compensation line 30; the function auxiliary line 40 is used to connect with a function signal line in the display panel to reduce a voltage drop on the function signal line.
Specifically, when the length of the load compensation line 30 is smaller than the length of the second data line connected to the load compensation line 30, the second end of the load compensation line 30 is further spaced from the frame of the display panel along the extending direction of the load compensation line 30. The conductive trace may continue to be provided in the direction of extension of the load compensation line 30 as the functional auxiliary line 40. Wherein the first end of the functional auxiliary line 40 is disconnected from the second end of the load compensation line 30 to achieve electrical isolation of the functional auxiliary line 40 from the load compensation line 30. The function auxiliary line 40 is used to connect with a function signal line in the display panel, and reduces the resistance of the function signal line, so that the voltage drop on the function signal line can be reduced. The load compensation line 30 and the function auxiliary line 40 are arranged in the same layer, so that the load compensation line 30 and the function auxiliary line 40 are formed in the same manufacturing process, and the manufacturing process of the display panel is simplified.
In the process of preparing the load compensation line 30 and the functional auxiliary line 40, a metal trace extending along the second data line may be disposed on one side of the second data line, and the metal trace may be disposed on the same layer as the second data line 20 or may be disposed on a different layer. The metal wiring is divided into a first connecting section and a second connecting section in an etching mode, and the first connecting section and the second connecting section are electrically isolated. The first connection section is used as a load compensation line 30 and the second connection section is used as a functional auxiliary line 40 located on the extension line of the load compensation line 30. One end of the first connecting section is connected with one end of the corresponding second data line and extends along part of the length of the second data line, and the first connecting section is used for forming parasitic compensation capacitance with the conductive film layer in the driving circuit of at least one sub-pixel. The second connection section extends along another part of the length of the second data line, and is connected with a functional signal line in the display panel to reduce the voltage drop on the functional signal line.
In addition, the load compensation line 30 is disposed in the same layer as the second data line, and the second data line, the load compensation line 30, and the function auxiliary line 40 may be formed in the same manufacturing process. Thereby further simplifying the manufacturing process of the display panel. Also, the second data line, the load compensation line 30, and the function auxiliary line 40 are prepared using the same metal layer in the display panel, and the thickness of the display panel can be reduced.
In one embodiment of the present invention, please continue to refer to fig. 4, the length of the second data line connected to the load compensation line 30 is equal to the sum of the length of the load compensation line 30, the length of the functional auxiliary line 40 located on the extension line of the load compensation line 30, and the distance between the two.
Specifically, the length of the second data line 20 connected to the load compensation line 30 is equal to the sum of the length of the load compensation line 30, the length of the functional auxiliary line 40 located on the extension line of the load compensation line 30, and the distance between the two, and the length of the metal routing used for preparing the load compensation line 30 and the functional auxiliary line 40 can be set according to the length of the second data line, so that the setting mode of the length of the metal routing is unified, and the setting mode of the length of the metal routing is simplified. The length of the load compensation line 30 is determined based on the parasitic compensation capacitance and the line resistance of the second data line corresponding to the load compensation line 30, and the remaining wires in the metal wires are used as the functional auxiliary lines 40. Therefore, the length of the second data line connected to the load compensation line 30 is set to be equal to the sum of the length of the load compensation line 30, the length of the function auxiliary line 40 located on the extension line of the load compensation line 30, and the distance between the two, so that the length of the function auxiliary line 40 can be increased by the maximum limit value while compensating the load on the second data line, thereby increasing the connectable length of the function auxiliary line 40 and the function signal line.
In one embodiment of the present invention, fig. 5 is a schematic structural view of the driving circuit unit in the region 2 in the structure shown in fig. 1, and referring to fig. 5 and 1, the function auxiliary line 40 may be connected to a power signal line (ELVDD line) in the display panel through a via B. The voltage drop on the power signal line (ELVDD line) is reduced, so that the voltage signal on the power signal line in the display panel is relatively stable, and the display effect of the display panel is improved. Alternatively, in another embodiment of the present invention, the function auxiliary line 40 may be connected to an initialization signal line (Vref line) in the display panel through the through hole A1, so as to reduce a voltage drop on the initialization signal line, so that the initialization signal on the initialization signal line in the display panel is relatively stable, and a reset function of the initialization signal line on the sub-pixel is improved, thereby improving a display effect of the display panel. The through holes A1 and B are not present at the same time, and the drawings are only for showing the positions of the through holes A1 and B for illustration. Fig. 6 is a schematic diagram of another driving circuit unit in the region 2 of the structure shown in fig. 1, and referring to fig. 6, the function auxiliary line 40 may be connected to an initialization signal line (Vref line) in the display panel through a via A2. The through hole A2 is an original through hole in the display panel, and the original through hole is utilized to connect the functional auxiliary line 40 and the initialization signal line, so that the need of newly adding the through hole is eliminated, and the modification to the structure of the display panel is reduced.
In one embodiment of the present invention, referring to fig. 1 and 2, the subpixels are uniformly spaced in the column direction; the length of the second data line 20 is smaller than the length of the first data line 10;
the difference value between the total resistance of the line resistance of the second data line and the line resistance of the load compensation line connected with the second data line and the line resistance of the first data line is smaller than a first preset value; the first preset value is set according to the actual design condition.
The sum of the parasitic capacitance load formed by the second data line and the parasitic compensation capacitance formed by the load compensation line connected with the second data line is smaller than a second preset value. The second preset value is set according to the actual design condition.
Specifically, the sub-pixels are uniformly arranged at intervals in the column direction, so that the number of the sub-pixels connected with the data line in unit length is the same, the number of the driving circuit units through which the data line passes in unit length is the same, and the parasitic capacitance formed by the data line in unit length is the same. In the manufacturing process, the widths of the data lines are generally the same, and the conductive materials are the same, that is, the widths of the first data lines 10 are the same as the widths of the second data lines 20, the materials of the first data lines 10 are the same as the materials of the second data lines 20, and the line resistances of the data lines per unit length are the same. Since the length of the first data line 10 is greater than the length of the second data line 20, the load of the first data line 10 is greater than the load of the second data line 20. One end of the load compensation line 30 is connected with one end of the corresponding second data line 20, and the second data line 20 and the load compensation line 30 can be connected in series, so that the line resistance of the second data line 20 and the line resistance of the load compensation line 30 are connected in series, meanwhile, the load compensation line 30 can also form parasitic compensation capacitance, and further the load of the second data line 20 can be increased, so that the load compensation of the load compensation line 30 on the load of the second data line 20 is realized, and the difference value between the total load of the second data line 20 and the total load of the first data line 10 is smaller than a preset value. Wherein, the difference between the total resistance of the line resistance of the second data line 20 and the line resistance of the load compensation line 30 connected with the second data line 20 and the line resistance of the first data line 10 is smaller than a first preset value; the sum of the parasitic capacitance formed by the second data line 20 and the parasitic compensation capacitance formed by the load compensation line 30 connected to the second data line 20 is less than a second preset value. The first preset value and the second preset value can be set according to actual conditions.
In one embodiment of the present invention, the first end of each load compensation line 30 is connected to the corresponding second data line 20 in the frame area of the display panel. For example, with continued reference to fig. 2, the first end of each load compensation line 30 is connected to the corresponding second data line 20 in the top frame region of the display panel, or the first end of each load compensation line 30 is connected to the corresponding second data line 20 in the bottom frame region of the display panel.
Specifically, the first ends of the load compensation lines 30 are connected to the corresponding second data lines 20 in the frame region 101 of the display panel, so that the connection of the load compensation lines 30 to the corresponding second data lines 20 can be facilitated. It should be noted that the first end of each load compensation line 30 is connected to an end of the second data line 20 remote from the data driver, such that the load compensation line 30 and the second data line 20 satisfy a serial connection relationship.
In one embodiment of the present invention, please continue with reference to fig. 2, optionally, the at least one second data line 20 includes a plurality of second data lines 20;
at least part of the second data lines 20 are different in length, and the load compensation lines 30 connected to the second data lines 20 of different lengths are different in length.
Specifically, the display panel includes a plurality of second data lines 20, and load compensation is required for the plurality of data lines in the display panel. Based on the configuration of the display panel, at least some of the second data lines 20 have different lengths, so that the loads on the different second data lines 20 are different, and the loads on the second data lines 20 need to be compensated. And thus the length of the load compensation line 30 connected to the second data line 20 of a different length is different. By providing each second data line 20 with an adapted length of the load compensation line 30, an adapted load compensation can be performed for the second data lines 20 of different lengths such that the total load on each second data line 20 is the same as, or not significantly different from, the total load on the first data line 10.
In one embodiment of the present invention, please continue to refer to fig. 2, a plurality of second data lines 20 are distributed on both sides of at least one first data line 10; and the length of the second data line 20 gradually decreases and the length of the load compensation line 30 gradually increases in a direction away from the at least one first data line 10.
The shape of the display area of the display panel may include a circle, an ellipse, or a racetrack.
In one embodiment of the present invention, please continue to refer to fig. 3, the display panel includes:
the light-emitting device comprises a substrate, a driving circuit layer arranged on the substrate and a light-emitting structure layer arranged on one side of the driving circuit layer far away from the substrate; the driving circuit layer comprises pixel driving units and a plurality of data lines which are arranged in an array manner; the light emitting structure layer includes a plurality of light emitting structures; each pixel driving unit and a corresponding light-emitting structure are used for forming a sub-pixel;
each data line is connected with a corresponding column of pixel driving units, and each data line is used for forming parasitic capacitance with a first electrode plate of a storage capacitor in the corresponding connected column of pixel driving units;
each load compensation line 30 forms a parasitic compensation capacitor C3 with the first electrode plate of the storage capacitor in at least one pixel driving unit.
Specifically, the display panel includes: the light-emitting device comprises a substrate, a driving circuit layer arranged on the substrate and a light-emitting structure layer arranged on one side of the driving circuit layer away from the substrate. The substrate may be flexible and may be formed of any suitable insulating material having flexibility. The driving circuit layer may include a plurality of driving circuit units, a plurality of data lines, a plurality of scan lines, a plurality of light emission control signal lines, and a plurality of power supply wirings and initialization signal lines. The light emitting structure includes a first electrode, a second electrode, and a light emitting material layer between the first electrode and the second electrode. The first electrode is electrically connected to a source electrode or a drain electrode of the thin film transistor through the contact hole. Each first electrode corresponds to a driving circuit unit containing at least two control transistors, and each driving circuit unit is a pixel driving circuit.
For example, the pixel driving circuit may be a "7T1C" circuit in the related art, including seven thin film transistors and one storage capacitor. Fig. 7 is a circuit diagram of a driving circuit unit according to an embodiment of the present invention, and referring to fig. 7, and in combination with fig. 3, each driving circuit unit includes seven thin film transistors (T1 to T7) and a storage capacitor C1, and the working principle of the "7T1C" circuit is the prior art and will not be repeated here.
FIG. 8 is a schematic structural view of the active structure in region 1 or region 2 of FIG. 1; FIG. 9 is a schematic view of the structure of the active structure and the first metal layer in region 1 or region 2 of FIG. 1; fig. 10 is a schematic view of the structure of the active structure, the first metal layer, and the second metal layer in the region 1 or the region 2 in fig. 1, and referring to fig. 7 to 10, a first Scan signal line for transmitting a first Scan signal Scan1, a second Scan signal line for transmitting a second Scan signal Scan2, a second electrode plate C11 of the storage capacitor C1, a light emission control signal line for transmitting a light emission control signal EM, and a third Scan signal line for transmitting a third Scan signal Scan3 in the pixel driving circuit are provided in the first metal layer (M1). An initialization signal line for transmitting an initialization signal Vref in the pixel driving circuit, a shielding layer 9 for shielding the data line from the T1 gate, and a first electrode plate C12 of the storage capacitor C1 are disposed in the second metal layer (M2). Referring to fig. 3 and 5, a Data line for transmitting a Data voltage Data in the pixel driving circuit, a power signal line for transmitting a power signal ELVDD are provided in the third metal layer (M3),
each data line is connected with a corresponding column of pixel driving units, and in the extending process, the data line has an overlapping area with the first electrode plate C12 of the storage capacitor C1 in the corresponding connected column of pixel driving units, so that at least part of parasitic capacitance C2 on the data line is formed. In other embodiments of the present invention, the data lines may also form parasitic capacitances with other structure traces or structures in the driving circuit layer during the extension process.
The load compensation lines 30 are disposed on the same layer as the data lines, and each load compensation line 30 may form a parasitic compensation capacitor C3 with the first electrode plate C12 of the storage capacitor C1 in at least one pixel driving unit during the extending process. Optionally, the metal layer where the first electrode plate c12 of the storage capacitor is located on a side, close to the substrate, of the metal layer where the data line is located. The load compensation line 30 and the data line are disposed in the M3 metal layer in the driving circuit layer, and the first electrode of the storage capacitor C1 is disposed in the M2 metal layer in the driving circuit layer.
In one embodiment of the present invention, the driving circuit layer further includes a plurality of power signal lines, each power signal line being connected to a corresponding sub-pixel;
at least part of the interval section of each power signal line is arranged on the same layer with the first electrode plate c 12; each load compensation line 30 forms a parasitic compensation capacitor C3 with a first electrode plate of a storage capacitor in at least one pixel driving unit and a power signal line disposed at the same layer as the first electrode plate. The shielding layer 9 for shielding the data line and the T1 gate is connected to the power signal line through a through hole, that is, the shielding layer 9 may be used as a partial section of the power signal line, which is arranged in the same layer as the first electrode plate c12.
In determining the parasitic compensation capacitance of the load compensation line 30, the parasitic capacitance formed between the data line (10/20) and each sub-pixel may be calculated according to the simulation result; then, determining the total number of the sub-pixels connected to the first data line 10, so that the parasitic compensation capacitance on the first data line 10 can be calculated according to the parasitic capacitance formed between the first data line 10 and each sub-pixel and the total number of the sub-pixels connected to the first data line 10; determining the total number of the sub-pixels connected to the second data line 20, so that the parasitic capacitance formed by the second data line can be calculated according to the parasitic capacitance formed between the second data line 20 and each sub-pixel and the total number of the sub-pixels connected to the second data line 20; the parasitic capacitance to be compensated for by each second data line 20 can be determined according to the difference between the parasitic capacitance formed by the first data line 10 and the parasitic capacitance formed by each second data line 20.
Then, determining a parasitic capacitance formed between the load compensation capacitance line 30 and each sub-pixel according to the simulation result; the number of pixels to be compensated is obtained by dividing the parasitic capacitance to be compensated by the second data line 20 by the parasitic capacitance that the load compensation line 30 and the individual pixels may form. If one load compensation line 30 is connected to the second data lines 20, the length of the load compensation line 30 corresponding to each second data line 20 can be determined according to the number of pixels to be compensated for by each second data line 20; and can be adaptively adjusted according to actual conditions.
Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 11, an embodiment of the present invention further provides a display device, including: the display panel 1001 described in any of the above embodiments. Has the same technical effects and is not described in detail herein.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (10)

1. A display panel, comprising:
the array arrangement comprises sub-pixels and a plurality of data lines; each data line is connected with a corresponding sub-pixel; the load comprises a plurality of data lines, wherein the plurality of data lines comprise at least one first data line and at least one second data line; the load of the first data line is greater than the load of the second data line;
at least one load compensation line located in a display area of the display panel; the first end of the load compensation line is connected with one end of a corresponding second data line, and the load compensation line is used for compensating the load of the second data line connected with the load compensation line so that the difference value between the total load of the second data line and the total load of the first data line is smaller than a preset value.
2. The display panel according to claim 1, wherein a length of at least one of the load compensation lines is smaller than a length of a second data line connected to the load compensation line;
preferably, the display panel further includes:
at least one functional auxiliary line arranged in the same layer as the load compensation line; each functional auxiliary line is correspondingly arranged on an extension line with the length smaller than that of the load compensation line; the functional auxiliary line is electrically isolated from the corresponding load compensation line; the function auxiliary line is used for being connected with a function signal line in the display panel so as to reduce the voltage drop on the function signal line;
preferably, the length of the second data line connected to the load compensation line is equal to the sum of the length of the load compensation line, the length of the functional auxiliary line on the extension line of the load compensation line, and the distance therebetween.
3. The display panel of claim 2, wherein the display panel comprises,
the functional auxiliary line is connected with a power signal line in the display panel through a through hole;
alternatively, the function auxiliary line is connected to an initialization signal line in the display panel through a via hole.
4. The display panel according to claim 1, wherein the subpixels are arranged at uniform intervals in a column direction; the length of the second data line is smaller than that of the first data line;
the difference value between the total resistance of the line resistance of the second data line and the line resistance of the load compensation line connected with the second data line and the line resistance of the first data line is smaller than a first preset value;
and the sum of the parasitic capacitance formed by the second data line and the parasitic compensation capacitance formed by the load compensation line connected with the second data line is smaller than a second preset value.
5. The display panel according to claim 1, wherein each of the load compensation lines has a first end connected to a corresponding second data line in a frame region of the display panel;
preferably, the first end of each load compensation line is connected to the corresponding second data line in the top frame region of the display panel, or the first end of each load compensation line is connected to the corresponding second data line in the bottom frame region of the display panel.
6. The display panel of claim 1, wherein the at least one second data line comprises a plurality of second data lines;
at least part of the second data lines have different lengths, and the lengths of the load compensation lines connected to the second data lines having different lengths are different.
7. The display panel of claim 6, wherein the display panel comprises,
the second data lines are distributed on two sides of the at least one first data line; and the length of the second data line gradually decreases and the length of the load compensation line gradually increases along a direction away from the at least one first data line;
preferably, the shape of the display area of the display panel includes a circle, an ellipse, or a racetrack shape.
8. The display panel according to claim 1, comprising:
the light-emitting device comprises a substrate, a driving circuit layer arranged on the substrate and a light-emitting structure layer arranged on one side of the driving circuit layer away from the substrate; the driving circuit layer comprises pixel driving units and a plurality of data lines which are arranged in an array manner; the light emitting structure layer includes a plurality of light emitting structures; each pixel driving unit and a corresponding light-emitting structure are used for forming one sub-pixel;
each data line is connected with a corresponding column of pixel driving units, and each data line is used for forming parasitic capacitance with a first electrode plate of a storage capacitor in the corresponding connected column of pixel driving units;
each load compensation line and a first electrode plate of a storage capacitor in at least one pixel driving unit form a parasitic compensation capacitor;
preferably, the load compensation line and the data line are arranged in the same layer; the metal layer where the first electrode plate is located at one side, close to the substrate, of the metal layer where the data line is located.
9. The display panel of claim 8, wherein the driving circuit layer further comprises a plurality of power signal lines, each power signal line being connected to a corresponding sub-pixel;
at least part of interval sections of each power signal line and the first electrode plate are arranged on the same layer; each load compensation line forms the parasitic compensation capacitance with a first electrode plate of a storage capacitor in at least one pixel driving unit and the power signal line arranged on the same layer with the first electrode plate.
10. A display device, comprising: the display panel of any one of claims 1 to 9.
CN202311076298.XA 2023-08-24 2023-08-24 Display panel and display device Pending CN117116181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311076298.XA CN117116181A (en) 2023-08-24 2023-08-24 Display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311076298.XA CN117116181A (en) 2023-08-24 2023-08-24 Display panel and display device

Publications (1)

Publication Number Publication Date
CN117116181A true CN117116181A (en) 2023-11-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311076298.XA Pending CN117116181A (en) 2023-08-24 2023-08-24 Display panel and display device

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Country Link
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