CN117113918A - Method, device, medium and terminal for calculating antenna door area parameters applied to LEF file - Google Patents
Method, device, medium and terminal for calculating antenna door area parameters applied to LEF file Download PDFInfo
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- 230000008569 process Effects 0.000 claims description 37
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- 239000002184 metal Substances 0.000 description 16
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- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
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- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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Abstract
The application provides a method, a device, a storage medium and an electronic terminal for calculating antenna gate area parameters applied to LEF files in the field of digital integrated circuit design, which are used for calculating SPICE netlists of a full chip to obtain the antenna gate area parameters and replacing the antenna gate area parameters in the LEF files generated from ABSTRACT software, thereby solving the problem that accurate antenna effect values cannot be calculated due to inaccurate data caused in the extraction process of the LEF files.
Description
Technical Field
The application relates to the field of digital integrated circuit design, in particular to an antenna door area parameter calculation method applied to LEF files.
Background
The antenna effect means that a large amount of free charges are generated by the plasma etching process in the chip production process, and the free charges are collected on the exposed conductor surface, so that the excessive charges accumulated on the conductor surface can not form a discharge path to the ground, and as a result, the gate oxide can be damaged, the gate oxide is damaged by the plasma, and the reliability and the service life of the device even the whole chip are seriously reduced. In order to quantify the effect of the antenna effect, the concept of the antenna effect ratio was introduced. The antenna effect ratio refers to the quotient of the area of a layer of metal and the area of the associated gate, the greater this ratio the higher the likelihood of breakdown. And the cumulative antenna effect ratio refers to the sum of the local antenna effect ratios of all the antenna effect generating metal layers in the full chip.
In the process of designing and verifying a digital integrated circuit, an IP core refers to a circuit module design with independent functions in a chip, and the layout inside the IP core can not be seen only from the appearance. Therefore, when designing a full chip with an IP core, in order to avoid the antenna effect, it is necessary to calculate the antenna effect value, that is, the area of the metal line to which the gate is connected. However, because of the characteristics of the black box of the IP core, the area of the IP core connected with the metal wire mesh in the full chip cannot be accurately calculated, so that the antenna effect value of the full chip is inaccurately calculated, and the antenna effect is generated.
In the prior art, the ABSTRACT software is adopted to extract the LEF file of the antenna, wherein the LEF file of the antenna records the file of the antenna information transmission between the IP core and the whole chip in the chip, but the ABSTRACT software has unstable errors which are difficult to eliminate in the extraction process, so that the antenna information contained in the LEF file is inaccurate. If the LEF file with the antenna information of the accurate IP core can be provided for the full chip in the design process, the antenna area of the full chip can be accurately calculated, the antenna effect value of the full chip is further calculated, the influence of the antenna effect of the full chip is quantized, and therefore the damage of the antenna effect to the chip is avoided.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a method, an apparatus, a storage medium and an electronic terminal for calculating an antenna gate area parameter for an LEF file, which are used for solving gate oxide damage caused by full-chip plasma due to a failure of a full-chip unit to perform accurate antenna effect value calculation in a digital integrated circuit design and verification process.
To achieve the above and other related objects, a first aspect of the present application provides an antenna gate area parameter calculation method applied to an LEF file, including receiving a SPICE netlist file and an LEF file of a full chip; generating and obtaining updated antenna gate area parameters based on the SPICE netlist file; and replacing the initial antenna door area parameter in the LEF file with the updated antenna door area parameter so as to update the LEF file between the black box functional module and the full chip.
In some embodiments of the first aspect of the present application, the process of calculating the antenna gate area parameters to be replaced based on the SPICE netlist file includes: extracting pin information from the SPICE netlist file, and judging whether each pin is connected with a grid electrode of a full chip one by one according to the pin information; and calculating single antenna door area parameters of each grid connected with the pin for the pin connected with the grid of the full chip, accumulating all the single antenna door area parameters of each grid connected with the pin to obtain a total antenna door area parameter, and multiplying the total antenna door area parameter by a preset coefficient to obtain the updated antenna door area parameter of the pin.
In some embodiments of the first aspect of the present application, the method for obtaining the area parameter of the single antenna door includes: s is(s) i ＝l i *w i *m i ；w i ＝(nfin i -1) process coefficients a; wherein s is i A single antenna gate area parameter representing an ith gate connected to the pin; l (L) i Representing the length, w, of the ith gate connected to the pin i Representing the width, m, of the ith gate connected to the pin i Indicating the number of MOSFET field effect transistors connected to the ith gate of the pin, nfin i Representing the number of the gates contained in the MOSFET field effect transistor connected with the ith gate electrode of the pin, selecting corresponding preset coefficients according to different process types,a is a constant.
In some embodiments of the first aspect of the present application, the method for obtaining the updated antenna door area parameter includes: s= Σs i * Process coefficient b; wherein S is the updated antenna door area parameter, S i And b is a constant, representing a single antenna gate area parameter of an ith gate connected to the pin.
In some embodiments of the first aspect of the present application, the MOSFET field effect transistor comprises an NMOS and a PMOS.
In some embodiments of the first aspect of the present application, the LEF file is generated from a unit description portion of the LEF file generating software.
In some embodiments of the first aspect of the present application, the method further comprises: the method further comprises the steps of generating a corresponding antenna effect value through the updated LEF file, and calculating the area of the reverse diode required for preventing the antenna effect based on the antenna effect value.
To achieve the above and other related objects, a second aspect of the present application provides an antenna door area parameter calculating apparatus applied to an LEF file. Comprising the following steps: an input module: the method comprises the steps of receiving SPICE netlist files and LEF files of a full chip; the calculation module: the method is used for calculating and obtaining the latest antenna gate area parameter based on the SPICE netlist file; and a numerical value replacement module: and the method is used for replacing the initial antenna door area parameter in the LEF file by using the latest antenna door area parameter so as to update the LEF file between the black box functional module and the full chip, and calculating a corresponding antenna effect value according to the updated LEF file.
To achieve the above and other related objects, a third aspect of the present application provides a computer-readable storage medium having stored thereon a computer program for antenna door area parameter calculation applied to an LEF file, which when executed by a processor implements the first aspect of the present application to provide an antenna door area parameter calculation method applied to an LEF file.
To achieve the above and other related objects, a fourth aspect of the present application provides an electronic terminal, comprising: a processor and a memory; the memory is configured to store a computer program, and the processor is configured to execute the computer program stored in the memory, so that the terminal executes the first aspect of the present application to provide an antenna door area parameter calculating method applied to an LEF file.
As described above, the method, the device, the storage medium and the electronic terminal for calculating the antenna door area parameter applied to the LEF file in the digital integrated circuit design field have the following beneficial effects: the application improves the accuracy of calculating the antenna effect value of the LEF file, and further avoids the damage of the chip caused by antenna effect.
Drawings
Fig. 1 is a flowchart of an embodiment of an antenna door area parameter calculation method applied to an LEF file according to the present application.
Fig. 2 is a schematic diagram of an antenna door area parameter calculating device according to an embodiment of the present application applied to an LEF file.
Fig. 3 is a flowchart illustrating an embodiment of an antenna door area parameter calculation method applied to an LEF file according to the present application.
Fig. 4 is a flowchart illustrating an embodiment of an antenna door area parameter calculation method applied to an LEF file according to the present application.
Fig. 5 is a schematic structural diagram of an electronic terminal for calculating antenna door area parameters applied to an LEF file according to an embodiment of the present application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
In the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures as being related to another element or feature.
In the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," "held," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.
In order to solve the problems in the background art, the application provides a method, a device, a storage medium and an electronic terminal for calculating antenna door area parameters of LEF files, and aims to calculate an antenna door area parameter with high accuracy by calculating a SPICE netlist of a full chip and replace the antenna door area parameter in the LEF files generated from ABSTRACT software, thereby solving the problem that the LEF files cannot calculate an accurate antenna effect value due to inaccurate data in the extraction process.
Meanwhile, in order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be further described in detail by the following examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Before explaining the present application in further detail, terms and terminology involved in the embodiments of the present application will be explained, and the terms and terminology involved in the embodiments of the present application are applicable to the following explanation:
<1> spice: SPICE is a circuit-level simulation program that is used primarily in the circuit analysis program of integrated circuits.
<2> spice netlist: code describing the interconnections between circuit elements, mainly including heading statements, annotation statements, circuit description statements, circuit characteristic analysis and control statements, and end statements. The corresponding circuit can be used for obtaining the names of circuit elements, the mutual connection relation and parameters thereof.
<3> lef (Library Exchange Format) document: the method is a file for abstractly describing a standard unit layout, is applied to an automatic layout and wiring (P & R) tool, has a readable ASCII format, comprises detailed pin information for interconnection, and does not comprise a polycrystalline silicon layer, a diffusion layer and other bottom structures in a chip.
<4> Gate: the grid electrode is a mesh-like or spiral-like electrode composed of metal filaments. The grid electrode is one or more electrodes having a fine mesh or spiral shape arranged between the anode and the cathode in the multipole electron tube, and functions to control the electric field intensity at the surface of the cathode so as to change the emission of electrons from the cathode or capture secondary emission electrons.
<5> antennagatea values: parameter values representing the area of the pins in contact with the gate are shown in the LEF file.
<6> virtuoso: is a unified integrated circuit and package design platform that provides functionality for driving simulation of integrated circuits and packages from a single schematic and layout and schematic verification based on an overall solution to the system. The VIRTUOSO contains two key flows: the implementation circuit and the analysis circuit.
<7> abstreact: tools for generating LEF files.
<8> antenna effect (PAE, process Antenna Effect): in the chip production process, the exposed metal wire or the conductor such as polysilicon can cause the potential to rise due to the collected charges (such as charged particles generated by plasma etching), just like an antenna. The longer the antenna, the more charge is collected and the higher the voltage. If the conductor only contacts the gate of the MOS, then the high voltage may break down the thin gate oxide, disabling the circuit, which is the "antenna effect". With the development of process technology, the size of the gate is smaller, the number of layers of metal is larger, and the possibility of antenna effect is larger.
<9> antenna effect value (Process Antenna Effect Value): the antenna effect value refers to the quotient of the metal line area and the gate area of the gate connection. The manufacturer defines a fixed value to reflect the value of the antenna effect that occurs, and in practice, the EDA tool determines the number of diodes to be hung on the metal line connected to the gate based on the antenna effect value provided by the manufacturer.
<10> plasma causes gate oxide damage: the plasma induced gate oxide damage (Plasma Induced Gate Oxide Damage, PID) refers to the fact that the conductor in the antenna effect where charge is accumulated is directly connected to the gate of the device, thereby causing the thin oxide layer under the polysilicon gate to tunnel current and drain the charge, thereby causing damage to the gate oxide layer.
<11> finfet: the FinFET structure differs from a conventional planar transistor structure in that the gate is designed as a forked 3D structure resembling a fin for both sides of the circuit to control the turn-on and turn-off of the circuit. FinFET devices may use thicker gate oxides than planar devices, which may reduce gate leakage current.
The embodiment of the application provides an antenna door area parameter calculation method applied to an LEF file, an antenna door area parameter calculation device applied to the LEF file, a storage medium storing an executable program for realizing the antenna door area parameter calculation method applied to the LEF file, and an electronic terminal for executing the antenna door area parameter calculation method applied to the LEF file.
With respect to implementation of the antenna door area parameter calculation method applied to the LEF file, an exemplary implementation scenario of the antenna door area parameter calculation applied to the LEF file will be described.
As shown in fig. 1, a flow chart of an antenna door area parameter calculation method applied to an LEF file in an embodiment of the present application is shown. The antenna door area parameter calculation method applied to the LEF file in the embodiment mainly comprises the following steps:
step S101: a full-chip SPICE netlist file and an LEF file are received.
In some embodiments of the present application, the software that receives the SPICE netlist file and the LEF file of the full chip may be a script file, where the script file includes a series of combinations of operational actions that can be performed by a controllable computer according to the SPICE netlist file, so as to implement a certain logic branching function. Scripting languages that may be employed by the script file include, but are not limited to: javaScript scripting language, PHP scripting language, SQL scripting language, perl scripting language, shell scripting language, python scripting language, ruby scripting language, etc.
In some embodiments of the application, the LEF file is extracted by a CADENCE company's generator. The software includes, but is not limited to, a VIRTUOSO ABSTRACT generator. Wherein VIRTUOSO ABSTRACT generator is a unified system-level integrated circuit packaging and design platform whose process of extracting LEF files includes, but is not limited to: establishing a library, designating a process file, establishing a layout unit, opening the layout unit, editing in a layout environment, extracting the file and the like.
Further, in the VIRTUOSO ABSTRACT generator, a process description part of the LEF file is generated by the VIRTUOSO generator, a unit description part is generated by the ABSTRACT generator, then the END statement from the definition statement of the first MARCO to the last MARCO is selected from the LEF file generated by the ABSTRACT to copy, and the content copied from the previous LEF file is pasted between the END statement and the END LIBRARY statement of the last layout in the VIRTUOSO-derived LEF file to generate a complete LEF file, wherein the antenna gate area parameters of each pin are generated by the generation unit description part of the ABSTRACT generator.
Specifically, the process of generating the resulting LEF by the generation unit description section of the abstrict generator includes: setting an environment variable of VIRTUOSO, extracting PIN from the layout according to the set environment variable, extracting required wiring from the layout marked with PIN, and extracting LEF files based on the PIN and the wiring.
In some embodiments of the application, the types of full chips include, but are not limited to: the system comprises a computing chip, a storage chip, a sensing chip, a communication chip, an energy chip and a system-on-chip. Wherein a system-in-chip is an integrated circuit that integrates a computing processor and other electronic systems into a single chip that can be used to process digital signals, analog signals, mixed signals, radio frequency signals, and the like.
Step S102: and calculating to obtain the latest antenna gate area parameter based on the SPICE netlist file.
In one embodiment of the present application, the process of calculating the antenna gate area parameters to be replaced based on the SPICE netlist file comprises: extracting pin information from the SPICE netlist, and judging whether each pin is connected with a grid electrode of a full chip one by one according to the pin information; and calculating single antenna door area parameters of each grid connected with the pin for the pin connected with the grid of the full chip, accumulating all the single antenna door area parameters of each grid connected with the pin to obtain a total antenna door area parameter, and obtaining the updated antenna door area parameters of the pin based on a preset coefficient and the total antenna door area parameter.
Further, the updated antenna door area parameter is obtained based on a preset coefficient and a total antenna door area parameter. Wherein the preset coefficient refers to a process coefficient corresponding to a process adopted by the full chip. Illustratively, the process factor is 1 when a planar process is employed and 2.5 when a FinFET process is employed. The planar process used refers to the process of manufacturing a semiconductor chip, and in transistors and integrated circuits manufactured through a series of operations such as oxidation, photolithography, diffusion, ion implantation, etc., the devices and circuits remain substantially planar throughout the chip. The FinFET process used refers to a FinFET having fin-like protrusions on its surface. The FinFET is a fin field effect transistor, and has the characteristics of being capable of operating at a lower voltage and providing a high driving current.
In some embodiments of the present application, one pin corresponds to a plurality of MOSFET field effect transistors, and one MOSFET field effect transistor includes a plurality of gates. Further, the method for obtaining the area parameter of the single antenna door includes:
s i ＝l i *w i *m i (equation 1)
w i ＝(nfin i -1) process coefficients a; (equation 2)
The method for obtaining the updated antenna door area parameter comprises the following steps:
S＝∑s i * Process coefficient b; (equation 3)
In the present embodiment, s i Representation and representationA single antenna gate area parameter of an ith gate connected to the pin; it is worth noting that for a single pin connected to a gate, there are n gates connected to the single pin, where n is 1 or more. l (L) i Representing the length, w, of the ith gate connected to the pin i Representing the width, m, of the ith gate connected to the pin i Indicating the number of MOSFET field effect transistors connected to the ith gate of the pin, nfin i Representing the number of gates included in the MOSFET having the ith gate connected to the pin. I.e. the individual antenna gate area parameter of the ith gate connected to the pin is the product of the length, width of the gate and the number of MOSFET field effect transistors connected to the pin. The MOSFET field effect transistor comprises an NMOS and a PMOS.
Further, the width of the ith gate corresponding to the current pin is obtained in the manner shown in formula 2. Wherein nfin i Representing the number of gates connected to the MOSFET, the process coefficients are selected according to different process types, and a is a constant, for example, a is 0.008.
In one embodiment of the present application, the updated antenna gate area parameter represents an updated antenna gate area parameter of a single pin, and is obtained based on the single antenna gate area parameter, the process coefficient, and the constant b of a plurality of gates connected to the current pin. Wherein b may be selected from the group consisting of, but not limited to, 0.001.
Step S103: and replacing the initial antenna door area parameter in the LEF file with the updated antenna door area parameter so as to update the LEF file between the black box functional module and the full chip.
In an embodiment of the present application, the black box function module may be an IP core. The IP core is a mature design module of a circuit module with independent functions in a chip, and the circuit module design can be applied to a full-chip design project containing the circuit module, so that the design workload is reduced, the design period is shortened, and the success rate of chip design is improved.
In an embodiment of the present application, automatic wiring and calculation are performed through a back-end tool according to the updated LEF file, so as to obtain a corresponding antenna effect value. The antenna effect value calculating method comprises the following steps:
antenna effect value = area of wire mesh/area of gate connected to wire mesh (equation 4)
Then, calculating the area of the reverse diode required for preventing the antenna effect according to the calculated antenna effect value, wherein the mode for calculating the area of the reverse diode required to be added comprises the following steps:
the antenna effect value is less than or equal to X, the area of the reverse diode is plus Y; (equation 5)
Where X, Y are constant parameters, for example: x is 400 and Y is 2200 when FinFET processes are used.
In an embodiment of the present application, the method for avoiding the antenna effect based on the antenna effect value obtained in the above steps includes, but is not limited to: the metal wire mesh connected to the gate electrode and possibly causing antenna effect is connected with a reverse diode, so that a charge release loop is formed to remove the antenna effect. If the wiring space of the whole chip is small and is blocked or the position of the metal wire net layer where the reverse diode needs to be added is located in the forbidden area, the metal wire net layer is extended to the area with enough space nearby through the through holes on the metal wire net layer and then connected with the reverse diode.
Further, in addition to the above-mentioned method of removing the antenna effect by connecting a reverse diode to the metal wire mesh connected to the gate, which may cause the antenna effect, the embodiment of the present application may also remove the antenna effect by inserting a buffer, the parameters of which need to be adjusted according to the antenna effect value, based on the antenna effect value calculated according to the updated LEF file, to cut off the metal charge that causes the antenna effect.
In an embodiment of the present application, before replacing the initial antenna door area parameter in the LEF file with the latest antenna door area parameter, the initial antenna door area parameter in the LEF file may be further determined, and if the initial antenna door area parameter in the LEF file is the same as the latest antenna door area parameter, the replacement is not required. If the initial antenna door area parameter in the LEF file is different from the latest antenna door area parameter, the LEF file is replaced. The method for judging in the embodiment can keep the correct initial antenna door area parameter extracted from the LEF file, thereby reducing the number of times of replacement and improving the processing efficiency.
As shown in fig. 2, a schematic structural diagram of an antenna door area parameter calculating device applied to an LEF file according to an embodiment of the present application is shown. In this embodiment, the antenna door area parameter calculating device 200 applied to the LEF file includes:
the input module 201: the method comprises the steps of receiving SPICE netlist files and LEF files of a full chip;
the calculation module 202: the method is used for calculating and obtaining the latest antenna gate area parameter based on the SPICE netlist file;
specifically, the process of calculating the latest antenna gate area parameter based on the SPICE netlist file comprises the following steps: extracting pin information from the SPICE netlist file, and judging whether each pin is connected with a grid electrode of a full chip one by one according to the pin information; and calculating single antenna door area parameters of each grid connected with the pin for the pin connected with the grid of the full chip, accumulating all the single antenna door area parameters of each grid connected with the pin to obtain a total antenna door area parameter, and multiplying the total antenna door area parameter by a preset coefficient to obtain the updated antenna door area parameter of the pin.
Numerical value replacement module 203: and replacing the initial antenna door area parameter in the LEF file with the updated antenna door area parameter so as to update the LEF file between the black box functional module and the full chip.
It should be noted that: the antenna door area parameter calculating device applied to the LEF file provided in the above embodiment is only exemplified by the division of the above program modules when performing the antenna door area parameter calculation applied to the LEF file, and in practical application, the above processing allocation may be performed by different program modules according to needs, that is, the internal structure of the device is divided into different program modules to complete all or part of the above processing. In addition, the antenna door area parameter calculating device applied to the LEF file and the antenna door area parameter calculating method applied to the LEF file provided in the foregoing embodiments belong to the same concept, and detailed implementation processes of the antenna door area parameter calculating device and the antenna door area parameter calculating method applied to the LEF file are detailed in the method embodiments and are not described herein again.
As shown in fig. 3 and 4, an embodiment of an antenna door area parameter calculation method applied to the LEF file according to the present application is shown. The antenna door area parameter calculation method applied to the LEF file in the embodiment mainly comprises the following steps:
step S301: a full-chip SPICE netlist file and an LEF file are received.
Step S302: and extracting pin information, and judging whether each pin is connected with a grid electrode one by one.
In some embodiments of the present application, based on the extracted pin information, determining whether the current pin has a gate connected to the current pin, if the current pin has a gate connected to the current pin, proceeding to step S303, and calculating a single antenna gate area parameter of the current pin; if the current pin has no grid connected with the current pin, skipping the pin, and continuing to judge whether the next pin has the grid connected with the current pin or not until all pins on the current metal wire network layer complete traversal.
Step S303: a single antenna gate area value is calculated for each gate connected to the current pin.
Step S304: an updated antenna gate area parameter is calculated based on the individual antenna gate area values for each gate connected to the current pin.
Step S305: the initial antenna gate area parameters in the LEF file are replaced with updated antenna gate area parameters.
In an embodiment of the present application, as shown in fig. 4, before the updated antenna door area parameter is replaced with the initial antenna door area parameter in the LEF file, the initial antenna door area parameter in the LEF file may be further determined, if the initial antenna door area parameter in the LEF file is consistent with the updated antenna door area parameter, the replacement is not performed, and if the initial antenna door area parameter in the LEF file is inconsistent with the updated antenna door area parameter, the replacement is performed, thereby saving time consumption for the replacement and improving efficiency.
It should be noted that, the above embodiment and the embodiment of the method for calculating the antenna door area parameter applied to the LEF file belong to the same concept, and the detailed implementation process of the embodiment of the method for calculating the antenna door area parameter applied to the LEF file is detailed in the embodiment of the method for calculating the antenna door area parameter applied to the LEF file, which is not described herein again.
The embodiments of the method and the device for calculating the antenna door area parameter applied to the LEF file are described in detail, and the electronic terminal for calculating the antenna door area parameter applied to the LEF file is described in detail below.
Referring to fig. 5, for a hardware structure of an electronic terminal for calculating an antenna door area parameter applied to an LEF file according to an embodiment of the present application, an optional hardware structure of an electronic terminal 500 for calculating an antenna door area parameter applied to an LEF file according to an embodiment of the present application may be implemented by a terminal side or a server side, where the terminal 500 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The electronic terminal 500 applied to the antenna door area parameter calculation of the LEF file includes: at least one processor 501, memory 502, at least one network interface 504, and a user interface 506. The various components in the device are coupled together by a bus system 505. It is understood that bus system 505 is used to enable connected communications between these components. The bus system 505 includes a power bus, a control bus, and a status signal bus in addition to a data bus. But for clarity of illustration the various buses are labeled as bus systems in fig. 3.
The user interface 506 may include, among other things, a display, keyboard, mouse, trackball, click gun, keys, buttons, touch pad, or touch screen, etc.
It is to be appreciated that memory 502 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read Only Memory (ROM), a programmable Read Only Memory (PROM, programmable Read-Only Memory), which serves as an external cache, among others. By way of example, and not limitation, many forms of RAM are available, such as static random Access Memory (SRAM, staticRandom Access Memory), synchronous static random Access Memory (SSRAM, synchronous Static RandomAccess Memory). The memory described by embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.
The memory 502 in an embodiment of the present application is used to store various categories of data to support the operation of the electronic terminal 500 for antenna door area parameter calculation applied to the LEF file. Examples of such data include: any executable program for operating on the electronic terminal 500 for antenna door area parameter calculation applied to the LEF file, such as an operating system 5021 and application 5022; the operating system 5021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 5022 may include various application programs such as a media player (MediaPlayer), a Browser (Browser), etc. for implementing various application services. The method for calculating the antenna door area parameter applied to the LEF file provided by the embodiment of the application can be contained in the application program 5022.
The method disclosed in the above embodiment of the present application may be applied to the processor 501 or implemented by the processor 501. The processor 501 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuitry in hardware or instructions in software in the processor 501. The processor 501 may be a general purpose processor, a digital signal processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 501 may implement or perform the methods, steps and logic blocks disclosed in embodiments of the present application. The general purpose processor 501 may be a microprocessor or any conventional processor or the like. The steps of the accessory optimization method provided by the embodiment of the application can be directly embodied as the execution completion of the hardware decoding processor or the execution completion of the hardware and software module combination execution in the decoding processor. The software modules may be located in a storage medium having memory and a processor reading information from the memory and performing the steps of the method in combination with hardware.
In an exemplary embodiment, the electronic terminal 500 for antenna gate area parameter calculation applied to the LEF file may be implemented by one or more application specific integrated circuits (ASIC, application Specific Integrated Circuit), DSP, programmable logic device (PLD, programmable Logic Device), complex programmable logic device (CPLD, complex Programmable LogicDevice) for performing the aforementioned method.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by computer program related hardware. The aforementioned computer program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
In the embodiments provided herein, the computer-readable storage medium may include read-only memory, random-access memory, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, U-disk, removable hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable and data storage media do not include connections, carrier waves, signals, or other transitory media, but are intended to be directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
In summary, the application provides a method, a device, a storage medium and an electronic terminal for calculating antenna door area parameters of LEF files, and the application provides a method for improving the efficiency and accuracy of calculating antenna door area parameters of LEF files, which calculates SPICE netlists of a whole chip to obtain antenna door area parameters, and replaces the antenna door area parameters in LEF files generated from ABSTRACT software, thereby solving the problem that the accurate antenna effect value cannot be calculated due to inaccurate data caused in the extraction process of LEF files. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. An antenna door area parameter calculation method applied to an LEF file, comprising:
receiving SPICE netlist files and LEF files of the full chip;
generating and obtaining updated antenna gate area parameters based on the SPICE netlist file;
and replacing the initial antenna door area parameter in the LEF file with the updated antenna door area parameter so as to update the LEF file between the black box functional module and the full chip.
2. The method for calculating the antenna gate area parameters for the LEF file according to claim 1, wherein the generating the updated antenna gate area parameters based on the SPICE netlist file comprises:
extracting pin information from the SPICE netlist file, and judging whether each pin is connected with a grid electrode of a full chip one by one according to the pin information;
and calculating single antenna door area parameters of each grid connected with the pin for the pin connected with the grid of the full chip, accumulating all the single antenna door area parameters of each grid connected with the pin to obtain a total antenna door area parameter, and multiplying the total antenna door area parameter by a preset coefficient to obtain the updated antenna door area parameter of the pin.
3. The method for calculating the antenna door area parameter for the LEF file according to claim 2, wherein the calculating the single antenna door area parameter comprises:
s i ＝l i *w i *m i ；
w i ＝(nfin i -1) process coefficients a;
wherein s is i A single antenna gate area parameter representing an ith gate connected to the pin; l (L) i Representing the length, w, of the ith gate connected to the pin i Representing the width, m, of the ith gate connected to the pin i Indicating the number of MOSFET field effect transistors connected to the ith gate of the pin, nfin i And the number of the grids contained in the MOSFET field effect transistor which is connected with the ith grid electrode through the pins is represented, the process coefficient is selected to be a corresponding preset coefficient according to different process types, and a is a constant.
4. The method for calculating the antenna door area parameter for the LEF file according to claim 3, wherein the means for obtaining the updated antenna door area parameter comprises:
S＝∑s i * Process coefficient b;
wherein S is the updated antenna door area parameter, S i And b is a constant, representing a single antenna gate area parameter of an ith gate connected to the pin.
5. The method of claim 3, wherein the MOSFET field effect transistor comprises an NMOS and a PMOS.
6. The method of claim 1, wherein the LEF file is generated in a unit description portion of LEF file generation software.
7. The method of claim 1, further comprising generating a corresponding antenna effect value from the updated LEF file, and calculating an area of a reverse diode required to prevent an antenna effect based on the antenna effect value.
8. An antenna door area parameter calculation device applied to an LEF file, comprising:
an input module: the method comprises the steps of receiving SPICE netlist files and LEF files of a full chip;
the calculation module: the method is used for calculating and obtaining updated antenna gate area parameters based on the SPICE netlist file;
and a numerical value replacement module: and replacing the initial antenna door area parameter in the LEF file with the updated antenna door area parameter so as to update the LEF file between the black box functional module and the full chip.
9. A computer readable storage medium for antenna door area parameter calculation applied to LEF files, having stored thereon a computer program, which when executed by a processor implements the method of any of claims 1 to 7.
10. An electronic terminal for calculating antenna door area parameters applied to an LEF file, comprising: a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the computer program stored in the memory, so that the terminal performs the method for calculating the antenna gate area parameter in the LEF file according to any of claims 1 to 7.
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| CN202311061723.8A CN117113918A (en) | 2023-08-22 | 2023-08-22 | Method, device, medium and terminal for calculating antenna door area parameters applied to LEF file |
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| CN202311061723.8A CN117113918A (en) | 2023-08-22 | 2023-08-22 | Method, device, medium and terminal for calculating antenna door area parameters applied to LEF file |
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