CN117113891A - Multi-node cache consistency system verification module and method based on FPGA - Google Patents

Abstract

The invention relates to a multi-node cache consistency system verification module and a multi-node cache consistency system verification method based on an FPGA, wherein the verification module is based on the design of the multi-node cache consistency system of the FPGA and comprises a read-write control unit, an instruction receiving and retaining station, an instruction submitting arbitration unit and a cache consistency system DUT of a multi-request node to be tested; the read-write control unit controls the read-write of the external memory, reads the instruction data from the external memory, sends the instruction data to the instruction receiving-sending reservation station, and writes the completed instruction information released by the instruction receiving-sending reservation station back to the external memory. The instruction receiving and transmitting reservation station has the functions of receiving, storing and transmitting instruction information and submitting and releasing the instruction information; the instruction submission arbitration unit has the functions of competing arbitration and buffering submission of the finished instruction, and submits the finished instruction to the instruction receiving and transmitting reservation station. The verification module and the method have flexible suitability and expandability for multi-node cache consistency system verification.

Description

Multi-node cache consistency system verification module and method based on FPGA

Technical Field

The invention relates to the technical field of Field Programmable Gate Array (FPGA) -based project development and chip prototype verification, in particular to a multi-node cache consistency system verification module and method based on an FPGA.

Background

FPGA (Field-programmable gate array): an FPGA is a programmable logic device with reconfigurable features. It can be programmed to implement various digital circuit functions and can be reconfigured at run-time. FPGAs have parallel processing capability and high flexibility, and are therefore widely used in hardware verification and prototype development.

Conventional multi-node cache coherency verification systems often require extensive emulation and debugging efforts. As the number of cores increases, so does the complexity and resource requirements of the verification, which are difficult to preserve in terms of flexibility, scalability, and authenticity assessment. Traditional cache consistency system verification based on FPGA uses FPGA as a verification platform to realize the design of cache consistency system level test cases. Through the verification method, the method has the advantages of flexibility, high performance, expandability, real performance evaluation, customizability and the like, but with the increase of the number of cores, the problems of limited resources and difficult debugging are also often faced.

Disclosure of Invention

In order to solve the technical problems, the multi-node cache consistency system verification module based on the FPGA comprises a read-write control unit, an instruction receiving and retaining station, an instruction submitting arbitration unit and a cache consistency system DUT of a multi-request node to be tested;

one end of the read-write control unit is provided with an external memory, an information interconnection structure is formed between the external memory and the read-write control unit, the other end of the read-write control unit is connected with the instruction receiving-transmitting reservation station, and the instruction receiving-transmitting reservation station returns the released instruction information to the read-write control unit; specifically, the read-write control unit controls the read-write of the external memory, reads the instruction data from the external memory to the instruction transceiving reservation station, and writes the completed instruction information released by the instruction transceiving reservation station back to the external memory.

Each request node Requsetnode is arranged in a cache consistency system DUT of the multi-request node to be tested, wherein the output end of the request node Requsetnode is connected with an instruction submitting arbitration unit, namely, the completion instruction information sent by the request node Requsetnode is received by an arbitration control module arranged in the instruction submitting arbitration unit, on the other hand, the receiving end of the request node Requsetnode is connected with an instruction receiving and transmitting reservation station, and an instruction storage entity arranged in the instruction receiving and transmitting reservation station sequentially sends stored instructions to the request node Requsetnode;

the DUT is an RTL code of the multi-Node cache consistency system to be tested, wherein the number of the RequsetNodes can be multiple, each request Node comprises a private cache in the cache consistency system, and the DUT also has a Slave Node for processing consistency transaction processing with the memory MEM in the cache consistency system.

In one embodiment of the present invention, the instruction transceiving reservation station includes a write pointer control module, a read address pointer control module, a write address pointer control module, an instruction store read write control module, a write address pointer FIFO, a read address pointer FIFO, an instruction store entity, and a State vector;

the write address pointer control module controls the read-write of the storage of the write address pointer FIFO according to the instruction of the read-write control unit and the control information of the read address pointer, and the read address pointer control module controls the read-write of the storage of the read address pointer FIFO according to the control information of the instruction storage read-write control module and the write address pointer; the instruction storage read-write control module controls the read-write of the instruction storage entity and the change of the State vector according to the control module information of the write address pointer control module and the read address pointer FIFO, and simultaneously sequentially sends the instructions stored in the instruction storage entity to the request nodes Requsettde in the cache consistency system DUT of the multiple request nodes to be tested.

In one embodiment of the present invention, the instruction commit arbitrating unit includes an arbitration control module, a completion instruction store read-write control module, and a completion instruction cache FIFO;

the arbitration control module receives the completion instruction information sent by each request node Requsenode in the DUT to be tested of the cache consistency system of the multiple request nodes, sorts the completion instruction information which generates competition submission, and stores the completion instruction information in a completion instruction cache FIFO; the finishing instruction storage read-write control module controls the read-write of the finishing instruction cache FIFO, stores finishing instructions into the finishing instruction cache FIFO according to the information of the arbitration control module, and simultaneously sends temporary finishing instruction information in the finishing instruction cache FIFO to the instruction receiving-transmitting reservation station.

In one embodiment of the present invention, the read-write control unit controls the external memory to read and write, and for the instruction information from the external memory to be verified, the read-write control unit sequentially reads the instructions according to the state information, where the instruction information includes node information CoreID, address, operation code Opcode, granularity Grid and Data; the completion instruction information submitted by the instruction receiving and transmitting reservation station is written into an external memory, and the instruction information comprises: completion instruction Count information Count, coreID, address, operation code Opcode, granularity Grid, and Data.

In one embodiment of the present invention, the instruction receiving, storing, transmitting and submitting the released function of the instruction receiving, transmitting and reserving station includes the following specific steps:

step S1: before receiving the first piece of information of the read-write control unit, the write address pointer control module stores all ID information into the write address FIFO, writes the write address pointer fully, and the ID is the address of the instruction storage entity or the unique mapping relation or the direct corresponding relation between the ID and the address of the instruction storage entity is built one by one;

step S2: when the write address pointer FIFO is full, the instruction information from the read-write control unit and the completion instruction information from the instruction submitting arbitration unit can be received;

step S3: the method comprises the steps that instruction information from a read-write control unit is received, an ID is read from a read-Address pointer FIFO by a read-Address pointer control module, an instruction of a corresponding Address of an instruction storage entity is stored by the instruction storage read-write control module according to the ID information, the instruction information is sent to a corresponding request node by matching with the ID and CoreID, a State vector is updated, the instruction information comprises an internal serial number ID, node point information CoreID, an Address, an operation code Optode, granularity Grid and Data, and each ID in the State vector has a Valid bit Valid and an occupied bit Busy;

and receiving finishing instruction information from the instruction submitting arbitration unit, wherein the finishing instruction information comprises an internal serial number ID, node point information CoreID, address, operation code Opcode, granularity Grid and Data, an instruction storage read-write control module and an instruction with an internal required ID released and stored in an instruction storage entity, so that a storage space is vacated, and a write Address pointer controls to store the ID information into the write Address pointer and simultaneously send the finishing instruction to the read-write control unit.

In one embodiment of the present invention, when receiving the instruction information from the read-write control unit in step S2, the write address pointer control module reads the ID in the write address pointer FIFO, stores the instruction information from the read-write control unit in the instruction storage entity according to the address relationship between the ID and the instruction storage entity, and updates the corresponding State vector, and simultaneously, the read address pointer control module writes the ID from the write address pointer FIFO in the FIFO of the read address pointer;

when receiving a completion instruction from the instruction submitting arbitration unit, the instruction storage read-write control module reads the instruction of the instruction storage entity according to the address relation between the ID in the completion instruction information and the instruction storage entity, updates the corresponding State vector, and simultaneously writes the ID in the completion instruction information into the write address pointer FIFO.

The invention also provides a verification method of the multi-node cache consistency system based on the FPGA, which is built based on the verification module and forms an automatic information flow aiming at the multi-node cache consistency system, and comprises the following steps:

step S11: initializing a system, namely initializing a write address pointer FIFO in an instruction transceiving reservation station, namely storing all ID information into the write address FIFO by a write address pointer control module, fully writing the write address pointer, and establishing an address mapping relation between the ID and an instruction storage entity;

step S12: the read-write control unit reads the generated instruction information from an external memory outside the FPGA prototype verification system, wherein the instruction information comprises node information CoreID, address, operation code Opcode, granularity Grid and Data;

step S13: the instruction receiving and transmitting reservation station stores and encodes instruction information from the read-write control unit, the encoded instruction information comprises a reservation station internal serial number ID, node information CoreID, an Address, an operation code Opcode, granularity Grid and Data, and then the encoded instruction information is sent to a request Node Requset Node in a cache consistency system DUT of a multi-request Node to be tested;

step S14: the method comprises the steps that an instruction submitting arbitration unit receives a completion instruction of a request node Requsenode in a cache consistency system DUT of a multi-request node to be tested, completion instruction information comprises a reservation station internal serial number ID, node point information CoreID, address, operation code Opcode, granularity Grid and Data, an instruction completed by the instruction submitting arbitration unit is sent to an instruction receiving and sending reservation station, the instruction receiving and sending reservation station releases an instruction stored in an instruction storage entity, and then the completion instruction is sent to a read-write control unit;

step S15: the read-write control unit writes the received completion instruction into the external memory in a completion state, and is reserved for inspection and analysis.

Compared with the prior art, the technical scheme of the invention has the following advantages: the verification module is used for verifying the multi-node cache consistency system to be tested, and has flexible expansibility; meanwhile, the verification method has the advantages that the storage, forwarding and release of the instructions are flexibly adapted to the simulation of external different storage instructions.

Drawings

In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings.

FIG. 1 is a general block diagram of an FPGA-based multi-node cache coherence system verification module of the present invention;

FIG. 2 is a block diagram of the internal architecture of the instruction transceiving reservation station according to the present invention;

FIG. 3 is a block diagram illustrating the internal structure of an instruction commit arbitrating module according to the present invention;

FIG. 4 is a schematic diagram of instruction information according to the present invention.

Detailed Description

The invention provides a multi-node cache consistency system verification module and a multi-node cache consistency system verification method based on an FPGA, which are further described in detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The invention provides a multi-node cache consistency system verification module and a method based on an FPGA, as shown in FIG. 1, wherein the multi-node cache consistency system verification module based on the FPGA comprises a read-write control unit, an instruction receiving and retaining station, an instruction submitting arbitration unit and a cache consistency system DUT of a multi-request node to be tested;

RTL code logic based on FPGA realizes all functions of the read-write control unit. The read-write control unit controls the external memory to read and write. For the instruction information which is required to be verified from the external memory, the read-write control unit sequentially reads the instructions according to the state information, wherein the instruction information comprises node information CoreID, address, operation code Optole, granularity Grid and Data. And writing the completion instruction information submitted by the instruction receiving and transmitting unit into an external memory. The instruction information comprises: completion instruction Count information Count, coreID, address, operation code Opcode, granularity Grid, and Data

And the RTL code logic based on the FPGA is realized, and all functions of the instruction receiving and transmitting reservation station are realized. As shown in fig. 2, the instruction transceiving reservation station has functions of receiving, storing, transmitting and submitting and releasing instruction information, and comprises a write address pointer control module, a read address pointer control module, a write address pointer control module, an instruction storing read-write control module, a write address pointer FIFO, a read address pointer FIFO, an instruction storing entity and a State vector. The write address pointer control module controls the reading and writing of the storage of the write address pointer FIFO according to the instruction of the read-write control unit and the control information of the read address pointer, and the read address pointer control module controls the reading and writing of the storage of the read address pointer FIFO according to the control information of the instruction storage read-write control module and the write address pointer. The instruction storage read-write control module controls the reading and writing of the instruction storage entity and the change of the State vector according to the information of the write address pointer control module and the read address pointer control module, and simultaneously sequentially sends the instruction stored by the instruction storage entity to a request node Requsenode in a cache consistency system DUT of the multiple request nodes to be tested.

RTL code logic based on FPGA realizes all functions of the submitting arbitration unit. As shown in fig. 3, the instruction commit arbitrating unit includes an arbitration control module, a completion instruction store read-write control module, and a completion instruction cache FIFO. The arbitration control module receives the completion instruction information sent by each request node Requsetnode in the DUT to be tested of the cache consistency system of the multiple request nodes, and sorts the completion instruction information according to the size of the generated competition ID. The finishing instruction storage read-write control module controls the finishing instruction cache FIFO, stores finishing instructions into the finishing instruction cache FIFO according to the sequence of the arbitration control module, and simultaneously controls temporary storage finishing instruction information in the finishing instruction cache FIFO to be sent to the instruction receiving-transmitting reservation station.

Based on an FPGA prototype verification system, the FPGA-based RTL code realization module is interconnected with a cache consistency system DUT of a multi-request Node to be tested, and system level verification is performed, as shown in FIG. 1, the cache consistency system DUT of the multi-request Node to be tested is the RTL code of the multi-Node cache consistency system to be tested, wherein a plurality of request nodes Requsetnode can be provided, each request Node comprises a private cache in the cache consistency system, and in addition, a Slave Node is used for processing consistency transaction processing with a memory MEM in the cache consistency system.

In addition, the instruction receiving, storing, transmitting and submitting and releasing functions of the instruction receiving, transmitting and reserving station comprise a method for processing instruction information by the instruction receiving, transmitting and reserving station, and the specific steps are as follows:

step S1: before receiving the first piece of information of the read-write control unit, the write address pointer control module stores all ID information into the write address FIFO, writes the write address pointer fully, and the ID is the address of the instruction storage entity or the unique mapping relation or the direct corresponding relation between the ID and the address of the instruction storage entity is built one by one;

step S2: when the write address pointer FIFO is full, instruction information from the read-write control unit and completion instruction information from the instruction commit arbitrating unit can be received.

When receiving instruction information from the read-write control unit, the write address pointer control module reads the ID in the write address pointer FIFO, stores the instruction information from the read-write control unit into the instruction storage entity according to the address relation between the ID and the instruction storage entity, and updates the corresponding State vector, and simultaneously, the read address pointer control module writes the ID from the write address pointer FIFO into the FIFO of the read address pointer.

When receiving a completion instruction from the instruction submitting arbitration unit, the instruction storage read-write control module reads the instruction of the instruction storage entity according to the address relation between the ID in the completion instruction information and the instruction storage entity, updates the corresponding State vector, and simultaneously writes the ID in the completion instruction information into the write address pointer FIFO.

Step S3: and receiving instruction information from the read-write control unit, reading an ID from the read-Address pointer FIFO by the read-Address pointer control module, sending an instruction of a corresponding Address of an instruction storage entity by the instruction storage read-write control module according to the ID information, and updating a State vector by matching the ID and CoreID to a corresponding request node, wherein the instruction information comprises an internal serial number ID, node point information CoreID, an Address, an operation code Optole, granularity Grid and Data, and each ID in the State vector has a Valid bit Valid and an occupied bit Busy as shown in figure 4.

And receiving the completion instruction information from the instruction submitting arbitration unit, as shown in fig. 4, the completion instruction information comprises an internal serial number ID, node point information CoreID, an Address, an operation code Opcode, granularity Grid and Data, an instruction storage read-write control module and an internal required ID release the instruction stored in the instruction storage entity, so that a storage space is reserved, the write Address pointer control stores the ID information into the write Address pointer, and meanwhile, the completion instruction is sent to the read-write control unit.

The invention also provides a multi-node cache consistency system verification method based on the FPGA, which comprises the following steps:

step S11: initializing a system, namely initializing a write address pointer FIFO in an instruction transceiving reservation station, namely storing all ID information into the write address FIFO by a write address pointer control module, fully writing the write address pointer, and establishing an address mapping relation between the ID and an instruction storage entity;

step S12: the read-write control unit reads the generated instruction information from an external memory outside the FPGA prototype verification system, wherein the instruction information comprises node information CoreID, address, operation code Opcode, granularity Grid and Data;

step S13: the instruction receiving and transmitting reservation station stores and encodes instruction information from the read-write control unit, the encoded instruction information comprises a reservation station internal serial number ID, node information CoreID, an Address, an operation code Opcode, granularity Grid and Data, and then the encoded instruction information is sent to a request Node Requset Node in a cache consistency system DUT of a multi-request Node to be tested;

step S14: the method comprises the steps that an instruction submitting arbitration unit receives a completion instruction of a request node Requsenode in a cache consistency system DUT of a multi-request node to be tested, completion instruction information comprises a reservation station internal serial number ID, node point information CoreID, address, operation code Opcode, granularity Grid and Data, an instruction completed by the instruction submitting arbitration unit is sent to an instruction receiving and sending reservation station, the instruction receiving and sending reservation station releases an instruction stored in an instruction storage entity, and then the completion instruction is sent to a read-write control unit;

step S15: the read-write control unit writes the received completion instruction into the external memory in a completion state, and is reserved for inspection and analysis.

The multi-node cache consistency system comprises: a multi-node cache coherency system refers to a system of multiple nodes, each having its own cache, and these caches need to be kept coherent. In parallel computing and distributed systems, multi-node cache coherency is an important issue, involving aspects such as data sharing and coherency maintenance.

The multi-node cache consistency system verification based on the FPGA uses the FPGA as a verification platform to realize the design of multi-node cache consistency system level test cases. By the verification method, the performance and the correctness of the cache consistency system can be verified and evaluated, and guidance is provided for optimization and improvement of the system.

It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.

Claims (7)

1. The multi-node cache consistency system verification module based on the FPGA is designed based on the multi-node cache consistency system of the FPGA and is characterized by comprising a read-write control unit, an instruction receiving and retaining station, an instruction submitting arbitration unit and a cache consistency system DUT of a multi-request node to be tested;

one end of the read-write control unit is provided with an external memory, an information interconnection structure is formed between the external memory and the read-write control unit, the other end of the read-write control unit is connected with the instruction receiving-transmitting reservation station, and the instruction receiving-transmitting reservation station returns the released instruction information to the read-write control unit;

each request node Requsetnode is arranged in a cache consistency system DUT of the multi-request node to be tested, wherein the output end of the request node Requsetnode is connected with an instruction submitting arbitration unit, namely, the completion instruction information sent by the request node Requsetnode is received by an arbitration control module arranged in the instruction submitting arbitration unit, on the other hand, the receiving end of the request node Requsetnode is connected with an instruction receiving and transmitting reservation station, and an instruction storage entity arranged in the instruction receiving and transmitting reservation station sequentially sends stored instructions to the request node Requsetnode;

the DUT is an RTL code of the multi-node cache consistency system to be tested, wherein the number of the RequsetNodes can be multiple, each request node comprises a private cache in the cache consistency system, and the DUT also has a SlaveNode for processing consistency transaction processing with the memory MEM in the cache consistency system.

2. The authentication module of claim 1, wherein: the instruction receiving and transmitting reservation station comprises a write pointer control module, a read address pointer control module, a write address pointer control module, an instruction storage read-write control module, a write address pointer FIFO, a read address pointer FIFO, an instruction storage entity and a State vector;

the write address pointer control module controls the read-write of the storage of the write address pointer FIFO according to the instruction of the read-write control unit and the control information of the read address pointer, and the read address pointer control module controls the read-write of the storage of the read address pointer FIFO according to the control information of the instruction storage read-write control module and the write address pointer; the instruction storage read-write control module controls the read-write of the instruction storage entity and the change of the State vector according to the control module information of the write address pointer control module and the read address pointer FIFO, and simultaneously sequentially sends the instructions stored in the instruction storage entity to the request nodes Requsettde in the cache consistency system DUT of the multiple request nodes to be tested.

3. The authentication module of claim 1, wherein: the instruction submitting arbitration unit comprises an arbitration control module, a finishing instruction storage read-write control module and a finishing instruction cache FIFO;

the arbitration control module receives the completion instruction information sent by each request node Requsenode in the DUT to be tested of the cache consistency system of the multiple request nodes, sorts the completion instruction information which generates competition submission, and stores the completion instruction information in a completion instruction cache FIFO; the finishing instruction storage read-write control module controls the read-write of the finishing instruction cache FIFO, stores finishing instructions into the finishing instruction cache FIFO according to the information of the arbitration control module, and simultaneously sends temporary finishing instruction information in the finishing instruction cache FIFO to the instruction receiving-transmitting reservation station.

4. The authentication module of claim 1, wherein: the read-write control unit controls the read-write of the external memory, and sequentially reads the instructions according to the state information of the instruction information which is needed to be verified from the external memory, wherein the instruction information comprises node information CoreID, address, operation code Optode, granularity Grid and Data; the completion instruction information submitted by the instruction receiving and transmitting reservation station is written into an external memory, and the instruction information comprises: completion instruction Count information Count, coreID, address, operation code Opcode, granularity Grid, and Data.

5. The authentication module of claim 1, wherein: the function of receiving, storing, transmitting and submitting the instruction information of the instruction receiving and transmitting reservation station comprises the method for processing the instruction information by the instruction receiving and transmitting reservation station, and the specific steps are as follows:

step S1: before receiving the first piece of information of the read-write control unit, the write address pointer control module stores all ID information into the write address FIFO, writes the write address pointer fully, and the ID is the address of the instruction storage entity or the unique mapping relation or the direct corresponding relation between the ID and the address of the instruction storage entity is built one by one;

step S2: when the write address pointer FIFO is full, the instruction information from the read-write control unit and the completion instruction information from the instruction submitting arbitration unit can be received;

step S3: the method comprises the steps that instruction information from a read-write control unit is received, an ID is read from a read-Address pointer FIFO by a read-Address pointer control module, an instruction of a corresponding Address of an instruction storage entity is stored by the instruction storage read-write control module according to the ID information, the instruction information is sent to a corresponding request node by matching with the ID and CoreID, a State vector is updated, the instruction information comprises an internal serial number ID, node point information CoreID, an Address, an operation code Optode, granularity Grid and Data, and each ID in the State vector has a Valid bit Valid and an occupied bit Busy;

and receiving finishing instruction information from the instruction submitting arbitration unit, wherein the finishing instruction information comprises an internal serial number ID, node point information CoreID, address, operation code Opcode, granularity Grid and Data, an instruction storage read-write control module and an instruction with an internal required ID released and stored in an instruction storage entity, so that a storage space is vacated, and a write Address pointer controls to store the ID information into the write Address pointer and simultaneously send the finishing instruction to the read-write control unit.

6. The authentication module of claim 5, wherein: when receiving instruction information from the read-write control unit, the write address pointer control module reads the ID in the write address pointer FIFO, stores the instruction information from the read-write control unit into the instruction storage entity according to the address relation between the ID and the instruction storage entity, updates the corresponding State vector, and simultaneously writes the ID from the write address pointer FIFO into the FIFO of the read address pointer;

when receiving a completion instruction from the instruction submitting arbitration unit, the instruction storage read-write control module reads the instruction of the instruction storage entity according to the address relation between the ID in the completion instruction information and the instruction storage entity, updates the corresponding State vector, and simultaneously writes the ID in the completion instruction information into the write address pointer FIFO.

7. The verification method is based on the construction of a verification module, and forms an automatic information flow aiming at the multi-node cache consistency system, and is characterized in that: the method comprises the following steps:

step S11: initializing a system, namely initializing a write address pointer FIFO in an instruction transceiving reservation station, namely storing all ID information into the write address FIFO by a write address pointer control module, fully writing the write address pointer, and establishing an address mapping relation between the ID and an instruction storage entity;

step S12: the read-write control unit reads the generated instruction information from an external memory outside the FPGA prototype verification system, wherein the instruction information comprises node information CoreID, address, operation code Opcode, granularity Grid and Data;

step S13: the instruction receiving and transmitting reservation station stores and encodes instruction information from the read-write control unit, the encoded instruction information comprises a reservation station internal serial number ID, node information CoreID, an Address, an operation code Opcode, granularity Grid and Data, and then the encoded instruction information is sent to a request Node Requset Node in a cache consistency system DUT of a multi-request Node to be tested;

step S14: the method comprises the steps that an instruction submitting arbitration unit receives a completion instruction of a request node Requsenode in a cache consistency system DUT of a multi-request node to be tested, completion instruction information comprises a reservation station internal serial number ID, node point information CoreID, address, operation code Opcode, granularity Grid and Data, an instruction completed by the instruction submitting arbitration unit is sent to an instruction receiving and sending reservation station, the instruction receiving and sending reservation station releases an instruction stored in an instruction storage entity, and then the completion instruction is sent to a read-write control unit;

step S15: the read-write control unit writes the received completion instruction into the external memory in a completion state, and is reserved for inspection and analysis.