CN117112485A - RISC-V instruction set-based automobile ultrasonic radar master control SoC chip - Google Patents

RISC-V instruction set-based automobile ultrasonic radar master control SoC chip Download PDF

Info

Publication number
CN117112485A
CN117112485A CN202310980966.5A CN202310980966A CN117112485A CN 117112485 A CN117112485 A CN 117112485A CN 202310980966 A CN202310980966 A CN 202310980966A CN 117112485 A CN117112485 A CN 117112485A
Authority
CN
China
Prior art keywords
ultrasonic radar
risc
ultrasonic
radar
instruction set
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310980966.5A
Other languages
Chinese (zh)
Inventor
王文林
何滇
张野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhu Research Institute of Xidian University
Original Assignee
Wuhu Research Institute of Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhu Research Institute of Xidian University filed Critical Wuhu Research Institute of Xidian University
Priority to CN202310980966.5A priority Critical patent/CN117112485A/en
Publication of CN117112485A publication Critical patent/CN117112485A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/93—Sonar systems specially adapted for specific applications for anti-collision purposes
    • G01S15/931—Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/539—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40234—Local Interconnect Network LIN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Signal Processing (AREA)
  • Acoustics & Sound (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The application discloses an automobile ultrasonic radar master control SoC chip based on RISC-V instruction set, comprising: a CPU based on RISC-V instruction set for controlling each part through AMBA bus; the LIN controller is used for sending the radar configuration parameters to a sensor end of the ultrasonic radar through the LIN bus to acquire echo data, and storing the echo data to the on-chip memory module after receiving the echo data through the LIN bus; the positioning module is used for positioning the obstacle based on the echo data after the echo data are read from the on-chip storage module, and storing the positioning result into the on-chip storage module; and the CAN FD controller is used for controlling the CAN FD bus to communicate with the outside, reading the positioning result in the on-chip memory module and transmitting the positioning result to the upper computer after receiving the transmission request. According to the application, the positioning module is designed based on the ultrasonic positioning algorithm, so that the processing capacity of the chip on ultrasonic radar signals is improved.

Description

RISC-V instruction set-based automobile ultrasonic radar master control SoC chip
Technical Field
The application belongs to the technical field of radars, and particularly relates to an automobile ultrasonic radar master control SoC chip based on a RISC-V instruction set.
Background
Ultrasonic waves have strong directivity and travel far in a medium, and are thus often used for distance measurement. The ultrasonic ranging forms an ultrasonic radar array through a plurality of ultrasonic radars, adopts a one-to-one multi-receiving mode, can realize accurate positioning of obstacles by matching with a related algorithm, and has the advantages of strong anti-interference capability, strong penetrability, small attenuation, simple principle, convenient manufacture, lower cost and the like. Ultrasonic radar is currently widely used in the automotive field, for example, in the related links of automatic driving or reversing assistance.
A System on Chip (SoC) is a complete System integrated on a single Chip, and the functions and performances of the Chip are greatly improved due to the integration of components including a processor, an accelerator, a bus, memory resources, a peripheral interface, and the like. However, the existing SoC is not specifically designed for the ultrasonic radar, and therefore the existing SoC cannot process the ultrasonic radar signal reasonably and efficiently.
Disclosure of Invention
In order to solve the problems in the prior art, the application provides an ultrasonic radar master control SoC chip based on a RISC-V kernel and an ultrasonic positioning method. The technical problems to be solved by the application are realized by the following technical scheme:
the application provides an automobile ultrasonic radar master control SoC chip based on RISC-V instruction set, comprising: a CPU, an on-chip memory module, a positioning module, a CAN FD controller and a local area network LIN controller based on a RISC-V instruction set; wherein,
the CPU based on RISC-V instruction set is used for controlling the on-chip memory module, the clock generator, the positioning module, the CAN FD controller and the local area network LIN controller through an AMBA bus;
the LIN controller is used for sending the radar configuration parameters to a sensor end of the ultrasonic radar through the LIN bus so that the sensor end can acquire echo data of the ultrasonic radar based on the radar configuration parameters, and after receiving the echo data through the LIN bus, the sensor end stores the echo data into the on-chip memory module;
the positioning module is used for positioning the obstacle based on the echo data after the echo data are read from the on-chip storage module, and storing the positioning result into the on-chip storage module;
and the CAN FD controller is used for controlling the CAN FD bus to communicate with other external systems, reading the positioning result in the on-chip memory module, and transmitting the positioning result to the upper computer after receiving a transmission request from the upper computer.
In one embodiment of the present application, the on-chip memory module includes a memory unit and an Error Correction Code (ECC) check unit; wherein,
the on-chip memory module is used for storing echo data of the ultrasonic radar;
and the error correction code ECC verification unit is used for storing a verification code into a special storage space after verifying the echo data stored in the on-chip storage module, and utilizing the verification code to verify the echo data when the on-chip storage module executes a reading operation on the stored echo data.
In one embodiment of the application, the positioning module comprises: the ultrasonic radar comprises a preprocessing unit, a data caching unit, an echo matching unit, a positioning operation unit and a result processing unit, wherein the ultrasonic radar comprises: the system comprises a first ultrasonic radar, a second ultrasonic radar, a third ultrasonic radar and a fourth ultrasonic radar, wherein the first ultrasonic radar is a radar sending out ultrasonic waves; wherein,
the preprocessing unit is used for calculating four groups of distance information according to the corrected sound velocity and echo data of the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar, and correcting the distance data in the four groups of distance information by utilizing the vehicle body speed; the four sets of distance information comprise obstacle distances calculated by the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar;
the data caching unit is used for storing the corrected four groups of distance information;
the echo matching unit is used for taking the distance information corrected by the first ultrasonic radar as reference distance information, taking one group containing the most distance data in the distance information corrected by the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar as distance information to be matched, and sequentially matching each distance data in the reference distance information with each distance data in the distance information to be matched;
the positioning operation unit is used for calculating the coordinates of each obstacle according to the matching result;
and the result processing unit is used for determining the distance of each obstacle according to the reference distance information, and settling the angle of each obstacle by combining the coordinates of each obstacle to obtain a positioning result.
In one embodiment of the present application, echo data of the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar, and the fourth ultrasonic radar respectively include: transmitting ultrasonic waves from the first ultrasonic radar until the time when an echo is detected by the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar, and the fourth ultrasonic radar;
the preprocessing unit corrects the sound velocity according to the following formula:
c＝c 0 +0.60714T；
wherein, c 0 Represents the sound velocity at 0 ℃, c 0 =335.1 m/s, T represents the ambient temperature.
In one embodiment of the present application, the preprocessing unit calculates distance information corresponding to the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar, and the fourth ultrasonic radar, respectively:
L 0 ＝(c·t)/2；
where t represents a time from when the first ultrasonic radar emits ultrasonic waves until an echo is detected by the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar, or the fourth ultrasonic radar itself, and c represents a sound velocity in the air.
In one embodiment of the application, the preprocessing unit corrects the distance data according to the following formula:
wherein v represents the vehicle body speed, L 0 Indicating distance data before correction.
In one embodiment of the present application, the result processing unit is further configured to generate a completion interrupt after obtaining the positioning result, and detect whether the CPU based on the RISC-V instruction set processes the positioning result within a preset period of time.
In one embodiment of the application, the system further comprises a Direct Memory Access (DMA) module;
if the CPU based on RISC-V instruction set does not process the positioning result in a preset time period, the result processing unit is further used for storing the positioning result to the on-chip memory module through a DMA module.
In one embodiment of the present application, the CAN FD controller is specifically configured to read the positioning result in the on-chip memory module through the DMA module.
In one embodiment of the present application, the apparatus further comprises a clock generator for providing clock signals of different frequencies to the RISC-V instruction set based CPU, on-chip memory module, positioning module, CAN FD controller and local interconnect network LIN controller through the AMBA bus.
Compared with the prior art, the application has the beneficial effects that:
the application provides an automobile ultrasonic radar master control SoC chip based on RISC-V instruction set, comprising: the system comprises a CPU (Central processing Unit) based on a RISC-V instruction set, an on-chip memory module, a positioning module, a CAN FD controller and a local area network LIN controller, wherein the positioning module is designed based on an ultrasonic positioning algorithm, so that a main control SoC chip applied to an ultrasonic radar is realized, and the structure of the SoC chip is more reasonable and efficient for processing ultrasonic radar signals.
The present application will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of an automobile ultrasonic radar master control SoC chip based on RISC-V instruction set provided in an embodiment of the present application;
fig. 2 is a schematic diagram of an Elmos radar interface module according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to specific examples, but embodiments of the present application are not limited thereto.
Fig. 1 is a schematic structural diagram of an automobile ultrasonic radar master control SoC chip based on RISC-V instruction set according to an embodiment of the present application. As shown in fig. 1, an embodiment of the present application provides an automobile ultrasonic radar master control SoC chip based on RISC-V instruction set, including: a CPU, an on-chip memory module, a positioning module, a CAN FD controller and a local area network LIN controller based on a RISC-V instruction set; wherein,
the CPU based on RISC-V instruction set is used for controlling the on-chip memory module, the clock generator, the positioning module, the CAN FD controller and the local area network LIN controller through the AMBA bus;
the LIN controller is used for sending the radar configuration parameters to the sensor end of the ultrasonic radar through the LIN bus so that the sensor end can acquire echo data of the ultrasonic radar based on the radar configuration parameters, and after receiving the echo data through the LIN bus, the LIN controller stores the echo data into the on-chip storage module;
the positioning module is used for positioning the obstacle based on the echo data after the echo data are read from the on-chip storage module, and storing the positioning result into the on-chip storage module;
and the CAN FD controller is used for controlling the CAN FD bus to communicate with other external systems, reading the positioning result in the on-chip memory module, and transmitting the positioning result to the upper computer after receiving a transmission request from the upper computer.
It should be noted that, the automobile ultrasonic radar master control SoC chip based on the RISC-V instruction set may further include a general peripheral module, where the general peripheral module is mainly a main function application interface, and the general peripheral module at least includes SPI, UART, I2C, PWM, WDT, TIMER, and may implement function call by using a CPU based on the RISC-V instruction set.
In this embodiment, a CPU based on a RISC-V instruction set is connected to an on-chip memory module, a positioning module, a CAN FD controller, a LIN (Local Interconnect Network ) controller, and a general peripheral module through an AMBA (Advanced Micro-Controller Bus Architecture) bus, so that a user CAN implement function call on an embedded program developed on the CPU, so that the above-mentioned ultrasonic radar main control SoC chip is suitable for most development scenarios.
Optionally, the on-chip memory module includes a memory unit and an error correction code ECC check unit; wherein,
the on-chip storage module is used for storing echo data of the ultrasonic radar;
and the error correction code ECC verification unit is used for storing the verification code into the special storage space after verifying the echo data stored in the on-chip storage module, and utilizing the verification code to verify the echo data when the on-chip storage module executes the reading operation on the stored echo data.
ECC (Error Correction Code ) is a check code technique for detecting and correcting errors in data transmission that enables a receiver to detect and correct errors that may be introduced during transmission by adding redundant information to the data.
Specifically, the ECC check unit in this embodiment adopts a Hamming Code, which is a Code widely used for memory and disk error correction, and can be used not only to detect errors occurring when transferring data, but also to correct errors. Illustratively, taking an n-bit binary code that needs to be checked as an example, in order to have error correction capability, k-bit detection bits are added to form an n+k-bit code. Then the newly added number of detection bits k should satisfy:
2 k -1≥n+k。
the coding rule of hamming codes is as follows:
s1, in newly encoded 2 (k-1) Filling 0 (i.e. check bit) on the (k is more than or equal to 0);
s2, filling the source codes into the rest bits of the new codes according to the original sequence;
s3, encoding check bits: the kth bit check code is from the newly encoded 2 nd bit (k-1) Bit start, 2 per calculation (k-1) Skip 2 after exclusive OR of bits (k-1) Bit, recalculate the next group 2 (k-1) Exclusive or of bits, fill in 2 (k-1) Bits.
For example: the 1 st bit check code is located at the 1 st bit (2 (1-1) =1), calculates the exclusive or of bits 1,3,5,7,9,11,13,15, …, then fills in the newly encoded bit 1; the 2 nd bit check code is located at the newly encoded 2 nd bit (2 (2-1) =2), calculates the xor of bits 2,3,6,7,10,11,14,15, …, and fills in the newly encoded bit 2; the 3 rd bit check code is located at the 4 th bit (2 (3-1) =4), calculates the exclusive or of the 4,5,6,7,12,13,14,15,20,21,22,23 th and … th bits, fills in the 4 th bit … … of the new code, and so on, to complete the coding of all check bits.
According to the embodiment, the ECC check unit is introduced into the on-chip memory module of the chip, so that the data stored in the on-chip memory module can be checked, and the check code is stored into the special memory space of the ECC check unit, so that the check code and the data in the special memory space can be checked when the on-chip memory module executes the data reading operation, the correctness of the data in the on-chip memory module is further ensured, and meanwhile, the functional safety of the chip can be ensured.
Further, the positioning module includes: the ultrasonic radar comprises a preprocessing unit, a data caching unit, an echo matching unit, a positioning operation unit and a result processing unit, wherein the ultrasonic radar comprises: the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar, wherein the first ultrasonic radar is a radar sending out ultrasonic waves; wherein,
the preprocessing unit is used for calculating four groups of distance information according to the corrected sound velocity and echo data of the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar, and correcting the distance data in the four groups of distance information by utilizing the vehicle body speed; the four sets of distance information comprise obstacle distances calculated by the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar;
the data caching unit is used for storing the corrected four groups of distance information;
the echo matching unit is used for taking the distance information corrected by the first ultrasonic radar as reference distance information, taking one group containing the most distance data in the distance information corrected by the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar as distance information to be matched, and sequentially matching each distance data in the reference distance information with each distance data in the distance information to be matched;
a positioning operation unit for calculating the coordinates of each obstacle according to the matching result;
and the result processing unit is used for determining the distance of each obstacle according to the reference distance information, and settling the angle of each obstacle by combining the coordinates of each obstacle to obtain a positioning result.
Wherein echo data of the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar respectively include: transmitting ultrasonic waves from the first ultrasonic radar until the time when an echo is detected by the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar, and the fourth ultrasonic radar;
the preprocessing unit corrects the sound velocity according to the following formula:
c＝c 0 +0.60714T；
wherein, c 0 Represents the sound velocity at 0 ℃, c 0 =335.1 m/s, T represents the ambient temperature.
The preprocessing unit calculates distance information corresponding to the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar according to the following formula:
L 0 ＝(c·t)/2；
where t represents a time from when the first ultrasonic radar emits ultrasonic waves until an echo is detected by the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar, or the fourth ultrasonic radar itself, and c represents a sound velocity in the air.
It should be appreciated that since the first ultrasonic radar continuously emits ultrasonic waves during the running of the vehicle, each ultrasonic radar continuously detects echoes and calculates a set of distance information including a plurality of distance data, respectively.
The preprocessing unit corrects the distance data according to the following formula:
wherein v represents the vehicle body speed, L 0 Indicating distance data before correction.
Specifically, for each ultrasonic radar, if the time from emission to detection of ultrasonic wave is t, the sound velocity c at 0 ℃ is first corrected based on the ambient temperature transmitted by the CPU of the RISC-V instruction set 0 The preprocessing unit calculates the distance between the obstacle and the ultrasonic radar by L= (c.t)/2, and then the preprocessing unit receives the vehicle body speed transmitted by the CPU based on RISC-V instruction set to further pair the distance data L 0 Correcting; wherein the corrected sound velocity c' =c 0 +0.60714T, corrected distance data is
Therefore, the positioning operation unit is based on a hardware circuit designed by a parallel operation circuit corresponding to the ultrasonic positioning algorithm, according to the characteristics of the ultrasonic positioning algorithm, the hardware circuit can be used for realizing floating point operation and matrix operation with large calculation amount and long time consumption in a modularized mode, and the characteristics of circuit parallel operation are utilized, so that the acceleration processing is realized, and the operation performance is improved.
Optionally, the result processing unit is further configured to generate a completion interrupt after obtaining the positioning result, and detect whether the CPU based on the RISC-V instruction set processes the positioning result within a preset period of time.
The automobile ultrasonic radar master control SoC chip based on the RISC-V instruction set also comprises a direct memory access DMA module;
if the CPU based on the RISC-V instruction set does not process the positioning result in the preset time period, the result processing unit is further used for storing the positioning result to the on-chip memory module through the DMA module.
Optionally, the CAN FD controller is specifically configured to read, by using the DMA module, the positioning result in the on-chip memory module.
In this embodiment, after completing settlement of coordinates, angles and distances of the obstacle, the result processing unit generates a completion interrupt, waits for the CPU processing based on the RISC-V instruction set, and if the CPU does not process in time, on the one hand, the result processing unit stores the positioning result into the on-chip memory module through the DMA (Direct Memory Access ) module. DMA is a technique for efficiently transferring data in a computer system by introducing a special DMA controller to which the data transfer is to be done without direct processing by the CPU. The DMA controller can independently access the system memory and directly perform data transmission with the peripheral equipment, thereby reducing the load of the CPU. In the process of using DMA to transfer data, the peripheral device sends a data transfer request to the DMA controller, and the DMA controller directly reads data from the peripheral device after acquiring the data transfer request, writes the data into a designated position in the system memory or reads the data from the system memory, and writes the data into the designated position of the peripheral device. After the transmission is completed, the DMA controller sends a signal of the completion of the transmission to the external device.
In addition, after the result processing unit obtains the positioning result through settlement, the result processing unit can obtain radar configuration parameters such as a detection range and a detection angle through a CPU, and respectively compare the distance and the detection range of the obstacle with the angle and the detection angle of the obstacle, if the angle of the obstacle exceeds the detection angle of the radar or the distance exceeds the detection range of the radar due to factors such as noise or errors, the result processing unit generates error interruption, the CPU reads the error interruption based on a RISC-V instruction set, and the parameter of the ultrasonic radar is reconfigured.
Optionally, the automobile ultrasonic radar master control SoC chip based on the RISC-V instruction set further includes a clock generator, where the clock generator is configured to provide clock signals with different frequencies to the CPU, the on-chip memory module, the positioning module, the CAN FD controller and the local interconnect network LIN controller based on the RISC-V instruction set through the AMBA bus.
Optionally, the automobile ultrasonic radar master control SoC chip based on RISC-V instruction set further comprises a clock generator and an Elmos radar interface module. Fig. 2 is a schematic diagram of an Elmos radar interface module according to an embodiment of the present application. As shown in fig. 2, since only one data line is used for communication between the ultrasonic radar and the main control chip and a special communication protocol is adopted, the embodiment designs a radar interface module for the IO port protocol of the Elmos radar, and the CPU can control the module to send a corresponding instruction to the radar or read and configure related parameters of the radar by configuring a corresponding register.
After the CPU SENDs a SEND or RECEIVE command through the interface module, the radar SENDs or RECEIVEs ultrasonic waves and outputs the ultrasonic waves to the IO port, the interface module records time data of the ultrasonic radar for detecting echo by matching with the timer peripheral module through monitoring the waveform of the IO port, and after detecting the detection completion information of the ultrasonic radar, the data are stored into the on-chip storage module through DMA.
According to the above embodiments, the beneficial effects of the application are as follows:
the application provides an automobile ultrasonic radar master control SoC chip based on RISC-V instruction set, comprising: the system comprises a CPU (Central processing Unit) based on a RISC-V instruction set, an on-chip memory module, a positioning module, a CAN FD controller and a local area network LIN controller, wherein the positioning module is designed based on an ultrasonic positioning algorithm, so that a main control SoC chip applied to an ultrasonic radar is realized, and the structure of the SoC chip is more reasonable and efficient for processing ultrasonic radar signals.
In the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The description of the terms "one embodiment," "some embodiments," "example," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims.
The foregoing is a further detailed description of the application in connection with the preferred embodiments, and it is not intended that the application be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.

Claims (10)

1. An automobile ultrasonic radar master control SoC chip based on RISC-V instruction set, which is characterized by comprising: a CPU, an on-chip memory module, a positioning module, a CAN FD controller and a local area network LIN controller based on a RISC-V instruction set; wherein,
the CPU based on RISC-V instruction set is used for controlling the on-chip memory module, the clock generator, the positioning module, the CAN FD controller and the local area network LIN controller through an AMBA bus;
the LIN controller is used for sending the radar configuration parameters to a sensor end of the ultrasonic radar through the LIN bus so that the sensor end can acquire echo data of the ultrasonic radar based on the radar configuration parameters, and after receiving the echo data through the LIN bus, the sensor end stores the echo data into the on-chip memory module;
the positioning module is used for positioning the obstacle based on the echo data after the echo data are read from the on-chip storage module, and storing the positioning result into the on-chip storage module;
and the CAN FD controller is used for controlling the CAN FD bus to communicate with other external systems, reading the positioning result in the on-chip memory module, and transmitting the positioning result to the upper computer after receiving a transmission request from the upper computer.
2. The automobile ultrasonic radar master control SoC chip based on RISC-V instruction set according to claim 1, wherein the on-chip memory module comprises a memory unit and an error correction code ECC check unit; wherein,
the on-chip memory module is used for storing echo data of the ultrasonic radar;
and the error correction code ECC verification unit is used for storing a verification code into a special storage space after verifying the echo data stored in the on-chip storage module, and utilizing the verification code to verify the echo data when the on-chip storage module executes a reading operation on the stored echo data.
3. The RISC-V instruction set based automotive ultrasonic radar master control SoC chip of claim 2, wherein the positioning module includes: the ultrasonic radar comprises a preprocessing unit, a data caching unit, an echo matching unit, a positioning operation unit and a result processing unit, wherein the ultrasonic radar comprises: the system comprises a first ultrasonic radar, a second ultrasonic radar, a third ultrasonic radar and a fourth ultrasonic radar, wherein the first ultrasonic radar is a radar sending out ultrasonic waves; wherein,
the preprocessing unit is used for calculating four groups of distance information according to the corrected sound velocity and echo data of the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar, and correcting the distance data in the four groups of distance information by utilizing the vehicle body speed; the four sets of distance information comprise obstacle distances calculated by the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar;
the data caching unit is used for storing the corrected four groups of distance information;
the echo matching unit is used for taking the distance information corrected by the first ultrasonic radar as reference distance information, taking one group containing the most distance data in the distance information corrected by the second ultrasonic radar, the third ultrasonic radar and the fourth ultrasonic radar as distance information to be matched, and sequentially matching each distance data in the reference distance information with each distance data in the distance information to be matched;
the positioning operation unit is used for calculating the coordinates of each obstacle according to the matching result;
and the result processing unit is used for determining the distance of each obstacle according to the reference distance information, and settling the angle of each obstacle by combining the coordinates of each obstacle to obtain a positioning result.
4. The RISC-V instruction set-based automotive ultrasonic radar master control SoC chip of claim 3, wherein echo data of the first, second, third and fourth ultrasonic radars respectively include: transmitting ultrasonic waves from the first ultrasonic radar until the time when an echo is detected by the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar, and the fourth ultrasonic radar;
the preprocessing unit corrects the sound velocity according to the following formula:
c＝c 0 +0.60714T；
wherein, c 0 Represents the sound velocity at 0 ℃, c 0 =335.1 m/s, T represents the ambient temperature.
5. The SoC chip of claim 4, wherein the preprocessing unit calculates distance information corresponding to the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar, and the fourth ultrasonic radar, respectively:
L 0 ＝(c·t)/2；
where t represents a time from when the first ultrasonic radar emits ultrasonic waves until an echo is detected by the first ultrasonic radar, the second ultrasonic radar, the third ultrasonic radar, or the fourth ultrasonic radar itself, and c represents a sound velocity in the air.
6. The automobile ultrasonic radar master control SoC chip based on RISC-V instruction set of claim 5, wherein the preprocessing unit corrects the distance data according to the following formula:
wherein v represents the vehicle body speed, L 0 Indicating distance data before correction.
7. The RISC-V instruction set based automotive ultrasonic radar master control SoC chip as claimed in claim 3, wherein the result processing unit is further configured to generate a completion interrupt after obtaining a positioning result, and to detect whether the RISC-V instruction set based CPU processes the positioning result within a preset time period.
8. The automobile ultrasonic radar master control SoC chip based on RISC-V instruction set of claim 7, further comprising a direct memory access DMA module;
if the CPU based on RISC-V instruction set does not process the positioning result in a preset time period, the result processing unit is further used for storing the positioning result to the on-chip memory module through a DMA module.
9. The automobile ultrasonic radar master control SoC chip based on the RISC-V instruction set of claim 8, wherein the CAN FD controller is specifically configured to read the positioning result in the on-chip memory module through the DMA module.
10. The RISC-V instruction set based automotive ultrasonic radar master control SoC chip of claim 1, further comprising a clock generator for providing clock signals of different frequencies to the RISC-V instruction set based CPU, on-chip memory module, positioning module, CAN FD controller and local interconnect network LIN controller through the AMBA bus.
CN202310980966.5A 2023-08-04 2023-08-04 RISC-V instruction set-based automobile ultrasonic radar master control SoC chip Pending CN117112485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310980966.5A CN117112485A (en) 2023-08-04 2023-08-04 RISC-V instruction set-based automobile ultrasonic radar master control SoC chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310980966.5A CN117112485A (en) 2023-08-04 2023-08-04 RISC-V instruction set-based automobile ultrasonic radar master control SoC chip

Publications (1)

Publication Number Publication Date
CN117112485A true CN117112485A (en) 2023-11-24

Family

ID=88811935

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310980966.5A Pending CN117112485A (en) 2023-08-04 2023-08-04 RISC-V instruction set-based automobile ultrasonic radar master control SoC chip

Country Status (1)

Country Link
CN (1) CN117112485A (en)

Similar Documents

Publication Publication Date Title
US11108499B2 (en) System and method for transferring data and a data check field
US7810013B2 (en) Memory device that reflects back error detection signals
US7984357B2 (en) Implementing minimized latency and maximized reliability when data traverses multiple buses
US20090024775A1 (en) Dual core architecture of a control module of an engine
EP2460085A1 (en) Device identifier selection
CN101901170A (en) Data processing equipment and be used for error-detecting and method of its error calibration
KR20150067896A (en) Serial communication test device, system including the same and method thereof
US8972838B2 (en) Data transmission detecting device, data transmission detecting method and electronic device thereof
CN102467975B (en) Data error check method, data transmission method and semiconductor storage
JP2021526649A (en) Ultrasonic radar arrays, obstacle detection methods, devices, storage media, programs and systems
US20230065623A1 (en) Processing system error management, related integrated circuit, apparatus and method
US11902297B2 (en) Controlled message error for message and electronic control unit mapping
CN117112485A (en) RISC-V instruction set-based automobile ultrasonic radar master control SoC chip
US20110066925A1 (en) Error detection
US10769085B2 (en) Bus system
US8392654B2 (en) Raid level migration for spanned arrays
WO2020107176A1 (en) Obstacle detection method and device
CN115158341A (en) Vehicle fault uploading method and device based on functional safety design
JP3170145B2 (en) Memory control system
KR20170100416A (en) Integrated circuit system
US20230280933A1 (en) Processing system, related integrated circuit, device and method
RU2566336C1 (en) METHOD OF CORRECTING ERRORS WHEN TRANSMITTING INFORMATION VIA Manchester-II DOUBLE-PULSE CODE AND DEVICE THEREFOR
TWI797905B (en) Apparatus and method for driving redundant array of independent disks (raid) engine
US20240134743A1 (en) Electronic device, electronic system, method for operating an electronic device, and method for operating an electronic system
US9230290B2 (en) Power meter consumption system and method to verify data stored in a register by comparing an address of the register with request for data of the register

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination