CN117098400A

CN117098400A - Integrated circuit chip and forming method thereof

Info

Publication number: CN117098400A
Application number: CN202310813434.2A
Authority: CN
Inventors: 陈姿妤; 黄楚杰; 陈宛桢; 张富宸; 石昇弘; 涂国基
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-07-28
Filing date: 2023-07-04
Publication date: 2023-11-21

Abstract

Various embodiments of the present disclosure are directed to memory cells including a barrier layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More specifically, the barrier layer and the ferroelectric layer are located between a top electrode of the memory cell and a bottom electrode of the memory cell, both comprising metal. Furthermore, a barrier layer is located between the ferroelectric layer and an electrode corresponding to one of the top electrode and the bottom electrode. In some embodiments, the metal of one of the top and bottom electrodes has the lowest electronegativity among the metals of the top and bottom electrodes, and is therefore the most reactive, and may diffuse between the metals of the top and bottom electrodes. Embodiments of the application also relate to integrated circuit chips and methods of forming the same.

Description

Integrated circuit chip and forming method thereof

Technical Field

Embodiments of the present application relate to the field of semiconductor technology, and more particularly, to an integrated circuit chip and a method of forming the same.

Background

Many modern electronic devices include non-volatile memory. Nonvolatile memory is electronic memory that is capable of storing data without electricity. A promising candidate for the next generation of nonvolatile memory includes ferroelectric random access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with Complementary Metal Oxide Semiconductor (CMOS) logic fabrication processes.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided an integrated circuit chip including a memory cell, wherein the memory cell includes: a first electrode and a second electrode, each comprising a metal; a ferroelectric layer between the first electrode and the second electrode; and a barrier layer between the ferroelectric layer and the first electrode; wherein the barrier layer is configured to block diffusion of the first metal of the first electrode into the ferroelectric layer, and wherein the first metal of the first electrode has a lower electronegativity than the second metal of the second electrode.

According to another aspect of an embodiment of the present application, there is provided an integrated circuit chip including a memory cell, wherein the memory cell includes: a bottom electrode located at the bottom of the memory cell; a top electrode at the top of the memory cell; a ferroelectric layer between the bottom electrode and the top electrode; and a diffusion barrier layer between the ferroelectric layer and the first electrode, wherein the first electrode is one of a bottom electrode and a top electrode, and wherein the first electrode comprises a metal having an electronegativity of less than about 1.6.

According to yet another aspect of an embodiment of the present application, there is provided a method of forming an integrated circuit chip, comprising: forming a bottom electrode over a substrate; depositing a stacked barrier layer, ferroelectric layer, and top electrode layer over a substrate; patterning the top electrode layer to form a top electrode; and patterning the barrier layer and the ferroelectric layer to delineate sections of the barrier layer and the ferroelectric layer that are separate from the memory cells; wherein after patterning the barrier layer and the ferroelectric layer, the bottom electrode and the top electrode and the segments of the barrier layer and the ferroelectric layer form a memory cell, wherein the bottom electrode and the top electrode comprise a metal, and wherein the barrier layer is located between the ferroelectric layer and the electrode having the lowest metal electronegativity among the bottom electrode and the top electrode.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of some embodiments of a memory cell including a barrier layer.

Fig. 2A and 2B illustrate cross-sectional views of some alternative embodiments of the memory cell of fig. 1.

Fig. 3A and 3B illustrate various views of some embodiments of the memory cell of fig. 1, where the memory cell is integrated into an interconnect structure of an Integrated Circuit (IC) chip.

Fig. 4A and 4B illustrate various views of some alternative embodiments of the memory cell of fig. 3A and 3B, in which the top electrode width is reduced relative to the rest of the memory cell.

Fig. 5 shows a cross-sectional view of some alternative embodiments of the memory cell of fig. 4A and 4B.

Fig. 6A and 6B illustrate various views of some alternative embodiments of the memory cell of fig. 3A and 3B, wherein the composition of the memory cell has a U-shaped profile.

Fig. 7A and 7B illustrate various views of some alternative embodiments of the memory cell of fig. 3A and 3B, with a top electrode surrounding a bottom electrode.

Fig. 8 shows a cross-sectional view of some alternative embodiments of the memory cell of fig. 3A and 3B, wherein the barrier layer is located at the bottom electrode.

9A-9D illustrate cross-sectional views of some alternative embodiments of the memory cell of FIG. 8.

Fig. 10 shows a cross-sectional view of some alternative embodiments of the memory cell of fig. 3A and 3B, where the memory cell has a barrier layer at the bottom electrode and a barrier layer at the top electrode.

11A-11D illustrate cross-sectional views of some alternative embodiments of the memory cell of FIG. 10.

Fig. 12A and 12B illustrate cross-sectional views of some embodiments of an IC chip including a memory cell integrated into a separate one-transistor-capacitor (1T 1C) cell and configured as in fig. 3A and 3B.

Fig. 13 illustrates a cross-sectional view of some alternative embodiments of the IC chip of fig. 12A and 12B.

Fig. 14 illustrates a top layout view of some embodiments of the IC chip of fig. 12A and 12B.

Fig. 15 illustrates a cross-sectional view of some embodiments of an IC chip including a ferroelectric field effect transistor (FeFET) that includes a barrier layer.

Fig. 16A and 16B illustrate cross-sectional views of some alternative embodiments of the FeFET of fig. 15.

17-27 illustrate a series of cross-sectional views of some embodiments of a method for forming an IC chip including a memory cell integrated into a separate 1T1C cell and including a barrier layer.

Fig. 28 shows a block diagram of some embodiments of the methods of fig. 17-27.

Fig. 29-36 show a series of cross-sectional views of some alternative embodiments of the method of fig. 17-27.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

An Integrated Circuit (IC) chip may include an interconnect structure and memory cells in the interconnect structure. The memory cell includes a bottom electrode, a ferroelectric layer over and in direct contact with the bottom electrode, and a top electrode over and in direct contact with the ferroelectric layer. The interconnect structure includes a bottom electrode lead below the memory cell and a top electrode lead above the memory cell. Further, the interconnect structure includes vias extending from the bottom electrode lead and the top electrode lead to the bottom electrode and the top electrode, respectively.

One challenge with memory cells is that the top electrode may comprise a metal with low electronegativity (electronegativity), and/or the bottom electrode may comprise a metal with low electronegativity. Such low electronegativity may be, for example, less than about 1.6 or some other suitable value. Metals with low electronegativity have a high reactivity and therefore a high tendency to diffuse during annealing. Thus, during annealing to increase the ferroelectric phase of the ferroelectric layer, the metal of the top electrode and/or the metal of the bottom electrode may have a high tendency to diffuse towards the ferroelectric layer.

The metal diffused from the top electrode and/or bottom electrode into the ferroelectric layer can negatively impact the performance of the ferroelectric layer and thus the memory cell. For example, the ferroelectric phase may be reduced, the remnant polarization (2 Pr) may be reduced, the polarization uniformity may be reduced, the leakage current may be increased, the capacitance may be reduced, the data retention may be degraded, the breakdown voltage may be reduced, or any combination of the foregoing.

Various embodiments of the present disclosure are directed to memory cells including a barrier layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More specifically, the barrier layer and ferroelectric layer are located between a top electrode of the memory cell and a bottom electrode of the memory cell, and the top electrode and the bottom electrode comprise separate metals. Furthermore, a barrier layer is located between the ferroelectric layer and one of the top electrode and the bottom electrode. In some embodiments, the metal of one of the top and bottom electrodes has the lowest electronegativity among the metals of the top and bottom electrodes, and is therefore the most reactive, and may diffuse between the metals of the top and bottom electrodes.

Due to the barrier layer, diffusion of metal into the ferroelectric layer may be minimized, including during annealing in order to increase the ferroelectric phase of the ferroelectric layer. By preventing diffusion of metal into the ferroelectric layer, the performance of the ferroelectric layer and thus the memory cell can be enhanced. For example, the ferroelectric phase may be increased, the remnant polarization (2 Pr) may be increased, the polarization uniformity may be increased, the leakage current may be reduced, the capacitance may be increased, the data retention may be enhanced, the breakdown voltage may be enhanced, or any combination of the foregoing. Furthermore, the memory cells are compatible with logic manufacturing processes, whereby the memory device cells may be used for embedded memory applications.

Referring to fig. 1, a cross-sectional view 100 of some embodiments of a memory cell 102 is provided in which a barrier layer 104 is configured to block diffusion of metal from a top electrode 106 to a ferroelectric layer 108. In some embodiments, the barrier layer 104 may additionally or alternatively be referred to as an interfacial layer, a hybrid layer, a diffusion barrier layer, or the like, or any combination of the foregoing. The memory cell 102 may be or include, for example, a metal-ferroelectric-metal (MFM) cell, a ferroelectric capacitor, a Ferroelectric Tunnel Junction (FTJ), or the like, or any combination of the foregoing.

Ferroelectric layer 108 is over bottom electrode 110, barrier layer 104 is over ferroelectric layer 108, and top electrode 106 is over barrier layer 104. In addition, the bottom electrode 110 and the top electrode 106 include separate metals, and the metals of the bottom electrode 110 and the top electrode 106 have high electronegativity and low electronegativity, respectively. Note that the low electronegativity is schematically shown by the diagonal lines on the top electrode 106. The metal of the top electrode 106 has a high reactivity due to low electronegativity and thus has a high tendency to diffuse into the ferroelectric layer 108. In contrast, the metal of the bottom electrode 110 has low reactivity due to high electronegativity, and thus has a low tendency to diffuse into the ferroelectric layer 108.

In some embodiments, the high electronegativity and the low electronegativity are related to each other. In some embodiments, the high electronegativity is an electronegativity that is greater than about 1.6, about 2.0, or some other suitable value, and/or an electronegativity that is about 1.6-2.4, about 1.6-2.0, about 2.0-2.4, or some other suitable value. In some embodiments, the low electronegativity is an electronegativity of less than about 1.6, about 1.5, or some other suitable value, and/or an electronegativity of about 1.1-1.6, or some other suitable value.

The metal diffused into the ferroelectric layer 108 negatively affects the ferroelectric layer 108 and thus the performance of the memory cell 102. Since the bottom electrode 110 has high electronegativity, diffusion of metal from the bottom electrode 110 to the ferroelectric layer 108 may be minimal. In contrast, because the top electrode 106 has low electronegativity, diffusion of metal from the top electrode 106 to the ferroelectric layer 108 may be significant. Thus, the placement of the barrier layer 104 between the top electrode 106 and the ferroelectric layer 108 may significantly reduce diffusion of metal into the ferroelectric layer 108. Furthermore, the barrier layer 104 may be more effective in reducing diffusion of metal into the ferroelectric layer 108 than if the barrier layer 104 were between the bottom electrode 110 and the ferroelectric layer 108.

By reducing diffusion of metal into ferroelectric layer 108, barrier layer 104 enhances the performance of ferroelectric layer 108 and, thus, memory cell 102. For example, the ferroelectric phase may be increased, the remnant polarization (2 Pr) may be increased, the polarization uniformity may be increased, the leakage current may be reduced, the capacitance may be increased, the data retention may be enhanced, the breakdown voltage may be increased, or any combination of the foregoing. Furthermore, as will be better seen below, the fabrication of the barrier layer 104 is compatible with logic fabrication processes, whereby the barrier layer 104 may be used in memory cells of embedded memory applications.

The ferroelectric corresponds to an orthorhombic phase and is in contrast to a tetragonal and a monoclinic phase. The higher the ratio of orthorhombic phase to other crystalline phases, the higher the remnant polarization (2 Pr) and thus the better the data retention. Thus, the barrier layer 104 increases the ratio of the orthorhombic phase to other crystalline phases. The ferroelectric phase may be measured and/or quantified, for example, by x-ray diffraction (XRD), electron back-scattering diffraction (EBSD), and the like.

As described above, the bottom electrode 110 comprises a metal with high electronegativity and the top electrode 106 comprises a metal with low electronegativity. In some embodiments, the low electronegativity metal is or includes titanium (e.g., ti/electronegativity of 1.54), tantalum (e.g., ta/electronegativity of 1.51), lanthanum (e.g., la/electronegativity of 1.11), some other suitable metal, or any combination of the foregoing. In some embodiments, the high electronegativity metal is or includes molybdenum (e.g., mo/electronegativity of 2.16), tungsten (e.g., W/electronegativity of 2.36), ruthenium (e.g., ru/electronegativity of 2.2), osmium (e.g., os/electronegativity of 2.18), rhodium (e.g., rh/electronegativity of 2.28), iridium (e.g., ir/electronegativity of 2.2), palladium (e.g., pd/electronegativity of 2.2), platinum (e.g., pt/electronegativity of 2.28), copper (e.g., cu/electronegativity of 1.9), silver (e.g., ag/electronegativity of 1.93), gold (e.g., au/electronegativity of 2.54), aluminum (e.g., al/electronegativity of 1.61), some other suitable metal, or any combination of the foregoing.

In some embodiments, the barrier layer 104 is or includes silicon oxide (e.g., siOx), silicon nitride (e.g., siNx), metal oxide, high-k dielectric, some other suitable material, or any combination of the preceding. For example, the high-k dielectric may be a dielectric having a dielectric constant, for example, greater than about 3.9, about 10, or some other suitable value. In some embodiments, the barrier layer 104 is a dielectric. For example, the barrier layer 104 may be or include silicon oxide, silicon nitride, a high-k dielectric, or some other suitable dielectric. In some embodiments, the barrier layer 104 is a semiconductor. For example, the barrier layer 104 may be or include a semiconductive metal oxide or some other suitable semiconductive material. In some embodiments, the barrier layer 104 is electrically conductive. For example, the barrier layer 104 may be or include a conductive metal oxide or some other suitable conductive material.

In some embodiments where the barrier layer 104 is or includes a metal oxide, the metal of the metal oxide has a high electronegativity. In some embodiments, the electronegativity of the metal of the top electrode 106 is high. Further, in some embodiments, the high electronegativity is an electronegativity that is greater than about 1.6, about 2.0, or some other suitable value, and/or an electronegativity that is about 1.6-2.4, about 1.6-2.0, about 2.0-2.4, or some other suitable value.

In some embodiments, the barrier layer 104 includes a metal that diffuses from the top electrode 106 to the ferroelectric layer 108. In some embodiments, the barrier layer 104 has an amorphous structure to eliminate grain boundaries and increase diffusion path complexity. Alternatively, in some embodiments, the barrier layer 104 has a nanocrystalline structure, and the grains of the barrier layer 104 are equiaxed grains (equiaxed grains) rather than columnar grains, to increase the complexity of the diffusion path. By increasing diffusion path complexity, diffusion of metal through the barrier layer 104 is reduced.

In some embodiments, the thickness T of the barrier layer 104 _b About 2 to 50 angstroms, about 2 to 26 angstroms, about 26 to 50 angstroms, or someOther suitable values. If the thickness T _b Too small (e.g., less than 2 angstroms), the barrier layer 104 may not be able to effectively block the diffusion of metal from the top electrode 106 to the ferroelectric layer 108. If the thickness T _b Too large (e.g., greater than 50 angstroms), the resistance of the barrier layer 104 may be too high and may result in a low current flow through the memory cell 102.

In some embodiments, the metal of the top electrode 106 diffuses minimally into the ferroelectric layer 108 even with the barrier layer 104. For example, the atomic percent of metal in ferroelectric layer 108 may be less than about 10%, about 5%, about 1%, or some other suitable percentage of non-zero values, and/or may be about 1% -10%, about 1% -5%, about 5% -10%, or some other suitable percentage. In some embodiments, minimal diffusion occurs entirely or mostly during annealing to increase the ferroelectric phase of ferroelectric layer 108. In some such embodiments, the atomic percent of metal in ferroelectric layer 108 is less than 10% at the end of the anneal when barrier layer 104 is present, and greater than 30% at the end of the anneal when no barrier layer is present.

In some embodiments, ferroelectric layer 108 is or includes a binary oxide, a ternary oxide or nitride, a quaternary oxide, some other suitable ferroelectric material, or any combination of the preceding. The binary oxide may be or include, for example, hafnium oxide (e.g., hafnium oxide or HfO ₂ ) And/or some other suitable binary oxide. The ternary oxide or nitride can be or include, for example, hafnium silicate (e.g., hfSiO _x ) Hafnium zirconate (e.g. HfZrO _x ) Barium titanate (e.g. BaTiO) ₃ ) Lead titanate (e.g. PbTiO) ₃ ) Strontium titanate (e.g., srTiO ₃ ) Calcium manganite (e.g. CaMnO ₃ ) Bismuth ferrite (e.g. BiFeO) ₃ ) Aluminum scandium nitride (e.g., alScN), aluminum gallium nitride (e.g., alGaN), aluminum yttrium nitride (e.g., alYN), some other suitable ternary oxide and/or nitride, or any combination of the preceding. The quaternary oxide may be or include, for example, barium strontium titanate (e.g., baSrTiO _x ) And/or some other suitable quaternary oxide.

In some embodiments, ferroelectric layer 108 has a nonmetallic element that is more electronegative than the metal of top electrode 106. In such embodiments, the difference between the electronegativity of the nonmetallic element and the metal of the top electrode is at least 1.7, 1.84, or some other suitable value, and/or is about 1.6-2.5, about 1.6-2.05, about 2.05-2.5, about 1.9-2.33, or some other suitable value. The nonmetallic element may be, for example, oxygen or the like.

In some embodiments, the thickness T of the ferroelectric layer 108 _f About 10-200 angstroms, about 10-105 angstroms, about 105-200 angstroms, or some other suitable value. If the thickness T _f Too small (e.g., less than 10 angstroms) or too large (e.g., greater than 200 angstroms), ferroelectric layer 108 may not have a remnant polarization or may have a small remnant polarization that is unusable. In addition, if the thickness T _f Too large (e.g., greater than 200 angstroms), the resistance of ferroelectric layer 108 may be too high and may result in a low current flow through memory cell 102.

During operation of the memory cell 102, the remnant polarization of the ferroelectric layer 108 is used to represent bits of data. For example, the positive polarity of the remnant polarization may represent a binary "0", while the negative polarity of the remnant polarization may represent a binary "1", or vice versa.

To set the remnant polarization to positive polarity, a first write voltage is applied from the top electrode 106 across the ferroelectric layer 108 to the bottom electrode 110. To set the remnant polarization to negative polarity, a second write voltage is applied from the top electrode 106 across the ferroelectric layer 108 to the bottom electrode 110. The first write voltage and the second write voltage have opposite polarities and have magnitudes exceeding the coercive voltage. In some embodiments, to read the polarity of the remnant polarization, the remnant polarization is set to positive or negative as described above. If the polarity of the remnant polarization is changed, a current pulse may occur. Otherwise, no current pulses occur. Thus, the current pulses can be used to identify the polarity of the remnant polarization.

Referring to fig. 2A and 2B, cross-sectional views 200A, 200B of some alternative embodiments of the memory cell 102 in fig. 1 are provided.

In fig. 2A, the barrier layer 104 is located between the bottom electrode 110 and the ferroelectric layer 108, rather than between the top electrode 106 and the ferroelectric layer 106. In addition, the metal of the bottom electrode 110 has low electronegativity, while the metal of the top electrode 106 has high electronegativity. The low electronegativity is schematically shown by the diagonal lines on the bottom electrode 110. Further, non-limiting examples of low electronegativity metals and high electronegativity metals are described above.

The metal of the bottom electrode 110 has a high reactivity due to the low electronegativity and thus has a high tendency to diffuse towards the ferroelectric layer 108. In contrast, the metal of the top electrode 106 has low reactivity due to high electronegativity and thus has a low tendency to diffuse into the ferroelectric layer 108. Thus, by providing the barrier layer 104 between the bottom electrode 110 and the ferroelectric layer 108, diffusion of metal into the ferroelectric layer 108 may be significantly reduced. This may significantly enhance the performance of ferroelectric layer 108 and thus memory cell 102.

In some embodiments where the barrier layer 104 is or includes a metal oxide, the metal of the metal oxide has a high electronegativity. In some embodiments, the electronegativity of the metal of the bottom electrode 110 is high. Further, in some embodiments, the high electronegativity is an electronegativity that is greater than about 1.6, about 2.0, or some other suitable value, and/or an electronegativity that is about 1.6-2.4, about 1.6-2.0, about 2.0-2.4, or some other suitable value.

In fig. 2B, the memory cell 102 has a pair of barrier layers 104, each of which is a corresponding layer described in fig. 1. The first barrier layer 104a between the top electrode 106 and the ferroelectric layer 108 blocks diffusion of metal from the top electrode 106 to the ferroelectric layer 108. The second barrier layer 104b between the bottom electrode 110 and the ferroelectric layer 108 blocks diffusion of metal from the bottom electrode 110 into the ferroelectric layer 108. By blocking the diffusion of metal into the ferroelectric layer 108, the first barrier layer 104a and the second barrier layer 104b may significantly enhance the performance of the ferroelectric layer 108 and, thus, the memory cell 102.

In some embodiments, both the metal of the bottom electrode 110 and the metal of the top electrode 106 have low electronegativity. The low electronegativity is schematically illustrated by the diagonal lines on the bottom electrode 110 and the top electrode 106. In some embodiments, the low electronegativity is an electronegativity of less than about 1.6, about 1.5, or some other suitable value, and/or an electronegativity of about 1.1-1.6, or some other suitable value. Furthermore, in some embodiments in which the first barrier layer 104a and the second barrier layer 104b comprise a metal oxide, the low electronegativity is low relative to the electronegativity of the metal oxide. Non-limiting examples of low electronegativity metals are described above.

Although fig. 1 and 2A depict the barrier layer 104 being located at the electrode of the top electrode 106 and the bottom electrode 110 having the lowest metal electronegativity, this may not be the case in alternative embodiments. For example, the barrier layer 104 may alternatively be located at the electrode having the highest metal electronegativity, or the top electrode 106 and the bottom electrode 110 may have the same metal electronegativity, which may be high or low. Furthermore, although fig. 1 and 2A depict one of the top electrode 106 and the bottom electrode 110 as having a low metal electronegativity and the other of the top electrode 106 and the bottom electrode 110 as having a high metal electronegativity, in alternative embodiments this may be the opposite, or in alternative embodiments both the top electrode 106 and the bottom electrode 110 may have a low metal electronegativity or a high metal electronegativity. Although fig. 2B depicts the top electrode 106 and the bottom electrode 110 as having low metal electronegativity, the top electrode 106 and the bottom electrode 110 may also have high metal electronegativity.

Although fig. 1, 2A and 2B describe the metal of the bottom and top electrodes in electronegativity, the metal may also be described in electropositivity. Metals with low electronegativity have high electropositivity, while metals with high electronegativity have low electropositivity. Thus, top electrode 106 and bottom electrode 110 of fig. 1 may also be considered to have high and low electropositivity, respectively, and top electrode 106 and bottom electrode 110 of fig. 2A may also be considered to have low and high electropositivity, respectively. In addition, the top electrode 106 and the bottom electrode 110 of fig. 2B may be considered to have high electropositivity.

Referring to fig. 3A, a cross-sectional view 300A of some embodiments of the memory cell 102 of fig. 1 is provided, wherein the memory cell 102 is integrated into an interconnect structure 302 of an IC chip.

A top electrode lead 304t is over the memory cell 102 and a Top Electrode Via (TEVA) 306t extends downward from the top electrode lead 304 to the top electrode 106. A bottom electrode lead 304b is below the memory cell 102, and a Bottom Electrode Via (BEVA) 306b extends upward from the bottom electrode lead 304b to the bottom electrode 110. The BEVA 306b includes a BEVA barrier 308 and a BEVA body 310. The BEVA barrier 308 covers the underside of the BEVA body 310 to separate the BEVA body 320 from the bottom electrode lead 304b. In an alternative embodiment, the BEVA barrier 308 is omitted such that the BEVA body 310 directly contacts the bottom electrode lead 304b. For example, the BEVA barrier 308 may be configured to block or otherwise substantially reduce diffusion of material from the bottom electrode lead 304b to the bottom electrode 110.

In some embodiments, the top electrode lead 304t, TEVA 306t, and bottom electrode lead 304b are or include copper, aluminum, tungsten, or the like, or any combination of the foregoing. In some embodiments, BEVA body 310 is or includes: (1) The same material as the top electrode lead 304t, TEVA 306t, bottom electrode lead 304b, or any combination of the foregoing; (2) the same material as BEVA barrier 308; (3) the same material as the bottom electrode 110; (4) some other suitable material; or (5) any combination of the foregoing. In some embodiments, BEVA barrier 308 is or includes titanium nitride, platinum, aluminum copper, gold, titanium, tantalum nitride, tungsten nitride, or the like, or any combination of the foregoing. In some embodiments, the BEVA barrier 308 has a thickness of about 50-200 angstroms or some other suitable value.

The hard mask 312 is over the top electrode 106, and the TEVA 306t extends from the top electrode lead 304t through the hard mask 312 to the top electrode 106. In an alternative embodiment, hard mask 312 is omitted. For example, the hard mask 312 may be or include titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, metal oxides, some other suitable material, or any combination of the preceding. The metal oxide may be or comprise, for example, titanium oxide, aluminum oxide, some other suitable metal oxide, or any combination of the preceding. In some embodiments, the hard mask 312 has a thickness of about 50-400 angstroms or some other suitable value.

As described with respect to fig. 1, the barrier layer 104 is configured to block diffusion of metal of the top electrode 106 into the ferroelectric layer 108. This in turn may enhance the performance of ferroelectric layer 108.

The bottom electrode 110, ferroelectric layer 108, barrier layer 104, top electrode 106, and hard mask 312 share a common width and form a pair of common sidewalls on opposite sides of the memory cell 102, respectively. Furthermore, the common side wall has a planar profile, but may alternatively have a curved profile or other suitable profile.

Sidewall spacer structures 314 are located on the common sidewalls. The sidewall spacer structure 314 may be or comprise, for example, titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, metal oxide, some other suitable material, or any combination of the preceding. The metal oxide may be or comprise, for example, titanium oxide, aluminum oxide, some other suitable metal oxide, or any combination of the preceding. In some embodiments, the sidewall spacer structures 314 are the same material as the hard mask 312.

A plurality of inter-metal dielectric (IMD) layers 316 surround the bottom electrode lead 304b and the top electrode lead 304t, respectively. In addition, the IMD layer 316 is separated by a first etch stop layer 318, a second etch stop layer 320, and a buffer layer 322. The first etch stop layer 318 surrounds the BEVA 306b vertically between the bottom electrode lead 304b and the memory cell 102. The second etch stop layer 320 and the buffer layer 322 cover and conform to the first etch stop layer 318 and the memory cell 102. In addition, a second etch stop layer 320 is located between the buffer layer 322 and the memory cell 102.

For example, IMD layer 316 may be or include silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, some other suitable dielectric, or any combination of the preceding. The first etch stop layer 318 and/or the second etch stop layer 320 may be or include, for example, a metal nitride, a metal oxide, a metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, some other suitable dielectric, or any combination of the preceding. In some embodiments, first etch stop layer 318 and second etch stop layer 320 are the same material. In some embodiments, the thickness of the first etch stop layer 318 is about 150-350 angstroms or some other suitable value. In some embodiments, the thickness of the second etch stop layer 320 is about 50-300 angstroms or some other suitable value. Buffer layer 322 may be or include, for example, tetraethyl orthosilicate (TEOS) oxide and/or some other suitable dielectric. In some embodiments, buffer layer 322 has a thickness of about 50-300 angstroms or some other suitable value.

Referring to fig. 3B, a top layout view 300B of some embodiments of the memory cell 102 of fig. 3A is provided. Further, the top-down layout of BEVA 306b and TEVA 306t is shown in dashed lines above memory cell 102. For example, the cross-sectional view 300A of FIG. 3A may be taken along line A-A'. Memory cells 102 have a square or rectangular top-down layout, but may alternatively have a circular top-down layout or some other suitable top-down layout. BEVA 306b and TEVA 306t have square or rectangular top-down layouts, but may have other suitable top-down layouts.

Referring to fig. 4A, a cross-sectional view 400A of some alternative embodiments of the memory cell 102 of fig. 3A is provided in which the top electrode width is reduced relative to the rest of the memory cell 102.

The bottom electrode 110, ferroelectric layer 108, and barrier layer 104 share a first common width and form a pair of first common sidewalls 402 on opposite sides of the memory cell 102, respectively. In addition, the top electrode 106 and the hard mask 312 share a second common width and form a pair of second common sidewalls 404 on opposite sides of the memory cell 102, respectively. The second common width is less than the first common width and the second common sidewalls 404 are laterally between the first common sidewalls 402. In addition, the second common sidewall 404 is covered by the sidewall spacer structure 314 over the barrier layer 104. The first common sidewall 402 and the second common sidewall 404 have planar profiles, but other suitable profiles are also suitable.

Referring to fig. 4B, a top layout 400B of some embodiments of the memory cell 102 of fig. 4A is provided. Further, the top-down layout of BEVA 306b and TEVA 306t is shown in dashed lines above memory cell 102. For example, the cross-sectional view 400A of FIG. 4A may be taken along line B-B'. The memory cells 102 have a square or rectangular top-down layout and the second common sidewalls 404 are laterally offset from and between the first common sidewalls 402. In alternative embodiments, the memory cells 102 may have a circular top-down layout or some other suitable top-down layout. BEVA 306b and TEVA 306t have square or rectangular top-down layouts, but may have other suitable top-down layouts.

Referring to fig. 5, a cross-sectional view 500 of some alternative embodiments of the memory cell 102 of fig. 4A is provided, wherein the BEVA barrier 308 and the BEVA body 310 are omitted. In addition, the bottom electrode barrier 502 and the bottom electrode 110 form the BEVA 306b. The bottom electrode barrier 502 is located between the bottom electrode 110 and the bottom electrode lead 304b, and may be, for example, the BEVA barrier 308 shown in fig. 3A. The bottom electrode barrier 502, bottom electrode 110, ferroelectric layer 108, barrier layer 104, top electrode 106, and hard mask 312 are recessed at BEVA 306b, and TEVA 306t is laterally offset from the center of memory cell 102.

Referring to fig. 6A, a cross-sectional view 600A of some alternative embodiments of the memory cell 102 of fig. 3A is provided, wherein the BEVA 306b, BEVA barrier 308, BEVA body 310, sidewall spacer structure 314, second etch stop layer 320, and hard mask 312 are omitted. In this way, the memory cell 102 extends from the bottom electrode lead 304 b. In addition, bottom electrode barrier 502, bottom electrode 110, ferroelectric layer 108, and barrier layer 104 encase the underside of top electrode 106. For example, the bottom electrode barrier 502, the bottom electrode 110, the ferroelectric layer 108, the barrier layer 104 may each have a U-shaped profile, etc. The bottom electrode barrier 502 is located between the bottom electrode 110 and the bottom electrode lead 304b, and may be, for example, the BEVA barrier 308 shown in fig. 3A.

Referring to fig. 6B, a top layout view 600B of some embodiments of the memory cell 102 of fig. 6A is provided. Further, the top-down layout of the TEVA 306t is shown in dashed lines over the memory cell 102. For example, the cross-sectional view 600A of FIG. 6A may be taken along line C-C'. The bottom electrode barrier 502 extends in a closed path around the bottom electrode 110, the bottom electrode 110 extends in a closed path around the ferroelectric layer 108, the ferroelectric layer 108 extends in a closed path around the barrier layer 104, and the barrier layer 104 extends in a closed path around the top electrode 106. Memory cells 102 have a square or rectangular top-down layout, but may alternatively have a circular top-down layout or some other suitable top-down layout. TEVA 306t has a square or rectangular top view layout, but may have other suitable top view layouts.

Referring to fig. 7A, a cross-sectional view 700A of some alternative embodiments of the memory cell 102 of fig. 3A is provided, wherein the BEVA 306b, BEVA barrier 308, BEVA body 310, sidewall spacer structure 314, second etch stop layer 320, and hard mask 312 are omitted. In this way, the memory cell 102 extends from the bottom electrode lead 304 b. In addition, an additional conductive line 304a is located below the TEVA 306t, flush with the bottom electrode conductive line 304b, and the top electrode 106, the barrier layer 104, and the ferroelectric layer 108 form a sidewall spacer structure.

The sidewall spacer structure is over the first etch stop layer 318 on the top sidewall portion of the bottom electrode 110. In addition, the sidewall spacer structure has a pair of spacer sections with a bottom electrode 110 disposed between the spacer sections. The TEVA 306t extends to a portion of the top electrode 106 at one of these sections and further into the first etch stop layer 318. In at least some embodiments, outside of the cross-sectional view 700B, the spacer sections are continuous with each other. The barrier layer 104 and ferroelectric layer 108 have an L-shaped portion at each spacer section. The L-shaped portions of ferroelectric layer 108 wrap around the bottom corners of the corresponding L-shaped portions of barrier layer 104, and the L-shaped portions of barrier layer 104 wrap around the bottom corners of the corresponding portions of top electrode 106.

Referring to fig. 7B, a top layout view 700B of some embodiments of the memory cell 102 of fig. 7A is provided. Further, the top-down layout of the TEVA 306t is shown in dashed lines over the memory cell 102. For example, the cross-sectional view 700A of FIG. 7A may be taken along line D-D'. The top electrode 106 extends in a closed path around the barrier layer 104, the barrier layer 104 extends in a closed path around the ferroelectric layer 108, and the ferroelectric layer 108 extends in a closed path around the bottom electrode 110. Memory cells 102 have a square or rectangular top-down layout, but may alternatively have a circular top-down layout or some other suitable top-down layout. TEVA 306t has a square or rectangular top view layout, but may alternatively have other suitable top view layouts.

Referring to fig. 8, a cross-sectional view 800 of some alternative embodiments of the memory cell 102 of fig. 3A and 3B is provided, wherein the barrier layer 104 is located at the bottom electrode 110 as shown in fig. 2A. In addition, the metal of the bottom electrode 110 has low electronegativity, while the metal of the top electrode 106 has high electronegativity.

Referring to fig. 9A-9D, cross-sectional views 900A-900D of some alternative embodiments of the memory cell 102 in fig. 8 are provided, wherein the memory cell 102 is configured as shown in fig. 4A, 5, 6A, and 7A, respectively.

Referring to fig. 10, a cross-sectional view 1000 of some alternative embodiments of the memory cell 102 of fig. 3A and 3B is provided, wherein the memory cell 102 has a pair of barrier layers 104 as shown in fig. 2B. In addition, the metal of the bottom electrode 110 and the metal of the top electrode 106 have low electronegativity.

Referring to fig. 11A-11D, cross-sectional views 1100A-1100D of some alternative embodiments of the memory cell 102 in fig. 10 are provided, wherein the memory cell 102 is configured as in fig. 4A, 5, 6A, and 7A, respectively.

Referring to fig. 12A, a cross-sectional view 1200A of some embodiments of an IC chip including a memory cell 102 is provided, wherein the memory cell 102 is integrated into a separate one-transistor-capacitor (1T 1C) cell 1202. Each memory cell 102 is as described with respect to the counterparts of fig. 3A and 3B.

The 1T1C cell 1202 includes a separate drain region 1204 and a separate drain side conductive path 1206. The drain regions 1204 are doped regions of the substrate 1208 and each have a doping type opposite to that of the adjoining regions of the substrate 1208. Further, drain region 1204 is electrically isolated by trench isolation structure 1210 and partially defines an access transistor 1212 (partially shown) for individually selecting memory cell 102. The trench isolation structure 1210 extends to the top of the substrate 1208 and comprises silicon oxide and/or some other suitable dielectric material. The substrate 1208 may be, for example, a bulk silicon substrate or some other suitable semiconductor substrate.

A drain side conductive path 1206 electrically couples drain region 1204 to memory cell 102 and is formed by interconnect structure 302, memory cell 102 being disposed in interconnect structure 302. Interconnect structure 302 includes a plurality of conductive lines 304 and a plurality of vias 306. The plurality of wires 304 includes a top electrode wire 304t and a bottom electrode wire 304b. In some embodiments, the top electrode lead 304t corresponds to the bit line BL. The plurality of vias 306 includes TEVA 306t and BEVA 306b. The level of via 306 closest to substrate 1208 is in interlayer dielectric (ILD) layer 1214, while the remaining levels of via 306 and conductive line 304 are in IMD layer 316. In addition to BEVA 306b, the conductive lines 304 and vias 306 may be or include, for example, copper, aluminum, some other suitable metal, or any combination of the preceding. For example, BEVA 306B may have its counterparts as described with respect to fig. 3A and 3B.

The peripheral area 1216 on one side of the 1T1C cell 1202 accommodates peripheral devices 1218 (only one of which is shown). The peripheral device 1218 may be, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a fin field effect transistor (finFET), a full-gate field effect transistor (GAA FET), or some other suitable type of semiconductor device. Each of the peripheral devices 1218 includes a pair of source/drain regions 1220 in the substrate 1208, and a gate electrode 1222 and a gate dielectric layer 1224 stacked between the source/drain regions 1220.

Referring to fig. 12B, a cross-sectional view 1200B of some embodiments of the IC chip of fig. 12A is provided, taken along an axis orthogonal to the axis taken by the cross-sectional view 1200A of fig. 12A. The 1T1C cell 1202 includes a separate memory cell 102, a separate drain side conductive path 1206, a separate access transistor 1212, and a separate source side conductive path 1226. Each memory cell 102 is as its counterpart described with respect to fig. 3A and 3B.

The access transistor 1212 is located on the substrate 1208, between the substrate 1208 and the interconnect structure 302, and is electrically isolated by the trench isolation structure 1210. The access transistor 1212 includes a separate drain region 1204, a separate source region 1228, a separate gate dielectric layer 1230, and a separate gate electrode 1232. Gate electrodes 1232 are respectively over the gate dielectric layer 1230 and, in some embodiments, form word lines. The drain region 1204 and the source region 1228 are doped regions of the substrate 1208 and each have a doping type opposite to that of the adjoining regions of the substrate 1208. Further, the drain region 1204 and the source region 1228 are adjacent to the gate electrode 1232, respectively. The access transistor 1212 may be, for example, MOSFET, finFET, GAA FET, or some other suitable type of semiconductor device.

Drain side conductive path 1206 electrically couples drain region 1204 to memory cell 102, and source side conductive path 1226 electrically couples source region 1228 to source line SL. The drain-side and source-side conductive paths 1206, 1226 are formed by the plurality of conductive lines 304 and the plurality of vias 306.

Although fig. 12A and 12B are shown using the memory cell embodiments in fig. 3A and 3B, the embodiments of the memory cells of any of fig. 1, 2A, 2B, 4A, 4B, 5, 6A, 6B, 7A, 7B, 8, 9A-9D, 10, and 11A-11D are applicable in alternative embodiments. For example, as shown in cross-sectional view 1300 of fig. 13, memory cells 102 of fig. 12A and 12B may alternatively be configured as shown in fig. 7A and 7B.

Referring to fig. 14, a top layout 1400 of some embodiments of the IC chip of fig. 12A and 12B is provided. For example, the cross-sectional views 1200A, 1200B of fig. 12A and 12B may be taken along line E and line F, respectively. The IC chip includes a plurality of 1T1C cells 1202 in a plurality of rows and a plurality of columns, forming a memory array 1402. Peripheral devices 1218 surround memory array 1402 at peripheral region 1216 of the IC chip. The peripheral 1218 may, for example, implement read/write circuitry and/or other suitable circuitry for operating the 1T1C cell 1202.

Referring to fig. 15, a cross-sectional view 1500 of some embodiments of an ic chip includes a ferroelectric field effect transistor (FeFET) 1502 in which a barrier layer 104 is configured to block diffusion of metal from a top gate electrode 1504 to a ferroelectric layer 108. A pair of source/drain regions 1506 are located in substrate 1208, with channel regions 1508 of substrate 1208 separating source/drain regions 1506. The source/drain regions 1506 may be, for example, doped regions of the substrate 1208, or the like.

A gate dielectric layer 1510, a floating gate electrode 1512, a ferroelectric layer 108, a barrier layer 104, a top gate electrode 1504, and a hard mask 1514 form a gate stack over the channel region 1508 and share a common width. In alternative embodiments, the floating gate electrode 1512 and/or the gate dielectric layer 1510 are omitted. The floating gate electrode 1512 and the top gate electrode 1504 are shown as bottom electrode 110 and top electrode 106, respectively, in fig. 1. Thus, the floating gate electrode 1512 has a high electronegativity, while the top gate electrode 1504 has a low electronegativity. Furthermore, the barrier layer 104 and the ferroelectric layer 108 are as described with respect to fig. 1, wherein the barrier layer 104 is configured to block diffusion of metal of the top gate electrode 1504 to the ferroelectric layer 108, thereby enhancing performance of the ferroelectric layer 108 and, thus, the memory cell 102.

Sidewall spacer structures 1516 are located on opposite sidewalls of the gate stack and interconnect structure 302 is over FeFET 1502 and electrically coupled to FeFET 1502. The interconnect structure 302 includes a plurality of conductive lines 304 and a plurality of vias 306 stacked to define a conductive path leading from the FeFET 1502. Although only one level of vias 306 and one level of wires 304 are shown, additional levels are contemplated. A contact etch stop layer 1518 covers FeFET 1502 and lines FeFET 1502, and ILD layer 1214 and IMD layer 316 are stacked over contact etch stop layer 1518. Contact etch stop layer 1518 and ILD layer 1214 surround via 306 and imd layer 316 surrounds conductive line 304.

In some embodiments, the hard mask 1514 is or includes titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, metal oxides, some other suitable material, or any combination of the preceding. In some embodiments, sidewall spacer structure 1516 is or includes titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, metal oxides, some other suitable material, or any combination of the preceding. In some embodiments, contact etch stop layer 1518 is or includes a metal nitride, a metal oxide, a metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, some other suitable dielectric, or any combination of the preceding.

During operation of the FeFET 1502, the remnant polarization of the ferroelectric layer 108 is used to represent a bit of data. For example, the positive polarity of the remnant polarization may represent a binary "0", while the negative polarity of the remnant polarization may represent a binary "1", or vice versa.

To set the remnant polarization to positive polarity, a first write voltage is applied from the top gate electrode 1504 across the ferroelectric layer 108 to the channel region 1508 (e.g., through the source/drain regions 1506). To set the remnant polarization to negative polarity, a second write voltage is applied from the top gate electrode 1504 across the ferroelectric layer 108 to the channel region 1508. The first write voltage and the second write voltage have opposite polarities and have magnitudes exceeding the coercive voltage.

The polarity of the remnant polarization changes the threshold voltage of FeFET 1502. The threshold voltage is at the first threshold or the second threshold depending on whether the remnant polarization is at the positive polarity or the negative polarity. To read the polarity of the remnant polarization, a read voltage that is less than the coercive voltage and that is between the first threshold voltage and the second threshold voltage is applied from the top gate electrode 1504 to the source regions in the source/drain regions 1506. Depending on whether channel region 1508 is conducting, the remnant polarization has a positive or negative polarity.

While fig. 15 shows FeFET1502 with barrier layer 104 at top gate electrode 1504, feFET1502 may also have barrier layer 104 at floating gate electrode 1512, as shown in cross-section 1600A of fig. 16A. In such alternative embodiments, the floating gate electrode 1512 has a low electronegativity and the top gate electrode 1504 has a high electronegativity. Furthermore, while fig. 15 shows FeFET1502 with a single barrier layer 104, feFET1502 may alternatively have a pair of barrier layers 104 as shown in cross-section 1600B of fig. 16B. In such an alternative embodiment, the first barrier layer 104a is located between the top gate electrode 1504 and the ferroelectric layer 108, and the second barrier layer 104b is located between the floating gate electrode 1512 and the ferroelectric layer 108. In addition, both the floating gate electrode 1512 and the top gate electrode 1504 have low electronegativity.

17-27, a series of cross-sectional views 1700-2700 of some embodiments of a method for forming an IC chip including a memory cell integrated into a single 1T1C cell and including a barrier layer is provided. For example, cross-sectional views 1700-2700 may correspond to the IC chips of fig. 12A and 12B, and/or may be taken, for example, along line E in fig. 14.

As shown in cross-section 1700 of fig. 17, interconnect structure 302 is formed partially over and electrically coupled to a plurality of access transistors 1212 (only partially shown) and peripheral devices 1218. The access transistors 1212 are separate from the plurality of 1T1C cells 1202 formed, and the peripheral devices 1218 are located at the peripheral region 1216 of the IC chip formed. The access transistor 1212 and peripheral devices 1218 are on the substrate 1208 and are formed in part from the substrate 1208 and are separated by trench isolation structures 1210 in the substrate 1208. The access transistor 1212 and the peripheral 1218 may be as described with respect to fig. 12A and 12B, for example.

The interconnect structure 302 includes a plurality of conductive lines 304 and a plurality of vias 306 stacked in a dielectric structure. The dielectric structure includes ILD layer 1214 and first IMD layer 316a over ILD layer 1204. The plurality of conductive lines 304 includes a plurality of bottom electrode conductive lines 304b along the top surface of the interconnect structure 302. The bottom electrode wires 304b are separate from the 1T1C cell 1202 formed and are located at the 1T1C cell 1202, respectively. In addition, bottom electrode leads 304b are electrically coupled to drain regions 1204 of access transistors 1212, respectively. The first IMD layer 316a may be formed, for example, by and/or using Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), some other suitable deposition process, or any combination of the preceding. The conductive lines 304 and the vias 306 may be formed, for example, by and/or using CVD, PVD, ALD, electroless plating, electroplating, some other suitable deposition process, or any combination of the preceding.

As shown in cross-section 1800 of fig. 18, a first etch stop layer 318 is deposited or otherwise formed over the interconnect structure 302. Note that for the sake of drawing compactness, the lower portion of the interconnect structure 302 is omitted here and in fig. 19-27 that follows. The first etch stop layer 318 is a dielectric and may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding.

As also shown in cross-sectional view 1800 of fig. 18, BEVA 306b extends through the first etch stop layer 318 to the bottom electrode lead 304b, respectively. The BEVA 306b includes a separate BEVA body 310 and separate BEVA barriers 308 that individually wrap the underside of the BEVA body 310. The BEVA body 310 and/or the BEVA barrier 308 may be formed, for example, by and/or using CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding.

As shown in the cross-sectional view 1900 of fig. 19, a bottom electrode layer 1101 is deposited over the BEVA 306b and the first etch stop layer 318. The bottom electrode layer 1101 is conductive and is or includes a metal having high electronegativity. Thus, the metal of the bottom electrode layer 1101 has low reactivity and thus has a low tendency to diffuse. The bottom electrode layer 1101 may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding.

In some embodiments, the high electronegativity is related to the electronegativity of a subsequently formed top electrode layer. In some embodiments, the high electronegativity is an electronegativity that is greater than about 1.6, about 2.0, or some other suitable value, and/or an electronegativity that is about 1.6-2.4, about 1.6-2.0, about 2.0-2.4, or some other suitable value. In some embodiments, the high electronegativity metal is or includes molybdenum (e.g., mo/electronegativity of 2.16), tungsten (e.g., W/electronegativity of 2.36), ruthenium (e.g., ru/electronegativity of 2.2), osmium (e.g., os/electronegativity of 2.18), rhodium (e.g., rh/electronegativity of 2.28), iridium (e.g., ir/electronegativity of 2.2), palladium (e.g., pd/electronegativity of 2.2), platinum (e.g., pt/electronegativity of 2.28), copper (e.g., cu/electronegativity of 1.9), silver (e.g., ag/electronegativity of 1.93), gold (e.g., au/electronegativity of 2.54), aluminum (e.g., al/electronegativity of 1.61), some other suitable conductive material, or any combination of the foregoing.

As shown in the cross-sectional view 1900 of fig. 19, the ferroelectric layer 108 is deposited on the bottom electrode layer 1101. Deposition may be performed, for example, by CVD, PVD, ALD, or the like, or any combination of the foregoing.

As shown in cross-section 2000 of fig. 20, barrier layer 104 is deposited on ferroelectric layer 108 and top electrode layer 1061 is deposited on barrier layer 104. The barrier layer 104 may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding. Similarly, top electrode layer 1061 may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding.

The top electrode layer 1061 includes a metal having low electronegativity, and the barrier layer 104 is configured to block diffusion of the metal into the ferroelectric layer 108. The low electronegativity is schematically shown by the diagonal lines on the top electrode layer 1061. In some embodiments, the electronegativity of the bottom electrode layer 1101 is low. In some embodiments, the low electronegativity is an electronegativity of less than about 1.6, about 1.5, or some other suitable value, and/or an electronegativity of about 1.1-1.6, or some other suitable value.

The metal of the top electrode layer 1061 has high reactivity due to low electronegativity and thus has a high tendency to diffuse into the ferroelectric layer 108. The metal diffused into the ferroelectric layer 108 negatively affects the performance of the ferroelectric layer 108. Thus, the barrier layer 104 enhances the performance of the ferroelectric layer 108 by blocking diffusion of metal from the top electrode layer 1061 to the ferroelectric layer 108. For example, the ferroelectric phase may be increased, the remnant polarization (2 Pr) may be increased, the polarization uniformity may be increased, the leakage current may be reduced, the capacitance may be increased, the data retention may be enhanced, the breakdown voltage may be increased, or any combination of the foregoing.

The metal of the bottom electrode layer 1101 has high electronegativity compared to the top electrode layer 1061, and thus has a low tendency to diffuse into the ferroelectric layer 108. Therefore, diffusion of metal from the bottom electrode layer 1101 to the ferroelectric layer 108 is almost minimal, and the barrier layer at the bottom electrode layer 110l can be omitted without significantly affecting the ferroelectric layer 108 performance.

In some embodiments, the barrier layer 104 is or includes silicon oxide (e.g., siO _x ) Silicon nitride (e.g. SiN _x ) A metal oxide, a high-k dielectric, some other suitable metal, or any combination of the preceding. For example, the high-k dielectric may be a dielectric having a dielectric constant greater than about 3.9, about 10, or some other suitable value. In some embodiments, the barrier layer 104 is a dielectric. For example, the barrier layer 104 may be or include silicon oxide, silicon nitride, a high-k dielectricOr some other suitable dielectric. In some embodiments, the barrier layer 104 is a semiconductor. For example, the barrier layer 104 may be or include a semiconductive metal oxide or some other suitable semiconductive material. In other embodiments, the barrier layer 104 is electrically conductive. For example, the barrier layer 104 may be or include a conductive metal oxide or some other suitable conductive material.

In some embodiments, the barrier layer 104 includes a metal that diffuses from the top electrode layer 1061 to the ferroelectric layer 108. In some embodiments, the barrier layer 104 has an amorphous structure to eliminate grain boundaries and increase diffusion path complexity. Alternatively, in some embodiments, the barrier layer 104 has a nanocrystalline structure, and the grains of the barrier layer 104 are equiaxed grains, rather than columnar grains, to increase the complexity of the diffusion path. By increasing diffusion path complexity, diffusion of metal through the barrier layer 104 is reduced.

In some embodiments, the thickness T of the barrier layer 104 _b About 2-50 angstroms, about 2-26 angstroms, about 26-50 angstroms, or some other suitable value. If the thickness T _b Too small (e.g., less than 2 angstroms), the barrier layer 104 may not effectively block the diffusion of metal from the top electrode layer 1061 to the ferroelectric layer 108. If the thickness T _b Too large (e.g., greater than 50 angstroms), the resistance of the barrier layer 104 may be too high and may result in low current flow through the formed memory cell.

In some embodiments, the metal of the top electrode layer 1061 diffuses minimally into the ferroelectric layer 108 even with the barrier layer 104. For example, the atomic percent of metal in ferroelectric layer 108 may be less than about 10%, about 5%, about 1%, or some other suitable percentage of non-zero values, and/or may be about 1% -10%, about 1% -5%, about 5% -10%, or some other suitable percentage. In some embodiments, minimal diffusion occurs entirely or mostly during annealing to increase the ferroelectric phase of ferroelectric layer 108. In some such embodiments, the atomic percent of metal in ferroelectric layer 108 is less than 10% at the end of the anneal when barrier layer 104 is present, and greater than 30% at the end of the anneal when barrier layer 104 is not present.

As shown in cross-sectional view 2100 of fig. 21, an anneal is performed to increase the ferroelectric phase in ferroelectric layer 108. Note that the annealing is schematically illustrated by the pattern variations of the ferroelectric layer 108 of fig. 20 to 21. Ferroelectric corresponds to an orthorhombic phase and is in contrast to tetragonal and monoclinic phases. The higher the ratio of orthorhombic phase to other crystalline phases in the ferroelectric layer 108, the higher the remnant polarization (2 Pr) and thus the better the data retention. Annealing may be performed, for example, at a temperature of about 300-1500 degrees celsius, about 300-900 degrees celsius, about 900-1500 degrees celsius, and the like.

During annealing, the metals of the top electrode layer 1061 and the bottom electrode layer 1101 have a higher reactivity and diffusion tendency. However, the metal of the bottom electrode layer 1101 still has a low diffusivity during annealing, and thus has little effect on the ferroelectric layer 108 during annealing. In contrast, the metal of the top electrode layer 1061 has an even higher diffusivity during annealing. However, despite the higher diffusivity, the metal of the top electrode layer 1061 has little effect on the ferroelectric layer 108 because the barrier layer 104 blocks diffusion of metal into the ferroelectric layer 108. In some embodiments, the atomic percent of metal in ferroelectric layer 108 is less than about 10%, 5%, or 1% at the end of the anneal when barrier layer 104 is present, and greater than about 30% at the end of the anneal when barrier layer 104 is not present.

As shown in cross-sectional view 2100 of fig. 21, a hard mask 312 is formed that is separate from the 1T1C cell 1202 that is formed. As seen below, the hard mask 312 has a pattern for the memory cells formed. The process for forming the hard mask 312 may, for example, include depositing a hard mask layer over the top electrode layer 1061, and then patterning the hard mask layer into the hard mask 312. The deposition may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding. Patterning may be performed, for example, by a photolithography/etching process or some other suitable patterning process.

With the hard mask 312 in place, the top electrode layer 1061, the barrier layer 104, the ferroelectric layer 108, and the bottom electrode layer 1101 are etched, as shown in the cross-sectional view 2200 of fig. 22. In some embodiments where the hard mask 312 is formed by a photolithography/etch process, the etching of the photolithography/etch process is the same as etching into the top electrode layer 1061, etc. The etch stops on the first etch stop layer 318, whereby the first etch stop layer 318 acts as an etch stop for the etch. In addition, the etching transfers the pattern of the hard mask 312 to the top electrode layer 1061, the barrier layer 104, the ferroelectric layer 108, and the bottom electrode layer 1101, forming the memory cells 102 over the BEVA 306b, respectively. The various sections of the top electrode layer 1061 at the memory cell 102 are hereinafter referred to as the top electrode 106, while the various sections of the bottom electrode layer 1101 at the memory cell 102 are hereinafter referred to as the bottom electrode 110.

As shown in cross-sectional view 2300 of fig. 23, sidewall spacers 314 are formed on the common sidewalls formed by hard mask 312, top electrode 106, barrier layer 104, ferroelectric layer 108, and bottom electrode 110. The process for forming sidewall spacer structure 314 may include, for example: 1) Depositing a sidewall spacer layer over the memory cell 102; and 2) etching back the sidewall spacer layer. However, other suitable processes are also possible. The sidewall spacer layer may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding.

As shown in cross-sectional views 2400-2700 of fig. 24-27, interconnect structure 302 is completed over memory cell 102 and around memory cell 102.

As shown in cross-sectional view 2400 of fig. 24, a second etch stop layer 320 is formed, the second etch stop layer 320 overlying the memory cell 102 and laterally offset from the peripheral region 1216. The process for forming the second etch stop layer 320 may include, for example: 1) Depositing a second etch stop layer 320 covering the memory cells 102 and the peripheral region 1216; and 2) patterning the second etch stop layer 320 to remove it from the peripheral region 1216. However, other suitable processes are also possible. The second etch stop layer 320 may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding. Patterning may be performed, for example, by a photolithography/etching process or some other suitable process.

As shown in cross-sectional view 2500 of fig. 25, a buffer layer 322 and a second IMD layer 316b are deposited over the first and second etch stop layers 318, 320 covering the memory cells 102 and the peripheral region 1216. In an alternative embodiment, buffer layer 322 is omitted. Buffer layer 322 and/or second IMD layer 316b may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding.

As shown in cross-sectional view 2500 of fig. 25, second IMD layer 316b, buffer layer 322, and first and second etch stop layers 318, 320 are patterned to form a plurality of via openings 2502. The via openings 2502 expose the top electrode 106 at the memory cell 102 and the conductive line 304 at the peripheral region 1216, respectively. Patterning may be performed, for example, by one or more photolithography/etching processes and/or some other suitable patterning process. In some embodiments, the first and second etch stop layers 318, 320 function as etch stop layers when performing the etching of the photolithography/etch process.

As shown in cross-sectional view 2600 of fig. 26, second IMD layer 316b is further patterned to form a plurality of wire openings 2602 that overlap via openings 2502. Patterning may be performed, for example, by a photolithography/etching process and/or some other suitable patterning process.

As shown in cross-sectional view 2700 of fig. 27, a plurality of additional conductive lines 304 and a plurality of additional vias 306 are formed filling via openings 2502 (see fig. 25) and conductive line openings 2602 (see fig. 26). The plurality of additional conductive lines 304 fill the conductive line openings 2602, respectively, and include a plurality of top electrode conductive lines 304t, the plurality of top electrode conductive lines 304t being separate from the memory cells 102 and over the memory cells 102, respectively. The plurality of additional vias 306 fill the via openings 2502 and include a plurality of TEVA 306t, respectively, that are separate from the top electrode 106 and are located at the top electrode 106, respectively. Further, TEVA 306t extends from top electrode leads 304t to top electrode 106, respectively.

For example, the process of forming the additional conductive lines 304 and the additional vias 306 may include: 1) Depositing a metal layer filling the via opening 2502 and the wire opening 2602; and 2) planarizing the metal layer and the second IMD layer 316b until the top surfaces of the second IMD layer 316b and the metal layer are flush with each other. However, other suitable processes are also possible. The metal layer may be deposited, for example, by CVD, PVD, ALD, electroless plating, electroplating, some other suitable deposition process, or any combination of the preceding.

Although fig. 17-27 are described with reference to one method, it should be understood that the structure shown in fig. 17-27 is not limited to this method, but may be independent of the method. While fig. 17-27 are described as a series of acts, it should be appreciated that the order of the acts may be varied in other embodiments. For example, instead of forming the barrier layer 104 between the ferroelectric layer 108 and the top electrode layer 106, the barrier layer 104 may be formed between the bottom electrode layer 1101 and the ferroelectric layer 108. In such an embodiment, the metal of the bottom electrode layer 1101 has low electronegativity and the metal of the top electrode layer 1061 has high electronegativity.

While fig. 17-27 illustrate and describe a particular set of acts, in other embodiments, some of the illustrated and/or described acts may be omitted. Moreover, acts not shown and/or described may be included in other embodiments. For example, another barrier layer may be formed between the bottom electrode layer 1101 and the ferroelectric layer 108. In such an embodiment, both the metal of the bottom electrode layer 1101 and the metal of the top electrode layer 1061 have low electronegativity and thus have high diffusivity.

Referring to fig. 28, a block diagram 2800 is provided for some embodiments of the methods of fig. 17-27.

At 2802, an interconnect structure is formed partially over the substrate, wherein the interconnect structure includes a bottom electrode lead at a memory region. See, for example, fig. 17.

An etch stop layer is deposited over the interconnect structure at 2804. See, for example, fig. 18.

At 2806, a bottom electrode via is formed, the bottom electrode via extending through the etch stop layer to a bottom electrode lead. See, for example, fig. 18.

At 2808, a bottom electrode layer, a ferroelectric layer, a barrier layer, and a top electrode layer are deposited over the bottom electrode via, wherein the barrier layer is located between the ferroelectric layer and a least electronegative electrode layer of the bottom electrode layer and the top electrode layer, and wherein the barrier layer is configured to block diffusion of metal from the electrode layer to the ferroelectric layer. See, for example, fig. 19 and 20.

At 2810, an anneal is performed to increase the ferroelectric phase of the ferroelectric layer. See, for example, fig. 21.

At 2812, a hard mask is formed over the top electrode layer. See, for example, fig. 21.

With the hard mask in place, the top electrode layer, barrier layer, ferroelectric layer, and bottom electrode layer are etched to form a memory cell 2814. See, for example, fig. 22.

At 2816, sidewall spacer structures are formed on sidewalls of the memory cells. See, for example, fig. 23.

At 2818, the interconnect structure is completed over and around the memory cells. See, for example, fig. 24-27.

While the block diagram 2800 of fig. 28 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events should not be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more of the acts described herein may be performed in one or more separate acts and/or phases.

29-36, a series of cross-sectional views 2900-3600 of some alternative embodiments of the method of FIGS. 17-27 are provided in which the memory cell 102 is formed as shown and described in FIG. 8. Thus, the IC chip formed by this method may correspond to the IC chip of fig. 13, for example.

As shown in cross-sectional view 2900 of fig. 29, the acts are described with respect to fig. 17, except that interconnect structure 302 has a different layout. For example, interconnect structure 302 has additional conductive lines along the top surface of interconnect structure 302.

As shown in cross-sectional view 3000 of fig. 30, a first etch stop layer 318 and a sacrificial layer 3002 are deposited over interconnect structure 302 such that first etch stop layer 318 is located between sacrificial layer 3002 and first IMD layer 316 a. The first etch stop layer 318 may be or include, for example, a metal nitride, a metal oxide, a metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or the like, or any combination of the foregoing. The sacrificial layer 3002 may be or include, for example, tetraethyl orthosilicate (TEOS) oxide, or the like. The first etch stop layer 318 and the sacrificial layer 3002 may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding.

As shown in the cross-sectional view 3100 of fig. 31, the first etch stop layer 318 and the sacrificial layer 3002 are patterned to form cell openings 3102 exposing the bottom electrode leads 304b, respectively. Patterning may be performed, for example, by a photolithography/etching process or some other suitable patterning process. In some embodiments, the lithography/etching includes: 1) Forming a photoresist mask 3104 on the sacrificial layer 3002 by photolithography; 2) With the photoresist mask 3104 in place, the first etch stop layer 318 and the sacrificial layer 3002 are etched; and 3) removing the photoresist mask 3104.

As shown in cross-section 3200 of fig. 32, bottom electrode layer 1101 is deposited over sacrificial layer 3002, filling cell opening 3102 (see, e.g., fig. 31). In some embodiments, the bottom electrode barrier layer of the spacer cell opening 3102 is first deposited and the bottom electrode layer 1101 is deposited over the bottom electrode barrier layer. The bottom electrode layer 1101 and/or bottom electrode barrier layer may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the preceding. The bottom electrode layer 1101 may be as shown, for example, in fig. 19, and/or the bottom electrode barrier layer may be as shown in fig. 5.

As shown in cross-section 3300 of fig. 33, the top surface of bottom electrode layer 1101 is recessed until it is flush or substantially flush with the top surface of sacrificial layer 3002. This divides the bottom electrode layer 1101 into bottom electrodes 110 that are separate from the memory cells being formed. The recessing may be performed, for example, by etching back, planarizing, or the like. Planarization may be performed, for example, by Chemical Mechanical Polishing (CMP) and/or some other suitable planarization.

As shown in a cross-sectional view 3400 of fig. 34, the sacrificial layer 3002 is removed (see fig. 33, for example). For example, the removal may be performed by etching or some other suitable removal process. In terms of performing removal by etching, the first etch stop layer 318 may serve as an etch stop layer for etching.

As shown in cross-sectional view 3400 of fig. 34, ferroelectric layer 108, barrier layer 104, and top electrode layer 1061 are deposited over bottom electrode 110 and first etch stop layer 318. The barrier layer 104 is over the ferroelectric layer 108 and the top electrode layer 1061 is over the barrier layer 104. For example, ferroelectric layer 108, barrier layer 104, and top electrode layer 1061 may be deposited as described with respect to fig. 19 and 20.

As shown in cross-section 3500 of fig. 35, an anneal is performed to increase the ferroelectric phase in ferroelectric layer 108, as described with respect to fig. 21. Note that the annealing is schematically illustrated by the pattern change of the ferroelectric layer 108 of fig. 34 to 35.

As shown in cross-section 3500 of fig. 35, ferroelectric layer 108, barrier layer 104, and top electrode layer 1061 are etched back. The etch back may be performed, for example, by vertical and/or anisotropic etching, etc. The etch back removes horizontal sections of ferroelectric layer 108, barrier layer 104, and top electrode layer 1061, thereby positioning ferroelectric layer 108, barrier layer 104, and top electrode layer 106 to sidewalls (e.g., sidewalls of bottom electrode 110). In addition, the remaining portion of the top electrode layer 1061 on the sidewall of the bottom electrode 110 is hereinafter referred to as the top electrode 106.

As shown in cross-sectional view 3600 of fig. 36, the acts described with respect to fig. 25-27 are performed to complete interconnect structure 302 over and around memory cell 102.

While fig. 29-36 are described with reference to one method, it should be understood that the structure shown in fig. 29-36 is not limited to this method, but may be independent of the method. While fig. 29-36 are described as a series of acts, it should be understood that the order of the acts may be varied in other embodiments. 29-36 are shown and described as a particular set of acts, some acts shown and/or described may be omitted in other embodiments. Moreover, acts not shown and/or described may be included in other embodiments.

In some embodiments, the present disclosure provides an IC chip including a memory cell, wherein the memory cell includes: a first electrode and a second electrode, each comprising a metal; a ferroelectric layer between the first electrode and the second electrode; and a barrier layer between the ferroelectric layer and the first electrode; wherein the barrier layer is configured to block diffusion of the first metal of the first electrode into the ferroelectric layer, and wherein the first metal of the first electrode has a lower electronegativity than the second metal of the second electrode. In some embodiments, the barrier layer directly contacts the ferroelectric layer and the first electrode, and wherein the second electrode directly contacts the ferroelectric layer. In some embodiments, the barrier layer is amorphous. In some embodiments, the barrier layer is a semiconductor. In some embodiments, the barrier layer is a conductive metal oxide. In some embodiments, the ferroelectric layer comprises a non-zero atomic percent of the first metal, the non-zero atomic percent being less than about 10%.

In some embodiments, the present disclosure provides another IC chip including a memory unit, wherein the memory unit includes: a bottom electrode located at the bottom of the memory cell; a top electrode at the top of the memory cell; a ferroelectric layer between the bottom electrode and the top electrode; and a diffusion barrier layer between the ferroelectric layer and the first electrode, wherein the first electrode is one of a bottom electrode and a top electrode, and wherein the first electrode comprises a metal having an electronegativity of less than about 1.6. In some embodiments, the memory cell further comprises a second diffusion barrier layer located between the ferroelectric layer and the second electrode, wherein the second electrode is the other of the bottom electrode and the top electrode, and wherein the first electrode comprises a metal having an electronegativity of less than about 1.6. In some embodiments, the ferroelectric layer directly contacts the second electrode, wherein the second electrode is the other of the bottom electrode and the top electrode, and wherein the second electrode comprises a metal having an electronegativity of greater than about 1.6. In some embodiments, the ferroelectric layer, the diffusion barrier layer, and one or both of the bottom electrode and the top electrode share a common width. In some embodiments, the ferroelectric layer, diffusion barrier layer, and bottom electrode have separate U-shaped profiles that wrap around the bottom of the top electrode. In some embodiments, the top electrode extends in a closed path around the bottom electrode, and wherein the top electrode has a bottom surface that is elevated relative to a bottom surface of the bottom electrode. In some embodiments, the ferroelectric layer and the diffusion barrier layer extend in separate closed paths around the bottom electrode and have separate bottom surfaces that are raised relative to the bottom surface of the bottom electrode. In some embodiments, the IC chip further comprises: a substrate; a semiconductor device located over and partially defined by the substrate; and a plurality of wires and a plurality of vias grouped into a plurality of wire levels and a plurality of via levels, respectively, the plurality of wire levels and the plurality of via levels being alternately stacked over and electrically coupled to the semiconductor device, wherein the plurality of wires include a bottom electrode wire and a top electrode wire, and the memory cell is disposed between the bottom electrode wire and the top electrode wire.

In some embodiments, the present disclosure provides a method comprising: forming a bottom electrode over a substrate; depositing a stacked barrier layer, ferroelectric layer, and top electrode layer over a substrate; patterning the top electrode layer to form a top electrode; and patterning the barrier layer and the ferroelectric layer to delineate sections of the barrier layer and the ferroelectric layer that are separate from the memory cells; wherein after patterning the barrier layer and the ferroelectric layer, the bottom electrode and the top electrode and the segments of the barrier layer and the ferroelectric layer form a memory cell, wherein the bottom electrode and the top electrode comprise a metal, and wherein the barrier layer is located between the ferroelectric layer and the electrode having the lowest metal electronegativity among the bottom electrode and the top electrode. In some embodiments, the method further comprises: depositing a bottom electrode layer over the substrate, wherein the barrier layer, ferroelectric layer, and top electrode layer are deposited over the bottom electrode layer; and performing etching on the bottom electrode layer, the ferroelectric layer, and the barrier layer using a common mask in place to pattern the bottom electrode layer into a bottom electrode and to further perform patterning of the barrier layer and the ferroelectric layer. In some embodiments, the method further comprises: an anneal is performed to increase the ferroelectric phase of the ferroelectric layer prior to patterning the top electrode layer and patterning the barrier layer and the ferroelectric layer. In some embodiments, a barrier layer, ferroelectric layer, and top electrode layer are deposited over the bottom electrode and on the sidewalls of the bottom electrode. In some embodiments, forming the bottom electrode includes: depositing a sacrificial layer on the dielectric layer, wherein the dielectric layer covers the wires; etching is performed through the dielectric layer and the sacrificial layer to form an opening exposing the conductive line; depositing a bottom electrode layer in the opening; performing planarization to the top surface of the sacrificial layer on the bottom electrode layer; and removing the sacrificial layer. In some embodiments, the patterning of the top electrode layer and the barrier and ferroelectric layers includes: etching back is performed on the top electrode layer, the barrier layer and the ferroelectric layer to remove horizontally extending sections of the top electrode layer, the barrier layer and the ferroelectric layer and to form sidewall structures on top sidewall portions of the bottom electrode, wherein the sidewall structures comprise sections of the top electrode and the barrier layer and the ferroelectric layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit chip comprising a memory cell, wherein the memory cell comprises:

a first electrode and a second electrode, each comprising a metal;

a ferroelectric layer between the first electrode and the second electrode; and

a barrier layer between the ferroelectric layer and the first electrode;

wherein the barrier layer is configured to block diffusion of a first metal of the first electrode to the ferroelectric layer, and wherein the first metal of the first electrode has a lower electronegativity than a second metal of the second electrode.

2. The integrated circuit chip of claim 1, wherein the barrier layer directly contacts the ferroelectric layer and the first electrode, and wherein the second electrode directly contacts the ferroelectric layer.

3. The integrated circuit chip of claim 1, wherein the barrier layer is amorphous.

4. The integrated circuit chip of claim 1, wherein the barrier layer is a semiconductor.

5. The integrated circuit chip of claim 1, wherein the barrier layer is a conductive metal oxide.

6. The integrated circuit chip of claim 1, wherein the ferroelectric layer comprises a non-zero atomic percent of the first metal, the non-zero atomic percent being less than 10%.

7. An integrated circuit chip comprising a memory cell, wherein the memory cell comprises:

a bottom electrode at a bottom of the memory cell;

a top electrode at the top of the memory cell;

a ferroelectric layer between the bottom electrode and the top electrode; and

a diffusion barrier layer between the ferroelectric layer and a first electrode, wherein the first electrode is one of the bottom electrode and the top electrode, and wherein the first electrode comprises a metal having an electronegativity of less than 1.6.

8. The integrated circuit chip of claim 7, wherein the memory cell further comprises:

a second diffusion barrier layer located between the ferroelectric layer and a second electrode, wherein the second electrode is the other of the bottom electrode and the top electrode, and wherein the first electrode comprises a metal having an electronegativity of less than 1.6.

9. The integrated circuit chip of claim 7, wherein the ferroelectric layer directly contacts a second electrode, wherein the second electrode is the other of the bottom electrode and the top electrode, and wherein the second electrode comprises a metal having an electronegativity greater than 1.6.

10. A method of forming an integrated circuit chip, comprising:

forming a bottom electrode over a substrate;

depositing a stacked barrier layer, ferroelectric layer, and top electrode layer over the substrate;

patterning the top electrode layer to form a top electrode; and

patterning the barrier layer and the ferroelectric layer to delineate sections of the barrier layer and the ferroelectric layer that are separate from memory cells;

wherein after patterning the barrier layer and the ferroelectric layer, the bottom and top electrodes and the segments of the barrier layer and the ferroelectric layer form the memory cell,

Wherein the bottom electrode and the top electrode comprise metal, and

wherein the barrier layer is located between the ferroelectric layer and the electrode having the lowest metal electronegativity among the bottom electrode and the top electrode.