CN117097311A - Withstand voltage circuit of enhanced power device - Google Patents
Withstand voltage circuit of enhanced power device Download PDFInfo
- Publication number
- CN117097311A CN117097311A CN202311130239.6A CN202311130239A CN117097311A CN 117097311 A CN117097311 A CN 117097311A CN 202311130239 A CN202311130239 A CN 202311130239A CN 117097311 A CN117097311 A CN 117097311A
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- voltage
- power device
- power
- circuit
- nmos
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- 230000002708 enhancing effect Effects 0.000 claims abstract description 12
- 230000015556 catabolic process Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a voltage-withstand circuit for enhancing a power device, which comprises the power device provided with a first power port and a second power port, a grid pull-down circuit connected between a grid electrode of the power device and the second power port of the power device, and a voltage-withstand enhancement auxiliary circuit electrically connected with the grid electrode of the power device, wherein the grid pull-down circuit is used for enabling the grid voltage to drop along with the voltage of the second power port so as to ensure the power device to be turned off, the voltage-withstand enhancement auxiliary circuit is used for lifting the voltage of the second power port, and the power device is provided as an N-type mos tube. The invention avoids selecting high voltage resistant device, saves cost and improves product reliability.
Description
Technical Field
The invention relates to the technical field of voltage-resistant circuits, in particular to a voltage-resistant circuit for enhancing a power device.
Background
The power device is used for bearing high withstand voltage through high current, and the control port is used for controlling the on-off of the power device, so that the current is allowed or forbidden to pass. During power device turn-on, the voltage difference between the first power port and the second power port is low due to the very low turn-on resistance. At the moment of disconnecting the power device, a very high positive voltage or a very low negative voltage is generated at the moment of the power port due to parasitic inductance or external equipment characteristics, so that the two ends of the power device bear high voltage difference, and if the voltage difference is too high, the power device breaks down and fails.
In general, in order to avoid this, a power device with a higher withstand voltage is selected, but this also means a higher cost, and depending on the application, it is difficult to cut the device with a higher withstand voltage.
Disclosure of Invention
In view of this, the present invention provides an auxiliary circuit for enhancing the voltage-withstanding circuit of a power device to detect a certain power port voltage, and when the voltage is too low or too high, the auxiliary circuit operates the control port to turn on the power device, and clamps the power port voltage with a low on-resistance of the power device so that the power device is not too low or too high, thereby preventing the power device from breakdown. Therefore, the selection of high-voltage-resistant devices is avoided, the cost is saved, and the reliability of products is improved.
In order to solve the technical problems, the invention adopts the following technical scheme: the voltage-withstand-voltage-enhancing circuit of the power device comprises the power device provided with a first power port and a second power port, a grid pull-down circuit connected between a grid of the power device and the second power port of the power device and a voltage-withstand-enhancing auxiliary circuit electrically connected with the grid of the power device, wherein the grid pull-down circuit is used for enabling the grid voltage to drop along with the voltage of the second power port so as to ensure that the power device is turned off, the voltage-withstand-enhancing auxiliary circuit is used for lifting the voltage of the second power port, and the power device is set as an N-type mos tube.
In the present invention, preferably, the voltage-withstand-enhancing auxiliary circuit includes a plurality of pmos transistors connected in series, a gate of the pmos transistor is connected to a drain thereof, a gate of the pmos transistor is connected to a gate of the power device, a source of the pmos transistor is connected to a drain of a next pmos transistor, and a source of the pmos transistor is externally connected to a reference voltage, and the reference voltage is externally connected to a power supply voltage.
In the present invention, preferably, the voltage-withstand-improving auxiliary circuit includes a plurality of nmos transistors connected in series, a gate of the first nmos transistor is connected to a drain thereof, a source of the first nmos transistor is connected to a gate of the power device, a drain of the first nmos transistor is connected to a source of a next nmos transistor, a drain of the last nmos transistor is externally connected to a reference voltage, and the reference voltage is externally connected to a power supply voltage.
In the present invention, preferably, the voltage-withstand-enhancing auxiliary circuit includes a plurality of pmos transistors connected in series and a plurality of nmos transistors connected in series, the gate of the first pmos transistor is connected to the drain thereof, the gate of the first pmos transistor is connected to the drain of the last nmos transistor, the source of the first pmos transistor is connected to the drain of the next pmos transistor, the source of the last pmos transistor is externally connected with a reference voltage, the reference voltage is externally connected with a power supply voltage, the gate of the first nmos transistor is connected to the drain thereof, the source of the first nmos transistor is connected to the gate of the power device, and the drain of the first nmos transistor is connected to the source of the next nmos transistor.
In the present invention, preferably, the voltage-withstand-improving auxiliary circuit includes a plurality of diodes connected in series.
In the present invention, preferably, the voltage-withstand-improving auxiliary circuit includes an nmos source follower, a drain electrode of the nmos source follower is externally connected with a power supply voltage, a source electrode of the nmos source follower is connected with a gate electrode of the power device, and a gate electrode of the nmos source follower generates a reference voltage, and the reference voltage is higher than the gate voltage of the power device by an nmos threshold value.
In the present invention, preferably, the withstand voltage enhancing auxiliary circuit includes a diode or a zener diode of reverse breakdown voltage.
In the present invention, preferably, the power device comprises a power device provided with a first power port and a second power port, and a voltage-withstand-enhancement auxiliary circuit connected with a gate of the power device, wherein the voltage-withstand-enhancement auxiliary circuit comprises a gate control circuit and a voltage comparator connected with the gate control circuit, the power device is provided with an N-type mos tube, the voltage comparator is used for comparing a reference voltage with a second power port voltage, and when the second power port voltage is too high or too low, the gate voltage is pulled up by the gate control circuit so as to clamp the second power port voltage.
The invention has the advantages and positive effects that: the voltage of a certain power port can be detected by arranging the voltage-resistant enhancement auxiliary circuit, when the voltage is too low or too high, the auxiliary circuit can operate the control port to open the power device, and the low on-resistance clamp of the power device is used for clamping the voltage of the power port, so that the power device cannot be broken down, the selection of a high voltage-resistant device is avoided, the cost is saved, and the reliability of a product is improved.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:
fig. 1 is an overall construction diagram of a withstand voltage circuit of an enhanced power device of the present invention;
fig. 2 is a schematic circuit diagram of an embodiment one of a voltage withstand circuit of an enhanced power device of the present invention;
fig. 3 is a schematic circuit diagram of a second embodiment of a voltage withstand circuit of an enhanced power device of the present invention;
fig. 4 is a circuit schematic of a third embodiment of a voltage withstand circuit of an enhanced power device of the present invention;
fig. 5 is a circuit schematic of an embodiment four of a voltage withstand circuit of an enhanced power device of the present invention;
fig. 6 is a circuit schematic of an embodiment five of a voltage withstand circuit of an enhanced power device of the present invention;
fig. 7 is a circuit schematic of a sixth embodiment of a withstand voltage circuit of an enhanced power device of the present invention;
fig. 8 is a circuit schematic of an embodiment seven of the voltage withstand circuit of the enhanced power device of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When a component is considered to be "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the invention provides a voltage-withstanding circuit for enhancing a power device, which comprises the power device provided with a first power port and a second power port, a gate pull-down circuit connected between a gate of the power device and the second power port of the power device, and a voltage-withstanding enhancement auxiliary circuit electrically connected with the gate of the power device, wherein the gate pull-down circuit is used for enabling the gate voltage to drop along with the voltage of the second power port so as to ensure that the power device is turned off, the voltage-withstanding enhancement auxiliary circuit is used for raising the voltage of the second power port, the power device is provided with an N-type mos tube, and if the power device is turned off, the second power port is a negative voltage relative to the first power port, the gate pull-down circuit should enable the gate voltage to drop along with the voltage of the second power port so as to ensure the turn-off.
Embodiment one:
as shown in fig. 2, in this embodiment, the voltage-withstanding enhancement auxiliary circuit includes a plurality of pmos transistors connected in series, the gate of the first pmos transistor is connected to the drain thereof, the gate of the first pmos transistor is connected to the gate of the power device, the source of the first pmos transistor is connected to the drain of the next pmos transistor, the source of the last pmos transistor is externally connected to a reference voltage, the reference voltage is externally connected to a power supply voltage, the voltage-withstanding enhancement auxiliary circuit is provided so as to prevent the negative voltage of the second power port from being too low, the voltage-withstanding enhancement auxiliary circuit is connected in series through a plurality of pmos transistors, the number of series is selected according to the voltage difference between the reference voltage and the desired limit of the second power port, the gate voltage is limited, when the voltage of the second power port is further reduced below the desired voltage, the pmos series structure is turned on, the gate voltage will not be lowered, so that the nmos transistor of the power device is turned on, and the voltage of the second power port is clamped.
Embodiment two:
as shown in fig. 3, in this embodiment, the voltage-withstand enhancement auxiliary circuit includes several nmos transistors connected in series, the gate of the first nmos transistor is connected to the drain thereof, the source of the first nmos transistor is connected to the gate of the power device, the drain of the first nmos transistor is connected to the source of the next nmos transistor, the drain of the last nmos transistor is externally connected to a reference voltage, and the reference voltage is externally connected to a power supply voltage, and the working principle is similar to that of the embodiment and will not be further described herein.
Embodiment III:
as shown in fig. 4, in this embodiment, the voltage-withstand-enhancement auxiliary circuit includes a plurality of pmos transistors connected in series and a plurality of nmos transistors connected in series, the gate of the first pmos transistor is connected to the drain thereof, the gate of the first pmos transistor is connected to the drain of the last nmos transistor, the source of the first pmos transistor is connected to the drain of the next pmos transistor, the source of the last pmos transistor is externally connected to a reference voltage, the reference voltage is externally connected to a power supply voltage, the gate of the first nmos transistor is connected to the drain thereof, the source of the first nmos transistor is connected to the gate of the power device, and the drain of the first nmos transistor is connected to the source of the next nmos transistor, and the operation principle thereof is similar to that of the embodiment and will not be further described herein.
Embodiment four:
as shown in fig. 5, in the present embodiment, the voltage-withstand-improving auxiliary circuit includes a plurality of diodes connected in series, and the working principle is similar to that of the embodiment, and will not be further described herein.
Fifth embodiment:
as shown in fig. 6, in this embodiment, the voltage-withstand-improving auxiliary circuit includes an nmos source follower, the drain of which is externally connected with a power supply voltage, the source of which is connected to the gate of the power device, and the gate of which generates a reference voltage that is higher than the gate voltage of the power device by one nmos threshold. The present embodiment limits the gate voltage with an nmos source follower, requiring the generation of a reference voltage that is one nmos threshold above the gate limit voltage, thereby limiting further drop of the gate.
Example six:
as shown in fig. 7, in the present embodiment, the withstand voltage enhancing auxiliary circuit includes a diode or a zener diode of reverse breakdown voltage. The present embodiment utilizes a diode or zener diode reverse breakdown voltage that also limits the gate voltage drop if it is close to the desired second power port limit voltage. In actual use, however, it may not be easy to find a device with a suitable breakdown voltage.
Embodiment seven:
as shown in fig. 8, in this embodiment, the power device includes a power device provided with a first power port and a second power port, and a voltage-withstand-enhancement auxiliary circuit connected to a gate of the power device, the voltage-withstand-enhancement auxiliary circuit includes a gate control circuit and a voltage comparator connected to the gate control circuit, the power device is provided as an N-type mos transistor, the voltage comparator is used for comparing a reference voltage with the second power port voltage, and when the second power port voltage is too high or too low, the gate voltage is pulled up by the gate control circuit to clamp the second power port voltage.
According to the invention, the voltage of a certain power port can be detected by arranging the voltage-withstand enhancement auxiliary circuit, when the voltage is too low or too high, the auxiliary circuit can operate the control port, the power device is turned on, and the low on-resistance of the power device clamps the voltage of the power port so that the power device cannot be too low or too high, and therefore, the power device cannot be broken down, the selection of a high voltage-withstand device is avoided, the cost is saved, and the reliability of a product is improved.
The foregoing describes the embodiments of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by this patent.
Claims (8)
1. The voltage withstand circuit of the enhancement power device is characterized by comprising a power device provided with a first power port and a second power port, a grid pull-down circuit connected between a grid of the power device and the second power port of the power device and a voltage withstand enhancement auxiliary circuit electrically connected with the grid of the power device, wherein the grid pull-down circuit is used for enabling the grid voltage to drop along with the voltage of the second power port so as to ensure the power device to be turned off, the voltage withstand enhancement auxiliary circuit is used for lifting the voltage of the second power port, and the power device is an N-type mos tube.
2. The voltage-withstanding circuit of the enhanced power device according to claim 1, wherein the voltage-withstanding enhanced auxiliary circuit comprises a plurality of pmos transistors connected in series, a gate of the pmos transistor is connected with a drain thereof, a gate of the pmos transistor is connected with a gate of the power device, a source of the pmos transistor is connected with a drain of a next pmos transistor, a source of the pmos transistor is externally connected with a reference voltage, and the reference voltage is externally connected with a power supply voltage.
3. The voltage-resistant circuit for enhancing a power device according to claim 1, wherein the voltage-resistant enhancing auxiliary circuit comprises a plurality of nmos tubes connected in series, wherein the grid electrode of the first nmos tube is connected with the drain electrode of the first nmos tube, the source electrode of the first nmos tube is connected with the grid electrode of the power device, the drain electrode of the first nmos tube is connected with the source electrode of the next nmos tube, the drain electrode of the last nmos tube is externally connected with a reference voltage, and the reference voltage is externally connected with a power supply voltage.
4. The voltage-resistant circuit for enhancing a power device according to claim 1, wherein the voltage-resistant enhancing auxiliary circuit comprises a plurality of pmos transistors connected in series and a plurality of nmos transistors connected in series, wherein a grid electrode of the first pmos transistor is connected with a drain electrode of the last nmos transistor, a source electrode of the first pmos transistor is connected with a drain electrode of the next pmos transistor, a source electrode of the last pmos transistor is externally connected with a reference voltage, the reference voltage is externally connected with a power supply voltage, a grid electrode of the first nmos transistor is connected with a drain electrode of the first nmos transistor, a source electrode of the first nmos transistor is connected with a grid electrode of the power device, and a drain electrode of the first nmos transistor is connected with a source electrode of the next nmos transistor.
5. The voltage-tolerant circuit of an enhanced power device of claim 1 wherein said voltage-tolerant enhancement auxiliary circuit comprises a plurality of diodes connected in series.
6. The voltage-tolerant circuit of claim 1, wherein the voltage-tolerant enhancement-aid circuit comprises an nmos source follower, a drain of the nmos source follower is externally connected with a power supply voltage, a source of the nmos source follower is connected with a gate of the power device, and a gate of the nmos source follower generates a reference voltage, the reference voltage is higher than the gate voltage of the power device by an nmos threshold.
7. The voltage-withstand voltage enhancing circuit of a power device according to claim 1, wherein the voltage-withstand enhancing auxiliary circuit includes a diode or a zener diode of reverse breakdown voltage.
8. The voltage-withstanding circuit of the enhancement power device according to claim 1, comprising a power device provided with a first power port and a second power port, a voltage-withstanding enhancement auxiliary circuit connected to a gate of the power device, the power device being provided as an N-type mos transistor, the voltage-withstanding enhancement auxiliary circuit comprising a gate control circuit and a voltage comparator connected to the gate control circuit, the voltage comparator being for comparing a reference voltage with a second power port voltage, and pulling up the gate voltage by the gate control circuit to clamp the second power port voltage when the second power port voltage is too high or too low.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311130239.6A CN117097311A (en) | 2023-09-04 | 2023-09-04 | Withstand voltage circuit of enhanced power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311130239.6A CN117097311A (en) | 2023-09-04 | 2023-09-04 | Withstand voltage circuit of enhanced power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117097311A true CN117097311A (en) | 2023-11-21 |
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ID=88773235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311130239.6A Pending CN117097311A (en) | 2023-09-04 | 2023-09-04 | Withstand voltage circuit of enhanced power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117097311A (en) |
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2023
- 2023-09-04 CN CN202311130239.6A patent/CN117097311A/en active Pending
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