CN117096175A

CN117096175A - Semiconductor device and method of forming the same

Info

Publication number: CN117096175A
Application number: CN202310445240.1A
Authority: CN
Inventors: 黄玉莲; 李资良; 李志鸿; 陈浚凯
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-07-14
Filing date: 2023-04-24
Publication date: 2023-11-21

Abstract

The application provides a semiconductor device and a method of forming the same. In one embodiment, a device includes: source/drain regions located over the semiconductor substrate; a dielectric layer over the source/drain regions, the dielectric layer comprising a first dielectric material; an interlayer dielectric over the dielectric layer, the interlayer dielectric comprising a second dielectric material and an impurity, the second dielectric material being different from the first dielectric material, a first portion of the interlayer dielectric having a first concentration of the impurity, a second portion of the interlayer dielectric having a second concentration of the impurity, the first concentration being less than the second concentration; and a source/drain contact extending through the interlayer dielectric and the dielectric layer to contact the source/drain region, a first portion of the interlayer dielectric disposed between the source/drain contact and a second portion of the interlayer dielectric.

Description

Semiconductor device and method of forming the same

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method of forming the same.

Background

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: materials of an insulating layer or a dielectric layer, a conductive layer, and a semiconductor layer are sequentially deposited over a semiconductor substrate, and the respective material layers are patterned using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems that should be solved arise.

Disclosure of Invention

According to an aspect of the present application, there is provided a device comprising: source/drain regions over the semiconductor substrate; a dielectric layer over the source/drain regions, the dielectric layer comprising a first dielectric material; an interlayer dielectric over the dielectric layer, the interlayer dielectric comprising a second dielectric material and an impurity, the second dielectric material being different from the first dielectric material, a first portion of the interlayer dielectric having a first concentration of the impurity, a second portion of the interlayer dielectric having a second concentration of the impurity, the first concentration being less than the second concentration; and source/drain contacts extending through the interlayer dielectric and the dielectric layer to contact the source/drain regions, a first portion of the interlayer dielectric being disposed between the source/drain contacts and the second portion of the interlayer dielectric.

According to another aspect of the application there is provided a device comprising: a first conductive feature over the semiconductor substrate; a dielectric layer over the first conductive feature; and a second conductive feature extending through the dielectric layer to contact the first conductive feature, a first portion of the dielectric layer surrounding the second conductive feature in a top view, a second portion of the dielectric layer being separated from the second conductive feature by the first portion of the dielectric layer in a top view, the second portion of the dielectric layer comprising silicon oxide having hydrogen impurities, the first portion of the dielectric layer comprising silicon oxide having no hydrogen impurities.

According to yet another aspect of the present application, there is provided a method comprising: depositing a dielectric material on the etch stop layer; patterning a contact opening in a dielectric material to expose the etch stop layer; reducing a first etch rate of a first portion of the dielectric material to be less than a second etch rate of a second portion of the dielectric material, the first portion of the dielectric material being disposed between the contact opening and the second portion of the dielectric material; extending the contact opening through the etch stop layer by performing an etching process, the first etch rate and the second etch rate being related to the etching process; and forming a contact in the contact opening.

Drawings

The aspects of the disclosure may be best understood from the following detailed description when read with the accompanying drawing figures. Note that the various features are not drawn to scale according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates an example of a fin field effect transistor (FinFET) according to some embodiments.

Fig. 2-23D are views of intermediate stages in the fabrication of finfets according to some embodiments.

Fig. 24A-24D are views of finfets according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "lower," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature to another element(s) or feature(s) shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to various embodiments, the openings for the contacts/vias are formed by a dielectric material such as an interlayer dielectric or an intermetallic dielectric. A dielectric material is disposed on the etch stop layer. One or more treatment processes are performed to reduce the etch rate of the dielectric material surrounding the opening relative to the etch process used to clean the opening. Damage to the dielectric material during the cleaning process may be reduced, thereby increasing the electrical isolation capability of the dielectric material.

Fig. 1 illustrates an example of a fin field effect transistor (FinFET) according to some embodiments. Fig. 1 is a three-dimensional view with some features of the FinFET omitted for clarity. The FinFET includes a fin 52 that extends higher than a major surface of a substrate 50 (e.g., a semiconductor substrate), where the fin 52 serves as a channel region 58 of the FinFET. Isolation regions 56, such as Shallow Trench Isolation (STI) regions, are disposed between adjacent fins 52, and fins 52 may protrude higher than these isolation regions 56 from between adjacent isolation regions 56. The isolation regions 56 between the fins 52 are fin isolation structures. Although isolation region 56 is depicted/illustrated as being separate from substrate 50, as used herein, the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and an isolation region. Furthermore, although the lower portion of fin 52 is shown as a single continuous material with substrate 50, the lower portion of fin 52 and/or substrate 50 may comprise a single material or multiple materials.

Gate dielectric 112 is along the sidewalls of fin 52 and over the top surface of fin 52. A gate electrode 114 is located over the gate dielectric 112. Source/drain regions 88 (shown in phantom) are disposed on opposite sides of fin 52 with respect to gate dielectric 112 and gate electrode 114. Source/drain region(s) 88 may refer to either a source or a drain, individually or collectively, depending on the context. Gate spacers 82 separate source/drain regions 88 from gate dielectric 112 and gate electrode 114. An interlayer dielectric (ILD) 94 is formed over the source/drain regions 88. Contacts (described later) to the source/drain regions 88 will be formed through ILD 94. The source/drain regions 88 may be shared between the various fins 52. For example, adjacent source/drain regions 88 may be electrically connected, such as by merging the source/drain regions 88 by epitaxial growth or by coupling the source/source regions 88 with the same source/drain contacts.

Fig. 1 further shows a reference section for use in later figures. The cross-section AA' is along the longitudinal axis of the fin 52 and in the direction of current flow between the source/drain regions 88 of, for example, a FinFET. Cross section BB 'is perpendicular to cross section AA' and along the longitudinal axis of gate electrode 114. Cross section CC 'is parallel to cross section BB' and extends through source/drain regions 88 of the FinFET. For clarity, subsequent figures refer to these reference sections.

Some embodiments discussed herein are discussed in the context of finfets formed using a gate last process. In other embodiments, a gate-first process may be used.

Fig. 2-23D are views of intermediate stages in the fabrication of finfets according to some embodiments. Fig. 2, 3, 4 and 5 are three-dimensional views showing three-dimensional views similar to fig. 1. Fig. 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, and 23A are sectional views shown along a section similar to the reference section AA' in fig. 1. Fig. 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, and 23B are sectional views shown along a section similar to the reference section BB' in fig. 1. Fig. 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C, 22C, and 23C are sectional views shown along a section similar to the reference section CC' in fig. 1. Fig. 19D and 23D are plan views.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor or semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with a p-type dopant or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, the SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer or a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination of the foregoing.

The substrate 50 has an N-type region 50N and a P-type region 50P. The N-type region 50N may be used to form an N-type device, such as an NMOS transistor, for example an N-type FinFET. The P-type region 50P may be used to form a P-type device, such as a PMOS transistor, for example, a P-type FinFET. The N-type region 50N may be physically separated from the P-type region 50P (not separately shown), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the N-type region 50N and the P-type region 50P. Although one N-type region 50N and one P-type region 50P are shown, any number of N-type regions 50N and P-type regions 50P may be provided.

Fins 52 are formed in the substrate 50. Fin 52 is a semiconductor strip, which may also be referred to as a semiconductor fin. Fin 52 may be formed in substrate 50 by etching a trench in substrate 50. The etching may be any acceptable etching process, such as Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching process may be anisotropic.

Fin 52 may be patterned by any suitable method. For example, fin 52 may be patterned using one or more photolithographic processes, including a double patterning process or a multiple patterning process. Typically, a double patterning process or multiple patterning process combines lithography and self-aligned processes, allowing patterns to be created with, for example, smaller pitches than those obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins. In some embodiments, a mask (or other layer) may remain on fin 52.

An insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide (e.g., silicon oxide), nitride, etc., or a combination thereof, and may be formed by a Chemical Vapor Deposition (CVD) process, such as high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it to another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In some embodiments, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. Although insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50 and fin 52. Thereafter, a filler material, such as one of the insulating materials previously described, may be formed over the liner.

In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. A removal process may be applied to the insulating material 54 to remove excess insulating material 54 over the fins 52. In some embodiments, a planarization process is used, such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like. The planarization process may expose the fin 52 such that after the planarization process, the top surfaces of the fin 52 and the insulating material 54 are substantially coplanar (within process variations). In embodiments where the mask remains on fin 52, the planarization process may expose the mask or remove the mask such that after the planarization process, the top surface of mask or fin 52, respectively, is substantially coplanar with insulating material 54 (within process variations).

The foregoing process is merely one example of how fin 52 may be formed. In some embodiments, fin 52 may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures may be epitaxially grown in the trenches to form fins 52. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 52. For example, fin 52 may be recessed, and a different material than fin 52 may be epitaxially grown over recessed fin 52. In such an embodiment, fin 52 includes a recessed material and an epitaxially grown material disposed over the recessed material. In still further embodiments, a dielectric layer may be formed over the top surface of the substrate 50 and trenches etched through the dielectric layer. A hetero-epitaxial structure may then be epitaxially grown in the trench using a material different from the substrate 50 to form the fin 52. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid previous and subsequent implants, although in situ doping and implant doping may be used together.

Still further, it may be advantageous to epitaxially grow a material in the N-type region 50N (e.g., NMOS region) that is different from the material of the P-type region 50P (e.g., PMOS region). In various embodiments, fin 52 may be made of silicon germanium (Si _x Ge _1-x Where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, and the like. For example, useful materials for forming the III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum phosphide, gallium phosphide, and the like.

In fig. 3, insulating material 54 is recessed to form STI regions 56. The insulating material 54 is recessed such that an upper portion of the fin 52 protrudes from between adjacent STI regions 56. Further, the top surface of STI region 56 may have a flat surface, convex, concave (e.g., dished), or a combination thereof, as shown. The top surface of STI region 56 may be formed flat, convex, and/or concave by a suitable etch. STI regions 56 may be recessed using an acceptable etching process, such as an etching process selective to the material of insulating material 54 (e.g., etching the material of insulating material 54 at a faster rate than the material of fin 52). For example, the oxide removal may be performed using dilute hydrofluoric acid (dHF).

Furthermore, suitable wells (not separately shown) may be formed in fin 52 and/or substrate 50. The well may have a conductivity type opposite to that of a source/drain region to be subsequently formed in each of the N-type region 50N and the P-type region 50P. In some embodiments, a P-type well is formed in N-type region 50N and an N-type well is formed in P-type region 50P. In some embodiments, a P-type well or an N-type well is formed in both the N-type region 50N and the P-type region 50P.

In embodiments with different well types, the different implantation steps of the N-type region 50N and the P-type region 50P may be implemented using a mask (not separately shown), such as a photoresist. For example, a photoresist may be formed over fin 52 and STI region 56 in N-type region 50N. The photoresist is patterned to expose the P-type region 50P of the substrate 50. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, it is in the P-type region 50PN-type impurity implantation is performed, and the photoresist may act as a mask to substantially prevent N-type impurities from being implanted into the N-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc. implanted into the region at a concentration of 10 or less ¹⁸ cm ^-3 For example at 10 ¹⁶ cm ^-3 To 10 ¹⁸ cm ^-3 Between them. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

After or before implantation of the P-type region 50P, a mask (not separately shown), such as a photoresist, is formed over the fin 52 and STI region 56 in the P-type region 50. The photoresist is patterned to expose N-type region 50N of substrate 50. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, P-type impurity implantation may be performed in the N-type region 50N, and the photoresist may act as a mask to substantially prevent P-type impurities from being implanted into the P-type region 50P. The p-type impurity may be boron, boron fluoride, indium, etc. implanted into the region at a concentration of 10 or less ¹⁸ cm ^-3 For example at 10 ¹⁶ cm ^-3 To 10 ¹⁸ cm ^-3 Between them. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

After implantation of the N-type region 50N and the P-type region 50P, an anneal may be performed to repair the implant damage and activate the implanted P-type and/or N-type impurities. In some embodiments where epitaxial growth of the epitaxial structure is performed on fin 52, the grown material may be doped in situ during growth, which may avoid previous and subsequent implants, although in situ doping and implant doping may be used together.

In fig. 4, a dummy dielectric layer 62 is formed on fin 52. The dummy dielectric material 62 may be formed of a dielectric material, such as silicon oxide, silicon nitride, combinations thereof, or the like, which may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 64 is formed over the dummy dielectric layer 62. A dummy gate layer 64 may be deposited over the dummy dielectric layer 62 and then planarized by CMP. The dummy gate layer 64 may be formed of an electrically conductive or non-conductive material, such as amorphous silicon, polysilicon (polysilicon), polysilicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, etc., which may be deposited by Physical Vapor Deposition (PVD), CVD, etc. The dummy gate layer 64 may be formed of a material having a high etch selectivity to an insulating material (e.g., the STI region 56 and/or the dummy dielectric layer 62). A mask layer 66 is formed over the dummy gate layer 64. A mask layer 66 may be deposited over the dummy gate layer 64. The mask layer 66 may be formed of a dielectric material (e.g., silicon nitride, silicon oxynitride, etc.). In this example, a single dummy gate layer 64 and a single mask layer 66 are formed over the N-type region 50N and the P-type region 50P. In the illustrated embodiment, the dummy dielectric layer 62 covers the fin 52 and the STI region 56 such that the dummy dielectric layer 62 extends over the STI region 52 and between the dummy gate layer 64 and the STI region 56. In another embodiment, the dummy dielectric layer 62 covers only the fin 52.

In fig. 5, mask layer 66 is patterned using acceptable photolithography and etching techniques to form mask 76. The pattern of mask 76 is then transferred to dummy gate layer 64 by any acceptable etching technique to form dummy gate 74. The pattern of mask 76 may optionally be further transferred to dummy dielectric layer 62 by any acceptable etching technique to form dummy dielectric 72. The dummy gate 74 overlies each channel region 58 of the fin 52. The mask 76 pattern may be used to physically separate adjacent dummy gates 74. The dummy gate 74 may also have a longitudinal direction that is substantially perpendicular (within process variations) to the longitudinal direction of the fin 52. The mask 76 may be removed during patterning of the dummy gate 74 or may be removed during subsequent processing.

Fig. 6A-23D illustrate various additional steps in the fabrication of the device of the embodiment. Fig. 6A-23D illustrate features of either of N-type region 50N and P-type region 50P. For example, the illustrated structure may be applicable to both N-type region 50N and P-type region 50P. Differences in the structure of N-type region 50N and P-type region 50P, if any, are explained in the description accompanying each figure.

In fig. 6A-6C, gate spacers 82 are formed over fin 52 and on exposed sidewalls of mask 76 (if present), dummy gate 74, and dummy dielectric 72. The gate spacers 82 may be formed by conformally depositing one or more dielectric materials and then etching the dielectric material(s). Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and the like, which may be formed by conformal deposition processes (e.g., chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like). Other dielectric materials formed by any acceptable process may be used. Any acceptable etching process (e.g., dry etching, wet etching, etc., or combinations thereof) may be performed to pattern the dielectric material(s). The etching may be anisotropic. This dielectric material(s) leaves a portion on the sidewalls of the dummy gate 74 (thereby forming gate spacers 82, see fig. 6A) when etched. In some embodiments, the etch used to form gate spacers 82 is adjusted so that, upon etching, this dielectric material(s) also has a portion that remains on the sidewalls of fin 52 (thereby forming fin spacers 84, see fig. 6C). After etching, fin spacers 84 (if present) and gate spacers 82 may have straight sidewalls (as shown) or may have sidewalls with rounded corners.

In addition, implantation may be performed to form lightly doped source/drain (LDD) regions (not separately shown) in fin 52. In embodiments with different device types, similar to the implantation for the wells described above, a mask (not separately shown), such as photoresist, may be formed over the N-type region 50N while exposing the P-type region 50P, and an appropriate type (e.g., P-type) of impurity may be implanted into the fin 52 exposed in the P-type region 50P. The mask may then be removed. Subsequently, a mask (not separately shown), such as a photoresist, may be formed over the P-type region 50P while exposing the N-type region 50N, and an appropriate type (e.g., N-type) of impurity may be implanted into the fin 52 exposed in the N-type region 50. The mask may then be removed. The n-type impurity may be any of the n-type impurities described previously, and the p-type impurity may be any of the p-type impurities described previously. During implantation, the channelRegion 58 remains covered by dummy gate 74 such that channel region 56 remains substantially free of implanted impurities to form an LDD region. The impurity concentration of the LDD region may be 10 ¹⁵ cm ^-3 To 10 ¹⁹ cm ^-3 Within a range of (2). Annealing may be used to repair implant damage and activate implanted impurities.

Note that the previous disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or more spacers may be used, a different sequence of steps may be used, spacers may be formed and removed, and so on. In addition, different structures and steps may be used to form n-type devices and p-type devices.

In fig. 7A-7C, epitaxial source/drain regions 88 are formed in fin 52. Epitaxial source/drain regions 88 are formed in the fin 52 such that each dummy gate 74 is disposed between a respective adjacent pair of epitaxial source/drain regions 88. In some embodiments, the epitaxial drain/source regions 88 may extend into the fin 52 and may also penetrate the fin 52. In some embodiments, the gate spacers 82 are used to separate the epitaxial source/drain regions 88 from the dummy gate 74 by an appropriate lateral distance so that the epitaxial source and drain regions 82 do not short the subsequently formed gates of the resulting FinFET. The material of the epitaxial source/drain regions 88 may be selected to apply stress in the corresponding channel regions 58 to improve performance.

Epitaxial source/drain regions 88 in N-type region 50N may be formed by masking P-type region 50P and etching the source/source regions of fin 52 in N-type region 50N to form a recess in fin 52. Epitaxial source/drain regions 88 in N-type region 50N are then epitaxially grown in the recess. Epitaxial source/drain regions 88 may comprise any acceptable material suitable for n-type devices. For example, if fin 52 is silicon, epitaxial source/drain regions 88 in N-type region 50N may include a material that imparts a tensile strain on channel region 58, such as silicon, silicon carbide, phosphorus doped silicon carbide, and the like. The epitaxial source/drain regions 88 in the N-type region 50N may be referred to as "N-type source/source regions". The epitaxial gate/drain regions 88 in the n-type region 50 may have a surface raised from the surface of the corresponding fin 52 and may have facets.

Epitaxial source/drain regions 88 in P-type region 50P may be formed by masking N-type region 50N and etching source/drain regions of fin 52 in P-type region 50P to form a recess in fin 52. Epitaxial drain/source regions 88 in P-type region 50P are then epitaxially grown in the recess. Epitaxial source/drain regions 88 may comprise any acceptable material suitable for p-type devices. For example, if fin 52 is silicon, epitaxial source/drain regions 88 in P-type region 50P may include a material that imparts a compressive strain on channel region 58, such as silicon germanium, boron doped silicon germanium, germanium tin, and the like. The epitaxial source/drain regions 88 in the P-type region 50P may be referred to as "P-type source/source regions". The epitaxial drain/source regions 88 in the p-type region 50 may have a surface raised from the surface of the corresponding fin 52 and may have facets.

The epitaxial source/drain regions 88 and/or fin 52 may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly doped source/source regions, followed by an anneal. The impurity concentration of the source/drain region may be 10 ¹⁹ cm ^-3 To 10 ²¹ cm ^-3 Between them. The n-type impurity and/or the p-type impurity of the source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions 88 may be doped in-situ during growth.

As a result of the epitaxial process used to form epitaxial source/drain regions 88, the upper surfaces of the epitaxial source/drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets cause adjacent epitaxial source or drain regions 88 to merge, as shown in fig. 1. In some embodiments, as shown in fig. 7C, adjacent epitaxial source/drain regions 88 remain separated after the epitaxial process is completed. In the illustrated embodiment, fin spacers 84 are formed to cover a portion of the sidewalls of fin 52 that extend higher than STI regions 56, thereby preventing epitaxial growth. In another embodiment, the spacer etch used to form gate spacers 82 is adjusted to not form fin spacers 84, allowing epitaxial source/drain regions 88 to extend to the surface of STI regions 56.

In fig. 8A-8C, a first ILD 94 is deposited over the epitaxial source/drain regions 88, the gate spacers 82, and the mask 76 (if present) or the dummy gate 74. The first ILD 94 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma Enhanced CVD (PECVD), FCVD, or the like. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass, undoped silicate glass, and the like. Other dielectric materials formed by any acceptable process may be used.

In some embodiments, a Contact Etch Stop Layer (CESL) 92 is formed between the first ILD 94 and the epitaxial source/drain regions 88, the gate spacers 82, and the mask 76 (if present) or the dummy gate 74. CESL 92 may be formed of a dielectric material having a high etch selectivity relative to first ILD 94. Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and the like, which may be formed by conformal deposition processes such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like.

In fig. 9A-9C, a removal process is performed to bring the top surface of the first ILD 94 flush with the top surface of the mask 76 (if present) or dummy gate 74. In some embodiments, a planarization process is used, such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like. The planarization process may also remove the mask 76 on the dummy gate 74 and portions of the gate spacers 82 along the sidewalls of the mask 76. After the planarization process, the top surfaces of the first ILD 94, CESL 92, gate spacers 82 and mask 76 (if present) or dummy gate 76 are substantially coplanar (within process variations). Thus, the top surface of the mask 76 (if present) or dummy gate 74 is exposed by the removal process. In the illustrated embodiment, the mask 74 remains and the planarization process leaves the top surface of the first ILD 76 flush with the top surface of the mask 76.

In fig. 10A-10C, the mask 76 (if present) and dummy gate 74 are removed in an etching process, thereby forming recess 96. Portions of the dummy dielectric 72 in the recess 96 may also be removed. In some embodiments, only the dummy gate 74 is removed and the dummy dielectric 72 remains and is exposed through the recess 96. In some embodiments, the dummy dielectric is removed from the recess 96 in a first region (e.g., core logic region) of the die and is left in the recess 96 in a second region (e.g., input/output region) of the die. In some embodiments, the dummy gate 74 is removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process using a reactive gas(s) that selectively etches the dummy gate 74 at a faster rate than the first ILD 94 or gate spacer 82. During the removal, the dummy dielectric 72 may act as an etch stop layer when the dummy gate 74 is etched. The dummy dielectric 72 may then be optionally removed after the dummy gate 74 is removed. Each recess 96 exposes and/or overlies a channel region 58 of a respective fin 52.

In fig. 11A-11C, a gate dielectric 112 and a gate electrode 114 are formed for replacement gate structures. Each pair of gate dielectric 112 and gate electrode 114 may be collectively referred to as a gate structure. Each gate structure extends along the sidewalls and top surface of the channel region 58 of the fin 52. A gate structure is also located over STI region 56.

Gate dielectric 112 includes one or more gate dielectric layers disposed on the top surface and sidewalls of fin 52 and on the sidewalls of gate spacer 82. The gate dielectric 112 may be formed of an oxide such as silicon oxide or metal oxide, a silicate such as metal silicate, combinations thereof, multilayers thereof, or the like. Additionally or alternatively, the gate dielectric 112 may be formed of a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material(s) of the gate dielectric 112 may be formed by Molecular Beam Deposition (MBD), ALD, PECVD, or the like. Although a single layer of gate dielectric 112 is shown, the gate dielectric 112 may include any number of interface layers and any number of main layers. For example, gate dielectric 112 may include an interfacial layer and an overlying high-k dielectric layer.

The gate electrode 114 includes one or more gate electrode layers disposed over the gate dielectric 112. The gate electrode 114 may be formed of a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multilayers thereof, and the like. Although a single layer of gate electrode 114 is shown, gate electrode 114 may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and filler materials.

As an example of forming the gate structure, gate dielectric layer(s) may be deposited in recess 96. Gate dielectric layer(s) may also be deposited on top surfaces of first ILD 94, CESL 92 and gate spacer 82. Subsequently, gate electrode layer(s) may be deposited over the gate dielectric layer(s) and in the remainder of recess 96. A removal process may then be performed to remove the excess portion of the gate dielectric layer(s) and gate electrode layer(s) that are located over the top surfaces of the first ILD 94, CESL 92 and gate spacers 82. After the removal process, the gate dielectric(s) have portions that remain in the recess 96 (thereby forming the gate dielectric 112). After the removal process, the gate electrode layer(s) have portions that remain in the recess 96 (thereby forming the gate electrode 114). In some embodiments, a planarization process is used, such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like. After the planarization process, the top surfaces of the gate spacer 82, CESL 92, first ILD 94, and gate structure (including gate dielectric 112 and gate electrode 114) are substantially coplanar (within process variations).

The formation of the gate dielectric 112 in the N-type region 50N and the P-type region 50P may be performed simultaneously such that the gate dielectric 112 in each region is formed of the same material(s), and the formation of the gate electrode 114 may be performed simultaneously such that the gate electrode 114 in each region is formed of the same material(s). In some embodiments, the gate dielectric 112 in each region may be formed by a different process such that the gate dielectric 112 may comprise a different material and/or have a different number of layers, and/or the gate electrode 114 in each region may be formed by a different process such that the gate electrode 112 may comprise a different material and/or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

In fig. 12A-12C, a gate mask 116 is formed over the gate structure (including gate dielectric 112 and gate electrode 114). In some embodiments, a gate mask 116 may also be formed over the gate spacers 82. A gate contact will then be formed to penetrate gate mask 116 to contact the top surface of gate electrode 114.

As an example of forming the gate mask 116, the gate structure may be recessed using any acceptable etching process. In some embodiments (not separately shown), the gate spacers 82 are also recessed. One or more dielectric materials are then conformally deposited in the recess. Dielectric material(s) may also be deposited on top surfaces of the first ILD 94, CESL 92 and gate spacers 82. Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and the like, which may be formed by conformal deposition processes such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), plasma Enhanced Atomic Layer Deposition (PEALD), and the like. Other dielectric materials formed by any acceptable process may be used. A removal process is performed to remove the excess portion of the dielectric material(s) that is over the top surfaces of the first ILD 94, CESL 92 and gate spacers 82, thereby forming a gate mask 116. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like is used. When planarized, the dielectric material(s) have portions left in the recesses (thereby forming gate mask 116). After the planarization process, the top surfaces of the gate spacers 82, CESL 92, first ILD 94, and gate mask 116 are substantially coplanar (within process variations).

In fig. 13A-13C, contact mask layer(s) 124 are formed over gate spacer 82, CESL 92, first ILD94, and gate mask 116. The contact mask layer(s) 124 will be patterned to define the locations where contact openings are subsequently formed through the first ILD 94. In some embodiments, contact mask layer(s) 124 include a lower mask layer 124A and an upper mask layer 124B, wherein upper mask layer 124B has a high etch selectivity relative to the etch of lower mask layer 124A. The lower mask layer 124A may be formed of a metal such as tungsten carbide, titanium nitride, tantalum nitride, or the like, which may be formed by a deposition process such as PVD, or the like. The upper mask layer 124B may be formed of a dielectric material such as silicon oxide, which may be formed by a deposition process such as CVD, ALD, PEALD. Other acceptable materials formed by any acceptable process may be used.

In some embodiments, a liner layer 122 is formed between the contact mask layer 124 and the gate spacer(s) 82, CESL 92, first ILD94, and gate mask 116. The liner layer 122 may be formed of a dielectric material such as an oxide, for example, silicon oxide, aluminum oxide, etc., which may be deposited by CVD, ALD, PEALD, etc. In some embodiments, the liner layer 122 is a flowable film formed by a flowable CVD method. In addition, an etch stop layer (not separately shown) may optionally be formed between the liner layer 122 and the gate spacers 82, CESL 92, first ILD94, and gate mask 116. The etch stop layer may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having a high etch selectivity to the etching of the liner layer 122.

A dicing mask layer 126 is formed on the contact mask layer(s) 124. The dicing mask layer 126 will be patterned to define where the kerfs between subsequently formed contact openings are located, e.g., which locations of the first ILD 94 will not be patterned so that subsequently formed contact openings are separated. The dicing mask layer 126 may be formed of an inorganic material such as silicon, which may be formed by CVD, ALD, or the like.

In fig. 14A-14C, the dicing mask layer 126 is patterned using acceptable photolithography and etching techniques to form a dicing mask 132. For example, anisotropic dry etching may be performed using the photoresist 134 as an etching mask. The photoresist 134 may be a single layer photoresist, a double layer photoresist, a triple layer photoresist, or the like. In some embodiments, the photoresist 134 is a three-layer photoresist, including a bottom layer (e.g., bottom antireflective coating), a middle layer (e.g., nitride, oxide, oxynitride, etc.), and a top layer (e.g., photosensitive material). The photoresist 134 (and thus the dicing mask 132) has a pattern that will separate subsequently formed contact openings. After forming the dicing mask 132, the photoresist 134 may be removed, for example, by an acceptable ashing process.

In fig. 15A-15C, contact mask layer(s) 124 are patterned using acceptable photolithography and etching techniques to form contact mask 136. For example, anisotropic dry etching may be performed using the dicing mask 132 and the photoresist 138 as a combined etching mask. The photoresist 138 may be a single layer photoresist, a dual layer photoresist, a triple layer photoresist, or the like. In some embodiments, the photoresist 138 is a three-layer photoresist, including a bottom layer (e.g., bottom antireflective coating), a middle layer (e.g., nitride, oxide, oxynitride, etc.), and a top layer (e.g., photosensitive material). The photoresist 138 and the dicing mask 132 (and thus the contact mask 136) together have a pattern in which subsequently formed contact openings will be located. After the contact mask 136 is formed, the dicing mask 132 and/or the photoresist 138 may be removed, for example, by an acceptable ashing process, an acceptable etching process, combinations thereof, or the like.

In fig. 16A-16C, contact openings 140 are formed through the first ILD 94. The contact openings 140 may be formed using acceptable etching techniques. The contact mask 136 serves as an etch mask. The pattern of the contact mask 136 is transferred to the liner layer 122 (if present) and/or the first ILD 94. In the illustrated embodiment, the etching process used to form the contact openings 140 is a self-aligned contact (SAC) etching process in which the gate spacers 82 and the gate mask 116 are exposed to an etchant during etching of the contact openings 140. The etching may include any acceptable etching process, such as an etching process selective to the material of the first ILD94 (e.g., selectively etching the material of the first ILD94 at a faster rate than the material(s) of the gate spacers 82, CESL 92, and gate mask 116). The etching process may be anisotropic. CESL 92 stops etching contact openings 140. Thus, the contact opening 140 exposes the CESL 92, and the CESL 92 still covers the epitaxial source/drain regions 88.

In fig. 17A-17C, a treatment process 142 is performed in the contact opening 140. After the treatment process 142, a cleaning process 144 is performed in the contact opening 140. The cleaning process 144 may be performed before the contact openings 140 extend through the CESL 92 (described later).

The processing 142 modifies the etch rate of the processing region of the first ILD 94. Specifically, the processing 142 modifies the region 94M of the first ILD 94 surrounding the contact opening 140, wherein the unmodified region 94U of the first ILD 94 is unaffected by the processing 142 (or at least less affected than the modified ILD region 94M). As described in more detail, a cleaning process 144 will be performed to clean residues of the first ILD 94 from the contact openings 140 prior to extending the contact openings 140 through the CESL 92. The cleaning process 144 includes an etching process. The modified ILD region 94M has a reduced etch rate for the etch used in the cleaning process 144. Thus, the modified ILD region 94M has an increased etch selectivity relative to the etch used in the cleaning process 144 as compared to the unmodified ILD region 94U. In some embodiments, the treatment process 142 reduces the etching of the modified ILD region 94M during the cleaning process 144 by an amount in the range of 60% to 98%. Damage to the first ILD 94 during the cleaning process 144, such as damage caused by the etchant used in the cleaning process 144, may be reduced.

Depending on the type of deposition process used to form the first ILD 94, the first ILD 94 may contain one or more impurities that are capable of reacting with the etchant to be used in the cleaning process 144. The impurities may include hydrogen, carbon, and the like. For example, when the first ILD 94 is formed from silicon oxide by FCVD, the first ILD 94 may contain hydrogen impurities and the hydrogen impurities may react with fluorine-based etchants that may be used in the cleaning process 144. The processing 142 reduces those in the modified ILD regions 94M byThe concentration of impurities reduces the etch rate of modified ILD region 94M to be less than the etch rate of unmodified ILD region 94U for the etch used in cleaning process 144. In some embodiments, the impurity is hydrogen, the first ILD 94 has a hydrogen impurity concentration in the range of 5% to 10% prior to the treatment process 142, and the treatment process 142 reduces the hydrogen impurity concentration of the modified ILD region 94M (compared to the unmodified ILD region 94U) by 2% to 10% such that the modified ILD region 94M has a hydrogen impurity concentration of less than 5%. Impurities may (or may not) be eliminated from modified ILD region 94M, but in either case modified ILD region 94M has a lower impurity concentration than unmodified ILD region 94U. When the impurity is removed from the modified ILD region 94M, the impurity concentration of the modified ILD region 94M is zero. When impurities are not removed from modified ILD region 94M, the impurity concentration of modified ILD region 94M is not zero. Lowering the concentration of impurities may increase the density of modified ILD region 94M, depending on the type of impurities removed. In some embodiments where the impurity includes hydrogen, the treatment process 142 increases the density of the modified ILD region 94M (as compared to the unmodified ILD region 94U) by 2% to 10% such that the modified ILD region 94M has a density of at 2.25g/cm ³ To 2.3g/cm ³ Density in the range.

The unmodified ILD region 94U remains unmodified or less modified by the processing process 142 than the modified ILD region 94M. In some embodiments, the unmodified ILD region 94U retains its initial composition such that the final composition of the unmodified ILD region 94U after the treatment process 142 is the same as the initial composition of the unmodified ILD region 94U prior to the treatment process 142. In some embodiments, the unmodified ILD region 94U is modified by the processing 142, but is less modified than the modified ILD region 94M, such that the final composition of the unmodified ILD region 94U is closer to the initial composition of the unmodified ILD region 94U than the final composition of the modified ILD region 94M.

In some embodiments, the treatment process 142 includes a nitridation process. The nitridation process increases the nitrogen concentration of modified ILD region 94M. In some embodiments, the first ILD 94 has a nitrogen concentration in the range of 0% to 5% prior to the treatment process 142, and the treatment process 142 increases the nitrogen concentration of the modified ILD region 94M (compared to the unmodified ILD region 94U) by 2% to 10% such that the modified ILD region 94M has a nitrogen concentration in the range of 5% to 25%. If the final nitrogen concentration is greater than 25%, the insulating capability of the first ILD 94 may be poor. If the final nitrogen concentration is less than 5%, excessive etching of the modified ILD region 94M may occur in the cleaning process 144.

In some embodiments, the nitridation process is a nitrogen radical treatment process in which modified ILD region 94M is reacted with nitrogen radicals. The modified ILD region 94M may also be bombarded with nitrogen cations (e.g., positively charged nitrogen ions) during the nitrogen radical treatment process. The nitrogen radical treatment process may be performed in a chamber. A gas source is distributed in the chamber. The gas source includes a nitrogen-containing gas and a carrier gas. The nitrogen-containing gas may include ammonia (NH) ₃ ) Nitrogen (N) ₂ ) Etc. The carrier gas may be an inert gas, such as Ar, he, xe, ne, kr, rn, or the like, or a combination thereof. Alternatively, hydrogen (H ₂ ) May also be included in the gas source. A plasma is generated from a gas source. The plasma may be generated by a plasma generator, such as an inductively coupled plasma system, a capacitively coupled plasma system, a microwave plasma generator, or the like. The plasma generator generates radio frequency power that generates plasma from the gas source by energizing the gas source into a plasma state. In some embodiments, the plasma generation power is pulsed between low power (e.g., substantially zero watts) and high power. The nitrogen radical treatment process may be performed using a plasma generation power having a high power in the range of 50 watts to 2000 watts. When a plasma is generated, nitrogen radicals and corresponding ions are generated and the portion of the first ILD 94 surrounding the contact opening 140 reacts with and/or is bombarded with nitrogen cations. Reacting the modified ILD region 94M with nitrogen radicals and/or bombarding the modified ILD region 94M with nitrogen cations breaks bonds with impurities (e.g., hydrogen) in the modified ILD region 94M to create open bonds of silicon atoms and produce impurity byproducts that may be exhausted from the chamber. Nitrogen is easily bonded to the open bond of the silicon atom, thereby The modified ILD region 94M is nitrided. The modified ILD region 94M is reacted with nitrogen radicals and/or bombarded with nitrogen cations until the modified ILD region 94M has been nitrided by a desired amount. In some embodiments, the modified ILD region 94M is reacted with and/or bombarded with nitrogen radicals for a time period of 1 second to 200 seconds at a temperature in the range of-40 ℃ to 140 ℃ and at a pressure in the range of 3mTorr to 500 mTorr. If the plasma generation power, temperature, duration, or pressure of the nitrogen radical treatment process is greater than the previously described values, the final nitrogen concentration may be too great. If the plasma generation power, temperature, duration, or pressure of the nitrogen radical treatment process is less than the previously described values, the final nitrogen concentration may be too small.

In some embodiments, the nitridation process is a nitrogen soak process in which the modified ILD region 94M is immersed in a nitrogen-containing gas without generating a plasma. The nitrogen soak process may be performed in a chamber. A gas source is distributed in the chamber. The gas source includes a nitrogen-containing gas and a carrier gas. The nitrogen-containing gas may include ammonia (NH) ₃ ) Nitrogen (N) ₂ ) Etc. The carrier gas may be an inert gas, such as Ar, he, xe, ne, kr, rn, or the like, or a combination thereof. Nitrogen in the nitrogen-containing gas breaks bonds with impurities (e.g., hydrogen) in the modified ILD region 94M to create open bonds for silicon atoms and produce impurity byproducts that may be exhausted from the chamber. Nitrogen readily bonds with the open bonds of silicon atoms, thereby nitriding the modified ILD region 94M. The modified ILD region 94M is immersed in a nitrogen-containing gas until the modified ILD region 94M has been nitrided by a desired amount. In some embodiments, the modified ILD region 94M is immersed in the nitrogen-containing gas at a temperature in the range of 20 ℃ to 140 ℃ and at a pressure in the range of 3mTorr to 200mTorr for a time period of 1 second to 200 seconds. If the temperature, duration, or pressure of the nitrogen soak process is greater than the previously described values, the final nitrogen concentration may be too great. If the temperature, duration, or pressure of the nitrogen soak process is less than the previously described values, the final nitrogen concentration may be too small.

In some embodiments, the treatment process 142 includes an ultraviolet curing process in which the modified ILD region 94M is exposed to ultraviolet light. Ultraviolet rayThe curing process may be performed in a chamber. A gas source is distributed in the chamber. The gas source may include Ar, he, H ₂ Etc., or a combination thereof. A plasma is generated from a gas source. The plasma may be generated by a plasma generator, such as an inductively coupled plasma system, a capacitively coupled plasma system, a microwave plasma generator, or the like. The plasma generator generates radio frequency power that generates plasma from the gas source by energizing the gas source into a plasma state. The plasma emits ultraviolet light. In some embodiments, the ultraviolet light has a wavelength in the range of 150nm to 386 nm. The ultraviolet light breaks bonds (e.g., si-H bonds) between the impurities and silicon atoms of the modified ILD region 94M, allowing the impurities to outgas, thereby removing the impurities from the modified ILD region 94M. The wavelength of the ultraviolet light is selected based on the impurities to be removed from the modified ILD region 94M. Specifically, the wavelength of the ultraviolet light is small enough to generate energy greater than the impurity dissociation energy. For example, when the impurity includes hydrogen bonded to silicon, the wavelength of ultraviolet light is less than or equal to 376nm, which generates energy greater than the dissociation energy of si—h bond (3.3 eV). Similarly, when the impurity includes hydrogen bonded to oxygen, the wavelength of ultraviolet light is less than or equal to 259nm, which generates energy greater than the dissociation energy of o—h bonds (4.8 eV). In some embodiments, the ultraviolet curing process is performed for a duration in the range of 5 seconds to 200 seconds. If the duration of the ultraviolet curing process is longer than this duration, the manufacturing cost may be excessive. If the duration of the ultraviolet curing process is less than this duration, excessive etching of the modified ILD region 94M may occur in the cleaning process 144.

The treatment process 142 may include a combination of the process (es) previously described. In some embodiments, the treatment process 142 includes a nitrogen radical treatment process and an ultraviolet curing process. For example, a nitrogen radical treatment process may be performed such that when a plasma is generated, nitrogen radicals, nitrogen cations, and ultraviolet light of a desired wavelength are generated.

In some embodiments, the processing 142 is performed in-situ with the etching of the contact opening 140. For example, the chamber used for the treatment process 142 may be the same as the etching chamber used in etching the contact opening 140. In some embodiments, the treatment process 142 is performed ex situ with respect to the etching of the contact opening 140. For example, the chamber used for the treatment process 142 may be different from the etching chamber used in etching the contact opening 140.

The cleaning process 144 cleans residues of the first ILD 94 from the contact openings 140. The cleaning process 144 may include an acceptable etching process. In some embodiments, the cleaning process 144 includes wet or dry etching using a fluorine-based etchant. For example, the etching may be a dry etching, such as Reactive Ion Etching (RIE), using one or more reactive gases (e.g., fluoromethane (CH) ₃ F) Etc.). As a result of performing the treatment process 142, the modified ILD region 94M has a reduced impurity concentration, to which the cleaning process 144 (e.g., etching process) is selective. Accordingly, the modified ILD region 94M has a reduced etch rate for the etchant(s) used in the cleaning process 144. Damage to the first ILD 94 during the cleaning process 144 may be reduced.

In fig. 18A-18C, the contact opening 140 extends through the CESL 92. CESL 92 is therefore opened such that contact openings 140 expose epitaxial source/drain regions 88. Acceptable etching techniques may be used to extend the contact openings 140 through the CESL 92. The etching may include any acceptable etching process, such as wet or dry etching using an etchant that is selective to the material of CESL 92 (e.g., etching the material of CESL 92 selectively at a faster rate than the material of first ILD 94). The etch process used to open CESL 92 is different from the etch process used to open first ILD 94 and cleaning process 144 (e.g., performed using different etch parameters, different etchants, and/or different types of etches).

In fig. 19A-19D, source/drain contacts 148 are formed in contact openings 140. A liner (not separately shown) such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the contact opening 140. The liner may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper alloy, silver, gold, aluminum, nickel, or the like. A removal process may be performed to remove excess material from the top surfaces of the gate mask 116, the first ILD 94, and the gate spacers 82. The removal process may also remove any remaining portions of the pad layer 122, the dicing mask 132, and/or the contact mask 136. The remaining liner and conductive material form source/drain contacts 148 in contact openings 140. In some embodiments, a planarization process, such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like, may be utilized. After the planarization process, the top surfaces of the source/drain contacts 148, the gate mask 116, the first ILD 94, and the gate spacers 82 are substantially coplanar (within process variations). Source/drain contacts 148 may be physically and electrically coupled to epitaxial source/drain regions 88.

Optionally, metal-semiconductor alloy regions 146 are formed at the interface between epitaxial source/drain regions 88 and source/drain contacts 148. The metal-semiconductor alloy region 146 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon germanide region formed of both a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 146 may be formed prior to the source/drain contact 148 by depositing metal in the contact opening 140 and then performing a thermal annealing process. The metal may be any metal capable of reacting with the semiconductor material (e.g., silicon-germanium, etc.) of the epitaxial source/drain regions 88 to form a low resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, PVD. After the thermal annealing process, a cleaning process (e.g., wet cleaning) may be performed to remove any residual metal from the contact openings 140 (e.g., from the surface of the metal-semiconductor alloy regions 146). Source/drain contacts 148 may then be formed on metal-semiconductor alloy regions 146.

Modified ILD region 94M is located between unmodified ILD region 94U and source/drain contact 148. In some embodiments, the modified ILD region 94M has a thickness in the range of 1nm to 5 nm. Performing the treatment process 142 prior to the cleaning process 144 (described with respect to fig. 17A-17C) reduces the amount of etching of the modified ILD region 94M during the cleaning process 144. In particular, damage caused by the etchant used for the cleaning process 144 may be reduced. Avoiding damage to the first ILD 94 may improve its film quality, which may reduce leakage between adjacent source/drain contacts 148. The performance and yield of the resulting device can be improved.

In fig. 20A-20C, a second ILD 154 is deposited over source/drain contacts 148, gate mask 116, first ILD 94 and gate spacers 82. In some embodiments, the second ILD 154 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 154 is formed of a dielectric material such as PSG, BSG, BPSG, USG, which may be deposited by any suitable method such as CVD, PECVD, or the like.

In some embodiments, an Etch Stop Layer (ESL) 152 is formed between the second ILD 154 and the source/drain contacts 148, the gate mask 116, the first ILD 94, and the gate spacers 82. The ESL 152 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having a high etch selectivity to the etch of the second ILD 154.

In fig. 21A-21C, a via opening 156 is formed through the second ILD 154. The via openings 156 may be formed using acceptable photolithography and etching techniques. The etching may include any acceptable etching process, such as a process that is selective to the material of the second ILD 154 (e.g., etching the material of the second ILD 154 selectively at a faster rate than the material of the ESL 152). The etching process may be anisotropic. The ESL 152 stops etching the via opening 156. Thus, the via openings 156 expose the ESL 152, and the ESL 152 still covers the source/drain contacts 148 and the gate mask 116.

After forming the via opening 156 through the second ILD 154, a processing process 158 is optionally performed in the via opening 156. After the treatment process 158, a cleaning process 160 is performed in the via opening 156. The cleaning process 160 may be performed before the via openings 156 extend through the ESL 152 (described later).

The processing 158 modifies the etch rate of the processed region of the second ILD 154. Specifically, the processing 158 modifies a region 154M of the second ILD 154 surrounding the via opening 156, wherein an unmodified region 154U of the second ILD 154 is unaffected by the processing 158 (or at least less affected than the modified ILD region 154M). The modified ILD region 154M has a reduced etch rate for the etch to be used in the cleaning process 160. The treatment process 158 may include any of the alternative methods of the treatment process 142 (previously described with respect to fig. 17A-17C). For example, the treatment process 158 may include a nitrogen radical treatment process (wherein the modified ILD region 154M is reacted with nitrogen radicals and/or bombarded with nitrogen cations), a nitrogen soak process (wherein the modified ILD region 154M is soaked in a nitrogen-containing gas without generating a plasma), and/or an ultraviolet curing process (wherein the modified ILD region 154M is exposed to ultraviolet light). The treatment process 158 may be the same as the treatment process 142 or may be different from the treatment process 142. The treatment process 158 may be performed in situ or ex situ with the etching of the via opening 156. The treatment process 158 reduces the amount of etching of the modified ILD region 154M during the cleaning process 160, similar to how the treatment process 142 reduces the etching of the modified ILD region 94M during the cleaning process 144 (described with respect to fig. 17A-17C).

The cleaning process 160 cleans the residues of the second ILD 154 from the via opening 156. The cleaning process 160 may include any of the alternative methods of the cleaning process 144 (previously described with respect to fig. 17A-17C). As a result of performing the treatment process 158, the modified ILD region 154M has a reduced concentration of impurities (to which the cleaning process 160 is selective).

In fig. 22A-22C, via openings 156 extend through ESL 152. Some of the via openings 156 also extend through the gate mask 116, where appropriate. The ESL 152 is thus opened such that each via opening 156 exposes a gate electrode 114 or source/drain contact 148. The via openings 156 may be extended through the ESL 152 using acceptable etching techniques. Etching may include any acceptable etching process, such as wet or dry etching using an etchant that is selective to the material of ESL 152 (e.g., etching the material of ESL 152 selectively at a faster rate than the material of second ILD 154).

In fig. 23A-23D, gate vias 162 and source/drain vias 164 are formed in via openings 156. A liner (not separately shown) such as a diffusion barrier layer, an adhesive layer, etc., and a conductive material are formed in the via opening 156. The liner may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper alloy, silver, gold, aluminum, nickel, or the like. A removal process may be performed to remove excess material from the top surface of the second ILD 154. The remaining liner and conductive material form gate vias 162 and source/drain vias 164 in the via openings 156. In some embodiments, a planarization process, such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like, may be utilized. After the planarization process, the top surfaces of the source/drain via 164, the gate via 162, and the second ILD 154 are substantially coplanar (within process variations). The gate via 162 and the source/drain via 164 may be physically and electrically coupled to the gate electrode 114 and the source/drain contact 148, respectively.

The gate via 162 and the source/drain via 164 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section in fig. 23A, it should be appreciated that each of the gate via 162 and the source/drain via 164 may be formed in different cross-sections, which may avoid contact shorting.

The modified ILD region 154M is located between the unmodified ILD region 154U and the gate via 162 or the source/drain via 164 (whichever applies). In some embodiments, the modified ILD region 154M has a thickness in the range of 1nm to 5 nm. In top view, modified ILD region 154M extends around gate via 162 or source/drain via 164. Performing the treatment process 158 (described with respect to fig. 21A-21C) prior to the cleaning process 160 reduces the amount of etching of the modified ILD region 154M during the cleaning process 160. In particular, damage caused by the etchant of the cleaning process 160 may be reduced. Avoiding damage to the second ILD 154 may improve its film quality, which may reduce leakage between adjacent gate vias 162 and/or adjacent source/drain vias 164. The performance and yield of the resulting device can be improved.

It should be appreciated that any combination of treatment process 142 (see fig. 17A-17C) and treatment process 158 (see fig. 21A-21C) may be utilized. In some embodiments, both treatment process 142 and treatment process 158 are performed. In other embodiments, the process 142 is performed and the process 158 is omitted. In still other embodiments, the treatment process 158 is performed while the treatment process 142 is omitted.

Embodiments may realize advantages. Performing the treatment process 158 and/or the treatment process 142 may help improve the quality of the second ILD 154 and/or the first ILD 94. Electrical isolation between adjacent source/drain vias 164, adjacent gate vias 162, and/or adjacent source/drain contacts 148 may be improved, thereby reducing leakage. The performance and yield of the resulting device can be improved.

The disclosed FinFET embodiments may also be applied to nanostructure devices, such as nanostructured (e.g., nanoplatelets, nanowires, gate-wrap-around structures, etc.) field effect transistors (NSFETs). In an NSFET embodiment, the fins are replaced with nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. The dummy gate stack and source/drain regions are formed in a manner similar to the embodiments described above. After the dummy gate stack is removed, the sacrificial layer in the channel region may be partially or completely removed. The replacement gate structure is formed in a manner similar to the embodiments described above, the replacement gate structure may partially or completely fill the opening left by the removal of the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. ILD and contacts to replacement gate structures and source/drain regions may be formed in a manner similar to the embodiments described above. The nanostructure device may be formed as disclosed in U.S. patent No.9,647,071, the entire contents of which are incorporated herein by reference.

Furthermore, finFET/NSFET devices may be interconnected by metallization layers in overlying interconnect structures to form integrated circuits. Additional features such as passive devices, memory (e.g., magnetoresistive Random Access Memory (MRAM), resistive Random Access Memory (RRAM), phase Change Random Access Memory (PCRAM), etc., may be integrated with the interconnect structure during back-end-of-line (BEOL) processing.

Fig. 24A-24D are views of finfets according to some embodiments. An interconnect structure is formed over the structure of fig. 23A-23D to interconnect the finfets to form an integrated circuit. The interconnect structure may be formed in a back end of line (BEOL) process in which a metallization layer is connected to the gate via 162 and the source/drain via 164.

An inter-metal dielectric (IMD) 204 is deposited over the second ILD 154, gate via 162, and source/drain via 164. In some embodiments, IMD 204 is a flowable film formed by a flowable CVD method. In some embodiments, IMD 204 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, which may be deposited by any suitable method, such as CVD, PECVD, or the like. IMD 204 may be formed of a low-k dielectric material having a k value less than about 3.0. IMD 204 may be formed of an ultra low k (ELK) dielectric material having a k value less than about 2.5.

In some embodiments, an Etch Stop Layer (ESL) 202 is formed between IMD 204 and second ILD 154, gate via 162, and source/drain via 164. The ESL 202 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a high etch selectivity relative to the etch of the IMD 204.

The interconnect 210 is formed to extend through the second ILD 154 and the ESL 202. Interconnect 210 may include metal lines and vias, which may be formed of conductive materials such as copper, aluminum, and the like. The interconnect 210 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

When forming an opening for interconnect 210, processing 206 may be performed after forming the opening in IMD 204. After the processing process 206, a cleaning process 208 is performed in the opening in the IMD 204. The cleaning process 208 may be performed prior to extending the opening through the ESL 202.

The processing process 206 modifies the etch rate of the processed region of the IMD 204. In particular, the processing process 206 modifies the region 204M of the IMD 204 around the interconnect opening, wherein the unmodified region 204U of the IMD 204 is not affected (or at least less affected) by the processing process 206 than the modified IMD region 204M. The modified IMD region 204M has a reduced etch rate for the etch to be used in the cleaning process 208. The treatment process 206 may include any of the alternative methods of the treatment process 142 (previously described with respect to fig. 17A-17C). For example, the treatment process 206 may include a nitrogen radical treatment process (wherein the modified IMD region 204M reacts with nitrogen radicals and/or is bombarded with nitrogen cations), a nitrogen soak process (wherein the modified IMD region 204M is soaked in a nitrogen-containing gas without generating a plasma), and/or an ultraviolet curing process (wherein the modified IMD region 204M is exposed to ultraviolet light). The treatment process 206 may be the same as the treatment process 142 or may be different from the treatment process 142. The treatment process 206 may be performed in situ or ex situ with the etching of the interconnect openings. The treatment process 206 reduces the amount of etching of the modified IMD region 204M during the cleaning process 208, similar to how the treatment process 142 reduces etching of the modified ILD region 94M during the cleaning process 144 (described with respect to fig. 17A-17C).

The cleaning process 208 cleans residues of the IMD 204 from the opening of the interconnect 210. The cleaning process 208 may include any of the alternative methods of the cleaning process 144 (previously described with respect to fig. 17A-17C). As a result of performing the treatment process 206, the modified IMD region 204M has a reduced concentration of impurities (to which the cleaning process 208 is selective).

Modified IMD region 204M is located between unmodified IMD region 204U and interconnect 210. In some embodiments, modified IMD region 204M has a thickness in the range of 1nm to 5 nm. In top view, modified IMD region 204M extends around interconnect 210. Performing the treatment process 206 prior to the cleaning process 208 reduces the amount of etching of the modified IMD region 204M during the cleaning process 208. In particular, damage caused by the etchant of the cleaning process 208 may be reduced. Avoiding damage to IMD 204 may reduce leakage between adjacent interconnects 210. The performance and yield of the resulting device can be improved.

It will be appreciated that, more generally, the previously described processing process (es) may be applied to any dielectric layer over the first conductive feature. The dielectric layer may be any of the previously described ILDs, IMDs, etc. The first conductive feature may be any of the previously described gate electrodes, source/drain contacts, etc. The second conductive feature may be formed through the dielectric layer to contact the first conductive feature. The second conductive feature may be any of the previously described metal vias, metal lines, etc. As a result of the treatment process (es), portions of the dielectric layer proximate to the second conductive feature may have a lower impurity concentration than portions of the dielectric layer distal from the second conductive feature. In some embodiments, the portion of the dielectric layer proximate the second conductive feature comprises silicon oxide free of hydrogen impurities, and the portion of the dielectric layer distal from the second conductive feature comprises silicon oxide with hydrogen impurities.

In one embodiment, a device includes: comprising the following steps: source/drain regions over the semiconductor substrate; a dielectric layer over the source/drain regions, the dielectric layer comprising a first dielectric material; an interlayer dielectric over the dielectric layer, the interlayer dielectric comprising a second dielectric material and an impurity, the second dielectric material being different from the first dielectric material, a first portion of the interlayer dielectric having a first concentration of the impurity, a second portion of the interlayer dielectric having a second concentration of the impurity, the first concentration being less than the second concentration; and source/drain contacts extending through the interlayer dielectric and the dielectric layer to contact the source/drain regions, a first portion of the interlayer dielectric being disposed between the source/drain contacts and the second portion of the interlayer dielectric. In some embodiments of the device, the first dielectric material is silicon nitride, the second dielectric material is silicon oxide, and the impurity is hydrogen. In some embodiments of the device, the first portion of the interlayer dielectric has a first density, the second portion of the interlayer dielectric has a second density, and the first density is greater than the second density. In some embodiments of the device, the interlayer dielectric further comprises nitrogen, the first portion of the interlayer dielectric having a third concentration of nitrogen, the second portion of the interlayer dielectric having a fourth concentration of nitrogen, the third concentration being greater than the fourth concentration. In some embodiments of the device, the first concentration is less than 5%. In some embodiments of the device, the first concentration is zero.

In one embodiment, a device includes: comprising the following steps: a first conductive feature over the semiconductor substrate; a dielectric layer over the first conductive feature; and a second conductive feature extending through the dielectric layer to contact the first conductive feature, a first portion of the dielectric layer surrounding the second conductive feature in a top view, a second portion of the dielectric layer being separated from the second conductive feature by the first portion of the dielectric layer in a top view, the second portion of the dielectric layer comprising silicon oxide having hydrogen impurities, the first portion of the dielectric layer comprising silicon oxide having no hydrogen impurities. In some embodiments of the device, the first conductive feature is a gate electrode. In some embodiments of the device, the first conductive feature is a source/drain contact. In some embodiments of the device, the second conductive feature is a metal via. In some embodiments of the device, the second conductive feature is a metal line. In some embodiments of the device, the dielectric layer is an interlayer dielectric or an intermetallic dielectric. In some embodiments of the device, the first portion of the dielectric layer has a greater density than the second portion of the dielectric layer.

In one embodiment, a method includes: comprising the following steps: depositing a dielectric material on the etch stop layer; patterning a contact opening in a dielectric material to expose the etch stop layer; reducing a first etch rate of a first portion of the dielectric material to be less than a second etch rate of a second portion of the dielectric material, the first portion of the dielectric material being disposed between the contact opening and the second portion of the dielectric material; extending the contact opening through the etch stop layer by performing an etching process, the first etch rate and the second etch rate being related to the etching process; and forming a contact in the contact opening. In some embodiments of the method, the dielectric material includes an impurity, and reducing the first etch rate of the first portion of the dielectric material includes: the first concentration of impurities in the first portion of the dielectric material is reduced to be less than the second concentration of impurities in the second portion of the dielectric material. In some embodiments of the method, the impurity is hydrogen and the etching process is performed with a fluorine-based etchant. In some embodiments of the method, reducing the first concentration of impurities in the first portion of the dielectric material comprises: a first portion of the dielectric material is nitrided. In some embodiments of the method, nitriding the first portion of the dielectric material comprises: a first portion of the dielectric material is immersed in a nitrogen-containing gas. In some embodiments of the method, nitriding the first portion of the dielectric material comprises: a first portion of the dielectric material is bombarded with nitrogen radicals. In some embodiments of the method, reducing the first concentration of impurities in the first portion of the dielectric material comprises: a first portion of the dielectric material is exposed to ultraviolet light.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A device, comprising:

source/drain regions over the semiconductor substrate;

a dielectric layer over the source/drain regions, the dielectric layer comprising a first dielectric material;

an interlayer dielectric over the dielectric layer, the interlayer dielectric comprising a second dielectric material and an impurity, the second dielectric material being different from the first dielectric material, a first portion of the interlayer dielectric having a first concentration of the impurity, a second portion of the interlayer dielectric having a second concentration of the impurity, the first concentration being less than the second concentration; and

A source/drain contact extends through the interlayer dielectric and the dielectric layer to contact the source/drain region, the first portion of the interlayer dielectric being disposed between the source/drain contact and the second portion of the interlayer dielectric.

2. The device of claim 1, wherein the first dielectric material is silicon nitride, the second dielectric material is silicon oxide, and the impurity is hydrogen.

3. The device of claim 1, wherein the first portion of the interlayer dielectric has a first density, the second portion of the interlayer dielectric has a second density, and the first density is greater than the second density.

4. The device of claim 1, wherein the interlayer dielectric further comprises nitrogen, the first portion of the interlayer dielectric having a third concentration of nitrogen, the second portion of the interlayer dielectric having a fourth concentration of nitrogen, the third concentration being greater than the fourth concentration.

5. The device of claim 1, wherein the first concentration is less than 5%.

6. The device of claim 1, wherein the first concentration is zero.

7. A device, comprising:

a first conductive feature over the semiconductor substrate;

a dielectric layer over the first conductive feature; and

a second conductive feature extending through the dielectric layer to contact the first conductive feature, a first portion of the dielectric layer surrounding the second conductive feature in a top view, a second portion of the dielectric layer separated from the second conductive feature by the first portion of the dielectric layer in a top view, the second portion of the dielectric layer comprising silicon oxide having hydrogen impurities, the first portion of the dielectric layer comprising silicon oxide having no hydrogen impurities.

8. The device of claim 7, wherein the first conductive feature is a gate electrode.

9. The device of claim 7, wherein the first conductive feature is a source/drain contact.

10. A method, comprising:

depositing a dielectric material on the etch stop layer;

patterning a contact opening in the dielectric material to expose the etch stop layer;

reducing a first etch rate of a first portion of the dielectric material to be less than a second etch rate of a second portion of the dielectric material, the first portion of the dielectric material being disposed between the contact opening and the second portion of the dielectric material;

Extending the contact opening through an etch stop layer by performing an etching process, the first etch rate and the second etch rate being related to the etching process;

contacts are formed in the contact openings.