TW202339282A - Semiconductor device and method for forming the same - Google Patents

Abstract

A semiconductor device including an etch stop layer and a method of forming is provided. The semiconductor device may include a source/drain region and a gate structure, wherein a first etch stop layer is over a conductive plug to a source/drain region and a second etch stop layer is over the gate structure. The first etch stop layer and the second etch stop layer may have different thicknesses. A dielectric layer may be formed over the first etch stop layer and the second etch stop layer, and contacts may be formed through the dielectric layer and the first and second etch stop layers.

Description

Semiconductor components and methods

without

Semiconductor components are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and components thereon.

The semiconductor industry continues to increase the volume density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing minimum feature sizes, which allows for the integration of more components into a given area.

without

The following disclosure provides many different implementations, or examples, for implementing various features of the present disclosure. Specific embodiments of components and arrangements are described below to simplify this disclosure. These are of course only examples and not intended to be limiting. For example, in the following description, the formation of the first feature above or on the second feature may include an embodiment in which the first feature and the second feature are in direct contact, or may include another embodiment. Features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, this disclosure may repeat reference numbers and/or text in different instances. Repetition is for the purpose of simplifying and clarifying the narrative and is not intended to define the relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "below", "below", "below", "above", "above" and other similar terms are used to facilitate the description of one element or feature in the figure and another. A relationship between a component or feature. Spatially relative terms cover not only the orientation depicted in the figures, but also other orientations of the device when in use or operation. That is, may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein interpreted accordingly.

Embodiments will be described with respect to a specific context, namely, a contact plug structure of a semiconductor element and a method of forming the same. Various embodiments discussed herein are in the context of Fin Field-Effect Transistor (FinFET) devices formed using a gate-last process. In other embodiments, a gate-first process may be used. However, various embodiments may be applied to elements including other types of transistors, such as planar FETs, nanostructured (eg, nanosheets, nanowires, gate-all-around (GAA), etc.) fields Effective transistors (NFETs/NSFETs), etc. instead of or in combination with FinFETs. In some embodiments, an etch stop layer is formed within the recess of the contact plug of the semiconductor component and is used during subsequent processing steps, such as forming conductive features on the contact plug. By forming an etch stop layer within the recesses, the overall thickness of the device can be reduced, which results in better contours of conductive features over the gate stack, source/drain regions, etc., thus improving electrical connections in the device.

Figure 1 illustrates an example of a Fin Field-Effect Transistor (FinFET) in a three-dimensional view according to some embodiments. FinFETs include fins 52 on a substrate 50 (eg, a semiconductor substrate). A plurality of isolation areas 56 are disposed in the substrate 50 , and the fins 52 are above and protrude from between adjacent isolation areas 56 . Although isolation region 56 is described/illustrated as separate from substrate 50, as used herein, the term "substrate" may be used to refer to a semiconductor substrate only or a semiconductor substrate including an isolation region. Additionally, although fin 52 is illustrated as a single continuous material as substrate 50 , fin 52 and/or substrate 50 may also comprise a single material or multiple materials. As used herein, fin 52 refers to the portion extending between adjacent isolation areas 56 .

Gate dielectric layer 92 is along the sidewalls of fin 52 and over the top surface of fin 52 , and gate 94 is over gate dielectric layer 92 . Source/drain regions 82 are disposed on opposite sides of fin 52 relative to gate dielectric layer 92 and gate 94 . Figure 1 also shows reference cross-sections (lines) used in the following figures. Cross-section A-A is along the longitudinal axis of the gate 94 and in a direction perpendicular to the direction of current flow between the epitaxial source/drain regions 82 of the FinFET, for example. Cross-section B-B is perpendicular to cross-section A-A and along the longitudinal axis of fin 52 and in the direction of current flow between, for example, the epitaxial source/drain regions 82 of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through the source/drain regions of the FinFET. For clarity, the subsequent drawings refer to these reference cross-sections.

Figures 2 to 27B are schematic cross-sectional views at an intermediate stage of manufacturing a FinFET device according to some embodiments. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 12A, Figure 13A, Figure 14A Figures, Figures 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A and Figure 27A is shown along reference cross-section A-A in Figure 1, with the cross-sectional schematic showing a plurality of fins/FinFETs for illustration purposes. Figure 8B, Figure 9B, Figure 10B, Figure 11B, Figure 12B, Figure 13B, Figure 14B, Figure 14C, Figure 15B, Figure 16B, Figure 17B, Figure 18B, Figure 19B Figures, Figure 20B, Figure 21B, Figure 22B, Figure 23B, Figure 24B, Figure 25B, Figure 26B and Figure 27B are along the reference cross section B-B in Figure 1, in which the schematic diagram of the section is shown Multiple fins/FinFETs are shown for illustration purposes. Figures 10C and 10D are along the reference cross-section C-C in Figure 1 , with the cross-sectional schematic showing multiple fins/FinFETs for illustration purposes.

In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (eg, with p-type or n-type dopants) or unadulterated. Substrate 50 may be a wafer, such as a silicon wafer. Generally speaking, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, usually a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors including Silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and/or phosphorus Indium gallium arsenide (GaInAsP), etc. or a combination thereof.

The substrate 50 has an n-type region 50N and a p-type region 50P. n-type region 50N may be used to form n-type components, such as NMOS transistors, for example, n-type FinFETs. The p-type region 50P may be used to form p-type components, such as PMOS transistors, for example, p-type FinFETs. n-type region 50N may be physically separated from p-type region 50P (as shown by separator 51), and any number of device features (eg, other active devices, doped regions, insulating regions, etc.) may be disposed between n-type region 50N and p-type area between 50P.

In Figure 3, fins 52 are formed in substrate 50 according to some embodiments. Fin 52 is a semiconductor strip. In some embodiments, fins 52 may be formed in substrate 50 by etching trenches in substrate 50 . The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic etching.

Fins 52 may be patterned by any suitable method. For example, the fins 52 may be patterned using one or more lithography processes, including a double-patterning or multi-patterning process. Generally speaking, a dual-patterning process or a multi-patterning process combines a lithography process with a self-aligned process, which allows the creation of pitches with, for example, smaller pitches than can be achieved using a single direct lithography process. pattern. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A self-aligned process is used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed and the remaining spacers can then be used as masks to form fins 52 . In some implementations, a mask (or other layer) may remain on fins 52 .

In Figure 4, insulating material 54 is formed over substrate 50 and between adjacent fins 52, according to some embodiments. The insulating material 54 may be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (flowable CVD), etc. CVD; FCVD) (e.g., depositing a CVD-based material in a remotely controlled plasma system and performing post curing to convert it into another material, such as an oxide), etc., or a combination thereof. Other insulating materials can be formed using any acceptable process. In the embodiment shown, insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, insulating material 54 is formed such that excess insulating material 54 covers fins 52 . Although insulating material 54 is shown as a single layer, in some implementations multiple layers may be used. For example, in some embodiments, pads (not shown) may be formed first along the surfaces of substrate 50 and fins 52 . Thereafter, filler materials such as those described above may be formed over the pad.

In FIG. 5 , a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fins 52 . In some embodiments, a planarization process may be used, such as chemical mechanical polish (CMP), etch-back process, combinations thereof, etc. The planarization process exposes the fins 52 such that the top surfaces of the fins 52 and the top surfaces of the insulating material 54 after the planarization process is completed are substantially coplanar or level (e.g., within the process variation of the planarization process). ). In embodiments where the mask remains on the fin 52 , the planarization process may expose the mask or remove the mask such that the top surface of the mask or the top surface of the fin 52 , respectively, is in contact with the insulating material after the planarization process is completed. The top surface of the 54 is flush.

In Figure 6, insulating material 54 is recessed to form shallow trench isolation (STI) regions 56, according to some embodiments. The insulating material 54 is recessed so that the upper portions of the fins 52 in the n-type region 50N and the p-type region 50P protrude between adjacent STI regions 56 . Additionally, the top surface of STI region 56 may have a flat surface as shown, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surface of STI region 56 may be formed by appropriate etching to form a flat surface, a convex surface, and/or a concave surface. STI region 56 may be recessed using an acceptable etch process, such as an etch process that is selective to the material of insulating material 54 (eg, etches the material of insulating material 54 at a faster rate than the material of fin 52 ). For example, dilute hydrofluoric acid (dHF) may be used to perform the oxidative removal process, but other processes may also be used.

The process described in FIGS. 2-6 may be just one example of how the fins 52 are formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50 and trenches may be etched through the dielectric layer to expose the underlying substrate 50 . Homoepitaxial epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed so that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial epitaxial structures may be used to form fins 52 . For example, the fins 52 in Figure 5 can be recessed, and a material different from that of the fins 52 can be epitaxially grown on the recessed fins 52. In such embodiments, fin 52 includes recessed material and epitaxially grown material disposed over the recessed material. In further embodiments, a dielectric layer may be formed over the top surface of substrate 50 and trenches may be etched through the dielectric layer. A material different from the substrate 50 can then be used to epitaxially grow the heteroepitaxial structure in the trench, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 52 . In the embodiment of epitaxial growth of a homogeneous epitaxial structure or a heterogeneous epitaxial structure, although in-situ and implanted doping can be used together, in-situ doping of epitaxially grown materials during growth can avoid the need for previous and implanted doping. Subsequent planting.

Furthermore, it may be advantageous to epitaxially grow different materials in n-type region 50N (eg, NMOS region) than in p-type region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium ( _{SixGe1 -x} , where x may range from 0 to 1), silicon carbide, pure or substantially pure germanium, III-V Compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, and indium aluminum arsenide. , gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

Further in Figure 6, suitable wells (not shown) may be formed in the fins 52 and/or the substrate 50. In some embodiments, a P-well may be formed in n-type region 50N, and an N-well may be formed in p-type region 50P. In some embodiments, P-wells or N-wells are formed in both n-type region 50N and p-type region 50P. In different well type embodiments, photoresists and/or other masks (not shown) may be used to achieve different implantation steps for n-type region 50N and p-type region 50P. For example, photoresist may be formed over fins 52 and over STI region 56 in n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50 . The photoresist can be formed using spin-on techniques and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type region 50P, and the photoresist acts as a mask to substantially prevent n-type impurities from being implanted in n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc. in the implanted region at a concentration equal to or less than 10 ¹⁸ cm ^-3 , such as in the range from about 10 ¹⁶ cm ^-3 to about 10 ¹⁸ cm ^-3 . After implantation, the photoresist is removed, such as by an acceptable ashing process.

After p-type region 50P is implanted, photoresist is formed over fin 52 and STI region 56 in p-type region 50P. The photoresist is patterned to expose n-type region 50N of substrate 50 . The photoresist can be formed using spin coating techniques and can be patterned using acceptable lithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted in p-type region 50P. The p-type impurity may be boron, boron fluoride, indium, etc., with a implantation concentration in the region equal to or less than 10 ¹⁸ cm ^-3 , such as in the range from about 10 ¹⁶ cm ^-3 to about 10 ¹⁸ cm ^-3 . After implantation, the photoresist is removed, such as by an acceptable ashing process.

After implantation of n-type region 50N and p-type region 50P, an anneal may be performed to repair implant damage and activate implanted p-type and/or n-type impurities. In some embodiments, although in-situ doping and implant doping can be used together, the epitaxial fin growth material can be doped in-situ during the growth process, so that implants are not necessary.

In FIG. 7 , dummy dielectric layer 60 is formed on fin 52 . Dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to acceptable techniques. The dummy gate layer 62 is formed over the dummy dielectric layer 60 , and the mask layer 64 is formed over the dummy gate layer 62 . The dummy gate layer 62 may be deposited over the dummy dielectric layer 60 and then planarized using a CMP process, for example. Mask layer 64 may be deposited over dummy gate layer 62 . The dummy gate layer 62 may be a conductive material and may be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. Dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art for depositing conductive materials. Dummy gate layer 62 may be made of other materials that have high etch selectivity for the etch of STI region 56 . Mask layer 64 may include, for example, one or more layers of silicon oxide, SiN, SiON, combinations thereof, and the like. In some embodiments, mask layer 64 may include a layer of silicon nitride and a layer of silicon oxide above the layer of silicon nitride. In some embodiments, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50N and region 50P. Note that for illustration purposes only, dummy dielectric layer 60 is shown covering only fins 52 . In some implementations, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI region 56 and extends between dummy gate layer 62 and STI region 56 .

Figures 8A-28B illustrate various additional steps in making embodiment devices. Figures 8A to 28B illustrate characteristics of any one of the n-type region 50N and the p-type region 50P. For example, the structures shown in FIGS. 8A to 28B can be applied to the n-type region 50N and the p-type region 50P. Structural differences, if any, between n-type region 50N and p-type region 50P are described in the text and in each of the accompanying figures.

In Figures 8A and 8B, mask layer 64 (see Figure 7) is patterned using acceptable lithography and etching techniques to form mask 74. The pattern of mask 74 is then transferred to dummy gate layer 62 . In some embodiments (not shown), the pattern of mask 74 may also be transferred to dummy dielectric layer 60 using acceptable etching techniques to form dummy gate 72 . Dummy gates 72 cover each channel area 58 of fin 52 . The pattern of mask 74 may be used to physically separate each dummy gate 72 from adjacent dummy gates. The longitudinal direction of the dummy gate 72 may also be substantially perpendicular to the longitudinal direction of each epitaxial fin 52 .

Additionally, in FIGS. 8A and 8B , gate seal spacers 80 may be formed on exposed surfaces of dummy gate 72 , mask 74 and/or fin 52 . Gate sealing spacers 80 may be formed following thermal oxidation or deposition followed by anisotropic etching. Gate seal spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

After the gate seal spacers 80 are formed, implantation for lightly doped source/drain (LDD) regions (not explicitly shown) may be performed. In embodiments with different element types, similar to the implants discussed above in Figure 6, a mask such as photoresist can be formed over n-type region 50N while exposing p-type region 50P, and the appropriate Type (eg, p-type) impurities are implanted into exposed fins 52 in p-type region 50P. The mask can then be removed. Subsequently, a mask such as photoresist may be formed over p-type region 50P while exposing n-type region 50N, and an appropriate type (eg, n-type) impurity may be implanted into the exposed n-type region 50N Fin 52 in. The mask can then be removed. The n-type impurity can be any n-type impurity discussed previously, and the p-type impurity can be any p-type impurity discussed previously. In some implementations, the low-doped source/drain regions may have impurity concentrations ranging from about 10 ¹⁵ cm ⁻³ to about 10 ¹⁹ cm ⁻³ . Annealing may be used to repair implant damage and/or activate implanted impurities.

In FIGS. 9A and 9B , gate spacers 86 are formed on gate seal spacers 80 along the sidewalls of dummy gate 72 and mask 74 . Gate spacers 86 may be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacer 86 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc. In some embodiments, gate spacer 86 includes multiple layers, which may be layers of different materials.

It should be noted that the above disclosure describes a general process for forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or additional additional spacers may be used, and a different sequence of steps may be used (e.g., gate seal spacers 80 may not be etched before gate spacers 86 are formed, resulting in an "L-shaped" gate seal spacer). can form and remove spacers and/or the like). Additionally, different structures and steps can be used to form n-type and p-type components. For example, the LDD region of the n-type device is formed before the gate sealing spacers 80 are formed, and the LDD region of the p-type device is formed after the gate sealing spacers 80 are formed.

In Figures 10A and 10B, epitaxial source/drain regions 82 are formed in fins 52. Epitaxial source/drain regions 82 are formed in fin 52 such that each dummy gate 72 is deposited between a respective adjacent pair of epitaxial source/drain regions 82 . In some embodiments, epitaxial source/drain regions 82 may extend into fins 52 or may penetrate fins 52 . In some embodiments, gate spacers 86 are used to separate epitaxial source/drain regions 82 from dummy gate 72 by a suitable lateral distance such that epitaxial source/drain regions 82 do not cause subsequent The gate of the FinFET is short-circuited. The materials of the epitaxial source/drain regions 82 may be selected to impart stress in the respective channel regions 58 to improve performance.

Epitaxial source/drain regions 82 in n-type region 50N may be formed by masking p-type region 50P and etching the source/drain regions of fin 52 in n-type region 50N to form trenches in fin 52 . Then, epitaxial source/drain regions 82 in n-type region 50N are epitaxially grown in the trench. Epitaxial source/drain regions 82 may comprise any acceptable material, such as materials suitable for n-type FinFETs. For example, if fin 52 is silicon, epitaxial source/drain regions 82 in n-type region 50N may include a material that imposes tensile strain on channel region 58 such as silicon, silicon carbide, phosphorus-doped silicon carbide, phosphide Silicon etc. Epitaxial source/drain regions 82 in n-type region 50N may have surfaces that are raised from respective surfaces of fins 52 and have facets.

Epitaxial source/drain regions 82 in p-type region 50P may be formed by masking n-type region 50N and etching the source/drain regions of fin 52 in p-type region 50P to form trenches in fin 52 . Then, the epitaxial source/drain regions 82 in the p-type region 50P are epitaxially grown in the trench. Epitaxial source/drain regions 82 may comprise any acceptable material, such as materials suitable for p-type FinFETs. For example, if fin 52 is silicon, epitaxial source/drain regions 82 in p-type region 50P may include a material that imparts compressive strain in channel region 58 , such as silicon germanium, boron doped silicon germanium, germanium , germanium tin, etc. Epitaxial source/drain regions 82 in p-type region 50P may have surfaces that are raised from respective surfaces of fins 52 and have facets.

Epitaxial source/drain regions 82 and/or fins 52 may be implanted with dopants to form source/drain regions (similar to the process previously discussed for forming low-doped source/drain regions), Then anneal. The source/drain regions may have impurity concentrations ranging from about 10 ¹⁹ cm ⁻³ to about 10 ²¹ cm ⁻³ . The n-type and/or p-type impurities in the source/drain regions can be any of the impurities discussed previously. In some embodiments, epitaxial source/drain regions 82 may be doped in situ during growth.

Due to the epitaxial process used to form epitaxial source/drain regions 82 in n-type region 50N and p-type region 50P, the upper surface of the epitaxial source/drain region has sidewalls that extend laterally outward beyond fin 52 facets. In some embodiments, these facets cause adjacent source/drain regions 82 of the same FinFET to merge together, as shown in Figure 10C. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source/drain regions 82 remain separated, as shown in Figure 10D. In the embodiment of FIGS. 10C and 10D , gate spacers 86 are formed to cover a portion of the sidewall of fin 52 extending above STI region 56 to prevent epitaxial growth. In some other embodiments, the etching of the spacers used to form gate spacers 86 may be adjusted to remove the spacer material while allowing the epitaxial growth region to extend to the surface of STI region 56 .

In Figures 11A and 11B, a first interlayer dielectric (ILD) 88 is deposited over the structure shown in Figures 10A and 10B. The first ILD 88 may be composed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include oxide, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass ; BPSG), undoped silicate glass (undoped silicate glass; USG), etc. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source/drain region 82 , between the mask 74 and the gate spacer 86 . CESL 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., that has a lower etch rate than the overlying first ILD 88 material.

In Figures 12A and 12B, a planarization process such as CMP may be performed to make the top surface of ILD 88 flush with the top surface of dummy gate 72 or mask 74. The planarization process may also remove mask 74 over dummy gate 72 , as well as remove gate seal spacers 80 and gate spacers 86 along the sidewalls of mask 74 . After the planarization process, the top surfaces of dummy gate 72, gate seal spacer 80, gate spacer 86, and first ILD 88 are flush. Therefore, the top surface of dummy gate 72 is exposed through first ILD 88 . In some embodiments, mask 74 may remain, in which case the planarization process makes the top surface of first ILD 88 flush with the top surface of mask 74 .

In Figures 13A and 13B, dummy gate 72 and mask 74 (if present) are removed in one or more etching steps, thereby forming recess 90. A portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only dummy gate 72 is removed, leaving dummy dielectric layer 60 exposed from groove 90 . In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first area of the wafer (eg, the core logic area), and the recess 90 in a second area of the wafer (eg, the input/output area) remains. slot 90. In some embodiments, dummy gate 72 is removed through an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches dummy gate 72 with little or no etching of first ILD 88 or gate spacer 86 . Each groove 90 exposes and/or overlies the channel area 58 of a respective fin 52 . Each channel region 58 is deposited between adjacent pairs of epitaxial source/drain regions 82 . During removal, dummy dielectric layer 60 may serve as an etch stop layer when dummy gate 72 is etched. The dummy dielectric layer 60 may then optionally be removed after the dummy gate 72 is removed.

In Figures 14A and 14B, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate electrode. Figure 14C shows a detailed view of area 89 of Figure 14B. Gate dielectric layer 92 is deposited in one or more layers of recess 90, such as on the top surface and sidewalls of fin 52, and on the sidewalls of gate seal spacers 80/gate spacers 86. Gate dielectric layer 92 may also be formed on the top surface of first ILD 88 . In some embodiments, gate dielectric layer 92 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxides, metal silicate, or the like. For example, in some embodiments, gate dielectric layer 92 includes an interface layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material such as hafnium, aluminum, zirconium, lanthanum, manganese, Metal oxides or silicates of barium, titanium, lead and combinations thereof. Gate dielectric layer 92 may include a dielectric layer having a k value greater than 7.0. The formation method of the gate dielectric layer 92 may include molecular-beam deposition (MBD), atomic layer deposition (ALD), PECVD, and similar methods. In embodiments where a portion of the dummy dielectric layer 60 remains in the recess 90 , the gate dielectric layer 92 includes the material of the dummy dielectric layer 60 (eg, silicon oxide, etc.).

Gates 94 are respectively deposited over the gate dielectric layer 92 and fill the remaining portion of the recess 90 . Gate 94 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although a single layer of gate 94 is shown in FIG. 14B, gate 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B and filling materials 94C, as shown in FIG. 14C. As shown in the figure. After filling recess 90 , a planarization process such as CMP may be performed to remove gate dielectric layer 92 and excess portions of gate 94 material above the top surface of first ILD 88 . The remaining material portions of gate 94 and gate dielectric layer 92 thus form a replacement gate for the resulting FinFET, and gate 94 and gate dielectric layer 92 may collectively be referred to as a "replacement gate," "gate structure," or "Gate stacking". Gates and gate stacks may extend along the sidewalls of channel regions 58 of fins 52 .

Formation of gate dielectric layer 92 in n-type region 50N and p-type region 50P may occur simultaneously, such that gate dielectric layer 92 in each region is formed of the same material, and formation of gate 94 may occur simultaneously. , so that the gate 94 in each area is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed by a different process, such that the gate dielectric layer 92 in each region is formed of a different material, and/or in each region The gates 94 may be formed through different processes, so that the gates 94 in each region are formed of different materials. When using different processes, various masking steps can be used to mask and expose appropriate areas.

In Figures 15A and 15B, according to some embodiments, the gate stack (eg, gate dielectric layer 92 and gate 94) is recessed and dielectric layer 100 is formed over the gate stack. Dielectric layer 100 may be formed, for example, by recessing a gate stack and depositing the dielectric material of dielectric layer 100 on the recessed gate stack. In some embodiments, a recessed gate is stacked below the top surface of the first ILD 88. The gate stack may be recessed using one or more etching processes, which may include one or more wet etching processes, dry etching processes, or a combination thereof. One or more of the etching processes may include an anisotropic etching process.

A dielectric layer 100 is then formed over the recessed gate stack and over the first ILD 88 . In some embodiments, dielectric layer 100 may include silicon nitride, silicon carbide, silicon carbonitride, other types of nitrides, combinations thereof, and the like, and may be formed using ALD, CVD, PVD, combinations thereof, and the like. In some cases, using oxygen-free materials to form dielectric layer 100 may reduce oxidation on gate 94 . In some implementations, dielectric layer 100 may include silicon oxide, silicon oxynitride, metal oxides, other types of oxides, combinations thereof, and the like. The dielectric layer 100 may be formed in a self-aligned manner, and sidewalls of the dielectric layer 100 may be aligned with corresponding sidewalls of the gate seal spacer 80 or the gate spacer 86 . A planarization process, such as a CMP process, may be performed to remove excess material of dielectric layer 100 (eg, from above first ILD 88). In some implementations, the top surfaces of dielectric layer 100, gate spacers 86, and first ILD 88 may be flush. In some embodiments, dielectric layer 100 may be formed to have a thickness ranging from about 10 nm to about 20 nm.

Figures 16A-17B illustrate the formation of conductive features 122 (see Figure 17B) in accordance with some embodiments. Conductive features 122 provide electrical connections to corresponding epitaxial source/drain regions 82, and in some cases may be considered "source/drain contact plugs" or the like.

Figures 16A and 16B illustrate a patterning process for the first ILD 88 and CESL 87 to form openings 118 in accordance with some embodiments. Openings 118 may expose the surface of epitaxial source/drain region 82 . The patterning process can be performed using acceptable lithography and etching techniques. For example, a photoresist may be formed and patterned over first ILD 88 and dielectric layer 100 . The photoresist can be formed using, for example, spin coating techniques and patterned using acceptable lithography techniques. Openings 118 are formed by performing one or more suitable etching processes using the patterned photoresist as an etch mask. The one or more etching processes may include wet and/or dry etching processes. One or more etching processes may be anisotropic. Figures 16A-16B illustrate opening 118 with sloped sidewalls, but opening 118 may also have substantially vertical sidewalls, curved sidewalls, or other sidewall profiles than shown.

In Figures 17A and 17B, a silicone layer 120 and conductive features 122 are formed in openings 118, according to some embodiments. Silicide layer 120 may be formed, for example, by depositing a metallic material in opening 118 . The metal material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, combinations thereof, etc., and may be produced using ALD, CVD, PVD, sputtering, combinations thereof, etc. form. Subsequently, an annealing process is performed to form the silicide layer 120 . In embodiments in which the epitaxial source/drain regions 82 include silicon, the annealing process may react the metallic material with the silicon to form a siliconization of the metallic material at the interface between the metallic material and the epitaxial source/drain regions 82 things. After the silicide layer 120 is formed, a suitable removal process (eg, a suitable etching process) may be used to remove the unreacted portion of the metal material.

After the silicide layer 120 is formed, conductive features 122 are formed in the openings 118 . Conductive features 122 provide electrical connections to corresponding epitaxial source/drain regions 82 . In some embodiments, conductive features 122 are formed by forming a liner (not shown) such as a barrier layer, an adhesive layer, etc., and conductive fill material is located in opening 118 . For example, a barrier layer may be formed first in opening 118 . The barrier layer may extend along the bottom and sidewalls of opening 118 . The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, multilayers thereof, and the like, and may be formed by ALD, CVD, PVD, sputtering, combinations thereof, and the like. Subsequently, an adhesive layer (not shown separately) may be formed over the barrier layer within opening 118 . The bonding layer may include cobalt, ruthenium, alloys thereof, combinations thereof, multiple layers thereof, etc., and may be formed by ALD, CVD, PVD, sputtering, combinations thereof, etc. The barrier layer and/or adhesive layer may be omitted in other embodiments.

Conductive fill material is then formed in openings 118 to form conductive features 122 . The conductive fill material may include cobalt, tungsten, ruthenium, copper, combinations thereof, alloys thereof, multilayers thereof, etc., and may be formed by, for example, electroplating, ALD, CVD, PVD, or other suitable methods. For example, in some embodiments, the conductive fill material may be formed by first forming a seed layer (not shown separately) over an adhesive layer within opening 118 . The seed layer may include copper, titanium, nickel, gold, manganese, combinations thereof, multiple layers thereof, etc., and may be formed by ALD, CVD, PVD, sputtering, combinations thereof, etc. A conductive fill material may then be formed over the seed layer within opening 118 . Other techniques for forming conductive fill materials may also be used.

In some embodiments, the conductive fill material overfills opening 118 . After the conductive fill material is formed, a planarization process may be performed to remove portions of the conductive fill material that overfill opening 118 . If a barrier layer, an adhesive layer and/or a seed layer are present, part of the barrier layer, an adhesive layer and/or a seed layer may also be removed. The remaining portions of the barrier layer, adhesion layer, seed layer, and conductive fill material are formed in the conductive features 122 in the openings 118 . The planarization process may include a CMP process, an etch-back process, a grinding process, a combination thereof, etc. After performing the planarization process, the top surfaces of the conductive features 122 and the top surface of the dielectric layer 100 may be substantially flush. In other embodiments, no planarization process is performed. In some embodiments, an optional annealing process is performed after the planarization process to recrystallize the conductive features 122 , expand the grain structure of the conductive features 122 , reduce microvoids in the conductive features 122 , and/or reduce the amount of microvoids in the conductive features 122 . of impurities.

18A and 18B illustrate a process of patterning conductive features 122 to form grooves 123 in accordance with some embodiments. Patterning can be performed using acceptable lithography and etching techniques. For example, a photoresist may be formed and patterned over conductive features 122 and first ILD 88 . The photoresist can be formed using, for example, spin coating techniques, and can be patterned using acceptable lithography techniques. Grooves 123 may be formed by performing one or more suitable etching processes using patterned photoresist as an etch mask. The one or more etching processes may include wet and/or dry etching processes. The wet etchant used may be hydrogen peroxide, hydrochloric acid, phosphoric acid, nitric acid, ammonia or other suitable wet etchants. The dry etchant used may be chlorine, oxygen or other suitable dry etchants. The wet etching process can be performed at temperatures ranging from about room temperature to about 200 ºC. The dry etchant used may be chlorine, fluorine, hydrogen, acetylacetone, hexafluoroacetylacetone or other suitable dry etchants. The dry etching process can be performed at temperatures ranging from about room temperature to about 300 ºC. One or more of the etching processes may be anisotropic. In some embodiments, a selective dry etching process, such as Cl ₂ /O ₂ , can be used without using a mask layer. The depth of groove 123 may range from about 1 nm to about 10 nm, although other depths are possible. In some implementations, groove 123 may expose the sidewalls of first ILD 88 .

In Figures 19A and 19B, an etch stop layer 124 (the etch stop layer 124 may also be called a "dielectric helmet") is deposited on the structure shown in Figures 18A and 18B. In some implementations, etch stop layer 124 may completely fill groove 123 . As discussed in greater detail below, second dielectric layer 126 (shown in Figures 21A-21B) will be formed over etch stop layer 124, and conductive features 142 (shown in Figures 26A-26B) will Through the second dielectric layer 126 to contact the conductive features 122, the etch stop layer 124 will act as an etch stop during the etching process. Etch stop layer 124 may be formed from a dielectric material that has a lower etch rate than subsequently formed dielectric layer 126 . The dielectric material may be aluminum oxide, aluminum nitride, tungsten nitride, molybdenum oxide, molybdenum nitride, boron nitride, etc., and may be deposited by any suitable method, such as ALD, CVD, plasma-enhanced ALD ALD;PEALD) or PECVD. Other dielectric materials formed by any acceptable process may be used. In some implementations, the material used to form etch stop layer 124 is different from the material used to form dielectric layer 100 . In some embodiments, alumina is deposited using trimethylaluminium (TMA) and hydrocarbon-based alcohol as ALD precursors at temperatures ranging from about 250°C to about 500°C. Hydrocarbyl alcohols can be used as oxygen sources during the deposition process because the oxidation strength of hydrocarbyl alcohols is weaker than that of oxygen sources such as oxygen, ozone, water, and nitrous oxide. The weaker oxidative strength of hydrocarbyl alcohols may help reduce oxidation in conductive features 122 . In some embodiments, ALD or CVD may be used for the deposition of aluminum oxide. In this case, the oxygen source is provided by a remote plasma, which also helps reduce oxidation in conductive features 122 and increases the deposition rate of etch stop layer 124 . In some embodiments, aluminum nitride is deposited using a precursor containing trimethylaluminum (TMA) and ammonia as ALD at a temperature ranging from about 250 ºC to about 500 ºC.

In Figures 20A and 20B, a planarization process, such as CMP, is performed to remove excess material of etch stop layer 124 (eg, from above dielectric layer 100). In some embodiments, after the planarization process, the etch stop layer 124, the first ILD 88, the CESL 87, the gate spacer 86, the gate seal spacer 80, and the top surface of the dielectric layer 100 may be flush. The thickness of etch stop layer 124 may range from about 1 nm to about 10 nm, although other thicknesses are possible. In some implementations, the thickness of etch stop layer 124 is different than the thickness of dielectric layer 100 . In some implementations, the thickness of etch stop layer 124 is less than the thickness of dielectric layer 100 . In some implementations, etch stop layer 124 may extend between and/or be in physical contact with the sidewalls of first ILD 88 . Etch stop layer 124 may have various top surface profiles, discussed in greater detail later in Figures 29A, 29B, and 29C.

In Figures 21A and 21B, the second ILD 126 is formed over the first ILD 88, the dielectric layer 100 and the etch stop layer 124. In some implementations, second ILD 126 may be of a similar material to first ILD 88 and may be formed in a similar manner. For example, second ILD 126 may be formed from a dielectric material such as oxide, PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD, PECVD, or FCVD. The second ILD 126 may have various top and bottom surface profiles, discussed in more detail later in Figures 30A, 30B, and 30C. After the second ILD 126 is formed, an annealing process may be performed. In some embodiments, the annealing process is performed at a temperature ranging from about 250 ºC to about 450 ºC. In some embodiments, the annealing process may be performed for a duration ranging from about 1 minute to about 1 hour. The second ILD 126 can have various top and bottom surface profiles after annealing, as discussed in more detail later in Figures 31A, 31B, and 31C.

In some embodiments, the material of etch stop layer 124 and/or the material of second ILD 126 is selected such that openings 134 and 135 are subsequently formed through second ILD 126 (as shown in Figures 24A-24B ), the etching rate of the etch stop layer 124 is less than the etching rate of the second ILD 126 . Because of etch stop layer 124, second ILD 126 can be formed over first ILD 88, dielectric layer 100, and conductive features 122 without depositing a blanket etch stop layer, allowing for a thinner overall element.

Figures 22A and 22B illustrate patterning of second ILD 126 and dielectric layer 100 to form openings 130 and 131 in accordance with some embodiments. Openings 130 and 131 extend through second ILD 126 and dielectric layer 100 to expose the top surface of gate 94 . Second ILD 126 and dielectric layer 100 may be patterned using acceptable lithography and etching techniques. For example, a first photoresist 128 may be formed over the second ILD 126 and patterned using a suitable lithography technique. The first photoresist 128 may be a single layer or a multi-layer photoresist structure and may be deposited using a suitable technique such as spin coating or deposition techniques. One or more suitable etching processes may then be performed using the patterned first photoresist 128 as an etch mask and the dielectric layer 100 (which may also be referred to as an etch stop layer) as an etch stop layer while etching through the first Two ILDs 126 are formed, thereby forming openings 130 and 131 . The one or more etching processes may include wet and/or dry etching processes. Figures 22A and 22B illustrate openings 130 and 131 having sloped sidewalls, but in other embodiments, openings 130 or 131 may have substantially vertical sidewalls, curved sidewalls, or other sidewall profiles. The first photoresist 128 may be removed using a process such as ashing or etching.

As previously discussed, by forming etch stop layer 124 over conductive features 122, second ILD 126 can be formed over first ILD 88, dielectric layer 100, and conductive features 122 without depositing a blanket etch stop layer, thereby reducing Minimize the thickness of the layer above gate 94 that needs to be etched when forming openings 130 and 131 . Reducing this thickness may result in a better profile of openings 130 and 131 .

In Figures 23A and 23B, a second photoresist 132 is formed over the second ILD 126 and in the openings 130 and 131, according to some embodiments. The second photoresist 132 may be a single layer or a multi-layer photoresist structure and may be deposited using a suitable technique such as spin coating or deposition techniques. As shown in FIG. 23B , the second photoresist 132 may overfill the openings 130 and 131 and extend over the second ILD 126 .

Figures 24A and 24B illustrate patterning of second photoresist 132, second ILD 126, and etch stop layer 124 to form openings 134 and 135 in accordance with some embodiments. Openings 134 and 135 extend through second ILD 126 and etch stop layer 124 to expose top surfaces of conductive features 122 . The second photoresist 132, the second ILD 126, and the etch stop layer 124 may be patterned using acceptable lithography and etching techniques. One or more suitable etching processes may then be performed using patterned second photoresist 132 as an etch mask to form openings 134 and 135 . The one or more etching processes may include wet and/or dry etching processes.

In some implementations, an etching process may be used to etch the second ILD 126 . In some embodiments, a dry etching process utilizing gas mixtures of CF ₄ /H ₂ /N ₂ /Ar, NF ₂ /H ₂ /N ₂ /Ar, or the like is used. The etching process may be performed at a power ranging from about 50W to about 1000W and at a temperature ranging from about -20°C to about 200°C. During the etching process, the etch rate of the second ILD 126 exceeds the etch rate of the etch stop layer 124 and may range from about 4:1 to about 1000:1. Accordingly, the etch process may remove portions of the second ILD 126 and then stop or slow down at the etch stop layer 124 , which reduces the chance of over-etching the conductive features 122 and therefore reduces the formation of leakage paths or other defects. opportunity.

A separate etch process may be performed to remove portions of etch stop layer 124 and expose the top surfaces of conductive features 122 . A separate etch process may use a different etchant than the etch process used to etch the second ILD 126 . In some embodiments, etch stop layer 124 may be dry etched using a gas mixture such as _N2 / _H2 / _O2 or the like. The dry etching process may be performed at a power ranging from about 50W to about 1000W and at a temperature ranging from about -20°C to about 200°C. In some embodiments, the etch stop layer 124 is etched using a wet etching process using hydrogen fluoride, hydrogen peroxide, water, chelating agents, or the like. The wet etching process may be performed at temperatures ranging from about 0°C to about 100°C.

In some implementations, opening 134 or opening 135 may expose sidewalls of etch stop layer 124 . In some implementations, opening 134 or opening 135 may expose the sidewalls of first ILD 88 . In some embodiments, opening 134 or opening 135 may expose the sidewalls of CESL 87. Figures 24A and 24B illustrate openings 134 and 135 with sloped sidewalls, but in other embodiments, openings 134 or 135 may have substantially vertical sidewalls, curved sidewalls, or other sidewall profiles.

In some embodiments, one or more etching processes are performed to form openings for butted contacts, such as with conductive features 122 (coupled to source/drain regions 82 ) and adjacent gate 94 Joint or combined contact. For example, the opening 135 shown in FIG. 24B illustrates an embodiment in which the opening 135 overlaps the second photoresist 132 above the gate 94 on the left side of the figure. In subsequent processing, second photoresist 132 is removed, thereby forming openings exposing gate 94 and conductive features 122 . The etch rate of the materials of each layer (e.g., gate seal spacer 80 , gate spacer 86 , CESL 87 , first ILD 88 , dielectric layer 100 and/or second photoresist 132 ) may be different than that of etch stop layer 124 Etch rate of the material. The difference in etch rate may cause the upper surface of the gate seal spacer 80, the gate spacer 86, the CESL 87, the first ILD 88, the dielectric layer 100 and/or the second photoresist 132 to be the same as, above or below the upper surface of conductive feature 122. Figure 24B illustrates gate seal spacer 80, gate spacer 86, CESL 87, first ILD 88, dielectric layer 100 and/or second photoresist An embodiment in which the etch rate of etch stop layer 132 is less than that of etch stop layer 124 .

In Figures 25A and 25B, second photoresist 132 is removed, forming openings 130, 134, and 136, according to some embodiments. The second photoresist 132 may be removed using a suitable technique such as ashing or etching. As shown in FIGS. 25A and 25B , the second photoresist 132 is removed and the previously formed opening 130 is exposed, which exposes the top surface of the gate 94 . Due to the overlap between the previously formed opening 131 and the opening 135, the second photoresist 132 is removed to form the combined opening 136, which exposes the top surface of the gate 94 previously exposed by the opening 131 and the top surface of the gate 94 previously exposed by the opening 131. Opening 135 exposes the top surface of conductive feature 122 . Opening 134 still exposes the top surface of conductive feature 122 . In some embodiments, a wet cleaning process is performed before and/or after removing the second photoresist 132 .

In Figures 26A and 26B, conductive features 140, 142, and combined conductive features 144 are formed in openings 130, 134, and combined openings 136, respectively. In some embodiments, forming conductive features 140 , 142 , 144 may include forming gaskets (not shown) (such as barrier layers, adhesive layers, etc.) and conductive materials in openings 130 , 134 , and 136 . The liner may contain titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 126 . The remaining pads and conductive material form conductive features 140, 142, 144. Conductive features 140, 142, 144 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that conductive features 140 , 142 , and/or conductive features 144 may be formed in different cross-sections, which may avoid/reduce the risk of short circuits. Conductive features 142 may have various widths, as discussed in greater detail in Figures 32A, 32B, and 32C.

Conductive feature 140 is electrically connected to gate 94 . Therefore, in some cases, conductive features 140 may be referred to as gate contacts or gate contact plugs. Conductive features 142 are electrically connected to conductive features 122 that are electrically connected to epitaxial source/drain regions 82 . Therefore, in some cases, the combination of conductive feature 142 and underlying conductive feature 122 may also be referred to as a source/drain contact or source/drain contact plug. Combined conductive feature 144 is electrically connected to gate 94 and epitaxial source/drain region 82 (via conductive feature 122). In this manner, a FinFET device can be formed that includes gate contact plugs and source/drain contact plugs. As previously described, by forming etch stop layer 124 over conductive features 122, second ILD 126 can be formed over first ILD 88, dielectric layer 100, and conductive features 122 without depositing a blanket etch stop layer, which can This provides better contouring of conductive features 140 and combined conductive features 144 and results in better electrical connection.

In Figures 27A and 27B, an interconnect structure including one or more layers of conductive features is formed over and electrically connected to the conductive features 140, 142, 144. In some embodiments, the interconnect structure includes a plurality of dielectric layers, such as inter-metal dielectric (IMD) layers, and conductive features within the IMD that provide various electrical interconnections. Figures 27A and 27B illustrate embodiments that include one IMD 152 with conductive features 150 and one IMD 155 with conductive features 154, although more or fewer IMDs or conductive features may be formed in other embodiments. . Conductive features 150 and 154 may include electrical routing, conductive vias, wires, etc., and may be formed using single damascene methods, dual damascene methods, combinations thereof, and the like.

In some embodiments, an etch stop layer 151 may be deposited first over the second ILD 126 and conductive features 140, 142, 144. The etch stop layer 151 may include materials such as silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, etc. or combinations thereof. Other materials are also possible. IMD 152 may then be formed over etch stop layer 151 . The material of IMD 152 may be similar to that described for first ILD 88 or second ILD 126, and may be formed in a similar manner. In some implementations, IMD 152 may be formed from a low-k dielectric material having a k value below about 3.5. Other materials or technologies are also possible. Openings may then be patterned in IMD 152 and etch stop layer 151 to expose the surfaces of conductive features 140, 142, and/or 144. An optional pad (not shown) may first be formed in the opening, which may be similar to the pads of conductive features 140, 142, 144 described previously. Conductive material may be deposited within the openings to form conductive features 150 . The conductive materials may be similar to those described for conductive features 140, 142, 144, and may be formed in a similar manner. Other conductive materials or technologies are also possible. A planarization process may be performed to remove excess conductive material from IMD 152 . Figures 27A and 27B illustrate conductive features 150 having sloped sidewalls, but in other embodiments, conductive features 150 may have substantially vertical sidewalls, curved sidewalls, or other sidewall profiles.

Conductive features 154 may be formed in a manner similar to the manner in which conductive features 150 are formed. For example, etch stop layer 153 may be formed over IMD 152 and conductive features 150 , and IMD 155 may be formed over IMD 152 . Etch stop layer 153 and IMD 152 may be patterned to form a plurality of openings. Some openings may expose conductive features 150 . Liners and conductive materials are then deposited in the openings, and a CMP process can be performed to remove excess material. Figures 27A and 27B illustrate conductive features 154 with sloped sidewalls, but in other embodiments, conductive features 154 may have substantially vertical sidewalls, curved sidewalls, or other sidewall profiles.

Certain features of the FinFET implementations discussed herein may also be applied to nanostructured devices, such as NFETs/NSFETs. As an example, Figures 28A and 28B are schematic cross-sectional views of NSFET devices according to some embodiments. NSFET devices are similar to the FinFET devices shown in Figures 27A and 27B. Therefore, similar features in Figures 27A-27B and Figures 28A-28B are labeled with similar reference numbers. The channel region of the NSFET device contains nanostructures 160 separated by fins 52 and surrounded by respective gate stacks (eg, gate dielectric 92 and gate 94), as shown in Figure 28A. Nanostructures 160 may include nanosheets, nanowires, or the like. Nanostructures 160 and substrate 50 may include similar semiconductor materials or different semiconductor materials. In some embodiments, a portion of the gate stack is interposed between adjacent nanostructures 160, and a spacer 162 is interposed between a portion of the gate stack and the epitaxial source/drain region 82, as shown in Figure 28B Show. Spacers 162 may serve as isolation features between the gate stack and epitaxial source/drain regions 82 . In some embodiments, spacers 162 comprise a material such as silicon nitride or silicon oxynitride, although any suitable material such as a low-k dielectric material may be utilized. The conductive features 140, 142, 144 that contact the top surface of the gate and the top surface of the conductive feature 122 may be formed in a manner similar to the FinFET implementation discussed previously. In some implementations, an etch stop layer 124 may be formed on the top surface of the conductive features 122, which may be formed in a similar manner to serve a similar purpose as the previously discussed FinFET implementations.

Figures 29A, 29B, and 29C illustrate various top surface profiles of the etch stop layer 124 after the planarization process discussed above, according to some embodiments. The structures shown in Figures 29A, 29B, and 29C are part of the structure in Figure 20B, in which the top surface of the etch stop layer 124 has a different top surface profile. For example, Figure 29A illustrates etch stop layer 124 with a flat top surface, wherein etch stop layer 124, first ILD 88, CESL 87, gate spacer 86, gate seal spacer 80, and dielectric layer 100 The top surface can remain flush. In some cases, forming the etch stop layer 124 with a flat top surface or forming the etch stop layer 124 with a uniform thickness results in better control of the etching process as the etch stop layer 124 is etched through, resulting in conductive features. A better etching profile of 142, as shown in Figure 26B. Figure 29B illustrates etch stop layer 124 having a convex or protruding top surface such that the top surface of etch stop layer 124 extends to etch stop layer 124, first ILD 88, CESL 87, gate spacer 86, gate seal above the top surface of spacers 80 and/or dielectric layer 100 . Figure 29C illustrates etch stop layer 124 having a concave or recessed top surface such that the top surface of etch stop layer 124 extends to etch stop layer 124, first ILD 88, CESL 87, gate spacer 86, gate seal Spacers 80 and below the top surface of dielectric layer 100 .

In some embodiments, the top surface profile of etch stop layer 124 may be controlled by controlling the polishing rate (R1) of etch stop layer 124 and the polishing rate (R2) of surrounding layers, such as first ILD 88, CESL 87, Gate spacers 86 , gate seal spacers 80 and/or dielectric layer 100 . In some embodiments, R1 is the same as R2, and the planarization process can result in an etch stop layer 124 with a flat top surface, such as shown in Figure 29A. In some embodiments, where R1 is smaller than R2, the planarization process may result in an etch stop layer 124 with a convex or protruding top surface, such as shown in Figure 29B. In some embodiments, where R1 is greater than R2, the planarization process may result in an etch stop layer 124 with a concave or recessed top surface, such as shown in Figure 29C.

Figures 30A, 30B, and 30C illustrate forming a second ILD 126 on the etch stop layer 124 of Figures 29A, 29B, and 29C, in accordance with some embodiments. The structures shown in Figures 30A, 30B, and 30C are part of the structure shown in Figure 21B, in which the upper surface of the second ILD 126 corresponds to the upper surface of the underlying etch stop layer 124. Figure 30A shows the formation of a second ILD 126 on the flat top surface of the etch stop layer 124 in Figure 29A in accordance with some embodiments. The second ILD 126 may have a flat top surface and a flat bottom surface. Figure 30B illustrates the formation of a second ILD 126 on the convex or protruding top surface of the etch stop layer 124 in Figure 29B in accordance with some embodiments. A portion of the top surface of the second ILD 126 above the etch stop layer 124 may be convex or protruding, while a portion of the bottom surface of the second ILD 126 above the etch stop layer 124 may be concave or recessed. Figure 30C illustrates the formation of a second ILD 126 on the concave or recessed top surface of the etch stop layer 124 in Figure 29C in accordance with some embodiments. A portion of the top surface of the second ILD 126 above the etch stop layer 124 may be concave or recessed, while a portion of the bottom surface of the second ILD 126 above the etch stop layer 124 may be convex or protruding.

Figures 31A, 31B, and 31C illustrate various embodiments of the shape of the etch stop layer 124 after an annealing process performed after the deposition of the second ILD 126 as previously described. Figures 31A, 31B and 31C may represent, for example, the shape of the etch stop layer 124 after the annealing process of Figure 30A. In some embodiments, as shown in FIG. 31A , both the etch stop layer 124 and the second ILD 126 may maintain a flat top surface after the annealing process. In some cases, forming the etch stop layer 124 with a flat top surface or forming the etch stop layer 124 with a uniform thickness results in better control of the etching process as the etch stop layer 124 is etched through, resulting in better conductive features 142 . Good outline, as shown in Figure 26B.

In some embodiments, as shown in FIG. 31B , the etch stop layer 124 may have a convex or protruding top surface after the annealing process. For example, the process of forming and/or annealing the second ILD 126 may use a relatively High temperatures, such as in the range from 400ºC to about 500ºC, and these higher temperatures may cause the etch stop layer 124 to expand due to the reduction in surface energy on the top surface of the etch stop layer 124 . Accordingly, a portion of the top surface of the second ILD 126 above the etch stop layer 124 may be convex or protruding, and a portion of the bottom surface of the second ILD 126 above the etch stop layer 124 may be concave or recessed. In other words, a portion of the bottom surface of second ILD 126 above etch stop layer 124 may extend to etch stop layer 124 , first ILD 88 , CESL 87 , gate spacer 86 , gate seal spacer 80 , and dielectric layer 100 above the top surface.

In some embodiments, as shown in FIG. 31C, the etch stop layer 124 may have a concave or recessed surface after the annealing process. This may be the result of shrinkage of the underlying conductive features 122 caused by metal grain growth or microvoids/impurities removal during the annealing process and/or recessing during the planarization process described above. Accordingly, a portion of the top surface of the second ILD 126 above the etch stop layer 124 may be concave, and a portion of the bottom surface of the second ILD 126 above the etch stop layer 124 may be protruding. In other words, a portion of the bottom surface of second ILD 126 above etch stop layer 124 may remain flat and remain flat between etch stop layer 124 , first ILD 88 , CESL 87 , gate spacer 86 , gate seal spacer 80 , and dielectric The layer 100 extends below the top surface.

Figures 32A, 32B, and 32C illustrate structures similar to those shown in Figure 26B, where the conductive features 142 have different widths. The width of the top surface of conductive features 122 is labeled "W1" and the width of the bottom surface of conductive features 142 is labeled "W2." According to some embodiments, FIG. 32A illustrates conductive features 142 having a width W2 that is less than width W1 of conductive features 122 . As shown in FIG. 32A , forming conductive features 142 having a width W2 that is less than width W1 may result in portions of the etch stop layer 124 remaining on the conductive features 122 after the conductive features 142 are formed. In some implementations, one or all opposing sidewalls of conductive features 142 may be in physical contact with sidewalls of etch stop layer 124 . For example, in some implementations, the bottoms of conductive features 142 may be at least partially surrounded by etch stop layer 124 . In some cases, forming conductive features 142 with a relatively small width W2 can reduce the risk of via-to-via leakage, via-bridging "tiger-tooth" defects, defects caused by lithography coverage issues, and the like.

Figure 32B illustrates conductive features 142 having a width W2 that is approximately the same as the width W1 of conductive features 122, according to some embodiments. As shown in Figure 32B, forming conductive features 142 having a width W2 that is approximately the same as width W1 may result in the removal of the etch stop layer 124 in the cross-sectional schematic view. In some implementations, conductive features 142 may physically contact the top of the sidewalls of first ILD 88 . In some implementations, the bottom of conductive features 142 may be at least partially surrounded by the top of first ILD 88 . In some cases, forming conductive features 142 with a width W2 that is approximately the same as width W1 may increase the contact area between conductive features 122 and 142 . Increasing the contact area in this manner may reduce contact resistance between conductive features 122 and 142 and improve device performance.

Figure 32C illustrates conductive features 142 having a width W2 that is greater than the width W1 of conductive features 122, according to some embodiments. As shown in Figure 32C, forming conductive features 142 with width W2 that is greater than width W1 may result in removal of etch stop layer 124 in the cross-sectional schematic view. In some embodiments, conductive features 142 may physically contact the top of the sidewalls of CESL 87. In some implementations, the bottom of conductive features 142 may be at least partially surrounded by the top of CESL 87.

The embodiments described herein have several advantages. For example, instead of depositing a blanket etch stop layer over the source/drain regions and the gate stack, the etch stop layer may be formed in the trenches connected to the conductive features of the source/drain regions. This reduces the overall thickness of the device (including the thickness of the layers above the gate stack) and therefore results in better control of the etching process when forming conductive features above the gate stack, which results in better conductive feature profiles. In this way, the electrical connection in the component is improved.

In one embodiment, a semiconductor device includes: a source/drain region on a substrate; a first conductive feature above the source/drain region; a first etch stop layer above the first conductive feature; and a gate. a gate structure on the substrate; a second etch stop layer above the gate structure, wherein the first etch stop layer and the second etch stop layer have different thicknesses; a first dielectric layer adjacent to the first conductive feature, the first The etch stop layer, the gate structure and the second etch stop layer; the second dielectric layer above the first dielectric layer; the source/drain contact extending through the second dielectric layer and the first etch stop layer to a first conductive feature; and a gate contact extending through the second dielectric layer and the second etch stop layer to the gate structure. In one embodiment, the first etch stop layer and the second etch stop layer are formed of different materials. In one embodiment, the thickness of the first etch stop layer ranges from 1 nm to 10 nm. In one embodiment, the thickness of the second etch stop layer is in a range between 10 nm and 20 nm. In one embodiment, the thickness of the first etch stop layer is less than the thickness of the second etch stop layer. In one embodiment, the first dielectric layer extends between the first etch stop layer and the second etch stop layer. In one embodiment, the top surface of the first etch stop layer is flush with the top surface of the first dielectric layer. In one embodiment, the gate spacers extend along sidewalls of the gate structure, and wherein a top surface of the first etch stop layer is flush with a top surface of the gate spacers.

In one embodiment, a semiconductor device includes: a source/drain region on a substrate; a first conductive feature above the source/drain region; a first etch stop layer above the first conductive feature, An etch stop layer includes a first material; a gate structure on the substrate; a second etch stop layer above the gate structure, the second etch stop layer includes a second material, wherein the first material and the second material are different material; a first dielectric layer between the first etch stop layer and the second etch stop layer; a second dielectric layer above the first dielectric layer; a source/drain contact extending through the second dielectric the electrical layer and the first etch stop layer to the first conductive feature; and the gate contact extending through the second dielectric layer and the second etch stop layer to the gate structure. In one embodiment, the first etch stop layer includes aluminum oxide, aluminum nitride, tungsten nitride, molybdenum oxide, molybdenum nitride, boron nitride, or a combination thereof. In one embodiment, the first conductive feature includes cobalt, tungsten, ruthenium, copper, or combinations thereof. In one embodiment, the second etch stop layer includes silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof. In one embodiment, the top surface of the first etch stop layer extends above the top surface of the first dielectric layer. In one embodiment, the top surface of the first etch stop layer extends below the top surface of the first dielectric layer.

In one embodiment, a method of forming a semiconductor device includes: forming a gate structure on a substrate; forming a source/drain region adjacent to the gate structure; forming a first dielectric layer in the source/drain region; forming an extension Contact plugs passing through the first dielectric layer to contact the source/drain regions; forming a dielectric cap on the contact plugs, wherein the top surface of the dielectric cap is flush with the top surface of the first dielectric layer; forming A second dielectric layer over the dielectric cap and gate structure; and forming conductive features through the second dielectric layer to the contact plugs. In one embodiment, forming the conductive features includes performing a first etching process to create an opening in the second dielectric layer, wherein the dielectric cap serves as an etch stop during the first etching process; and performing a second etching process, to remove portions of the dielectric cap to expose the contact plugs. In one embodiment, the conductive features physically contact sidewalls of the dielectric cap. In one implementation, the conductive features physically contact sidewalls of the first dielectric layer. In one embodiment, the conductive features electrically connect the gate structure and the source/drain regions. In one embodiment, the gate spacers are along sidewalls of the gate structure, and wherein the top surface of the dielectric cap is flush with the top surface of the gate spacers.

The above summary of features of various embodiments allows those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure may be readily used as a basis for designing or modifying other processes and structures that carry out the same purposes and/or achieve the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and various changes, substitutions and modifications may be made herein without departing from the spirit and scope of the disclosure. .

50:Substrate 50N:Area 50P:Area 51:divider 52:fins 54:Insulating materials 56: Isolation (STI) area 58: Passage area 60: Dummy dielectric layer 62: Dummy gate layer 64: Mask layer 72: Dummy gate 74:Mask 80: Gate seal spacer 82: Epitaxial source/drain region 86: Gate spacer 87: Contact Etch Stop Layer (CESL) 88: First interlayer dielectric layer (ILD) 89:Area 90: Groove 92: Gate dielectric layer 94: Gate 94A:Packing layer 94B: Work function adjustment layer 94C: Filling material 100:Dielectric layer 118:Open your mouth 120: Silicone layer 122: Conductive characteristics 123: Groove 124: Etch stop layer 126: Second dielectric layer 128:The first photoresist 130:Open your mouth 131:Open your mouth 132: Second photoresist 134:Open your mouth 135:Open your mouth 136:Open your mouth 140: Conductive characteristics 142: Conductive characteristics 144: Conductive characteristics 150: Conductive characteristics 151: Etch stop layer 152: Intermetal dielectric layer (IMD) 153: Etch stop layer 154: Conductive characteristics 155: Intermetal dielectric layer (IMD) 160: Nanostructure 162: Spacer W1: Width W2: Width A-A: cross section B-B: cross section C-C: cross section

The disclosure will be fully understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, features are not drawn to scale and are for illustration purposes only. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. Figure 1 illustrates an example of a Fin Field-Effect Transistor (FinFET) in a three-dimensional view according to some embodiments. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8A, Figure 8B, Figure 9A, Figure 9B, Figure 10A, Figure 10B, Figure 10C Figure, Figure 10D, Figure 11A, Figure 11B, Figure 12A, Figure 12B, Figure 13A, Figure 13B, Figure 14A, Figure 14B, Figure 14C, Figure 15A, Figure 15B, Figure 16A, Figure 16B, Figure 17A, Figure 17B, Figure 18A, Figure 18B, Figure 19A, Figure 19B, Figure 20A, Figure 20B, Figure 21A, Figure 21B, Figure 22A Figure, Figure 22B, Figure 23A, Figure 23B, Figure 24A, Figure 24B, Figure 25A, Figure 25B, Figure 26A, Figure 26B, Figure 27A, Figure 27B, Figure 29A, Figure 29B, Figure 29C, Figure 30A, Figure 30B, Figure 30C, Figure 31A, Figure 31B, Figure 31C, Figure 32A, Figure 32B and Figure 32C are manufactured according to some embodiments. Schematic cross-section of the intermediate stage of a FinFET device. Figures 28A and 28B are schematic cross-sectional views at an intermediate stage of manufacturing a Nanostructure Field-Effect Transistor (NSFET) device according to some embodiments.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

50:Substrate

52:fins

82: Epitaxial source/drain region

94: Gate

100:Dielectric layer

122: Conductive characteristics

124: Etch stop layer

126: Second dielectric layer

Claims (20)

A semiconductor component containing: a source/drain region on a substrate; a first conductive feature above the source/drain region; a first etch stop layer above the first conductive feature; a gate structure on the substrate; a second etch stop layer above the gate structure, wherein the first etch stop layer and the second etch stop layer have different thicknesses; a first dielectric layer adjacent the first conductive feature, the first etch stop layer, the gate structure, and the second etch stop layer; a second dielectric layer above the first dielectric layer; a source/drain contact extending through the second dielectric layer and the first etch stop layer to the first conductive feature; and A gate contact extends through the second dielectric layer and the second etch stop layer to the gate structure. The semiconductor device of claim 1, wherein the first etching stop layer and the second etching stop layer are formed of different materials. The semiconductor device according to claim 1, wherein a thickness of the first etching stop layer is in a range between 1 nm and 10 nm. The semiconductor device according to claim 1, wherein a thickness of the second etching stop layer is in a range between 10 nm and 20 nm. The semiconductor device of claim 1, wherein a thickness of the first etching stop layer is less than a thickness of the second etching stop layer. The semiconductor device of claim 1, wherein the first dielectric layer extends between the first etch stop layer and the second etch stop layer. The semiconductor device of claim 1, wherein a top surface of the first etch stop layer is flush with a top surface of the first dielectric layer. The semiconductor device of claim 1, wherein a gate spacer extends along a side wall of the gate structure, and wherein a top surface of the first etch stop layer is flush with a top surface of the gate spacer . A semiconductor component containing: a source/drain region on a substrate; a first conductive feature above the source/drain region; a first etch stop layer above the first conductive feature, the first etch stop layer including a first material; a gate structure on the substrate; a second etch stop layer above the gate structure, the second etch stop layer includes a second material, wherein the first material and the second material are different materials; a first dielectric layer between the first etch stop layer and the second etch stop layer; a second dielectric layer above the first dielectric layer; a source/drain contact extending through the second dielectric layer and the first etch stop layer to the first conductive feature; and A gate contact extends through the second dielectric layer and the second etch stop layer to the gate structure. The semiconductor device of claim 9, wherein the first etching stop layer includes aluminum oxide, aluminum nitride, tungsten nitride, molybdenum oxide, molybdenum nitride, boron nitride or a combination thereof. The semiconductor device of claim 9, wherein the first conductive feature includes cobalt, tungsten, ruthenium, copper or a combination thereof. The semiconductor device of claim 9, wherein the second etching stop layer includes silicon nitride, silicon carbide, silicon carbonitride or a combination thereof. The semiconductor device of claim 9, wherein a top surface of the first etch stop layer extends above a top surface of the first dielectric layer. The semiconductor device of claim 9, wherein a top surface of the first etch stop layer extends below a top surface of the first dielectric layer. A method of forming a semiconductor component, comprising: forming a gate structure on a substrate; forming a source/drain region adjacent the gate structure; forming a first dielectric layer on the source/drain region; forming a contact plug extending through the first dielectric layer to contact the source/drain region; Forming a dielectric cap on the contact plug, wherein a top surface of the dielectric cap is flush with a top surface of the first dielectric layer; forming a second dielectric layer on the dielectric cap and the gate structure; and A conductive feature is formed through the second dielectric layer to the contact plug. The method of claim 15, wherein forming the conductive feature includes: performing a first etch process to create an opening in the second dielectric layer, wherein the dielectric cap serves as an etch stop layer during the first etch process; and A second etching process is performed to remove portions of the dielectric cap to expose the contact plug. The method of claim 15, wherein the conductive feature physically contacts a plurality of sidewalls of the dielectric cap. The method of claim 15, wherein the conductive feature physically contacts a plurality of sidewalls of the first dielectric layer. The method of claim 15, wherein the conductive feature electrically connects the gate structure and the source/drain region. The method of claim 15, wherein a gate spacer extends along a side wall of the gate structure, and wherein the top surface of the dielectric cap is flush with a top surface of the gate spacer.

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