CN117096097A

CN117096097A - Semiconductor device and method of forming the same

Info

Publication number: CN117096097A
Application number: CN202310458933.4A
Authority: CN
Inventors: 侯承浩; 蔡欣宏; 李达元; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-07-14
Filing date: 2023-04-26
Publication date: 2023-11-21

Abstract

The present disclosure provides semiconductor devices and methods of forming the same. A method comprising: forming a first capacitor electrode; forming a first oxygen barrier layer on the first capacitor electrode; forming a capacitor insulator layer on the first oxygen barrier layer; forming a second oxygen barrier layer on the capacitor insulator layer; forming a second capacitor electrode on the second oxygen barrier layer; and forming a first contact plug electrically coupled to the first capacitor electrode and a second contact plug electrically coupled to the second capacitor electrode.

Description

Semiconductor device and method of forming the same

Technical Field

The present disclosure relates generally to the field of semiconductor technology, and more particularly to semiconductor devices and methods of forming the same.

Background

Metal-insulator-metal (MIM) capacitors have been widely used in functional circuits such as mixed signal circuits, analog circuits, radio Frequency (RF) circuits, dynamic Random Access Memories (DRAMs), embedded DRAMs, and logic operation circuits. In system-on-chip applications, different capacitors for different functional circuits must be integrated on the same chip for different purposes. For example, in a mixed signal circuit, a capacitor is used as a decoupling capacitor and a high frequency noise filter. For DRAM and embedded DRAM circuits, capacitors are used for memory storage, while for RF circuits, capacitors are used in oscillator and phase shift networks for coupling and/or bypass purposes. For microprocessors, capacitors are used for decoupling.

Decoupling capacitors are used to decouple some parts of the grid from other parts. Noise caused by certain circuit elements is shunted through the decoupling capacitor, thus reducing the impact of noise producing circuit elements on adjacent circuits. Furthermore, decoupling capacitors are also used in the power supply, so that the power supply can accommodate variations in current draw and noise (variations) in the power supply voltage can be suppressed.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a method comprising: forming a first capacitor electrode; forming a first oxygen barrier layer on the first capacitor electrode; forming a capacitor insulator layer on the first oxygen barrier layer; forming a second oxygen barrier layer on the capacitor insulator layer; forming a second capacitor electrode on the second oxygen barrier layer; and forming a first contact plug electrically coupled to the first capacitor electrode and a second contact plug electrically coupled to the second capacitor electrode.

According to another aspect of the present disclosure, there is provided a method comprising: depositing a first conductive material over the dielectric layer; patterning the first conductive material to form a first electrode; depositing a first barrier layer as a capping layer over the first electrode, wherein the barrier layer comprises a first metal oxide; depositing a first insulator layer as a capping layer over the first barrier layer, wherein the first insulator layer comprises a second metal oxide different from the first metal oxide; depositing a second barrier layer as a capping layer over the first insulator layer, wherein the second barrier layer comprises a first metal oxide; depositing a second conductive material over the second barrier layer; and patterning the second conductive material to form a second electrode.

According to yet another aspect of the present disclosure, there is provided a device comprising: a first via on the first conductive feature; a second via on the second conductive feature; and a capacitive stack comprising: an electrode layer comprising first electrode layers and second electrode layers, wherein the first electrode layers are alternately arranged with the second electrode layers, wherein the first electrode layers are electrically coupled to the first via and the second electrode layers are electrically coupled to the second via; insulator layers, wherein each insulator layer is between a respective first electrode layer and a respective second electrode layer; first barrier layers, wherein each first barrier layer is between a bottom surface of a respective insulator layer and a top surface of a respective electrode layer; and second barrier layers, wherein each second barrier layer is between a top surface of a respective insulator layer and a bottom surface of a respective electrode layer.

Drawings

The aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It is noted that the various features are not drawn to scale according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of a package assembly including one or more metal-insulator-metal (MIM) capacitors, according to some embodiments.

Fig. 2-18 illustrate cross-sectional views of intermediate stages in the formation of a capacitor according to some embodiments.

Fig. 19-25 illustrate cross-sectional views of intermediate stages in the formation of a capacitor according to some embodiments.

Fig. 26 illustrates a plan view of a device including a plurality of capacitors, in accordance with some embodiments.

Fig. 27A and 27B illustrate cross-sectional views of a capacitor including one blocking layer under forward bias and reverse bias, in accordance with some embodiments.

Fig. 28A and 28B illustrate cross-sectional views of a capacitor including two barrier layers under forward bias and reverse bias, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of elements and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper" and the like) may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A capacitor and a method of forming the same are provided. According to some embodiments, the formation of a metal-insulator-metal (MIM) capacitor includes depositing a bottom barrier layer between an insulator layer and a lower electrode, and depositing a top barrier layer between the insulator layer and an upper electrode. Forming both the top barrier and the bottom barrier allows the capacitor to have more consistent behavior in forward and reverse bias. In particular, the electric field across the insulator layer may be reduced in both forward and reverse bias, which may improve the reliability and lifetime of the capacitor. In addition, forming a capacitor with two barrier layers may result in a more similar forward biased capacitance and reverse biased capacitance.

The embodiments discussed herein are provided to provide examples to enable the subject matter of the present disclosure to be made or used, and those skilled in the art will readily appreciate modifications that may be made while remaining within the intended scope of the various embodiments. Like reference numerals are used to denote like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

Fig. 1 illustrates a cross-sectional view of a package assembly 100 including one or more capacitors 146 therein, according to some embodiments. In some embodiments, capacitor 146 may be a metal-insulator-metal (MIM) capacitor. The package assembly 100 may be, for example, a device wafer, an interposer wafer, a package (e.g., an integrated fan-out (InFo) package, etc.), and so forth. In the embodiment shown later, the device wafer is used as an example structure of the package assembly 100, but the capacitor 146 may be formed in other structures or other areas of the device wafer, such as in a back-end redistribution structure of the device wafer. Accordingly, those skilled in the art will appreciate that the formation of the capacitor 146 described herein is not limited to the examples shown and described in this disclosure. Three example capacitors 146A, 146B, and 146C are shown in fig. 1, and for simplicity, "capacitor 146" as used herein may refer to any or all of the capacitors 146A-146C, or to other capacitors 146 not explicitly shown in fig. 1.

Referring to fig. 1, a package assembly 100 includes a substrate 110, according to some embodiments. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 110 may be a wafer, such as a silicon wafer. Typically, the SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulator layer is provided on the substrate, typically a silicon or glass substrate. Other substrates, such as multi-layer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 110 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon-germanium, gallium arsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. In an alternative embodiment, the substrate 110 is based on an insulating core, such as a fiberglass reinforced resin core or an organic core. The insulating core may comprise materials such as: fiberglass resin, bismaleimide-triazine (BT) resin, printed Circuit Board (PCB) material or film, a build-up film such as Ajinomoto build-up film (ABF), other laminates, and the like, or combinations thereof.

According to some embodiments, the device 112 may be formed at or near the surface of the substrate 110. Device 112 may be an integrated circuit device and may include active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.). The transistor may be, for example, a planar Field Effect Transistor (FET), a fin field effect transistor (FinFET), a nanostructure field effect transistor (NSFET, nanoflake FET, etc.), or the like.

According to some embodiments, the package assembly 100 may further include an interlayer dielectric (ILD) 114 and an interconnect structure 116 over the substrate 110. In some cases, ILD 114 may surround and/or cover device 112.ILD 114 may comprise one or more dielectric layers formed of materials such as: silicon nitride, silicon oxide, phosphosilicate glass (PSG), boro-silicate glass (BSG), boron doped phospho-silicate glass (BPSG), undoped Silicate Glass (USG), and the like, or combinations thereof.

In some embodiments, the interconnect structure 116 includes conductive features, such as metallization patterns, redistribution layers, etc., formed in one or more dielectric layers 118. In some cases, one or more of dielectric layers 118 may be an inter-metal dielectric (IMD) layer. Interconnect structure 116 may be electrically connected to device 112 to form a functional circuit. In some embodiments, the functional circuitry formed by interconnect structure 116 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input/output circuitry, image sensor circuitry, and the like, or combinations thereof.

Dielectric layer 118 may include one or more layers of one or more suitable dielectric materials, such as silicon oxide, PSG, BSG, BPSG, USG, low dielectric constant (low-k) materials, fluorosilicate glass (FSG), silicon oxycarbide, carbon Doped Oxide (CDO), flowable oxide, polymer, and the like, or combinations thereof. In some cases, the material of one or more dielectric layers 118 may be similar to the material of ILD 114. Dielectric layer 118 may be deposited using any suitable technique, such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), plasma Enhanced ALD (PEALD), plasma Enhanced CVD (PECVD), flowable CVD (FCVD), spin-on, the like, or combinations thereof. Other materials or formation techniques are possible.

Conductive features of interconnect structure 116 may include, for example, conductive lines 120, vias 122, conductive pads 128, and the like. In some embodiments, conductive pads 128 are formed in the top dielectric layer 118 of the interconnect structure 116. The interconnect structure 116 shown in fig. 1 is an example, and it should be understood that the interconnect structure 116 may include any number of dielectric layers 118, with various conductive features disposed in the dielectric layers 118. In some embodiments, the interconnect structure 116 may be formed as part of a back-end-of-line (BEOL) process or an intermediate-end-of-line (MEOL) process. The conductive features may be formed using suitable techniques such as damascene, dual damascene, or other techniques. In some embodiments, the conductive features may include a liner (not shown) (e.g., diffusion barrier layer, adhesion layer, etc.) as well as a conductive material. The liner may comprise titanium, titanium nitride, tantalum nitride, the like, or combinations thereof. The conductive material may include copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, ruthenium, or the like, or combinations thereof. The material(s) of the conductive feature may be deposited using suitable techniques such as ALD, CVD, PVD, plating, electroless plating, or the like, or combinations thereof. Other materials or formation techniques are possible.

In some embodiments, metal pads 130 are formed on interconnect structure 116 and electrically coupled to interconnect structure 116. Metal pad 130 may be electrically coupled to device 112 through conductive pad 128, wire 120, and via 122 of interconnect structure 116. The metal pads 130 may be, for example, aluminum pads or aluminum-copper pads, although other materials are possible. According to some embodiments, the metal pad 130 is in physical contact with an underlying conductive feature of the interconnect structure 116, and the interconnect structure 116 may include an uppermost conductive feature of the interconnect structure 116. For example, as shown in fig. 1, metal pad 130 has a bottom surface that is in physical and electrical contact with the top surface of conductive pad 128.

As also shown in fig. 1, in some embodiments, a passivation layer 132 may be formed over the interconnect structure 116. In some embodiments, passivation layer 132 is formed on conductive pad 128 and on top dielectric layer 118 of interconnect structure 116. Passivation layer 132 may include one or more layers of dielectric materials such as USG, silicon oxide, silicon nitride, silicon oxynitride, non-porous dielectric materials, low-k dielectric materials, and the like, or combinations thereof. Other materials or combinations of materials are possible. Passivation layer 132 may be formed using one or more suitable techniques. The passivation layer 132 is patterned such that a central portion of the metal pad 130 is exposed. In some embodiments, edge portions of the metal pad 130 may remain covered by the passivation layer 132. In some embodiments, some top surfaces of passivation layer 132 and metal pad 130 are flush.

In some embodiments, a dielectric layer 136 is formed over the metal pad 130 and the passivation layer 132. In some embodiments, the dielectric layer 136 is formed of one or more polymeric materials, such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In some cases, the polymer material of the dielectric layer 136 may be photosensitive. In alternative embodiments, the dielectric layer 136 may be formed of one or more materials, such as silicon oxide, silicon nitride, PSG, BSG, BPSG, and the like, or combinations thereof. The dielectric layer 136 may be formed, for example, by spin coating, lamination, CVD, or the like. Other materials or techniques are possible.

In some embodiments, a post-passivation interconnect (PPI) 138 may be formed over the dielectric layer 136. The PPI 138 may include, for example, a line portion above a top surface of the dielectric layer 136 and/or a via portion extending into the dielectric layer 136. In some embodiments, the PPI 138 may be electrically connected to the metal pad 130. The PPI 138 may be formed of one or more conductive materials, such as copper, copper alloy, titanium, tungsten, aluminum, and the like. Other materials are possible.

In some embodiments, a dielectric layer 142 may be formed over the dielectric layer 136 and the PPI 138. Dielectric layer 142 may be formed from one or more materials similar to those described previously for dielectric layer 136. Dielectric layer 136 and dielectric layer 142 may be formed of the same material(s) or may be formed of different materials.

In some embodiments, the PPI 150 is formed over the dielectric layer 142. The PPI 150 may be electrically connected to the PPI 138 and thus to the device 112. The PPI 150 may include conductive features such as redistribution lines, metal pads, under Bump Metallization (UBM), and the like. According to some embodiments, a dielectric layer 152 may be formed over the PPI 150. The dielectric layer 152 may cover and/or surround the conductive features of the PPI 150, and the dielectric layer 152 may physically contact the top surface of the dielectric layer 142. Dielectric layer 152 may be formed of one or more materials similar to those previously described for dielectric layer 136, or may be formed of another material such as a molding compound, a sealant, or the like. Other materials are possible.

According to some embodiments, a conductive connector 154 is formed on the PPI 150. The conductive connectors 154 may be Ball Grid Array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro-bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or the like. The conductive connector 154 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 154 is formed by initially forming a solder layer by evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 154 includes metal posts (e.g., copper posts) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or combinations thereof, and may be formed by a plating process. In some embodiments, the conductive connector 154 may be surrounded by the dielectric layer 152 or embedded in the dielectric layer 152. The conductive connector 154 may be formed before or after the deposition of the dielectric layer 152. In some embodiments, a separation process (e.g., sawing process, etc.) may be performed to separate the structures into individual package assemblies 100 that each include at least one capacitor 146. In some embodiments, the separate package assembly 100 is a device die or the like. The separation process may be performed before or after the formation of the conductive connectors 154.

According to some embodiments, the package assembly 100 includes one or more capacitors 146. As previously described, capacitor 146 is represented in fig. 1 by capacitors 146A, 146B, and/or 146C. The capacitor 146 may be formed in one or more dielectric layers of the package assembly 100, such as the dielectric layer 118 or the dielectric layers 136/142 of the interconnect structure 116. In this manner, the capacitor 146 may be formed as part of a MEOL process and/or a BEOL process. The capacitor 146A represents a capacitor 146 formed in an upper dielectric layer 118 of the interconnect structure 116 (e.g., the dielectric layer 118 at or near the top of the interconnect structure 116). The capacitor 146A may be formed under the passivation layer 132 as shown in fig. 1. In some embodiments, capacitor 146A is electrically coupled to conductive pad 128. The capacitor 146B represents the capacitor 146 formed in one or more dielectric layers 118 within the interconnect structure 116. For example, the capacitor 146B may be formed at or near the bottom or middle of the interconnect structure 116. In some embodiments, capacitor 146B is electrically coupled to wire 120 or via 122 of interconnect structure 116. Capacitor 146C represents capacitor 146 formed over passivation layer 132 (e.g., in dielectric layer 136 and/or dielectric layer 142). In some embodiments, dielectric layers 136 and/or 142 may be polymer layers, as previously described. In some embodiments, the capacitor 146C is electrically coupled to the PPI 138 and/or the PPI 150.

In some embodiments, the capacitor 146 is electrically coupled to other features of the package assembly through vias or contact plugs that are in physical and electrical contact with the top electrode(s) and bottom electrode(s) of the capacitor 146. In some embodiments, capacitor 146 is a decoupling capacitor in which the top electrode(s) and bottom electrode(s) of capacitor 46 are electrically coupled to power supply lines such as VDD and VSS. In this way, the capacitor 146 may be used to filter or suppress power supply noise and/or may be used to reduce the effects of voltage variations from the power supply. According to an alternative embodiment of the present disclosure, the top electrode(s) and bottom electrode(s) of the capacitor 146 are connected to the signal line, and the capacitor 146 is used to filter or suppress signal line noise. In other embodiments, the capacitor 146 as described herein may be used in other structures or for other purposes. As a non-limiting example, the capacitor 146 may be used in a Dynamic Random Access Memory (DRAM) cell. Other structures or devices having a capacitor 146 as described herein are possible.

Fig. 2-18 illustrate cross-sectional views of intermediate stages in the formation of a capacitor 146 (see fig. 18) according to some embodiments. The processes of fig. 2-18 are shown in the context of forming capacitor 146A similar to fig. 1, but it should be understood that the techniques described herein may be applied to forming capacitor 146B, capacitor 146C, or other capacitors formed in other layers. In this manner, the cross-sectional views of fig. 2-18 may correspond to enlarged views of a portion of the package assembly 100 of fig. 1 (e.g., a portion of the interconnect structure 116). Capacitor 146 shown in fig. 18 includes alternating electrode layers 212 (shown as electrodes 212A, 212B, 212C, and 212D, respectively) and insulator layers 216 (shown as insulators 216A, 216B, and 216C, respectively). As used in this disclosure, the term "electrode 212" may refer to any or all of the electrodes 212A-212D, and the term "insulator 216" may refer to any or all of the insulators 216A-216C. In some cases, electrode 212A may be considered a "bottom electrode" and electrode 212D may be considered a "top electrode". In some cases, insulator 216A may be considered a "bottom insulator" and insulator 216C may be considered a "top insulator". Each insulator 216 is separated from the lower electrode 212 by a bottom barrier layer 214 (shown as bottom barrier layers 214A, 214B, and 214C, respectively) and from the upper electrode 212 by a top barrier layer 218 (shown as top barrier layers 218A, 218B, and 218C, respectively). The capacitor 146 shown in fig. 18 is an example, and other capacitors 146 having different configurations, different layouts, different numbers of various layers (e.g., electrode 212, bottom barrier 214, insulator 216, and/or top barrier 218) or different arrangements of features are possible.

Referring to fig. 2, conductive features 202 in a dielectric layer 204 are shown in accordance with some embodiments. In some embodiments, the conductive features 202 may be similar to conductive features of the interconnect structure 116, such as the conductive lines 120, vias 122, or conductive pads 128. In other embodiments, the conductive feature 202 may be similar to other features, such as the metal pad 130, the PPI 138, the PPI 150, etc. Conductive feature 202 may be formed within dielectric layer 204, and in some embodiments, dielectric layer 204 may be similar to dielectric layer 118 of interconnect structure 116. For example, the dielectric layer 204 may include silicon oxide, silicon nitride, or the like. In other embodiments, dielectric layer 204 may be similar to another dielectric layer, such as dielectric layer 136, dielectric layer 142, and the like. For example, in some embodiments, the dielectric layer 204 may include a polymer. Other materials are possible.

According to some embodiments, an etch stop layer 206 and a dielectric layer 208 are formed over the conductive features 202 and the dielectric layer 204. The etch stop layer 206 is an optional layer and may in some cases comprise one or more layers of dielectric material having a lower etch rate than the underlying dielectric layer 204 and/or the overlying dielectric layer 208. In some embodiments, the etch stop layer 206 may include one or more material layers, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and the like, or combinations thereof. The etch stop layer 206 may be formed using a suitable technique such as CVD, PECVD, LPCVD, PVD, ALD. Other materials or formation techniques are possible. In some embodiments, etching The stop layer 206 may have a thickness of aboutTo about->A thickness T1 in the range, but other thicknesses are possible.

Dielectric layer 208 may be formed from materials similar to those previously described for dielectric layer 204, dielectric layer 118, or dielectric layers 136/142, and may be formed using similar techniques. For example, in some embodiments, the dielectric layer 208 comprises silicon nitride, silicon oxynitride, or the like. Other materials are possible. Dielectric layer 208 may be the same material as underlying dielectric layer 204 or may be a different material. In some embodiments, the dielectric layer 208 may be deposited to a thickness of aboutTo about 10Initial thickness T2 in the range, but other thicknesses are possible.

In fig. 3, an electrode layer 210A is deposited over the dielectric layer 208, according to some embodiments. Electrode layer 210A is then patterned to form electrode 212A (see fig. 5) of capacitor 146 (see fig. 18). Electrode layer 210A may be formed of one or more conductive materials, such as titanium nitride, tantalum nitride, another metal nitride, tungsten, platinum, iridium, ruthenium oxide (e.g., ruO) ₂ ) Etc. Electrode layer 210A may be deposited as a capping layer and may be deposited using a suitable technique such as CVD, PECVD, ALD. In some embodiments, electrode layer 210A may have a thickness of about To about->Thickness T3 in the range, but other thicknesses are possible. In some embodimentsIn prior to depositing electrode layer 210A, a planarization process, such as a Chemical Mechanical Polishing (CMP) process, is used to thin dielectric layer 208.

In fig. 4, an etch mask 211 is formed over electrode layer 210A, according to some embodiments. The etch mask 211 may be formed by depositing a mask layer (not separately shown) over the electrode layer 210A and then patterning the mask layer to form the etch mask 211. The pattern of the etching mask 211 corresponds to the pattern of the electrode 212A (see fig. 5) formed later. The mask layer may be, for example, photoresist, a multi-layer photoresist structure, a hard mask material, or the like. The mask layer may be formed using a suitable technique, for example using spin-on techniques. Other materials or techniques are possible. The mask layer may be patterned using suitable photolithographic techniques to form the etch mask 211.

In fig. 5, electrode layer 210A is etched using etch mask 211 to form electrode 212A, according to some embodiments. Electrode 212A may be the bottom-most electrode of capacitor 146 and may be considered a "bottom electrode" or "first electrode" in some cases. In other embodiments, a single electrode 212A or other number of electrodes 212A may be formed. In some embodiments, the electrode 212A may be separate from or otherwise electrically isolated from the other electrode 212A. Any acceptable etching process may be used to etch electrode layer 210A, such as a wet etching process, a dry etching process, reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. In some embodiments, etching may stop on dielectric layer 208. According to some embodiments, the use includes, for example, tiCl _x 、TaCl _x 、WCl _x Chlorine (Cl) ₂ ) And the like. In some embodiments, the process gases of the dry etching process may include one or more fluorine-containing gases, such as CHF ₃ 、CF ₄ Etc. In some embodiments, the process gas of the dry etching process may include oxygen (O ₂ ). According to some embodiments, the dry etch process includes a process pressure in a range of about 5mTorr to about 10 mTorr. The flow rate of the process gas (es) may beTo be in the range of about 20sccm to about 800 sccm. The power of the power source (used to generate the plasma) may be in the range of about 1000 watts to about 1500 watts. The bias power may be in the range of about 80 watts to about 100 watts. Other process gases or other process parameters are possible. According to an alternative embodiment, the etching is performed by a wet etching process. The wet etching process may include a wet etchant including NH ₄ OH (e.g., ammonia), H ₂ O ₂ 、H ₂ O, etc., or a combination thereof. Other wet etchants are possible. After patterning the electrode layer 210A to form the electrode 212A, an acceptable process (e.g., an ashing process, etc.) may be used to remove the etch mask 211.

In fig. 6, a bottom barrier layer 214A is deposited over electrode 212A and dielectric layer 208, according to some embodiments. A bottom barrier layer 214 (e.g., bottom barrier layer 214A) may be formed between the electrode 212 (e.g., electrode 212A) and the upper insulator 216 (e.g., insulator 216A, see fig. 7) to block or reduce diffusion of oxygen from the upper insulator 216 into the electrode 212. In this way, in some cases, the bottom barrier 214 may be considered a "diffusion barrier", "oxygen barrier", or the like. In some cases, reducing oxygen diffusion into the electrode 212 by forming the bottom barrier 214 as described herein may reduce leakage in the capacitor 146 and may improve reliability, improve lifetime, and/or improve uniformity of the capacitor 146.

In some embodiments, the bottom barrier 214A is formed of a material such as: titanium oxide (e.g. TiO) ₂ ) Titanium oxynitride (e.g., tiON), aluminum oxide (e.g., al ₂ O ₃ ) Another metal oxide, or the like, combinations thereof, or multilayers thereof. In some embodiments, the bottom barrier layer 214A is conformally deposited using a suitable technique such as ALD, PEALD, thermal ALD, and the like. In other embodiments, the bottom barrier layer 214A is formed using an oxidation process, and example embodiments are described below with respect to fig. 19-25. In some embodiments where the bottom barrier layer 214A is titanium oxide deposited using a PEALD process, the precursor may include tetra (dimethylamino) titanium (TDMAT) and an oxygen plasma. The PEALD process may include a temperature in the range of about 160 ℃ to about 300 °cIs not limited, and the process temperature of the same is not limited. In some embodiments where the bottom barrier layer 214A is titanium oxide deposited using a thermal ALD process, the precursors may include TiCl4 and H ₂ O. The thermal ALD process may include a process temperature in the range of about 150 ℃ to about 300 ℃. These are examples and other materials, precursors, process parameters, or deposition techniques are possible. In some embodiments, the bottom barrier 214A may have a thickness of aboutTo about->Thickness T4 in the range, but other thicknesses are possible.

Fig. 7 illustrates the formation of an insulator 216A over the bottom barrier layer 214A, according to some embodiments. Insulator 216A may comprise one or more materials having a high dielectric constant (e.g., high k) to achieve a larger capacitance value for the resulting capacitor 146. For example, in some embodiments, insulator 216A may include hafnium oxide (e.g., hfO ₂ ) Zirconia (e.g. ZrO ₂ 、ZrO ₃ Etc.), hafnium zirconium oxide (e.g., hfZro), aluminum oxide (e.g., al ₂ O ₃ ) Etc., combinations thereof or multilayers thereof. The insulator 216A may be deposited as a conformal layer using a suitable technique such as ALD or the like. In some embodiments, zrCl4 may be used as the zirconium supply precursor, hfCl4 as the hafnium supply precursor, trimethylaluminum (TMA) as the aluminum supply precursor, and/or H ₂ O (e.g., water vapor or steam) acts as an oxygen supply precursor to deposit insulator 216A. In some embodiments, insulator 216A may be deposited using a process pressure in the range of about 0.1 torr to about 100 torr and a process temperature in the range of about 220 ℃ to about 330 ℃. Other materials, precursors, or process parameters are possible. In some embodiments, insulator 216A may have a thickness of aboutTo about->RangeInner thickness T5, but other thicknesses are possible.

In fig. 8, a top barrier layer 218A is deposited over insulator 216A, according to some embodiments. Fig. 8 also shows an enlarged view 147 of a portion of the structure. A top barrier layer 218 (e.g., top barrier layer 218A) may be formed between the insulator 216 (e.g., insulator 216A) and the upper electrode 212 (e.g., electrode 212B, see fig. 11) to block or reduce diffusion of oxygen from the insulator 216 into the upper electrode 212. Similar to the bottom barrier layer 214, the use of the top barrier layer 218 as described herein may reduce leakage in the capacitor 146 and may improve reliability, improve lifetime, and/or improve uniformity of the capacitor 146. In addition, the use of both the bottom barrier 214 and the top barrier 218 as described herein may further improve the reliability and lifetime of the capacitor 146, as described in more detail below.

In some embodiments, the top barrier layer 218A is formed of one or more materials, such as titanium oxide (e.g., tiO ₂ ) Titanium oxynitride (e.g., tiON), aluminum oxide (e.g., al ₂ O ₃ ) Zirconia (e.g. ZrO ₂ ) Another metal oxide, or the like, combinations thereof, or multilayers thereof. In some embodiments, the top barrier layer 218A is conformally deposited using a suitable technique such as ALD, PEALD, thermal ALD, and the like. In some embodiments, the top barrier layer 218 comprises titanium oxide deposited using techniques similar to those previously described for the bottom barrier layer 214A. The top barrier layer 218A may be a similar or different material than the bottom barrier layer 214A. Other materials are possible. In some embodiments, the top barrier layer 218A may have a thickness of aboutTo aboutThickness T6 in the range, but other thicknesses are possible. The thickness T6 of the top barrier layer 218A may be less than, about the same as, or greater than the thickness T4 of the bottom barrier layer 214A.

In fig. 9, an electrode layer 210B is deposited over the top barrier layer 218A, according to some embodiments. Electrode layer 210B is then patterned to form electrode 212B (see fig. 11) of capacitor 146 (see fig. 18). Electrode layer 210B may be similar to electrode layer 210A described previously with respect to fig. 3, and may be formed using similar techniques. The thickness of the electrode layer 210B may be less than, about equal to, or greater than the thickness T3 of the electrode layer 210A (see fig. 3).

In fig. 10, an etch mask 213 is formed over the electrode layer 210B and patterned, according to some embodiments. The etch mask 213 may be similar to the etch mask 211 described previously with respect to fig. 4, and may be patterned using similar techniques. For example, a mask layer may be deposited over electrode layer 210B and patterned using suitable photolithographic techniques to form etch mask 213. The pattern of the etching mask 213 corresponds to the pattern of the electrode 212B (see fig. 11) formed later.

In fig. 11, electrode layer 210B is etched using etch mask 213 to form electrode 212B, according to some embodiments. Fig. 11 also shows an enlarged view 147 of a portion of the structure similar to fig. 8. Electrode 212B is in the opposite direction of insulator 216A from electrode 212A, and in some cases electrode 212B may be considered a "top electrode" or a "second electrode. In other embodiments, more than one electrode 212B may be formed. Electrode layer 210B may be etched using any acceptable etching process, such as those previously described for etching electrode layer 210A. The etching may be anisotropic. In some embodiments, the etch may stop on top barrier layer 218A.

In some cases, the barrier layer of the capacitor may be a material capable of capturing electrons, such as titanium oxide. In these cases, the barrier layer may have an accumulation of trapped electrons at or near the side of the barrier layer closest to the positive bias electrode (e.g., the other electrode is less positively biased, grounded, or negatively biased). For example, the collection of trapped electrons within the barrier layer may be near the adjacent electrode if the adjacent electrode is positively biased, or near the insulator if the electrode opposite the insulator is positively biased.

For capacitors with a single blocking layer, the collection of trapped electrons near the insulator may create a stronger electric field within the insulator than when the collection of trapped electrons is far from the insulator (e.g., near an adjacent electrode). This effect is due, at least in part, to the electric field being concentrated in the insulator when the trapped electrons are near the insulator, and the electric field being distributed across both the insulator and the barrier layer when the trapped electrons are near the adjacent electrode.

As an illustrative example, fig. 27A-27B show a portion of a capacitor 400 having a first electrode 412A, a barrier layer 414 having trapped electrons 415, an insulator 416, and a second electrode 412B. Fig. 27A shows capacitor 400 in a "forward bias" state, wherein first electrode 412A is biased more negatively and second electrode 412B is biased more positively. As shown in fig. 27A, this bias causes trapped electrons 415 to accumulate near insulator 416. The electric field EA between the electrodes 412A-412B extends from the second electrode 412B into the insulator 416 and terminates (or partially terminates) at the trapping electron 415. Thus, most or all of the electric field EA is within the insulator 416.

Fig. 27B shows the capacitor 400 in a "reverse bias" state, wherein the first electrode 412A is more positively biased and the second electrode 412B is more negatively biased. As shown in fig. 27B, this bias causes the trapped electrons 415 to accumulate near the second electrode 412A. The electric field EB between the electrodes 412A-412B extends from the trapped electrons 415 (and/or the first electrode 412A) into the insulator 416 and terminates at the second electrode 412B. Thus, all of the electric field EB is within both the barrier layer 414 and the insulator 416. In this way, the electric field EB spreads over a larger distance than the electric field EA. Thus, for the same voltage difference between the electrodes 412A-412B, the insulator 416 of the reverse bias capacitor 400 of FIG. 27B experiences a smaller electric field than the insulator 416 of the forward bias capacitor 400 of FIG. 27A.

In this way, for a capacitor with a single blocking layer, biasing the capacitor in one direction (e.g., "forward biasing") may create a higher electric field in the insulator than biasing the capacitor in the opposite direction (e.g., "reverse biasing"). Insulators that experience a larger electric field during operation may have a greater defect generation rate, increased leakage opportunities, smaller breakdown voltages, and/or reduced lifetime (e.g., time-dependent dielectric breakdown (TDDB) lifetime). Such increased electric fields in the insulator due to electron trapping in the barrier layer can result in a strong dependence of the capacitor life on the bias polarity. For example, in some cases, the lifetime of a reverse biased capacitor may be 10000 times longer than the lifetime of a similar capacitor that is forward biased.

The use of a symmetrical barrier/insulator/barrier structure as described herein may reduce the impact of electron trapping in the barrier. As an illustrative example, fig. 28A-28B show an enlarged view 147 of capacitor 146, similar to enlarged view 147 shown in fig. 11. Fig. 28A shows capacitor 146 in a "forward bias" state, where electrode 212A is biased more negatively and electrode 212B is biased more positively. As shown in fig. 28A, this bias causes trapped electrons 215 in bottom barrier 214A to collect near insulator 216A, while trapped electrons 219 in top barrier 218A collect near electrode 212B. The electric field EA between the electrodes 212A-212B extends from the trapped electrons 219 (and/or the electrode 212B) into the insulator 216 and terminates (or partially terminates) at the trapped electrons 215. Thus, most or all of the electric field EA is within both the top barrier 218A and the insulator 216A.

Fig. 28B shows capacitor 146 in a "reverse bias" state, wherein electrode 212A is more positively biased and electrode 212B is more negatively biased. As shown in fig. 28B, this bias causes trapped electrons 215 in bottom barrier 214A to collect near electrode 212A, while trapped electrons 219 in top barrier 218A collect near insulator 216A. The electric field EB between the electrodes 212A-212B extends from the trapped electrons 215 (and/or the electrode 212A) into the insulator 216 and terminates (or partially terminates) at the trapped electrons 219. Thus, most or all of the electric field EB is within both the bottom barrier 214A and the insulator 216A.

28A-28B, for either bias polarity, an electric field (e.g., EA or EB) extends through insulator 216A and into one of barrier layers 214A/218A. This allows the presence of one of the barrier layers 214A/218A to compensate for the electron trapping effect of the other, and in some cases may allow the distance of the electric field to be the same or similar for either bias polarity. In this manner, by sandwiching the insulator 216 between the two barrier layers 214A/218A, the electric field across the insulator 216A does not increase significantly for a particular bias polarity. In other words, forming the top barrier layer 218A in addition to the bottom barrier layer 214A may reduce the electric field across the insulator 216A when the capacitor 146 is forward biased. By reducing the electric field across the insulator 216 for both bias polarities, the capacitor 146 may have a smaller defect generation rate, a reduced leakage opportunity, a greater breakdown voltage, and/or an increased lifetime (e.g., TDDB lifetime or Time To Failure (TTF) lifetime). In some cases, the lifetime of the capacitor may be increased by about 100-fold or more using the techniques described herein.

In addition, the effect of electron trapping on the electric field strength is reduced for either bias polarity, which may result in a more uniform capacitance of the capacitor 146 under different voltage biases of either polarity. In some embodiments, the addition of a second barrier layer as described herein may not significantly affect the capacitance of the capacitor at either bias polarity. For example, in some cases, the addition of the second barrier layer may reduce the capacitance of the capacitor by less than about 10%.

Turning now to fig. 12, a bottom barrier 214B, an insulator 216B, and a top barrier 218B are formed over the electrode 212B, according to some embodiments. Layers 214B/216B/218B may also be formed over the exposed portions of top barrier layer 218A, as shown in fig. 12. The bottom barrier 214B, insulator 216B, and/or top barrier 218B may be formed using materials or techniques similar to those previously described for bottom barrier 214A, insulator 216A, and top barrier 218A, respectively. For example, in some embodiments, the layers 214B/216B/218B may be blanket layers deposited using ALD, PEALD, thermal ALD, or the like. Other materials or techniques are possible. In some embodiments, the thickness of bottom barrier 214B, insulator 216B, and/or top barrier 218B is similar to the thickness of bottom barrier 214A, insulator 216A, and/or top barrier 218A, respectively. Other thicknesses are possible. In other embodiments, no additional bottom barrier, insulator, top barrier, or electrode is formed over electrode 212B for the formation of capacitor 146.

Fig. 13 illustrates the formation of electrode 212C, bottom barrier 214C, insulator 216C, top barrier 218C, and electrode 212D, in accordance with some embodiments. Electrodes 212C-212D and layers 214C/216C/218C may be formed using materials or techniques similar to those previously described for electrodes 212A and layers 214A/216A/218A, respectively. For example, electrode 212C may be formed by depositing an electrode layer over top barrier layer 218B and then patterning the electrode layer. In some cases, electrode 212C may be considered a "third electrode". Then, a bottom barrier layer 214C, an insulator 216C, and a top barrier layer 218C may be deposited over the electrode 212C and over the exposed portions of the top barrier layer 218B. Electrode 212D may be formed by depositing an electrode layer over top barrier layer 218C and then patterning the electrode layer. Electrode 212D may be the topmost electrode of capacitor 146 and may be considered the "top electrode" or "fourth electrode" in some cases. In other embodiments, a single electrode 212D or other number of electrodes 212D may be formed. In some embodiments, the electrode 212D may be separate from or otherwise electrically isolated from the other electrode 212D. In other embodiments, one or more additional bottom barrier, insulator, top barrier, and/or electrode may be formed over electrode 212D for the formation of capacitor 146.

In fig. 14, a dielectric layer 220 is deposited over electrode 212D and top barrier layer 218C, according to some embodiments. Dielectric layer 220 may be formed from material(s) similar to that previously described for dielectric layer 204, dielectric layer 118, or dielectric layer 136/142, and may be formed using similar techniques. For example, in some embodiments, dielectric layer 220 comprises silicon nitride, silicon oxynitride, a polymer, or the like. Other materials are possible. Dielectric layer 220 may be the same material as dielectric layer 208 or may be a different material. In some embodiments, a planarization process, such as a CMP process or a polishing process, is performed on the dielectric layer 220. In some embodiments, dielectric layer 220 has a thickness of aboutTo about->A thickness in the range, but other thicknesses are possible.

Fig. 15, 16, and 17 illustrate cross-sectional views of intermediate steps in the formation of contact plugs 226A-226B and conductive lines 228A-228B, according to some embodiments. In fig. 15, according to some embodiments, contact openings 222 are formed to expose surfaces of electrodes 212A-212D and surfaces of conductive features 202. In other embodiments, the openings 222 may expose only the surfaces of the electrodes 212A-212D and not the surfaces of the conductive features 202. For example, the opening 222 may be formed by performing one or more etching processes using the etching mask 221. In some embodiments, etch mask 221 may be formed using techniques similar to those described previously for etch mask 211 (see fig. 4) or etch mask 213 (see fig. 10). For example, the etch mask 221 may be formed by forming a photoresist structure over the dielectric layer 220, and then patterning the photoresist structure using a suitable photolithographic technique. According to some embodiments, the etch mask 221 includes a photoresist or photoresist structure, which may include an anti-reflective coating. The etching mask 221 may have a single layer structure, a double layer structure, a triple layer structure, or the like.

One or more etching processes may then be performed using the etch mask 221 to form openings 222 extending through the dielectric layer 220, the electrodes 212A-212D, the top barrier layers 218A-218C, the insulators 216A-216C, and the bottom barrier layers 214A-214C. In some embodiments, the opening 222 may also extend through the dielectric layer 208 and the etch stop layer 206. The one or more etching processes may include a wet etching process and/or a dry etching process. One or more of these etching processes may be anisotropic. In some cases, different materials may be etched using different etching processes. For example, electrodes 212A-212D may be etched using an etch process similar to the etch process described previously for etching electrode layer 210A. In some embodiments, a first dry etch process may be performed that stops on the etch stop layer 206, and then a second dry etch process may be performed to etch and expose the conductive feature 202 to the etch stop layer 206. This is an example and other techniques or etching processes may be used to form the opening 222 in other embodiments. After etching the opening 222, the etch mask 221 may be removed using a suitable process (e.g., an ashing process or an etching process).

In fig. 16, a seed layer 224 and a plating mask 225 are formed, according to some embodiments. A seed layer 224 is formed over dielectric layer 220 and in opening 222. The seed layer 224 may be in physical and electrical contact with the electrodes 212A-212D and/or the surface of the conductive feature 202. In some embodiments, seed layer 224 is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer 224 includes a titanium layer and a copper layer over the titanium layer, although other materials are possible. The seed layer 224 may be formed using, for example, PVD, CVD, metal Organic Chemical Vapor Deposition (MOCVD), and the like. A plating mask 225 is then formed over the seed layer 224 and patterned. Plating mask 225 may be similar to one or more of the etching masks 211, 213, or 221 previously described. For example, in some embodiments, the plating mask 225 may be a photoresist. The plating mask 225 may be patterned using suitable photolithographic techniques. In some embodiments, the pattern of plating mask 225 may expose seed layer 224 in and around opening 222.

In fig. 17, conductive material is deposited in openings 222 to form contact plugs 226A-226B and conductive lines 228A-228B, according to some embodiments. A conductive material may be formed on the exposed portions of seed layer 224 in opening 222. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, nickel, tungsten, aluminum, alloys thereof, and the like. The combination of the conductive material and the underlying portions of seed layer 224 form contact plugs 226A-226B and conductive lines 228A-228B. The portion of the conductive material and seed layer 224 below the top surface of the dielectric layer 220 may be considered a contact plug 226B, while the portion of the conductive material and seed layer 224 above the top surface of the dielectric layer 220 or along the top surface of the dielectric layer 220 is considered a conductive line 228A-228B. In some embodiments, contact plug 226A and wire 228A may be part of a continuous conductive feature, while contact plug 226B and wire 228B may be part of another continuous conductive feature. In some embodiments, the wires 228A-228B may be similar to conductive features of the interconnect structure 116, such as the wire 120, the via 122, or the conductive pad 128. In other embodiments, the conductive lines 228A-228B may be similar to other features, such as the metal pad 130, the PPI 138, the PPI 150, and the like.

The contact plugs 226A-226B may physically and electrically contact the conductive feature 202, and in some cases the contact plugs 226A-226B may be considered vias. The contact plugs 226A-226B are also in physical and electrical contact with the electrodes 212A-212D. For example, contact plug 226B contacts electrode 212A, electrode 212B, and electrode 212D, while contact plug 226A contacts electrode 212A, electrode 212C, and electrode 212D. Thus, a capacitor 146 is formed that includes a first set of electrodes 212A, 212B, and 212D that collectively function as first capacitor electrodes and a second set of electrodes 212A, 212C, and 212D that function as second capacitor electrodes. In some cases, a majority of the capacitance of the capacitor 146 is provided by the capacitive region 149, with the first set of electrodes interdigitated (e.g., alternating) with the second set of electrodes within the capacitive region 149. In this manner, the capacitive region 149 may include a stack of electrodes 212, wherein each electrode 212 is separated from each adjacent electrode 212 by a bottom barrier 214, an insulator 216, and a top barrier 218, respectively.

In fig. 18, according to some embodiments, the plating mask 225 is removed and an optional passivation layer 230 is formed. Portions of the plating mask 225 and underlying seed layer 224 may be removed using, for example, an ashing process and/or an etching process. According to some embodiments, passivation layer 230 may then be deposited over dielectric layer 220 and conductive lines 228A-228B. Passivation layer 230 may be formed from material(s) similar to that previously described for dielectric layer 220, dielectric layer 204, dielectric layer 118, or dielectric layer 136/142, and may be formed using similar techniques. For example, in some embodiments, the passivation layer 230 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, polymers, and the like, or combinations thereof. Other materials are possible. Passivation layer 230 may be an alloy The dielectric layer 220 may be the same material or may be a different material. In some embodiments, the passivation layer 230 has a thickness of aboutTo about-> A thickness in the range, but other thicknesses are possible. In this way, the capacitor 146 may be formed, but the capacitor 146 may have a different configuration or may be formed using other manufacturing steps in other embodiments.

Fig. 19-25 illustrate cross-sectional views of intermediate steps in the formation of a capacitor 346 (see fig. 25) according to some embodiments. Capacitor 346 is similar to capacitor 146 described with respect to fig. 1-18, except that the bottom barrier 314 of capacitor 346 is formed using an oxidation process rather than a deposition process. For example, capacitor 346 utilizes both bottom barrier 314 and top barrier 218 to achieve benefits such as those previously described for capacitor 146. Capacitor 346 may be used in a similar manner to the embodiments described herein for capacitor 146. For example, the capacitor 346 may be used as the capacitor 146A, 146B, or 146C shown in fig. 1. Capacitor 346 may be formed using some materials or techniques similar to those previously described for capacitor 146, and thus some details may not be repeated.

In fig. 19, an oxidation process is performed on electrode 212A to form bottom barrier 314A, according to some embodiments. The electrode 212A shown in fig. 19 may be similar to the electrode 212A described previously with respect to fig. 5, and may be formed using similar techniques. For example, the electrode 212A shown in fig. 19 may be formed of titanium nitride, but other materials are possible. Thus, the structure shown in fig. 19 can follow the structure shown in fig. 5. In other embodiments, a single electrode 212A or other number of electrodes 212A may be formed. In some embodiments, the electrode 212A may be separate from or otherwise electrically isolated from the other electrode 212A.

In some embodiments, the oxidation process oxidizes a surface portion of electrode 212A, forming a bottom barrier layer 314A that includes an oxide of the material of electrode 212A. As an example, for embodiments in which electrode 212A is titanium nitride, the oxidation process converts a surface portion of the titanium nitride into a titanium oxynitride (e.g., tiON) layer. In this manner, the titanium oxynitride layer forms a bottom barrier layer 314A, the bottom barrier layer 314A covering the electrode 212A. In some embodiments, the oxidation process may expose other surfaces, such as the surface of dielectric layer 208. The number of bottom barrier layers 314A formed may depend on the number of electrodes 212A present, and in other embodiments, another number of bottom barrier layers 314A is possible.

In some embodiments, an oxygen-containing process gas (e.g., oxygen (O) ₂ ) Steam or vapor (H) ₂ O), the like, or a combination thereof) performs the oxidation process. Other process gases are possible. The oxidation process may be performed at a temperature in the range of about 250 ℃ to about 400 ℃. The oxidation process may be performed for a duration of about 5 seconds to about 60 seconds. Other process parameters are possible. According to some embodiments, the bottom barrier layer 314A formed by an oxidation process has a thickness of aboutTo about->A thickness in the range, but other thicknesses are possible.

In fig. 20, an insulator 216A is deposited over the bottom barrier layer 314A and the dielectric layer 208, according to some embodiments. The insulator 216A may be similar to the insulator 216A described previously with respect to fig. 7 and may be formed using similar techniques. As shown in fig. 20, in some embodiments, portions of insulator 216A may be deposited on exposed surfaces of dielectric layer 208.

In fig. 21, a top barrier layer 218A is deposited over insulator 216A, according to some embodiments. The top barrier layer 218A may be similar to the top barrier layer 218A described previously with respect to fig. 8 and may be formed using similar techniques. For example, the top barrier layer 218A may be formed using ALD, PEALD, thermal ALD, or the like.

In fig. 22, an electrode 212B is formed over the top barrier layer 218A, according to some embodiments. Fig. 22 also shows an enlarged view 347 of a portion of the structure. The electrode 212B may be similar to the electrode 212B described previously with respect to fig. 11, and may be formed using similar techniques. For example, an electrode layer (e.g., similar to electrode layer 210B) may be deposited over the structure and patterned using an etch mask (e.g., similar to etch mask 213).

In fig. 23, a bottom barrier layer 314B is formed using an oxidation process, according to some embodiments. Similar to the formation of bottom barrier layer 314A, bottom barrier layer 314B may be formed by performing an oxidation process to convert a surface portion of electrode 212B to an oxide material. The oxidation process may be similar to the oxidation process previously described for forming the bottom barrier layer 314A. Thus, in some embodiments, bottom barrier 314B may be similar to bottom barrier 314A. As shown in fig. 23, in some embodiments, portions of the top barrier layer 218A may remain exposed after performing the oxidation process.

Fig. 24 illustrates the formation of electrode 212C, bottom barrier 314C, insulator 216C, top barrier 218C, and electrode 212D, in accordance with some embodiments. The electrodes 212C-212D may be formed using materials or techniques similar to those described previously for the electrodes 212A-212B. The bottom barrier layer 314C may be formed by performing an oxidation process on the electrode 212C, similar to the formation of the bottom barrier layers 314A-314B. The insulators 216B-216C can be formed using materials or techniques similar to those previously described for the insulator 216A, and the top barrier layer 218C can be formed using materials or techniques similar to those previously described for the top barrier layers 218A-218B. In some embodiments, the materials or techniques used to form the features may be different than those previously described for the respective features. For example, in other embodiments, the capacitor may have both bottom barrier layer(s) 214 formed using deposition (e.g., ALD, etc.) and bottom barrier layer(s) 314 formed using an oxidation process.

Fig. 25 illustrates the formation of contact plugs 226A-226B and conductive lines 228A-228B according to some embodiments. The contact plugs 226A-226B and the conductive lines 228A-228B may be similar to the corresponding features shown in fig. 18 and may be formed using materials or techniques similar to those previously described with respect to fig. 14-18. For example, dielectric layer 220 may be formed over the structure, openings may be etched (e.g., similar to openings 222), and conductive material may be deposited (e.g., plated) to form contact plugs 226A-226B and conductive lines 228A-228B. In some embodiments, the passivation layer 230 may be formed. In this way, the capacitor 346 may be formed, but in other embodiments, the capacitor 346 may have a different configuration or may be formed using other manufacturing steps.

Fig. 26 illustrates a plan view of a portion of a device 500 including a plurality of capacitors 146, according to some embodiments. The device 500 may be, for example, a semiconductor die, chip, package, interposer, another structure or device, or the like. The plan view shown in fig. 26 is an illustrative example, and other configurations, layouts, or arrangements are possible. Fig. 26 shows conductive features 202A-202C under a plurality of contact plugs 226 in electrical contact. The conductive features 202A-202C may be, for example, wires or the like. The sets of contact plugs 226 are capacitively coupled through the capacitor 146. For example, FIG. 26 shows a capacitor 146 coupled to three contact plugs 226 connected to each of the conductive features 202A-202C, respectively. In other embodiments, the capacitor 146 may couple a set of two contact plugs 226 or a set of more than three contact plugs 226. The conductive features 202A-202C may correspond to similar or different voltages. For example, in some embodiments, conductive features 202A and 202C may be coupled to one supply voltage and conductive feature 202B may be coupled to a second supply voltage. Other configurations are possible.

As an example, fig. 26 shows a capacitive region 149 of each capacitor 146. The capacitive region 149 may completely or partially surround (e.g., encircle) one or more contact plugs 226, as shown in fig. 26. In other embodiments, the capacitive region 149 may exist only between adjacent contact plugs 226. Other arrangements of the capacitive areas 149 are possible. The capacitive region 149 may be offset from each contact plug 226, for example, by a distance D1 in the range of about 0.2 μm to about 1.2 μm, although other distances are possible. In some embodiments, the capacitive region 149 between adjacent contact plugs 226 may have a width D2 in the range of about 0.2 μm to about 2 μm, although other widths are possible. In this manner, multiple capacitors 146 may be utilized, for example, to reduce noise or voltage fluctuations in the device 500.

Embodiments of the present disclosure have some advantageous features. By forming barrier layers on both sides of the insulator layer of the capacitor, the electric field across the insulator can be reduced for both forward and reverse bias. By reducing the electric field across the insulator for both bias polarities, the capacitor may have improved reliability and increased lifetime. Forming a "symmetric" capacitor structure in this manner may also achieve a more uniform capacitance across the two bias polarities. The techniques described herein may allow for improved capacitor performance without significantly reducing the capacitance of the capacitor. The capacitor described herein is thus suitable for use as, for example, a decoupling capacitor.

According to some embodiments of the present disclosure, a method comprises: forming a first capacitor electrode; forming a first oxygen barrier layer on the first capacitor electrode; forming a capacitor insulator layer on the first oxygen barrier layer; forming a second oxygen barrier layer on the capacitor insulator layer; forming a second capacitor electrode on the second oxygen barrier layer; and forming a first contact plug electrically coupled to the first capacitor electrode and a second contact plug electrically coupled to the second capacitor electrode. In one embodiment, forming the first contact plug includes: etching an opening exposing sidewalls of the first capacitor electrode, the first oxygen barrier layer, the capacitor insulator layer and the second oxygen barrier layer; and depositing a conductive material in the opening, wherein the conductive material physically contacts exposed sidewalls of the first capacitor electrode, the first oxygen barrier layer, the capacitor insulator layer, and the second oxygen barrier layer. In one embodiment, forming the first oxygen barrier layer includes performing an oxidation process on the first capacitor electrode. In one embodiment, forming the first oxygen barrier layer includes performing an Atomic Layer Deposition (ALD) process. In one embodiment, the first oxygen barrier layer is a layer with the second oxygen barrier layerOxygen layers are different materials. In one embodiment, the first oxygen barrier layer comprises titanium oxynitride. In one embodiment, forming the capacitor insulator layer includes depositing a hafnium zirconium oxide layer using an ALD process. In one embodiment, the thickness of the second oxygen barrier layer is To->

According to some embodiments of the present disclosure, a method comprises: depositing a first conductive material over the dielectric layer; patterning the first conductive material to form a first electrode; depositing a first barrier layer as a capping layer over the first electrode, wherein the barrier layer comprises a first metal oxide; depositing a first insulator layer as a capping layer over the first barrier layer, wherein the first insulator layer comprises a second metal oxide different from the first metal oxide; depositing a second barrier layer as a capping layer over the first insulator layer, wherein the second barrier layer comprises a first metal oxide; depositing a second conductive material over the second barrier layer; and patterning the second conductive material to form a second electrode. In one embodiment, the method includes forming a first contact plug penetrating the first electrode and a second contact plug penetrating the second electrode. In one embodiment, the first metal oxide comprises titanium oxide. In one embodiment, the method includes depositing a third barrier layer over the second electrode; depositing a second insulator layer over the third barrier layer; depositing a fourth barrier layer over the second insulator layer; depositing a third conductive material on the fourth barrier layer; and patterning the third conductive material to form a third electrode. In one embodiment, the first insulator layer physically contacts the top surface of the dielectric layer. In one embodiment, the first conductive material and the second conductive material are titanium nitride. In one embodiment, the thickness of the first barrier layer is different from the thickness of the second barrier layer.

According to some embodiments of the present disclosure, a device includes: a first via on the first conductive feature; a second via on the second conductive feature; and a capacitive stack comprising: an electrode layer comprising first electrode layers and second electrode layers, wherein the first electrode layers are alternately arranged with the second electrode layers, wherein the first electrode layers are electrically coupled to the first via and the second electrode layers are electrically coupled to the second via; insulator layers, wherein each insulator layer is between a respective first electrode layer and a respective second electrode layer; first barrier layers, wherein each first barrier layer is between a bottom surface of a respective insulator layer and a top surface of a respective electrode layer; and second barrier layers, wherein each second barrier layer is between a top surface of a respective insulator layer and a bottom surface of a respective electrode layer. In one embodiment, each first barrier layer physically contacts a respective insulator layer and a respective electrode layer. In one embodiment, the first barrier layer is a different material than the second barrier layer. In one embodiment, at least one second barrier layer physically contacts two respective insulator layers. In one embodiment, the first via physically contacts the first electrode layer, the insulator layer, and the second barrier layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor device, comprising:

forming a first capacitor electrode;

forming a first oxygen barrier layer on the first capacitor electrode;

forming a capacitor insulator layer on the first oxygen barrier layer;

forming a second oxygen barrier layer on the capacitor insulator layer;

forming a second capacitor electrode on the second oxygen barrier layer; and

a first contact plug electrically coupled to the first capacitor electrode and a second contact plug electrically coupled to the second capacitor electrode are formed.

2. The method of claim 1, wherein forming the first contact plug comprises:

Etching an opening exposing sidewalls of the first capacitor electrode, the first oxygen barrier layer, the capacitor insulator layer, and the second oxygen barrier layer; and

a conductive material is deposited in the opening, wherein the conductive material physically contacts exposed sidewalls of the first capacitor electrode, the first oxygen barrier layer, the capacitor insulator layer, and the second oxygen barrier layer.

3. The method of claim 1, wherein forming the first oxygen barrier layer comprises performing an oxidation process on the first capacitor electrode.

4. The method of claim 1, wherein forming the first oxygen barrier layer comprises performing an Atomic Layer Deposition (ALD) process.

5. The method of claim 1, wherein the first oxygen barrier layer is a different material than the second oxygen barrier layer.

6. The method of claim 1, wherein the first oxygen barrier layer comprises titanium oxynitride.

7. The method of claim 1, wherein forming the capacitor insulator layer comprises: a hafnium zirconium oxide layer is deposited using an ALD process.

8. The method of claim 1, wherein the thickness of the second oxygen barrier layer is atTo->Within a range of (2).

9. A method of forming a semiconductor device, comprising:

depositing a first conductive material over the dielectric layer;

patterning the first conductive material to form a first electrode;

depositing a first barrier layer as a capping layer over the first electrode, wherein the barrier layer comprises a first metal oxide;

depositing a first insulator layer as a capping layer over the first barrier layer, wherein the first insulator layer comprises a second metal oxide, the second metal oxide being different from the first metal oxide;

depositing a second barrier layer as a capping layer over the first insulator layer, wherein the second barrier layer comprises the first metal oxide;

depositing a second conductive material over the second barrier layer; and

the second conductive material is patterned to form a second electrode.

10. A device, comprising:

a first via on the first conductive feature;

a second via on the second conductive feature; and

a capacitive stack comprising:

a plurality of electrode layers including a first electrode layer and a second electrode layer, wherein the first electrode layer is alternately arranged with the second electrode layer, wherein the first electrode layer is electrically coupled to the first via and the second electrode layer is electrically coupled to the second via;

A plurality of insulator layers, wherein each insulator layer is between a respective first electrode layer and a respective second electrode layer of the plurality of electrode layers;

a plurality of first barrier layers, wherein each first barrier layer of the plurality of first barrier layers is between a bottom surface of a respective insulator layer and a top surface of a respective electrode layer; and

a plurality of second barrier layers, wherein each of the plurality of second barrier layers is between a top surface of a respective insulator layer and a bottom surface of a respective electrode layer.