CN116648133A - Semiconductor device, metal-insulator-metal capacitor structure and forming method - Google Patents
Semiconductor device, metal-insulator-metal capacitor structure and forming method Download PDFInfo
- Publication number
- CN116648133A CN116648133A CN202310347054.4A CN202310347054A CN116648133A CN 116648133 A CN116648133 A CN 116648133A CN 202310347054 A CN202310347054 A CN 202310347054A CN 116648133 A CN116648133 A CN 116648133A
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- insulator
- conductor
- conductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 213
- 239000002184 metal Substances 0.000 title claims abstract description 213
- 239000003990 capacitor Substances 0.000 title claims abstract description 113
- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000004020 conductor Substances 0.000 claims description 289
- 239000012212 insulator Substances 0.000 claims description 187
- 238000000151 deposition Methods 0.000 claims description 28
- 238000000059 patterning Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 21
- 239000010410 layer Substances 0.000 description 744
- 230000008569 process Effects 0.000 description 38
- 239000000463 material Substances 0.000 description 36
- 238000002161 passivation Methods 0.000 description 30
- 238000005530 etching Methods 0.000 description 24
- 230000004888 barrier function Effects 0.000 description 19
- 239000004642 Polyimide Substances 0.000 description 15
- 238000000231 atomic layer deposition Methods 0.000 description 15
- 238000005137 deposition process Methods 0.000 description 15
- 238000005240 physical vapour deposition Methods 0.000 description 15
- 229920001721 polyimide Polymers 0.000 description 15
- 239000010949 copper Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 150000002739 metals Chemical class 0.000 description 7
- 229910052718 tin Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 5
- 239000005368 silicate glass Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- -1 FSG Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000003491 array Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Via array configurations for metal-insulator-metal (MIM) capacitor structures are disclosed herein. An example MIM capacitor structure includes a capacitor bottom metal layer, a first dielectric layer over the capacitor bottom metal layer, a capacitor middle metal layer over the first dielectric layer, a second dielectric layer over the capacitor middle metal layer, and a capacitor top metal layer over the second dielectric layer. An array of metal vias having first and second metal vias is connected to the capacitor top and bottom metal layers. Portions of the capacitor top metal layer cover regions of the second dielectric layer extending from the first metal via to the second metal via. Embodiments of the present invention also provide semiconductor devices and methods of forming metal-insulator-metal capacitor structures.
Description
Technical Field
Embodiments of the present invention relate to semiconductor devices, metal-insulator-metal capacitor structures, and methods of forming.
Background
The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs.
For example, as the geometry of semiconductor devices decreases, passive devices, which sometimes consume large surface area, are moved to back-end-of-line (BEOL) structures. Metal-insulator-metal (MIM) capacitors are examples of such passive devices. A typical MIM capacitor includes a plurality of conductor plate layers that are insulated from each other by a plurality of insulator layers. Each contact via is connected to and/or extends through one or more of the plurality of conductor plate layers of the MIM capacitor. While the existing configuration of contact via regions for MIM structures is generally adequate for their intended purposes, improvements are still needed as the scale of IC technology increases.
Disclosure of Invention
Some embodiments of the present invention provide a semiconductor device including: a metal-insulator-metal (MIM) capacitor structure disposed over a substrate, wherein the MIM capacitor structure comprises: a first conductor layer, a second conductor layer, and a third conductor layer, wherein the second conductor layer is located between the first conductor layer and the third conductor layer, and a first insulator layer and a second insulator layer, wherein the first insulator layer is located between the first conductor layer and the second conductor layer, and the second insulator layer is located between the second conductor layer and the third conductor layer; a first via extending vertically through the second insulator layer, the second conductor layer, and the first insulator layer; a second via extending vertically through the third conductor layer, the second insulator layer, the first insulator layer, and the first conductor layer, wherein the second via is laterally spaced from the first via along the first direction; and a third via extending vertically through the third conductor layer, the second insulator layer, the first insulator layer, and the first conductor layer, wherein the third via is laterally spaced from the second via along a second direction different from the first direction, and the third conductor layer extends from the third via to the second via along the second direction.
Other embodiments of the present invention provide a metal-insulator-metal (MIM) capacitor structure comprising: a capacitor bottom metal layer; a first dielectric layer over the capacitor bottom metal layer; the middle metal layer of the capacitor is positioned above the first dielectric layer; a second dielectric layer over the capacitor middle metal layer; a capacitor top metal layer over the second dielectric layer; and an array of metal vias connected to the capacitor top metal layer and the capacitor bottom metal layer, wherein the array of metal vias has a first metal via and a second metal via, and a portion of the capacitor top metal layer covers an area of the second dielectric layer extending from the first metal via to the second metal via.
Still further embodiments of the present invention provide a method of forming a metal-insulator-metal (MIM) capacitor structure, the method comprising: depositing and patterning a first metal layer, wherein a portion of the patterned first metal layer is located in a first via region for a first via and a second via region for a second via; depositing a first insulator layer over the patterned first metal layer, wherein portions of the first insulator layer are located in the first via region and the second via region; depositing and patterning a second metal layer, wherein the patterned second metal layer is located over the first insulator layer; depositing a second insulator layer over the patterned second metal layer, wherein portions of the second insulator layer are located in the first via region and the second via region; depositing and patterning a third metal layer, wherein the patterned third metal layer is located over the second insulator layer, a portion of the patterned third metal layer is located in the first via region and the second via region, and a portion of the patterned third metal layer covers a region of the second insulator layer located between the first via region and the second via region; and forming a first via in the first via region and a second via in the second via region, wherein the first via and the second via extend through portions of the patterned third metal layer, portions of the second insulator layer, portions of the first insulator layer, and portions of the patterned first metal layer.
Still other embodiments of the present invention provide a pseudo-metal-insulator-metal structure within a via.
Drawings
The invention is best understood from the following detailed description when read in connection with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A and 1B are partial schematic views of a partial or complete metal-insulator-metal (MIM) capacitor according to various aspects of the present invention.
Fig. 2-18 are partial schematic cross-sectional views of a partial or unitary device 100 at various stages of its MIM capacitor structure according to various aspects of the present invention.
Fig. 19A and 19B are partial schematic views of a partial or complete via array that may be implemented in the devices of fig. 2-18, according to some embodiments of the invention.
Fig. 20A and 20B are partial schematic views of another via array, either partially or wholly, that may be implemented in the devices of fig. 2-18, according to some embodiments of the invention.
Fig. 21A and 21B are partial schematic views of yet another array of vias, partially or entirely, that may be implemented in the devices of fig. 2-18, according to some embodiments of the invention.
Fig. 22 is a partially schematic top view of yet another array of vias, partially or entirely, that may be implemented in the device of fig. 2-18, in accordance with some embodiments of the invention.
Fig. 23 is a flow chart of a method of fabricating a MIM structure having an enhanced via structure in accordance with various aspects of the invention.
Detailed Description
The present invention relates generally to Integrated Circuit (IC) devices and/or semiconductor devices, and more particularly to metal-insulator-metal (MIM) capacitors.
The following disclosure provides many different embodiments, or examples, of the different components used to implement the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include examples in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. In addition, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above …," "above," "below …," "below …," "upward," "downward," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), are used to facilitate the relationship of one component to another in accordance with the present invention. Spatially relative terms are intended to encompass different orientations of the device in which the component is included. Furthermore, when values or ranges of values are described by "about," "approximately," or the like, the term is intended to encompass values within a reasonable range that take into account variations that inherently occur during manufacture as understood by one of ordinary skill in the art. For example, a value or range of values encompasses a reasonable range including the recited value, such as within +/-10% of the recited value, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value. For example, a material layer having a thickness of "about 5nm" may cover a size range from 4.5nm to 5.5nm, with a manufacturing tolerance of +/-10% associated with depositing the material layer as known to one of ordinary skill in the art. Still further, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Metal-insulator-metal (MIM) capacitors have been widely used in functional circuits such as mixed signal circuits, analog circuits, radio Frequency (RF) circuits, dynamic Random Access Memory (DRAM), embedded DRAM, logic circuits, other circuits, or combinations thereof. In a System On Chip (SOC) application, different capacitors for different functional circuits may be integrated on the same chip to serve different purposes. For example, for mixed signal circuits, capacitors are used for decoupling and/or as high frequency noise filters. For DRAM circuits and embedded DRAM circuits, capacitors are used for memory storage, while for RF circuits, capacitors are used in oscillators and phase shift networks for coupling and/or bypass purposes. For microprocessors, capacitors are used for decoupling.
Fig. 1A is a partially schematic top view of a partial or unitary MIM capacitor 10 according to various aspects of the present invention. Fig. 1B is a partially schematic cross-sectional view of a partial or complete MIM capacitor 10 along line B-B of fig. 1A in accordance with various aspects of the invention. As the name suggests, MIM capacitors include a sandwich of alternating metal layers and insulator layers. In fig. 1A and 1B, MIM capacitor 10 includes a bottom conductor plate layer (CBM and/or MIM 1) 12, a middle conductor plate layer (CMM and/or MIM 2) 14 located above bottom conductor plate layer 12, and a top conductor plate layer (CTM and/or MIM 3) 16 located above middle conductor plate layer 14, each conductor plate layer being insulated from adjacent conductor plate layers by a dielectric layer, such as a high-k dielectric layer. For example, MIM capacitor 10 includes a dielectric layer 18 between bottom conductor plate layer 12 and middle conductor plate layer 14, and a dielectric layer 20 between middle conductor plate layer 14 and top conductor plate layer 16. In some embodiments, MIM capacitor 10 includes an additional conductor plate layer, such as another top conductor plate layer (e.g., MIM 4), located above top conductor plate layer 16.
MIM capacitor 10 further comprises via array 25 and via array 30, via array 25 comprising contacts/vias 28, and via array 30 comprising contacts/vias 32. The via array 25 is spaced apart from the via array 30 along the x-direction, the vias 28 form via columns along the y-direction and the vias 28 are spaced apart from each other along the y-direction, and the vias 32 form via columns along the y-direction and the vias 32 are spaced apart from each other along the y-direction. The middle conductor pole plate layer 14 is laterally offset with respect to the top conductor pole plate layer 16 and the bottom conductor pole plate layer 12 such that the vias 28 extend through the top conductor pole plate layer 16 and the bottom conductor pole plate layer 12 (e.g., the vias 28 are CTM/CBM redistribution vias), while the vias 32 extend through the middle conductor pole plate layer 14 (e.g., the vias 32 are CMM redistribution vias). Vias 28 and 32 also extend through dielectric layer 18 and dielectric layer 20. One or more vias 28 may extend to respective contacts 40 (e.g., metal lines) and one or more vias 32 may extend to respective contacts 42 (e.g., metal lines). The bottom conductor pole plate layer 12, the middle conductor pole plate layer 14, the top conductor pole plate layer 16, the dielectric layer 18, the dielectric layer 20, the via array 25 (including the vias 28), the via array 30 (including the vias 32), the contacts 40, and the contacts 42 may be disposed in one or more dielectric layers 50 and/or passivation layers. For clarity, fig. 1A and 1B have been simplified to better understand the inventive concepts of the present invention. Additional components may be added to the via array and some of the components described below may be replaced, modified, or eliminated in other embodiments of the via array.
In some cases, stresses may be induced on MIM capacitors such as MIM capacitor 10 by surrounding layers and/or components (e.g., such as dielectric layer 50, via 28, and via 32). As a result, the MIM capacitor may be damaged. In some examples, the induced stress may form a crack that may propagate to the MIM capacitor. The patterns of the bottom, middle, and top conductor pole layers in the contact via areas (such as the areas including via array 25 and/or via array 32) are sometimes configured to be substantially identical to reduce such stress and/or cracking. For example, the pattern of bottom and top conductor pole layers in the contact via areas for the CTM/CBM vias is configured such that the CTM/CBM vias extend through the same number of layers and/or materials. Each CTM/CBM via may extend through a respective portion of the top conductor pole layer. In other words, the CTM/CBM vias may extend through portions of the top conductor pole plate layer that are not connected to each other. In some embodiments, these portions are considered to be dummy conductor layers (also referred to as dummy conductor pads). It has been observed that configuring CTM/CBM vias as separate portions with top conductor pole plates layers may expose the underlying dielectric layer to subsequent processing. During patterning of the upper conductor layer, the underlying dielectric layer (e.g., dielectric layer 20) that is exposed may be damaged and/or inadvertently thinned, especially if the MIM capacitor includes more than a plurality of top conductor plate layers, such as MIM3 layers and MIM4 layers. In order to reduce the exposed, underlying dielectric layer area in the contact via region of the MIM structure, the present invention proposes incorporating a top conductor plate layer through which adjacent contact vias of the MIM structure extend. In such embodiments, the dielectric layer extending between adjacent contact vias is covered by the merged top conductor pole layer. Details of the proposed via array configuration for MIM structures will be described in the following pages.
Fig. 2-18 are partially schematic cross-sectional views of a partial or unitary device 100 at various stages in the fabrication of its MIM structure in accordance with various aspects of the invention. Fig. 2-18 depict cross-sectional views of the device 100 in the X-Z plane, such as cross-sectional views of the device 100 along a line corresponding to line B-B of fig. 1A. For clarity, fig. 2 to 18 have been simplified to better understand the inventive concept of the present invention. Additional components may be added to the device 100 and some of the components described below may be replaced, modified, or eliminated in other embodiments of the device 100.
Referring to fig. 2, one or more dielectric layers are formed over the device substrate 102. In some embodiments, the device substrate 202 is and/or includes a semiconductor substrate (wafer), such as a silicon substrate. The semiconductor substrate comprises an elemental semiconductor such as silicon and/or germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor such as SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP or a combination thereof; or a combination thereof. In some embodiments, the semiconductor substrate is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate may include various doping configurations depending on design requirements known in the art.
In some embodiments, the device substrate 102 includes a device layer DL and a multilayer interconnect MLI disposed over the device layer DL. In some embodiments, the device layer DL may include circuitry fabricated thereon and/or thereon by a front end of line (FEOL) process, and the multi-layer interconnect MLI may include circuitry fabricated thereon and/or thereon by an intermediate process (MOL) process and/or a back end of line (BEOL) process. The device substrate 102 may include various device components/features such as a semiconductor substrate, doped wells (e.g., n-wells and/or p-wells), isolation features (e.g., shallow Trench Isolation (STI) structures and/or other suitable isolation structures), metal gates (e.g., metal gates having gate electrodes located over gate dielectrics), gate spacers along metal gate sidewalls, source/drain features (e.g., epitaxial source/drain), other suitable device components, or combinations thereof. The device substrate 102 may include various passive microelectronic devices and active devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type FETs (NFETs), metal Oxide Semiconductor (MOS) FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar Junction Transistors (BJTs), laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The individual transistors may be configured as planar transistors or non-planar transistors (e.g., finFET and/or gate all-around (GAA) transistors) depending on design requirements.
The multilayer interconnect MLI may electrically connect devices of the device layer DL, components of the device layer DL, devices within the multilayer interconnect MLI (e.g., MIM capacitors), components of the multilayer interconnect MLI, or combinations thereof, such that the respective devices andand/or the components may function in a manner as dictated by the design requirements of the device 100. The multilayer interconnect MLI includes a combination of conductive layers (e.g., patterned metal layers formed of wires, conductive vias, conductive contacts, or combinations thereof) and dielectric layers configured to form an interconnect (routing) structure, which may provide interconnections (e.g., routing) between various devices and/or components of the device 100. The conductive layers form vertical interconnect structures, such as device level contacts and/or vias, that connect horizontal interconnect structures, such as conductive lines, in different layers/levels (or different planes) of the multi-layer interconnect MLI. In some embodiments, the interconnect structure routes electrical signals between devices and/or components of the device layer DL and/or the multi-layer interconnect MLI. In some embodiments, the interconnect structure distributes electrical signals (e.g., clock signals, voltage signals, and/or ground signals) to devices and/or device components of the device layer DL and/or the multi-layer interconnect MLI. In some embodiments, the wires may include Cu, al, alCu, ru, co, other suitable conductive materials, or a combination thereof. In some embodiments, the contacts and/or vias may include Cu, al, alCu, ru, co, W, other suitable conductive materials, or a combination thereof. In some embodiments, the dielectric layer may comprise silicon oxide or a silicon and oxygen containing material, wherein silicon is present in various suitable forms. In some embodiments, the dielectric layer may comprise a low-k dielectric layer (e.g., having a dielectric constant less than SiO 2 Dielectric constant, siO of (2) 2 Such as tetraethyl orthosilicate (TEOS) oxide, undoped Silicate Glass (USG), doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), other doped silicon oxide, or combinations thereof), other suitable low-k dielectric materials, or combinations thereof.
An interlayer dielectric (ILD) 110 is formed over the substrate 102. ILD 110 comprises a silicon and oxygen containing material (e.g., silicon oxide) and/or a low-k dielectric material layer such as TEOS oxide, undoped Silicate Glass (USG), doped silicate glass (e.g., BPSG, FSG, PSG, BSG or combinations thereof), other low-k dielectric material, or combinations thereof. ILD 110 may be deposited by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), other deposition processes, or combinations thereof. In some embodiments, ILD 110 has a thickness of about 150nm to about 130nm (e.g., about 200 nm). ILD 110 may be conformally deposited and ILD 110 has a substantially uniform thickness.
A carbide layer 115 is formed over ILD 110. In some embodiments, carbide layer 115 is a silicon carbide (SiC) layer, however other types of carbide materials are contemplated by the present invention. The carbide layer 115 may be deposited by CVD, PVD, ALD, other deposition processes, or a combination thereof. In some embodiments, carbide layer 115 has a thickness of about 45nm to about 65nm (e.g., 55 nm). In some embodiments, the carbide layer 115 is conformally deposited and the carbide layer 115 has a substantially uniform thickness.
A dielectric layer 120 is formed over carbide layer 115. Dielectric layer 120 may include a material comprising silicon and oxygen (e.g., silicon oxide). In some embodiments, dielectric layer 120 includes Undoped Silicate Glass (USG) and may be referred to as a USG layer. In some embodiments, dielectric layer 120 is a Plasma Enhanced Oxide (PEOX) USG (PEOX-USG) layer. Dielectric layer 120 may be deposited by Plasma Enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), sub-atmospheric CVD (SACVD), ALD, PVD, other deposition processes, or combinations thereof. In some embodiments, the dielectric layer 120 has a thickness of about 575nm to about 675nm (e.g., about 620 nm). In some embodiments, the dielectric layer 120 is conformally deposited and the dielectric layer 120 has a substantially uniform thickness.
A dielectric layer 125 is formed over dielectric layer 120. Dielectric layer 125 may include a nitrogen-containing material and/or a carbon-containing material. For example, the dielectric layer 125 includes silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxynitride (SiOCN), silicon nitride (SiN), other nitrogen-containing materials and/or carbon-containing materials, or combinations thereof. In some embodiments, dielectric layer 125 is a silicon nitride layer. In some embodiments, the dielectric layer 125 has a thickness of about 45nm to about 55nm (e.g., about 50 nm). The dielectric layer 125 may be deposited by CVD, ALD, PVD, other deposition processes, or a combination thereof. In some embodiments, dielectric layer 125 may act as an Etch Stop Layer (ESL).
A dielectric layer 130 may be deposited over dielectric layer 125. In some embodiments, dielectric layer 130 includes a silicon and oxygen containing material (e.g., silicon oxide). For example, the dielectric layer 130 is a USG layer and/or a PEOX-USG layer. The dielectric layer 130 may be deposited by PECVD, HDP-CVD, SACVD, ALD, PVD, other deposition processes, or a combination thereof. In some embodiments, the dielectric layer 130 has a thickness of about 800nm to about 1000nm (e.g., 900 nm). In some embodiments, the dielectric layer 130 is conformally deposited and the dielectric layer 130 has a substantially uniform thickness.
A hard mask layer 135 is formed over the dielectric layer 130. In some embodiments, hard mask layer 135 comprises a nitrogen-containing material. For example, hard mask layer 135 may be a SiON layer, however other types of hard mask materials are contemplated by the present invention. The hard mask layer 135 may be deposited by CVD, PVD, ALD, other deposition processes, or a combination thereof. In some embodiments, the hard mask layer 135 has a thickness of about 50nm to about 70nm (e.g., 60 nm). In some embodiments, the hard mask layer 135 is conformally deposited and the hard mask layer 135 has a substantially uniform thickness.
Turning to fig. 3, dielectric layer 130 is patterned to form trenches therein, such as trench 138A, trench 138B, and trench 138C. In some embodiments, trenches 138A-138C expose dielectric layer 125. In some embodiments, patterning the dielectric layer 130 may use an appropriate combination of photolithographic processes (e.g., photoresist deposition, exposure, and development) to form a first etch mask, the first etch process using the first etch mask to pattern the hard mask layer 135, thereby forming a second etch mask (e.g., patterned hard mask layer 135'), and the second etch process using the second etch mask to pattern the dielectric layer 130 (i.e., form the trenches 138A-138C in the dielectric layer 130). The first etching process and/or the second etching process may be a dry etching, a wet etching, or a combination thereof.
Turning to fig. 4, lower contacts 140A, 140B, 140C are formed in trenches 138A, 138B, and 138C, respectively, of dielectric layer 130. Although the lower contacts 140A-140C are disposed below the upper contacts (discussed below), the lower contacts 140A-140C are sometimes referred to as Top Metal (TM) contacts because they represent the top metal layer of the MLI structure. The lower contact 140A includes a plug 142A, the lower contact 140B includes a plug 142B, and the lower contact 140C includes a plug 142C. In some embodiments, lower contact 140A includes a pad 144A, lower contact 140B includes a pad 144B, and lower contact 140C includes a pad 144C. Plugs 142A-142C may also be referred to as fill layers, bulk layers, and the like. The liners 144A-144C may also be referred to as barrier layers. Plugs 142A-142C and pads 144A-144C comprise a conductive material such as aluminum, copper, titanium, tantalum, tungsten, ruthenium, molybdenum, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof (e.g., tiN, taN, taC, taCN, tiAl, tiAlN, etc.), silicides thereof (e.g., niSi, coSi, cuSi, taSiN, etc.), or combinations thereof. In some embodiments, plugs 142A-142C are copper plugs. In some embodiments, the gaskets 144A-144C include TiN, ta, taN or a combination thereof.
In some embodiments, forming the lower contacts 140A-140C includes forming a barrier layer over the dielectric layer 130 that partially fills the trenches 138A-138C, forming a metal fill layer over the barrier layer that fills the remaining portions of the trenches 138A-138C, and performing a planarization process to remove the barrier layer and the metal fill layer from the top surface of the dielectric layer 130 such that the barrier layer and the remaining portions of the metal fill layer form the pads 144A-144C and the plugs 142A-142C, respectively. The planarization process may be a Chemical Mechanical Planarization (CMP) process. The barrier layer and/or the metal fill layer may be deposited by ALD, CVD, PVD, other deposition processes (e.g., plating), or combinations thereof. The barrier layer and/or the metal filling layer may comprise a plurality of layers. In some embodiments, the barrier layer has a thickness of about 0.5nm to about 20 nm. In some embodiments, the metal fill layer has a thickness of about 80nm to about 2000 nm. In some embodiments, the lower contacts 140A-140C have a thickness of about 750nm to about 950 nm.
Turning to fig. 5, a passivation layer 150 is formed over the lower contacts 140A-140C. Passivation layer 150 may include multiple layers such as dielectric layer 152 and dielectric layer 154. For example, dielectric layer 152 is formed over lower contacts 140A-140C, and dielectric layer 154 is formed over dielectric layer 152. In some embodiments, dielectric layer 152 comprises a nitrogen-containing material and/or a carbon-containing material, and dielectric layer 154 comprises a silicon-and oxygen-containing material. For example, dielectric layer 152 is a silicon nitride layer and dielectric layer 154 is a USG layer and/or PEOX-USG layer. The dielectric layer 152 may be deposited by CVD, ALD, PVD, other deposition processes, or a combination thereof. Dielectric layer 154 may be deposited by PECVD, HDP-CVD, SACVD, ALD, PVD, other deposition processes, or a combination thereof. In some embodiments, the dielectric layer 152 may prevent and/or inhibit oxidation of the lower contacts 140A-140C. In some embodiments, the dielectric layer 152 has a thickness of about 65nm to about 85 nm. In some embodiments, dielectric layer 154 has a thickness of about 150nm to about 350 nm.
Turning to fig. 6-12, a metal-insulator-metal (MIM) capacitor structure, such as MIM structure 160, is formed over device substrate 102. As described below, fabricating MIM structure 160 involves a number of processes such as deposition and patterning of individual conductor layers (e.g., bottom conductor plate, middle conductor plate, and top conductor plate), and forming insulators between adjacent conductor plates. Thus, as shown in fig. 12, in some embodiments MIM structure 160 includes a plurality of metal layers that are metal plates of a capacitor, such as conductor layer 162, conductor layer 166, conductor layer 170 (including, for example, conductor layer 170A and conductor layer 170B), and conductor layer 174 (including, for example, conductor layer 174A and conductor layer 174B). MIM structure 160 also includes a plurality of insulator layers, such as insulator layer 164, insulator layer 168, and insulator layer 172. Insulator layer 164 is located between conductor layer 162 and conductor layer 166 and between conductor layer 162 and conductor layer 170B. Insulator layer 168 is located between conductor layer 166 and conductor layer 170A, between conductor layer 166 and conductor layer 170B, and between conductor layer 162 and conductor layer 170B. Insulator layer 172 is located between conductor layer 170A and conductor layer 174A and between conductor layer 170B and conductor layer 174B.
MIM structure 160 thus has four conductor layers (electrodes), which may be referred to as a first conductor layer (MIM 1) (i.e., conductor layer 162), a second conductor layer (MIM 2) (i.e., conductor layer 166), a third conductor layer (MIM 3) (i.e., conductor layer 170), and a fourth conductor layer (MIM 4) (i.e., conductor layer 174). As an example, MIM structure 160 can be used to implement one or more capacitors that can be connected to other microelectronic components (e.g., including active devices and/or passive devices as described above). For example, the capacitor may be provided by conductor layer 162, conductor layer 166, and conductor layer 170B, where conductor layer 162 is a CBM, conductor layer 166 is a CMM, and conductor layer 170B is a CTM of the capacitor. In another example, a capacitor may be provided by conductor layer 166, conductor layer 170B, and conductor layer 174A, where conductor layer 166 is a CBM, conductor layer 170B is a CMM, and conductor layer 174A is a CTM of the capacitor. Furthermore, and in some embodiments, MIM structure 160 allows capacitors to be packaged closely together in both the vertical and lateral directions, thereby reducing the amount of lateral spacing required to implement the capacitors. As a result, MIM structure 160 may accommodate ultra-high density capacitors.
Turning to fig. 6, a patterned conductor layer 162 is formed over dielectric layer 154, for example, by depositing and patterning a conductive material over dielectric layer 154. Patterning may include lithographic processes (e.g., forming a patterned etch mask over the conductive material) and etching processes (e.g., etching the conductive material using a patterned etch mask). In some embodiments, the conductor layer 162 is a metal nitride layer, such as a TiN layer. The conductor layer 162 may be subjected to a surface treatment such as using nitrous oxide (N) 2 O) sidewall passivation of the gas. In some embodiments, the conductor layer 162 has a thickness of about 35nm to about 45 nm.
Turning to fig. 7-12, insulator layer 164 is formed over conductor layer 162 (fig. 7), patterned conductor layer 166 is formed over insulator layer 164 (fig. 8), insulator layer 168 is formed over conductor layer 166 (fig. 9), patterned conductor layer 170 is formed over insulator layer 168 (fig. 10), insulator layer 172 is formed over conductor layer 170 (fig. 11), and patterned conductor layer 174 is formed over insulator layer 172 (fig. 12). The conductor layer 166, the conductor layer 170, and the conductor layer 174 may be formed in a similar manner to that used to form the conductor layer 162, but the patterns of the conductor layer 166, the conductor layer 170, and the conductor layer 174 may be different from the patterns of the conductor layer 166 and/or the patterns of the conductor layer 166, the conductor layer 170, and the conductor layer 174 may be different from each other, such as depicted. In some embodiments, conductor layer 166, conductor layer 170, and conductor layer 174 are metal nitride layers, such as TiN layers. In some embodiments, conductor layer 166, conductor layer 170, and conductor layer 174 have a thickness of about 35nm to about 45 nm. In the depicted embodiment, conductor layer 162, conductor layer 166, conductor layer 170, and conductor layer 174 have different patterns, but conductor layer 162, conductor layer 166, conductor layer 170, and conductor layer 174 are formed of the same material and have the same thickness. In some embodiments, conductor layer 162, conductor layer 166, conductor layer 170, conductor layer 174, or a combination thereof, are formed of different materials and/or have different thicknesses. In some embodiments, conductor layer 162, conductor layer 166, conductor layer 170, conductor layer 174, or a combination thereof, comprises any suitable conductive material.
Insulator layer 164, insulator layer 168, insulator layer 172, or combinations thereof may be deposited by ALD, CVD, PVD, other deposition processes, or combinations thereof. In some embodiments, insulator layer 164 is conformally deposited and insulator layer 164 has a substantially uniform thickness (e.g., insulator layer 164 has approximately the same thickness on the top and sidewall surfaces of conductor layer 162). In some embodiments, insulator layer 168 is conformally deposited and insulator layer 168 has a substantially uniform thickness (e.g., insulator layer 168 has approximately the same thickness on the top and sidewall surfaces of conductor layer 166). In some embodiments, insulator layer 172 is conformally deposited and insulator layer 172 has a substantially uniform thickness (e.g., insulator layer 172 has approximately the same thickness on the top and sidewall surfaces of conductor layer 170).
In some embodiments, insulator layer 164, insulator layer 168, insulator layer 172, or combinations thereof, comprise a high-k dielectric material having a dielectric constant (k value) greater than that of silicon oxide. In some embodiments, insulator layer 164, insulator layer 168, insulator layer 172, or a combination thereof, has a three-layer structure that is selected from The bottom to the top comprises a first zirconia (e.g. ZrO 2 ) Layer, alumina (Al) 2 O 3 ) Layer and second zirconia (ZrO 2 ) A layer. In such embodiments, insulator layer 164, insulator layer 168, insulator layer 172, or a combination thereof may be referred to as ZAZ layers. In such embodiments, each of the ZAZ layers can have a thickness of from about 1.5nm to about 2.5 nm. In some embodiments, insulator layer 164, insulator layer 168, insulator layer 172, or a combination thereof, may be relatively thin to increase the capacitance value while maintaining a sufficient thickness to avoid potential dielectric breakdown of the capacitor in MIM structure 160 (e.g., when two capacitor plates have a high potential difference, there may be leakage current between the plates, causing breakdown). In some embodiments, insulator layer 164, insulator layer 168, insulator layer 172, or a combination thereof, has a thickness of about 5nm to about 7 nm.
Turning to fig. 13, a passivation layer 175 is formed over MIM structure 160. In some embodiments, passivation layer 175 comprises a material comprising silicon and oxygen. For example, passivation layer 175 is a USG layer and/or a PEOX-USG layer. Passivation layer 175 may be deposited by PECVD, HDP-CVD, SACVD, ALD, PVD, other deposition processes, or a combination thereof. In some embodiments, for example, a planarization process (e.g., CMP) and/or an etching process is performed on the passivation layer 175 to reduce its thickness. In some embodiments, the passivation layer 175 has a thickness of about 450nm to about 650 nm. In some embodiments, the passivation layer 175 includes multiple layers.
Turning to fig. 14, contact openings are formed to expose lower contacts 140A-140C, such as contact opening 184A, contact opening 184B, and contact opening 184C, respectively. Contact opening 184A extends from top to bottom through passivation layer 175, insulator layer 172, insulator layer 168, insulator layer 164, and passivation layer 150 (e.g., dielectric layer 154 and dielectric layer 152) to expose a top surface of lower contact 140A. Contact opening 184B extends from top to bottom through passivation layer 175, portions of MIM structure 160 (including, for example, conductor layer 174A, insulator layer 172, conductor layer 170A, insulator layer 168, conductor layer 166, and insulator layer 164), and passivation layer 150 to expose a top surface of lower contact 140B. Contact opening 184C extends from top to bottom through passivation layer 175, portions of MIM structure 160 (including, for example, conductor layer 174B, insulator layer 172, conductor layer 170B, insulator layer 168, insulator layer 164, and conductor layer 162), and passivation layer 150 to expose a top surface of lower contact 140C. The contact openings 184A-184C may expose sidewalls of the respective layers through which the contact openings 184A-184C extend, respectively.
In some embodiments, forming contact openings 184A-184C includes forming a patterned etch mask over passivation layer 175 (e.g., by a photolithographic process) and etching passivation layer 175, conductor layer 174A, conductor layer 174B, insulator layer 172, conductor layer 170A, conductor layer 170B, insulator layer 168, conductor layer 166, insulator layer 164, conductor layer 162, and passivation layer 150. The etching is a dry etching, a wet etching, other suitable etching, or a combination thereof. The etching may be a multi-step process. For example, the etching may alternate etchants when etching the conductor layer and the insulator layer. In some embodiments, the pattern of conductor layers is configured to ensure that the contact openings 184A-184C pass through the same number of conductor layers, which may improve uniformity during etching. For example, in fig. 14, contact openings 184B and 184C extend through three conductor layers. Contact opening 184B passes through conductor layer 174A, conductor layer 170A, and conductor layer 166 (i.e., through MIM4, MIM3, and MIM 2). Contact opening 184C passes through conductor layer 174B, conductor layer 170B, and conductor layer 162 (i.e., through MIM4, MIM3, and MIM 1).
Turning to fig. 15, upper contacts, such as upper contact 190A, upper contact 190B, and upper contact 190C, are formed in and over contact openings 184A-184C, respectively. The upper contacts 190A-190C may be referred to as contact vias, metal lines, or a combination thereof. In some embodiments, the upper contacts 190A-190C may be referred to as contact pads. The upper contact 190A includes a plug 192A, the upper contact 190B includes a plug 192B, and the upper contact 190C includes a plug 192C. In some embodiments, the upper contact 190A includes a pad 194A, the upper contact 190B includes a pad 194B, and the upper contact 190C includes a pad 194C. Plugs 192A-192C may also be referred to as fill layers, bulk layers, and the like. The spacers 194A-194C may also be referred to as barrier layers and/or seed layers. Plugs 192A-192C and pads 194A-194C comprise a conductive material such as aluminum, copper, titanium, tantalum, tungsten, ruthenium, molybdenum, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof (e.g., tiN, taN, taC, taCN, tiAl, tiAlN, etc.), silicides thereof (e.g., niSi, coSi, cuSi, taSiN, etc.), or combinations thereof. In some embodiments, the plugs 192A-192C are AlCu plugs. In some embodiments, the pads 194A-194C are seed layers comprising a material configured for AlCu plugs.
In some embodiments, forming upper contacts 190A-190C includes forming a barrier layer over passivation layer 175 that partially fills contact openings 184A-184C, forming a metal fill layer over the barrier layer that fills the remaining portions of contact openings 184A-184C, and patterning the metal fill layer and the barrier layer to form pads 194A-194C and plugs 192A-192C, respectively. Patterning may include forming a patterned mask layer (e.g., forming a patterned SiON layer over the metal fill layer using a photolithography process and an etching process) and etching the metal fill layer and the barrier layer using the patterned mask layer as an etching mask. The metal fill layer and barrier layer are patterned to provide plugs 192A-192C and pads 194A-194C having upper portions, the upper portions of plugs 192A-192C and pads 194A-194C extending from contact openings 184A-184C and over the top surface of passivation layer 175. The barrier layer and/or the metal fill layer may be deposited by ALD, CVD, PVD, other deposition processes (e.g., plating), or combinations thereof. The barrier layer and/or the metal filling layer may comprise a plurality of layers. In some embodiments, plugs 192A-192C have a thickness of about 1000nm to about 3000nm.
The upper contacts 190A-190C provide electrical contact to the lower contacts 140A-140C, respectively. Further, and as shown in the depicted embodiment, upper contact 190B is electrically coupled to conductor layer 174A, conductor layer 170A, and conductor layer 166, while being electrically isolated from conductor layer 174B, conductor layer 170B, and conductor layer 162. Further, upper contact 190C is electrically coupled to conductor layer 174B, conductor layer 170B, and conductor layer 162, while being electrically isolated from conductor layer 174A, conductor layer 170A, and conductor layer 166. Thus, upper contact 190B provides electrical contact to a first terminal of MIM structure 160, and upper contact 190C provides electrical contact to a second terminal of MIM structure 160. In some embodiments, the upper contacts 190A-190C are portions that include a redistribution layer (RDL) for redistributing the bond pads to individual metal lines at different locations, such as from peripheral locations to locations uniformly distributed over the chip surface. The upper contacts 190A-190C may therefore be referred to as redistribution vias. In some embodiments, RDLs may couple a multi-layer interconnect (MLI) structure to bond pads for connection to external circuitry.
Turning to fig. 16, a passivation layer 200 is formed over the upper contacts 190A-190C and passivation layer 175. Passivation layer 200 may include multiple layers such as dielectric layer 205 and dielectric layer 210. For example, dielectric layer 205 is formed over the upper portions of upper contacts 190A-190C and passivation layer 175, and dielectric layer 210 is formed over dielectric layer 205. In some embodiments, dielectric layer 205 comprises a silicon and oxygen containing material and dielectric layer 210 comprises a nitrogen containing material and/or a carbon containing material. For example, dielectric layer 205 is a USG layer and/or PEOX-USG layer, and dielectric layer 210 is a silicon nitride layer and/or a Plasma Enhanced (PE) silicon nitride layer. The dielectric layer 205 may be deposited by PECVD, HDP-CVD, SACVD, ALD, PVD, other deposition processes, or a combination thereof. The dielectric layer 210 may be deposited by CVD, ALD, PVD, other deposition processes, or a combination thereof.
Turning to fig. 17, openings (trenches) are formed in passivation layer 200 exposing upper contacts 190A-190C, such as openings 212A, 212B, and 212C, respectively. Openings 212A-212C extend through dielectric layer 210 and dielectric layer 205 from top to bottom to expose top surfaces of upper contacts 190A-190C, respectively. In some embodiments, forming openings 212A-212C includes forming a patterned etch mask (e.g., by a photolithographic process) over passivation layer 200 and etching dielectric layer 210 and/or dielectric layer 205 using the patterned etch mask. The etching may include dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, dielectric layer 205 may be etched using patterned dielectric layer 210 as an etch mask. The etching may be a multi-step process. In some embodiments, openings 212A-212C may expose sidewalls of the respective layers through which openings 212A-212C extend.
Turning to fig. 18, in some embodiments, a patterned Polyimide (PI) layer 215 is formed over the passivation layer 200. In some embodiments, forming PI layer 215 includes depositing a polyimide material over passivation layer 200 that partially fills openings 212A-212C, and patterning the polyimide material, for example, to expose top surfaces of upper contacts 190A-190C. In some embodiments, the polyimide material is conformally deposited by spin coating and/or other suitable deposition processes. In some embodiments, a bake process is performed after depositing the polyimide material. In some embodiments, patterning includes forming a patterned mask layer over the polyimide material (e.g., by a photolithographic process), and etching the polyimide material using the patterned mask layer as an etch mask. In some embodiments, PI layer 215 includes a photoactive chemistry such that PI layer 215 may be directly patterned by a photolithographic process without a subsequent etching process.
In some embodiments, a bump process is performed to form an Under Bump Metal (UBM), a metal pillar (or metal bump), and a solder bump. For example, UBM 220A, copper (Cu) pillars 225A, and solder bumps 230A are formed over PI layer 215 and upper contact 190A; forming UBM 220B, cu pillars 225B and solder bumps 230B over PI layer 215 and upper contact 190B; UBM 220C, cu posts 225C and solder bumps 230C are formed over PI layer 215 and upper contact 190C. UBM 220A-220C and Cu pillars 225A-225C fill openings 212A-212C, respectively, and extend over the top surface of PI layer 215. Cu pillars 225A-225C are disposed over UBMs 220A-220C, respectively, and solder bumps 230A-230C are disposed over Cu pillars 225A-225C, respectively. In some embodiments, UBM 220A-220C, cu posts 225A-225C and solder bumps 230A-230C provide a contact structure of device 100 that can facilitate connection to external circuits.
In some embodiments, UBM 220A-220C provides an RDL low resistance electrical connection into the upper portion of upper contacts 190A-190C. UBM 220A-220C may also hermetically seal and prevent other bump metals from diffusing into device 100. In some embodiments, UBM 220A-220C includes a plurality of different metal layers, such as adhesion layers (e.g., ti, cr, al, other metals, or combinations thereof), diffusion barrier layers (e.g., crCu alloys and/or other suitable metals), solderable layers, and oxidation barrier layers (e.g., au and/or other suitable metals). The various layers of UBM 220A-220C may be deposited by electroplating, sputtering, evaporation, other methods, or combinations thereof. In some embodiments, a Cu seed layer is formed between Cu pillars 225A-225C and UBM 220A-220C, for example, by an electroplating process. In some embodiments, a diffusion barrier (e.g., ni and/or other suitable metals) is formed between Cu pillars 225A-225C and solder bumps 230A-230C, for example, to prevent the formation of intermetallic layers therebetween and/or to prevent the formation of micro-vias. UBM 220A-220C, cu pillars 225A-225C and solder bumps 230A-230C can be deposited by electroplating, sputtering, evaporation, other methods, or a combination thereof. After deposition of the respective materials for UBM 220A-220C, cu pillars 225A-225C and solder bumps 230A-230C. A patterning process (e.g., a photolithography process and/or an etching process) may be performed to pattern one or more of the various material layers deposited during the bump process. In some embodiments, a reflow process may be performed after the deposition of the solder material to form solder bumps 230A-230C.
Fig. 19A and 19B are partial schematic views of a partial or complete via array that may be implemented in device 100 according to some embodiments of the invention. Fig. 19A depicts a top view of a one by three (1 x 3) via array of device 100 that may correspond to top via array 25 of fig. 1A, and fig. 19B is a cross-sectional view of device 100 in the Y-Z plane, such as a cross-sectional view of device 100 along line C-C of fig. 19A (which may correspond to line C-C of fig. 1A). Fig. 19A and 19B have been simplified for the sake of clarity to better understand the inventive concepts of the present invention. Additional components may be added to the via array and some of the components described below may be replaced, modified, or eliminated in other embodiments of the via array.
In fig. 19A and 19B, the VIA array includes a first VIA (VIA 1) (e.g., upper contact 190C), a second VIA (VIA 2) (e.g., upper contact 190D), and a third VIA (VIA 3) (e.g., upper contact 190E) arranged along the y-direction and aligned with each other. For example, VIA1 is spaced apart from VIA2 by a distance Y1 along the Y-direction, and VIA2 is spaced apart from VIA3 by a distance Y1 along the Y-direction. VIA1, VIA2, and VIA3 each extend through the respective top conductor layer (i.e., MIM 4), the respective middle conductor layer (i.e., MIM 3), and the bottom conductor layer (i.e., MIM 1). In other words, MIM3 and MIM4 are patterned to provide each via (e.g., contacts 190C-190E) with a respective MIM3 and a respective MIM4 through which they extend. Each respective MIM4 wraps around and covers a respective MIM3 and a respective portion of insulator layer 172 that is located between the respective MIM4 and the respective MIM3 (i.e., insulator layer 172 is patterned to provide each via with a respective portion through which it extends). With such a configuration, in top view (fig. 19A), VIA1, VIA2, and VIA3 are surrounded by respective MIMs 4, and insulator layer 164 surrounds MIMs 4. Extending VIA1, VIA2, and VIA3 through the same number of layers and/or materials may reduce stress and/or cracking.
Incorporating individual MIMs 3 and/or individual MIMs 4 into an array of vias exposes portions of insulator layer 164, such as portions of insulator layer 164 extending between adjacent vias that are not covered by MIMs 3 and/or MIMs 4. The exposed lower portion of insulator layer 164 may be damaged during patterning of the upper conductor layer, such as by an etching process used to pattern the conductive layer to form MIM3 and/or MIM4 and/or an etching process associated with the fabrication of the MIM structure described with reference to fig. 8-12. In fig. 19B, a portion of insulator layer 164 is exposed between MIM4 through which VIA1 extends and MIM4 through which VIA2 extends, and a portion of insulator layer 164 is exposed between MIM4 through which VIA2 extends and MIM4 through which VIA3 extends. Such exposed portions of insulator layer 164 extend a distance Y2 between adjacent vias. In some embodiments, the ratio of Y2 to Y1 (i.e., Y2/Y1) corresponds to the amount of insulator layer 164 exposed between adjacent vias when individual MIMs 3 and/or individual MIMs 4 are implemented into the via array. It has been observed that such a via configuration may result in a ratio corresponding to about 40% to about 80% of the insulator layer 164 (and/or other underlying insulator layers) exposed between adjacent vias of the via array. It is further observed that as the size of the via array decreases, the amount of insulator layer exposed increases (i.e., a more compact via array exposes more insulator layer).
Fig. 20A and 20B are partial schematic views of another array of vias, either partially or wholly, that may be implemented in device 100 according to some embodiments of the invention. Fig. 20A depicts a top view of a one by three (1 x 3) via array of device 100 that may correspond to top via array 25 of fig. 1A, and fig. 20B is a cross-sectional view of device 100 in the Y-Z plane, such as a cross-sectional view of device 100 along line C-C of fig. 20A (which may correspond to line C-C of fig. 1A). For clarity, fig. 20A and 20B have been simplified to better understand the inventive concepts of the present invention. Additional components may be added to the via array and some of the components described below may be replaced, modified, or eliminated in other embodiments of the via array.
In fig. 20A and 20B, the VIA array includes VIA1, VIA2, and VIA3 arranged along the y-direction and aligned with each other. VIA1 is spaced apart from VIA2 by a distance Y1 along the Y-direction, and VIA2 is spaced apart from VIA3 by a distance Y1 along the Y-direction. Rather than having corresponding MIM3 and MIM4, in fig. 20A and 20B MIM3 and MIM4 of the vias of the via array merge together between adjacent vias. For example, VIA1, VIA2, and VIA3 each extend through the top conductor layer (i.e., MIM 4), the middle conductor layer (i.e., MIM 3), and the bottom conductor layer (i.e., MIM 1). With such a configuration, MIM3 and MIM4 extend a distance Y1 between adjacent VIAs such that MIM3 covers insulator layer 164 between VIA1 and VIA2 and between VIA2 and VIA3, and MIM4 covers insulator layer 172 between VIA1 and VIA2 and between VIA2 and VIA3. In top view (fig. 20A), VIA1, VIA2, and VIA3 are surrounded by MIM4 (and/or MIM 3), and insulator layer 172 surrounds MIM4.
Fig. 21A and 21B are partial schematic views of another array of vias, either partially or wholly, that may be implemented in device 100 according to some embodiments of the invention. Fig. 21A depicts a top view of a one by three (1 x 3) via array of device 100 that may correspond to top via array 25 of fig. 1A, and fig. 21B is a cross-sectional view of device 100 in the Y-Z plane, such as a cross-sectional view of device 100 along line C-C of fig. 21A (which may correspond to line C-C of fig. 1A). The via arrays of fig. 21A and 21B are similar to the via arrays of fig. 20A and 20B except that the vias have separate MIMs 3 in the via arrays of fig. 21A and 21B. In other words, MIM4 of a via of the via array is merged together between adjacent vias, while MIM3 of a via of the via array is not merged between adjacent vias. For example, VIA1, VIA2, and VIA3 each extend through the top conductor layer (i.e., MIM 4), the corresponding middle conductor layer (i.e., MIM 3), and the bottom conductor layer (i.e., MIM 1). With such a configuration, MIM4 extends a distance Y1 between adjacent VIAs such that MIM4 covers insulator layer 172 between VIA1 and VIA2 and between VIA2 and VIA 3. In top view (fig. 21A), VIA1, VIA2, and VIA3 are surrounded by MIM4, and insulator layer 172 surrounds MIM4. For clarity, fig. 21A and 21B have been simplified to better understand the inventive concepts of the present invention. Additional components may be added to the via array and some of the components described below may be replaced, modified, or eliminated in other embodiments of the via array.
Incorporating MIM3 and/or MIM4, such as provided in fig. 20A, 20B, 21A, and 21B, significantly reduces the amount of exposed insulator layers of the MIM structure and thus prevents damage to the insulator layers of the MIM structure, such as may result when patterning its conductor layers. Reducing and/or preventing damage to the insulator layer may improve reliability and/or performance of the MIM structure. Different embodiments may have different advantages and do not require any particular advantage of the embodiments.
In some embodiments, VIA2 and VIA3 may be dummy VIAs that are not electrically connected to voltage and/or external circuitry. In such embodiments, a dummy conductor layer (also referred to as a dummy conductor pad) may be incorporated into the contact/via area of the device 100 such that the contact/via extends through the same number of layers and/or materials, which may reduce stress and/or cracking. For example, in some embodiments, MIM3 and MIM4 through which VIA2 and VIA3 extend may be dummy conductor layers, such as a dummy middle conductor layer (CDMM) and a dummy top conductor layer (CDTM), respectively.
The present invention contemplates implementing the merging of MIM3 and/or MIM4 (e.g., top and/or middle conductor layers of a MIM structure) in via arrays having various configurations. For example, in fig. 20A and 21A, the via array is a one-dimensional array. In some embodiments, MIM3 and/or MIM4 are combined in a two-dimensional array of vias, such as depicted in fig. 22. In some embodiments, fig. 22 is a partially schematic top view of a two-by-three (2 x 3) via array that may be implemented in device 100. In the VIA array, a first column of VIAs is arranged and aligned along the y-direction, such as VIA1, VIA2, and VIA3, and a second column of VIAs is arranged and aligned along the y-direction, such as VIA4, VIA5, and VIA6. The through holes of the first column are aligned with corresponding through holes of the second column. For example, VIA1, VIA2, and VIA3 are aligned with VIA4, VIA5, and VIA6, respectively, along the x-direction. MIM4 and/or MIM3 surround VIA1, VIA2, VIA3, VIA4, VIA5, and VIA6.MIM4 and/or MIM3 extend between adjacent VIAs such that MIM4 covers insulator layer 172 between adjacent VIAs along the y-direction (e.g., between VIA1 and VIA2, between VIA2 and VIA3, between VIA4 and VIA5, between VIA5 and VIA 6) and between adjacent VIAs along the x-direction (e.g., between VIA1 and VIA4, between VIA2 and VIA5, and between VIA3 and VIA 6), and/or MIM3 covers insulator layer 164 between adjacent VIAs along the y-direction (e.g., between VIA1 and VIA2, between VIA2 and VIA3, between VIA4 and VIA5, between VIA5 and VIA 6) and between adjacent VIAs along the x-direction (e.g., between VIA1 and VIA4, between VIA2 and VIA5, and between VIA3 and VIA 6). Further, insulator layer 172 surrounds MIM4. For clarity, fig. 22 has been simplified to better understand the inventive concepts of the present invention. Additional components may be added to the via array and some of the components described below may be replaced, modified, or eliminated in other embodiments of the via array.
Fig. 23 is a flow chart of a method 300 for fabricating a MIM capacitor structure with improved via reliability in accordance with various aspects of the invention. At block 315, the method 300 includes depositing and patterning a first metal layer (e.g., fig. 1A, 1B, 6, 20A, 20B, 21A, 21B, etc.). Portions of the patterned first metal layer are located in a first via region for a first via of the MIM capacitor structure and a second via region for a second via. At block 320, a first insulator layer (e.g., fig. 1A, 1B, 7, 20A, 20B, 21A, 21B, etc.) is deposited over the patterned first metal layer. Portions of the first insulator layer are located in the first via region and the second via region. At block 325, the method 300 includes depositing and patterning a second metal layer (e.g., fig. 1A, 1B, 8, 20A, 20B, 21A, 21B, etc.). A patterned second metal layer is over the first insulator layer. At block 330, a second insulator layer (e.g., fig. 1A, 1B, 9, 11, 20A, 20B, 21A, 21B, etc.) is deposited over the patterned second metal layer. Portions of the second insulator layer are located in the first via region and the second via region. At block 335, the method 300 includes depositing and patterning a third metal layer (e.g., fig. 1A, 1B, 10, 12, 20A, 20B, 21A, 21B, etc.). A patterned third metal layer is over the second insulator layer. Portions of the patterned third metal layer are located in the first and second via regions, and portions of the patterned third metal layer cover regions of the second insulator layer located between the first and second via regions. At block 340, a first via is formed in the first via region and a second via is formed in the second via region (e.g., fig. 1A, 1B, 13-15, 20A, 20B, 21A, 21B, etc.). The first and second vias extend through portions of the patterned third metal layer, portions of the second insulator layer, portions of the first insulator layer, and portions of the patterned first metal layer. Additional steps may be provided before, during, and after method 300, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of method 300.
The present invention provides many different embodiments. An example device includes a metal-insulator-metal (MIM) capacitor structure disposed above a substrate. The MIM capacitor structure comprises a first conductor layer, a second conductor layer and a third conductor layer. The second conductor layer is located between the first conductor layer and the third conductor layer. The MIM capacitor structure further includes a first insulator layer and a second insulator layer. The first insulator layer is located between the first conductor layer and the second conductor layer, and the second insulator layer is located between the second conductor layer and the third conductor layer. The first via extends vertically through the second insulator layer, the second conductor layer, and the first insulator layer. The second via extends vertically through the third conductor layer, the second insulator layer, the first insulator layer, and the first conductor layer. The second through hole is laterally spaced from the first through hole along the first direction. The third via extends vertically through the third conductor layer, the second insulator layer, the first insulator layer, and the first conductor layer. The third through-hole is laterally spaced from the second through-hole along a second direction different from the first direction. The third conductor layer extends from the third via hole to the second via hole along the second direction.
In some embodiments, the second insulator layer extends from the third via to the second via in the second direction, and the third conductor layer covers the second insulator layer between the third via and the second via. In some embodiments, the third conductor layer surrounds the second via and the third via from a top view, and the second insulator layer surrounds the third conductor layer. In some embodiments, the MIM capacitor structure comprises a first via array comprising a first via and a second via array comprising a second via and a third via. In some embodiments, the first conductor layer, the second conductor layer, and the third conductor layer comprise a first metal material; the first through hole, the second through hole and the third through hole comprise a second metal material; and the first insulator layer and the second insulator layer comprise a high-k dielectric material.
In some embodiments, the MIM capacitor structure further comprises a fourth conductor layer and a third insulator layer. The fourth conductor layer is located between the third conductor layer and the second conductor layer. The third insulator layer is located between the third conductor layer and the fourth conductor layer, and the second insulator layer is located between the fourth conductor layer and the second conductor layer. The second via and the third via extend vertically through the fourth conductor layer and the third insulator layer. The fourth conductor layer extends from the third via hole to the second via hole along the second direction. In some embodiments, the second insulator layer extends from the third via to the second via in the second direction, and the fourth conductor layer covers the second insulator layer between the third via and the second via. In some embodiments, a third insulator layer extends from the third via to the second via in the second direction, and the third conductor layer covers the third insulator layer between the third via and the second via. In some embodiments, the fourth conductor layer has a first portion extending through by the second via and a second portion extending through by the third via. The first portion is not connected to the second portion along the second direction. In some embodiments, the third insulator layer is located between the third conductor layer and the sidewalls of the first portion and between the third conductor layer and the sidewalls of the second portion.
An exemplary metal-insulator-metal (MIM) capacitor structure includes a capacitor bottom metal layer, a first dielectric layer over the capacitor bottom metal layer, a capacitor middle metal layer over the first dielectric layer, a second dielectric layer over the capacitor middle metal layer, and a capacitor top metal layer over the second dielectric layer. The MIM capacitor structure further includes an array of metal vias connected to the capacitor top metal layer and the capacitor bottom metal layer. The metal via array has a first metal via and a second metal via. Portions of the capacitor top metal layer cover regions of the second dielectric layer extending from the first metal via to the second metal via.
In some embodiments, the capacitor top metal layer is a first capacitor top metal layer and the MIM capacitor structure further comprises a second capacitor top metal layer over the second dielectric layer and a third dielectric layer over the second capacitor top metal layer. The first capacitor top metal layer is located above the second capacitor top metal layer. The third dielectric layer is located between the second capacitor top metal layer and the first capacitor top metal layer. In some embodiments, a portion of the second capacitor top metal layer covers a region of the second dielectric layer extending from the first metal via to the second metal via, and a portion of the first capacitor top metal layer covers a region of the third dielectric layer extending from the first metal via to the second metal via. In some embodiments, a portion of the second capacitor top metal layer covers a portion of a region of the second dielectric layer extending from the first metal via to the second metal via. In some embodiments, a portion of the second capacitor top metal layer covers a portion of the region of the second dielectric layer extending from the first metal via to a second metal via; and the portion of the first capacitor top metal layer covers a region of the third dielectric layer extending from the first metal via to the second metal via.
In some embodiments, the portion of the capacitor top metal layer surrounds the first metal via and the second metal via from a top view. In some embodiments, the array of metal vias further comprises a third metal via. The first metal via, the second metal via, and the third metal via are arranged to provide an array of via-in-three metal vias, and the capacitor top metal layer covers an area of the second dielectric layer extending from the second metal via to the third metal via. In some embodiments, the array of metal vias is a two-by-three metal via array, and the capacitor top metal layer covers an area of the second dielectric layer extending between adjacent metal vias of the two-by-three metal via array. In some embodiments, the array of metal vias is a first array of metal vias, and the MIM capacitor structure may include a second array of metal vias connected to a middle metal layer of the capacitor.
An exemplary method of forming a MIM capacitor structure includes depositing and patterning a first metal layer. Portions of the patterned first metal layer are located in a first via region for the first via and a second via region for the second via. The method further includes depositing a first insulator layer over the patterned first metal layer. Portions of the first insulator layer are located in the first via region and the second via region. The method further includes depositing and patterning a second metal layer. A patterned second metal layer is over the first insulator layer. The method further includes depositing a second insulator layer over the patterned second metal layer. Portions of the second insulator layer are located in the first via region and the second via region. The method further includes depositing and patterning a third metal layer. A patterned third metal layer is over the second insulator layer, a portion of the patterned third metal layer is in the first and second via regions, and the portion of the patterned third metal layer covers a region of the second insulator layer between the first and second via regions. The method further includes forming a first via in the first via region and forming a second via in the second via region. The first and second vias extend through portions of the patterned third metal layer, portions of the second insulator layer, portions of the first insulator layer, and portions of the patterned first metal layer.
In some embodiments, the method includes depositing a third insulator layer over the patterned third metal layer. Portions of the third insulator layer are located in the first via region and the second via region. In some embodiments, the method further comprises depositing and patterning a fourth metal layer. A patterned fourth metal layer is over the third insulator layer, and portions of the patterned fourth metal layer are in the first and second via regions. The first via and the second via also extend through portions of the patterned fourth metal layer and portions of the third insulator layer.
In some embodiments, the portion of the first insulator layer is a first portion and the portion of the second insulator layer is a first portion, the second portion of the first insulator layer and the second portion of the second insulator layer are located in a third via region for a third via, and the portion of the patterned second metal layer is located in the third via region. The method may further include forming a third via in the third via region. The third via extends through the second portion of the second insulator layer, the portion of the patterned second metal layer, and the second portion of the first insulator layer.
An exemplary device structure includes a metal-insulator-metal (MIM) structure disposed over a substrate. The MIM structure includes a first conductor layer, a second conductor layer, and a first dielectric layer between the first conductor layer and the second conductor layer. The MIM structure further includes a first dummy conductor layer, a second dummy conductor layer, and a second dielectric layer between the first dummy conductor layer and the second dummy conductor layer. The first via extends vertically through the first dummy conductor layer, the second dielectric layer, and the second dummy conductor layer. The second via extends vertically through the first dummy conductor layer, the second dielectric layer, and the second dummy conductor layer. The second dummy conductor layer covers a region of the second dielectric layer located between the first via and the second via.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.
Claims (10)
1. A semiconductor device, comprising:
a metal-insulator-metal (MIM) capacitor structure disposed above a substrate, wherein the metal-insulator-metal capacitor structure comprises:
a first conductor layer, a second conductor layer and a third conductor layer, wherein the second conductor layer is located between the first conductor layer and the third conductor layer, and
a first insulator layer and a second insulator layer, wherein the first insulator layer is located between the first conductor layer and the second conductor layer, and the second insulator layer is located between the second conductor layer and the third conductor layer;
a first via extending vertically through the second insulator layer, the second conductor layer, and the first insulator layer;
a second via extending vertically through the third conductor layer, the second insulator layer, the first insulator layer, and the first conductor layer, wherein the second via is laterally spaced from the first via along a first direction; and
a third via extending vertically through the third conductor layer, the second insulator layer, the first insulator layer, and the first conductor layer, wherein the third via is laterally spaced from the second via along a second direction different from the first direction, and the third conductor layer extends from the third via to the second via along the second direction.
2. The semiconductor device of claim 1, wherein the second insulator layer extends from the third via to the second via along the second direction, and the third conductor layer covers the second insulator layer between the third via and the second via.
3. The semiconductor device of claim 1, wherein:
the metal-insulator-metal capacitor structure further includes a fourth conductor layer and a third insulator layer, wherein the fourth conductor layer is located between the third conductor layer and the second conductor layer, the third insulator layer is located between the third conductor layer and the fourth conductor layer, and the second insulator layer is located between the fourth conductor layer and the second conductor layer; and
the second via and the third via extend vertically through the fourth conductor layer and the third insulator layer.
4. A semiconductor device according to claim 3, wherein the fourth conductor layer extends from the third via to the second via along the second direction.
5. The semiconductor device of claim 4, wherein:
the second insulator layer extends from the third via to the second via along the second direction, and the fourth conductor layer covers the second insulator layer between the third via and the second via; and
The third insulator layer extends from the third via to the second via along the second direction, and the third conductor layer covers the third insulator layer between the third via and the second via.
6. A semiconductor device according to claim 3, wherein the fourth conductor layer has a first portion through which the second via extends and a second portion through which the third via extends, the first portion being unconnected to the second portion along the second direction, and the third insulator layer being located between the third conductor layer and a sidewall of the first portion and between the third conductor layer and a sidewall of the second portion.
7. The semiconductor device according to claim 1, wherein the third conductor layer surrounds the second via hole and the third via hole in a plan view, and the second insulator layer surrounds the third conductor layer.
8. The semiconductor device of claim 1, further comprising a first array of vias comprising the first via and a second array of vias comprising the second via and the third via.
9. A metal-insulator-metal (MIM) capacitor structure comprising:
a capacitor bottom metal layer;
a first dielectric layer over the capacitor bottom metal layer;
a capacitor middle metal layer positioned above the first dielectric layer;
a second dielectric layer located over the capacitor middle metal layer;
a capacitor top metal layer over the second dielectric layer; and
an array of metal vias connected to the capacitor top metal layer and the capacitor bottom metal layer, wherein the array of metal vias has a first metal via and a second metal via, and a portion of the capacitor top metal layer covers a region of the second dielectric layer extending from the first metal via to the second metal via.
10. A method of forming a metal-insulator-metal (MIM) capacitor structure, the method comprising:
depositing and patterning a first metal layer, wherein a portion of the patterned first metal layer is located in a first via region for a first via and a second via region for a second via;
depositing a first insulator layer over the patterned first metal layer, wherein portions of the first insulator layer are located in the first via region and the second via region;
Depositing and patterning a second metal layer, wherein the patterned second metal layer is located over the first insulator layer;
depositing a second insulator layer over the patterned second metal layer, wherein portions of the second insulator layer are located in the first and second via regions;
depositing and patterning a third metal layer, wherein the patterned third metal layer is located over the second insulator layer, portions of the patterned third metal layer are located in the first and second via regions, and the portions of the patterned third metal layer cover regions of the second insulator layer located between the first and second via regions; and
a first via is formed in the first via region and a second via is formed in the second via region, wherein the first via and the second via extend through the portion of the patterned third metal layer, the portion of the second insulator layer, the portion of the first insulator layer, and the portion of the patterned first metal layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63/337,502 | 2022-05-02 | ||
| US17/901,352 US20230352396A1 (en) | 2022-05-02 | 2022-09-01 | Dummy Metal-Insulator-Metal Structures Within Vias |
| US17/901,352 | 2022-09-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116648133A true CN116648133A (en) | 2023-08-25 |
Family
ID=87614205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310347054.4A Pending CN116648133A (en) | 2022-05-02 | 2023-04-03 | Semiconductor device, metal-insulator-metal capacitor structure and forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116648133A (en) |
-
2023
- 2023-04-03 CN CN202310347054.4A patent/CN116648133A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10373905B2 (en) | Integrating metal-insulator-metal capacitors with air gap process flow | |
| US9362222B2 (en) | Interconnection between inductor and metal-insulator-metal (MIM) capacitor | |
| TWI718268B (en) | Methods of forming semiconductor structures | |
| CN102593096A (en) | Forming metal-insulator-metal capacitors over a top metal layer | |
| KR20110055342A (en) | Pad structure for semiconductor devices | |
| US9520371B2 (en) | Planar passivation for pads | |
| US20200058642A1 (en) | Ic with larger and smaller width contacts | |
| CN113314499A (en) | Semiconductor device and method of forming the same | |
| US11728262B2 (en) | Metal plate corner structure on metal insulator metal | |
| US20150061156A1 (en) | Pad solutions for reliable bonds | |
| US20220367605A1 (en) | Method of forming a stress reduction structure for metal-insulator-metal capacitors | |
| US20220359387A1 (en) | Structure and method of forming a semiconductor device with resistive elements | |
| US20230187315A1 (en) | Through Via Structure | |
| US11532695B2 (en) | Stress reduction structure for metal-insulator-metal capacitors | |
| CN116648133A (en) | Semiconductor device, metal-insulator-metal capacitor structure and forming method | |
| CN114188302B (en) | Semiconductor element with inter-metal dielectric pattern and manufacturing method thereof | |
| US20230352396A1 (en) | Dummy Metal-Insulator-Metal Structures Within Vias | |
| CN220569675U (en) | Semiconductor structure | |
| US20230352395A1 (en) | Semiconductor structure and method for forming the same | |
| US11961880B2 (en) | Metal-insulator-metal structure | |
| US11791371B2 (en) | Resistor structure | |
| US20230360946A1 (en) | Method for forming semiconductor structure | |
| US20230069830A1 (en) | Metal-insulator-metal capacitor (mimcap) and methods of forming the same | |
| US12027574B2 (en) | Resistor structure | |
| US20230178589A1 (en) | Guard Ring Design For Through Via |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |