CN117092398A - Novel voltage detection power supply clamp circuit for excessive electrical stress event - Google Patents

Abstract

The application discloses a power supply clamping circuit. The power clamp circuit is coupled to an internal circuit of the integrated circuit through a power line and a ground line, and comprises a switch, a first resistor, a capacitor, an inverter and a voltage detection circuit. The switch is coupled between the power line and the ground line. The first resistor is coupled between the power line and the first node. The capacitor is coupled between the first node and the ground line. The input end of the inverter is coupled to the first node, and the output end of the inverter is coupled to the control end of the switch. The voltage detection circuit is used for detecting the voltage of the power supply on line. In response to detecting that the voltage of the power supply line exceeds a threshold, the voltage detection circuit electrically connects the first node to the ground line, so that a low potential signal from the ground line is input from the first node to the input terminal of the inverter, and the switch is turned on to form a discharge path.

Description

Novel voltage detection power supply clamp circuit for excessive electrical stress event

Technical Field

The present application relates to a power clamp circuit for an integrated circuit (Integrated Circuit, IC), and more particularly, to a power clamp circuit capable of forming a discharge path for excessive electrical stress (Electrical Over Stress, EOS).

Background

The IC may be provided with a power clamp circuit to form a discharge path for electrostatic discharge (Electrostatic Discharge, ESD) to prevent current from the ESD surge from flowing into the internal circuitry of the IC to burn the IC. However, EOS (or system ESD) may also occur during normal operation of the IC, and is typically on the order of microseconds compared to the ESD event duration. Therefore, the existing power clamp circuit is not easy to form a discharge path for the EOS to prevent the current of the EOS surge from flowing into the internal circuit of the IC to burn the IC.

Disclosure of Invention

In view of the shortcomings of the prior art, it is an object of the present application to provide a power clamp circuit that can form a discharge path for an EOS to prevent an EOS surge current from flowing into the internal circuitry of the IC to burn out the IC.

In order to achieve the above object, the present application provides a power clamp circuit. The power clamp circuit is coupled to an internal circuit of the IC through a power line and a ground line, and includes a switch, a first resistor, a capacitor, an inverter, and a voltage detection circuit. The switch is coupled between the power line and the ground line. The first resistor is coupled between the power line and the first node. The capacitor is coupled between the first node and the ground line. The inverter is coupled between the first node and a control terminal of the switch. The input end of the inverter is coupled to the first node, and the output end of the inverter is coupled to the control end of the switch. The voltage detection circuit is coupled to the power line, the first node and the ground line and is used for detecting the voltage of the power line. In response to detecting that the voltage of the power supply line exceeds a threshold value, the voltage detection circuit electrically connects the first node to the ground line, so that a low-potential signal from the ground line is input from the first node to the input end of the inverter, and the switch is turned on to form a discharge path.

For a further understanding of the nature and the technical aspects of the present application, reference should be made to the following detailed description of the application and to the accompanying drawings, which are provided for purposes of illustration only and are not intended to limit the application.

Drawings

Fig. 1 is a schematic diagram of a power clamp circuit according to an embodiment of the application.

Fig. 2 is a schematic diagram of a voltage detection circuit according to a first embodiment of the present application.

Fig. 3 is a schematic diagram of a voltage detection circuit according to a second embodiment of the present application.

Fig. 4 is a schematic diagram of a voltage detection circuit according to a third embodiment of the present application.

Fig. 5 is a schematic diagram of a voltage detection circuit according to a fourth embodiment of the present application.

Fig. 6 is a schematic diagram of a voltage detection circuit according to a fifth embodiment of the present application.

Symbol description:

1: power supply clamping circuit

10: switch

14: inverter with a high-speed circuit

16: voltage detection circuit

Mn1, mn2, mn3_1 to Mn3_n, mn4, mn5: n-channel metal oxide semiconductor field effect transistor

Mp1_1 to Mp1_n, mp2, mp3: p-channel metal oxide semiconductor field effect transistor

R1 and R2: resistor

C: capacitance device

PL: power line

GL: grounding wire

N1, N2, N3: node

GND: ground voltage

D_1 to d_n: diode

VDD: supply voltage

20: internal circuit of IC

Detailed Description

The following embodiments of the present application are described in terms of specific examples, and those skilled in the art will appreciate the advantages and effects of the present application from the disclosure provided herein. The application is capable of other and different embodiments and its several details are capable of modifications and various other uses and applications, all of which are obvious from the description, without departing from the spirit of the application. The drawings of the present application are merely schematic illustrations, and are not drawn to actual dimensions, and are not previously described. The following embodiments will further illustrate the related art content of the present application in detail, but the content provided is not intended to limit the scope of the present application.

Referring to fig. 1, fig. 1 is a schematic diagram of a power clamp circuit according to an embodiment of the application. The power clamp circuit 1 is an internal circuit 20 coupled to the IC through a power line PL and a ground line GL. The ground line GL is coupled to the ground voltage GND, and the power clamp circuit 1 includes a switch 10, a resistor R1, a capacitor C, an inverter 14, and a voltage detection circuit 16. The switch 10 is coupled between the power line PL and the ground line GL. The resistor R1 is coupled between the power line PL and the first node N1. The capacitor C is coupled between the first node N1 and the ground line GL. The inverter 14 is coupled between the first node N1 and the control terminal of the switch 10. The input terminal of the inverter 14 is coupled to the first node N1, and the output terminal of the inverter 14 is coupled to the control terminal of the switch 10. The voltage detection circuit 16 is coupled to the power line PL, the first node N1 and the ground line GL for detecting a voltage on the power line PL. In response to detecting that the voltage on the power line PL exceeds a threshold, the voltage detection circuit 16 electrically connects the first node N1 to the ground line GL, so that a low-potential signal from the ground line GL is input from the first node N1 to the input terminal of the inverter 14, thereby turning on the switch 10 to form a discharge path.

Specifically, the switch 10 may be an N-channel mosfet Mn1, the drain of the N-channel mosfet Mn1 is coupled to the power line PL, the source of the N-channel mosfet Mn1 is coupled to the ground line GL, and the gate of the N-channel mosfet Mn1 is coupled to the output of the inverter 14 as the control terminal, but the application is not limited thereto. In other embodiments, the switch 10 may be an NPN bipolar junction transistor, a collector of the NPN bipolar junction transistor is coupled to the power line PL, an emitter of the NPN bipolar junction transistor is coupled to the ground line GL, and a base of the NPN bipolar junction transistor is coupled to the output of the inverter 14 as the control terminal, but the application is not limited thereto. The present application is not limited to the specific embodiment of the switch 10, but for convenience of the following description, the switch 10 provided in the present application uses only the N-channel mosfet Mn1 as an example. The N-channel mosfet Mn1 is turned on in response to the gate receiving the high signal output from the inverter 14, and turned off in response to the gate receiving the low signal output from the inverter 14.

In addition, the inverter 14 outputs a low potential signal in response to a high potential signal from the first node N1 input terminal thereof, and outputs a high potential signal in response to a low potential signal from the first node N1 input terminal thereof. The resistor R1 and the capacitor C are connected in series between the power line PL and the ground line GL to constitute an RC circuit, and the RC circuit is also connected in parallel with the N-channel mosfet Mn1. In other embodiments, the resistor R1 may be replaced by a pmos or nmos, and the capacitor C may be replaced by a diode, but the application is not limited thereto. It should be noted that, during normal operation of the internal circuit 20 in which the power supply voltage VDD is applied to the power supply line PL to be supplied to the IC, the power supply clamp circuit 1 causes a high-potential signal from the power supply line PL to be input from the first node N1 to the input terminal of the inverter 14, thereby turning off the N-channel mosfet Mn1.

However, if the voltage detection circuit 16 is not yet provided in the power supply clamp circuit 1, when an EOS surge is applied to the power supply line PL (i.e., EOS occurs), the RC circuit charges the capacitor C according to the RC time constant of the resistor R1 and the capacitor C. Because the EOS event duration is typically in the microsecond level, and the RC time constant of the resistor R1 and the capacitor C also typically sets the time required for the capacitor C to be charged to be in the microsecond level, when the EOS event occurs, there is a chance that the capacitor C is charged to be completed, so that the first node N1 is in a high state to generate a high signal to be input to the input terminal of the inverter 14, and thus the N-channel mosfet Mn1 is also turned off to fail to form a discharge path. Thus, the EOS surge current at this time flows into the internal circuit 20 of the IC.

On the other hand, when the voltage on the power line PL rises to the breakdown voltage of the nmos Mn1, the power clamp 1 can only form a discharge path from the drain to the base of the nmos Mn1, but in the nmos Mn1, there is often a non-uniform drain to base conduction, and thus the discharge capability is limited, so that it is not easy to prevent the EOS surge current from flowing into the internal circuit 20 of the IC. In order to solve the above-mentioned problem, the power clamp circuit 1 provided by the present application is capable of electrically connecting the first node N1 to the ground line GL when EOS occurs through the voltage detection circuit 16, so that a low-potential signal from the ground line GL is input from the first node N1 to the input terminal of the inverter 14, and the N-channel mosfet Mn1 is turned on to form a discharge path. Therefore, the EOS surge current at this time can flow to the ground line GL through the N-channel mosfet Mn1.

It should be appreciated that voltage detection circuit 16 determines that EOS occurs in response to detecting that the voltage on power line PL exceeds a threshold. Thus, the threshold is determined based on the IC's sustainable voltage for the EOS specification. Next, various embodiments of the voltage detection circuit 16 are described below with reference to fig. 2 to 6. Referring to fig. 2, fig. 2 is a schematic diagram of a voltage detection circuit according to a first embodiment of the application. In the first embodiment, the voltage detection circuit 16 may include a plurality of diodes d_1 to d_n, a resistor R2, and an N-channel mosfet Mn2. The plurality of diodes d_1 to d_n are connected in series between the power supply line PL and the second node N2, and N is an integer greater than 1.

Specifically, the anode of the first diode d_1 of the plurality of diodes d_1 to d_n is coupled to the power line PL, the cathode of the nth diode d_n of the plurality of diodes d_1 to d_n is coupled to the second node N2, and the cathode of the ith diode d_i of the plurality of diodes d_1 to d_n is coupled to the anode of the (i+1) th diode d_i+1. i is an integer from 1 to n-1. In addition, the resistor R2 is coupled between the second node N2 and the ground line GL. The drain of the N-channel MOSFET Mn2 is coupled to the first node N1, the gate of the N-channel MOSFET Mn2 is coupled to the second node N2, and the source of the N-channel MOSFET Mn2 is coupled to the ground line GL.

It can be seen that the plurality of diodes D1-Dn are used as switches coupled between the power line PL and the second node N2, and the number of the plurality of diodes D1-Dn (i.e., N) is determined according to the threshold voltage of each diode and the power voltage VDD supplied to the IC. For example, assuming that the threshold voltage of each diode is 0.8 volts, this means that the plurality of diodes d_1 to d_n can all be turned on only when the voltage on the power line PL exceeds (n×0.8) volts, i.e., current can flow through the plurality of diodes d_1 to d_n to the second node N2 at this time. Thus, the present embodiment may determine that the number of the plurality of diodes d_1 to d_n is 3 if the power voltage VDD supplied to the IC is 1.8 volts, or determine that the number of the plurality of diodes d_1 to d_n is 5 if the power voltage VDD supplied to the IC is 3.3 volts. That is, during normal operation, since the power voltage VDD supplied to the IC is less than (n×0.8) volts, current does not flow to the second node N2 through the plurality of diodes d_1 to d_n, so that the N-channel mosfet Mn2 is turned off, and the voltage detection circuit 16 does not cause additional leakage and malfunction.

In contrast, when the voltage on the power line PL exceeds (n×0.8) v, a current flows to the second node N2 through the plurality of diodes d_1 to d_n, so that the N-channel mosfet Mn2 is turned on, and the voltage detection circuit 16 electrically connects the first node N1 to the ground line GL. Also, therefore, a low potential signal from the ground line GL is inputted from the first node N1 to the input terminal of the inverter 14, thereby turning on the N-channel mosfet Mn1 to form a discharge path. Since the operation principles of the diodes d_1 to d_n, the resistor R2 and the N-channel mosfets Mn1 and Mn2 are well known to those skilled in the art, the details of the voltage detection circuit 16 of the first embodiment will not be repeated.

Referring to fig. 3, fig. 3 is a schematic diagram of a voltage detection circuit according to a second embodiment of the application. The voltage detection circuit 16 of the second embodiment is similar to the voltage detection circuit 16 of the first embodiment, so the same parts of the two embodiments will not be repeated. It should be noted that, unlike the first embodiment which uses a plurality of diodes d_1 to d_n as switches coupled between the power line PL and the second node N2, the second embodiment uses a plurality of ppszfjfet's Mp1_1 to Mp1_n as switches coupled between the power line PL and the second node N2. In other words, the voltage detection circuit 16 of the second embodiment includes a plurality of P-channel mosfets mp1_1 to mp1_n, a resistor R2, and an N-channel mosfet Mn2. The P-channel mosfets mp1_1 to mp1_n are connected in series between the power line PL and the second node N2.

Specifically, the source of the first one of the P-channel mosfets m1_1 to m1_n is coupled to the power line PL, and the drain of the N-th one of the P-channel mosfets m1_1 to m1_n is coupled to the second node N2. In addition, the gate and drain of each of the plurality of P-channel metal-oxide-semiconductor field-effect transistors Mp1_1 to Mp1_n are coupled together, and the drain of the ith P-channel metal-oxide-semiconductor field-effect transistor Mp1_i of the plurality of P-channel metal-oxide-semiconductor field-effect transistors Mp1_1 to Mp1_n is coupled to the source of the ith +1th P-channel metal-oxide-semiconductor field-effect transistor Mp1_i+1 of the plurality of P-channel metal-oxide-semiconductor field-effect transistors Mp1_1 to Mp1_n. Therefore, when the voltage on the power line PL exceeds the threshold, the plurality of pmos transistors mp1_1 to mp1_n may be turned on, so that the current flows to the second node N2 through the plurality of pmos transistors mp1_1 to mp1_n, thereby also turning on the nmos transistor Mn2.

Referring to fig. 4, fig. 4 is a schematic diagram of a voltage detection circuit according to a third embodiment of the application. The voltage detection circuit 16 of the third embodiment is also similar to the voltage detection circuit 16 of the second embodiment, so the same parts of the two embodiments will not be repeated. It should be noted that, unlike the second embodiment which uses a plurality of pmos field effect transistors mp1_1 to mp1_n as the switches coupled between the power line PL and the second node N2, the third embodiment uses a plurality of nmos field effect transistors mn3_1 to mn3_n as the switches coupled between the power line PL and the second node N2. In other words, the voltage detection circuit 16 of the third embodiment includes a plurality of N-channel mosfets mn3_1 to mn3_n, a resistor R2, and an N-channel mosfet Mn2. The N-channel metal-oxide-semiconductor field effect transistors mn3_1 to mn3_n are connected in series between the power line PL and the second node N2.

Specifically, the drain of the first N-channel mosfet mn3_1 of the plurality of N-channel mosfets mn3_1 to mn3_n is coupled to the power line PL, and the source of the N-channel mosfet mn3_n of the plurality of N-channel mosfets mn3_1 to mn3_n is coupled to the second node N2. In addition, the gate and drain of each of the plurality of N-channel metal oxide semiconductor field effect transistors mn3_1 to mn3_n are coupled together, and the source of the i-th N-channel metal oxide semiconductor field effect transistor mn3_i of the plurality of N-channel metal oxide semiconductor field effect transistors mn3_1 to mn3_n is coupled to the drain of the i+1th N-channel metal oxide semiconductor field effect transistor mn3_i+1 of the plurality of N-channel metal oxide semiconductor field effect transistors mn3_1 to mn3_n. Therefore, when the voltage on the power line PL exceeds the threshold, the plurality of N-channel mosfets mn3_1 to mn3_n may be turned on, such that current flows through the plurality of N-channel mosfets mn3_1 to mn3_n to the second node N2, thereby also turning on the N-channel mosfets Mn2.

Referring to fig. 5, fig. 5 is a schematic diagram of a voltage detection circuit according to a fourth embodiment of the application. Unlike the first embodiment, the fourth embodiment uses a P-channel mosfet Mp2 instead of the resistor R2, and is coupled between the second node N2 and the ground line GL. In other words, the voltage detection circuit 16 of the fourth embodiment includes a plurality of diodes d_1 to d_n, a P-channel mosfet Mp2, and an N-channel mosfet Mn2. Specifically, the source of the pmos Mp2 is coupled to the second node N2, the drain of the pmos Mp2 is coupled to the ground line GL, and the gate and drain of the pmos Mp2 are coupled together. Since the principle of the P-channel mosfet Mp2 to replace the resistor R2 is well known to those skilled in the art, the details of the fourth embodiment will not be repeated.

Similarly, referring to fig. 6, fig. 6 is a schematic diagram of a voltage detection circuit according to a fifth embodiment of the application. Unlike the fourth embodiment, the fifth embodiment uses an N-channel mosfet Mn4 instead of the resistor R2, and is coupled between the second node N2 and the ground line GL. In other words, the voltage detection circuit 16 of the fifth embodiment includes a plurality of diodes d_1 to d_n and N-channel mosfets Mn2, mn4. Specifically, the drain of the N-channel mosfet Mn4 is coupled to the second node N2, the source of the N-channel mosfet Mn4 is coupled to the ground line GL, and the gate of the N-channel mosfet Mn4 is coupled to the power line PL. Since the operation principle of the N-channel mosfet Mn4 instead of the resistor R2 is well known to those skilled in the art, the details of the fifth embodiment will not be repeated.

On the other hand, the inverter 14 may be a static Complementary Metal Oxide Semiconductor (CMOS) inverter, but the application is not limited thereto. The static CMOS inverter includes P-channel mosfet Mp3 and N-channel mosfet Mn5. The source of the P-channel MOSFET Mp3 is coupled to the power line PL, the gate of the P-channel MOSFET Mp3 is coupled to the first node N1, and the drain of the P-channel MOSFET Mp3 is coupled to the gate of the N-channel MOSFET Mn1 through the third node N3. In addition, the source of the N-channel mosfet Mn5 is coupled to the ground line GL, the gate of the N-channel mosfet Mn5 is coupled to the gate of the P-channel mosfet Mp3, and the drain of the N-channel mosfet Mn5 is coupled to the third node N3. Since the operation principle of the static CMOS inverter is well known to those skilled in the art, the details thereof will not be repeated.

In addition, the switch 10 may be a P-channel mosfet or a PNP bipolar junction transistor in addition to an nmos or an NPN bipolar junction transistor. In this case, since the switch 10 is turned on in response to the control terminal receiving the low-level signal, the power clamp circuit 1 provided by the present application may further include an odd number of inverters coupled between the input terminal of the inverter 14 and the control terminal of the switch 10, so that the pmos or PNP bipolar junction transistor as the switch 10 can also be turned on to form a discharge path when EOS occurs. The odd number of inverters may be the same as inverter 14, but the application is not limited thereto.

In summary, the power clamp circuit of the present application has the beneficial effects that the first node is electrically connected to the ground line through the voltage detection circuit when EOS occurs, so that the low-potential signal from the ground line is input from the first node to the input terminal of the inverter, and the N-channel mosfet is turned on to form the discharge path.

While the preferred and practical embodiments of the present application have been disclosed, these embodiments are not intended to limit the present application, and those skilled in the art may make various changes to the technical features of the present application according to the explicit or implicit disclosure of the present application, and all such changes are within the patent protection Fan Wei sought herein, in other words, the patent protection scope of the present application shall be deemed to be as set forth in the claims of the present application.

Claims (10)

1. A power clamp circuit, the power clamp circuit coupled to an internal circuit of an integrated circuit via a power line and a ground line, the power clamp circuit comprising:

a switch coupled between the power line and the ground line;

a first resistor coupled between the power line and a first node;

a capacitor coupled between the first node and the ground line;

an inverter coupled between the first node and a control terminal of the switch, wherein an input terminal of the inverter is coupled to the first node, and an output terminal of the inverter is coupled to the control terminal of the switch; and

and the voltage detection circuit is coupled with the power line, the first node and the grounding line and is used for detecting the voltage of the power line, wherein the voltage detection circuit is used for electrically connecting the first node to the grounding line so that a low-potential signal from the grounding line is input into the input end of the inverter from the first node and then the switch is turned on to form a discharge path in response to detecting that the voltage of the power line exceeds a threshold value.

2. The power clamp circuit of claim 1, wherein the switch is a first nmos having a drain coupled to the power line, a source coupled to the ground line, and a gate coupled to the output of the inverter as the control terminal.

3. The power clamp of claim 2, wherein the threshold is determined based on an sustainable voltage of the integrated circuit for an excessive electrical stress specification.

4. The power clamp circuit of claim 3, wherein said voltage detection circuit comprises:

the drain electrode of the second N-channel metal oxide semiconductor field effect transistor is coupled with the first node, the gate electrode of the second N-channel metal oxide semiconductor field effect transistor is coupled with the second node, and the source electrode of the second N-channel metal oxide semiconductor field effect transistor is coupled with the grounding wire.

5. The power supply clamp circuit of claim 4, wherein said voltage detection circuit further comprises:

a second resistor coupled between the second node and the ground line; and

a plurality of diodes connected in series between the power supply line and the second node.

6. The power clamp circuit of claim 5, wherein the number of the plurality of diodes is determined based on a threshold voltage of each of the plurality of diodes and a supply voltage supplied to the integrated circuit, the inverter is a static complementary metal oxide semiconductor inverter, and the inverter comprises:

a first pmos, wherein a source of the first pmos is coupled to the power line, a gate of the first pmos is coupled to the first node, and a drain of the first pmos is coupled to the gate of the first nmos through a third node; and

the source electrode of the third N-channel metal oxide semiconductor field effect transistor is coupled with the grounding wire, the gate electrode of the third N-channel metal oxide semiconductor field effect transistor is coupled with the gate electrode of the first P-channel metal oxide semiconductor field effect transistor, and the drain electrode of the third N-channel metal oxide semiconductor field effect transistor is coupled with the third node.

7. The power supply clamp circuit of claim 4, wherein said voltage detection circuit further comprises:

a second resistor coupled between the second node and the ground line; and

the first P-channel metal-oxide-semiconductor field effect transistors are connected in series between the power line and the second node;

wherein the inverter is a static complementary metal oxide semiconductor inverter and comprises:

a second pmos, wherein a source of the second pmos is coupled to the power line, a gate of the second pmos is coupled to the first node, and a drain of the second pmos is coupled to the gate of the first nmos through a third node; and

the source electrode of the third N-channel metal oxide semiconductor field effect transistor is coupled with the grounding wire, the gate electrode of the third N-channel metal oxide semiconductor field effect transistor is coupled with the gate electrode of the second P-channel metal oxide semiconductor field effect transistor, and the drain electrode of the third N-channel metal oxide semiconductor field effect transistor is coupled with the third node.

8. The power supply clamp circuit of claim 4, wherein said voltage detection circuit further comprises:

a second resistor coupled between the second node and the ground line; and

the third N-channel metal-oxide-semiconductor field effect transistors are connected in series between the power line and the second node;

wherein the inverter is a static complementary metal oxide semiconductor inverter and comprises:

a first pmos, wherein a source of the first pmos is coupled to the power line, a gate of the first pmos is coupled to the first node, and a drain of the first pmos is coupled to the gate of the first nmos through a third node; and

and a fourth N-channel metal-oxide-semiconductor field effect transistor, wherein a source electrode of the fourth N-channel metal-oxide-semiconductor field effect transistor is coupled with the grounding wire, a gate electrode of the fourth N-channel metal-oxide-semiconductor field effect transistor is coupled with the gate electrode of the first P-channel metal-oxide-semiconductor field effect transistor, and a drain electrode of the fourth N-channel metal-oxide-semiconductor field effect transistor is coupled with the third node.

9. The power supply clamp circuit of claim 4, wherein said voltage detection circuit further comprises:

a first pmos, wherein a source of the first pmos is coupled to the second node, a drain of the first pmos is coupled to the ground line, and a gate of the first pmos and the drain are coupled together; and

a plurality of diodes connected in series between the power line and the second node;

wherein the inverter is a static complementary metal oxide semiconductor inverter and comprises:

a second pmos, wherein a source of the second pmos is coupled to the power line, a gate of the second pmos is coupled to the first node, and a drain of the second pmos is coupled to the gate of the first nmos through a third node; and

the source electrode of the third N-channel metal oxide semiconductor field effect transistor is coupled with the grounding wire, the gate electrode of the third N-channel metal oxide semiconductor field effect transistor is coupled with the gate electrode of the second P-channel metal oxide semiconductor field effect transistor, and the drain electrode of the third N-channel metal oxide semiconductor field effect transistor is coupled with the third node.

10. The power supply clamp circuit of claim 4, wherein said voltage detection circuit further comprises:

a third N-channel mosfet, wherein a drain of the third N-channel mosfet is coupled to the second node, a source of the third N-channel mosfet is coupled to the ground line, and a gate of the third N-channel mosfet is coupled to the power line; and

a plurality of diodes connected in series between the power line and the second node;

wherein the inverter is a static complementary metal oxide semiconductor inverter and comprises:

a first pmos, wherein a source of the first pmos is coupled to the power line, a gate of the first pmos is coupled to the first node, and a drain of the first pmos is coupled to the gate of the first nmos through a third node; and

and a fourth N-channel metal-oxide-semiconductor field effect transistor, wherein a source electrode of the fourth N-channel metal-oxide-semiconductor field effect transistor is coupled with the grounding wire, a gate electrode of the fourth N-channel metal-oxide-semiconductor field effect transistor is coupled with the gate electrode of the first P-channel metal-oxide-semiconductor field effect transistor, and a drain electrode of the fourth N-channel metal-oxide-semiconductor field effect transistor is coupled with the third node.