CN117082752A - Fine circuit board processing method - Google Patents
Fine circuit board processing method Download PDFInfo
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- CN117082752A CN117082752A CN202311141226.9A CN202311141226A CN117082752A CN 117082752 A CN117082752 A CN 117082752A CN 202311141226 A CN202311141226 A CN 202311141226A CN 117082752 A CN117082752 A CN 117082752A
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
- H05K3/424—Plated through-holes or plated via connections characterised by electroplating method by direct electroplating
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention provides a fine circuit board processing method, which takes a single-layer or multi-layer circuit board as a core board substrate, and a photosensitive heat-resistant insulating resin adhesive film is arranged on at least one surface of the core board substrate; forming holes at positions to be formed on the surface of a core board substrate with the photosensitive heat-resistant insulating resin adhesive film through film or direct exposure and development, and setting the photosensitive heat-resistant insulating resin adhesive film at other positions through high-temperature curing; simultaneously, carrying out metal coating on the hole wall and other positions of the hole to form a conductive seed crystal layer; pasting a dry film or coating liquid photoresist on the conductive seed crystal layer, and forming a corresponding loop pattern by an exposure development mode; and (3) carrying out pattern and hole filling electroplating on the exposed conductive seed crystal layer, removing the dry film or the liquid photoresist after electroplating, and carrying out flash etching to complete circuit manufacture and hole interconnection, thereby obtaining the multilayer circuit board. The invention does not need laser drilling, has simple implementation and improves the binding force between the metal layer and the hole wall.
Description
Technical Field
The invention belongs to the field of circuit board manufacturing, and particularly relates to a processing method of a fine circuit board.
Background
Due to the development of end products, the circuit boards and carrier lines are characterized by smaller widths/spacings and smaller and denser holes. In the manufacturing process of circuit boards and carrier boards, high-temperature hot-pressed insulating materials are generally used as build-up base materials, blind holes are formed through laser drilling, metal materials are compounded on one side or both sides of the base materials, and etching is performed on the metal materials to obtain the circuit boards. As examples of insulating substrates, rigid substrates (also known as hard sheets) may be used, such as one or more of organic polymeric rigid sheets, ceramic sheets (such as alumina, aluminum nitride), glass sheets, etc., which in turn may include one or more of BT, FR-4, PTFE, CTFE, FEP, PPE, elastomeric sheets, fiberglass cloth/ceramic filler reinforced sheets, which are sheets based on organic polymeric materials such as epoxy, modified epoxy, BT, CE, PTFE, PPO, etc., with fiberglass cloth/ceramic filler as the reinforcing phase. In addition, flexible sheets (also known as flexible sheets) such as organic polymer films, including one or more of PI, PTO, PC, PSU, PES, PPS, PS, PE, PP, PEI, PTFE, PEEK, PA, PET, PEN, LCP or PPA, may also be used as the insulating substrate.
In the prior art, the manufacturing method for manufacturing the circuit board or the flexible circuit board (including the PCB and the FPC) is to mechanically or laser drill holes on the copper-clad plate at first, and then obtain a circuit pattern on the copper-clad plate through processes such as exposure, development, etching and the like (commonly called as a subtractive method). The process needs to etch copper foil of the non-pattern part, and has the advantages of long process flow and high production cost. Moreover, metal is etched many times in the whole process flow, so that a large amount of sewage containing metal ions is generated, and the environment is seriously harmed. Also, because of the difficulty in manufacturing and laminating an ultra-thin copper foil in the lamination process, and because of the limitation of etching accuracyAnd manufacturing, resulting in difficulty in manufacturing fine wiring. Although semi-additive processes can be used to fabricate fine lines, hole metallization by laser drilling and electroless copper deposition is still required. In forming single or multi-layer circuit boards with metallized holes, laser drilling techniques, including CO, are currently only used if holes with a hole diameter of less than 100 μm are to be drilled in the substrate 2 Infrared laser drilling and Nd: YAG ultraviolet laser drilling (UV laser drilling for short). The organic polymer material has no obvious difference in light absorption of different wavelengths, the copper foil and the glass fiber have very different light absorption rates of different frequencies, and have higher ultraviolet light absorption rate and lower infrared light absorption rate.
CO 2 After infrared laser is absorbed by workpiece, the temp. of material rises in very short time, and gasification is "hot working", and the output light spot size is proportional to light wavelength (generally lambda CO2 =9.4 μm), CO 2 The minimum aperture of the infrared laser is above 75 μm. CO 2 There are two main paths for infrared laser drilling to process the micropores. Firstly, directly laser drilling copper foil with copper, firstly thinning the copper foil of a part to be drilled, then brown-oxidizing, and then using CO 2 Drilling by infrared laser, and then copper deposition and electroplating are carried out after drilling. The number of steps increases, and the processing cost increases. The second is that copper at the punching position is etched away by the pattern transferring mode of film pasting, exposure and development without copper reduction and browning in a window opening mode, and then CO is used 2 Drilling by using infrared laser. The number of steps is also large, and the processing cost increases. CO 2 The infrared laser has some defects such as insufficient combustion, residual organic carbide at the bottom of a blind hole, excessive ablation of the wall of the hole with improper energy control to form a drum shape, protruding glass fiber and the like
The UV laser breaks the molecular bond of organic molecules, the metal bond of metal crystals and the ionic bond of inorganic matters by utilizing ultraviolet chemical energy to form small particles or atoms and molecular groups, and the small particles or atoms and molecular groups are taken away by vacuum adsorption, thus the UV laser belongs to cold working. Although UV laser can directly punch holes on the surface of a non-browned or 'windowed' copper foil, the UV laser belongs to rotary hole forming, the punching efficiency is low, and the UV laser becomes a bottleneck process in the whole process flow, lambda UV =0.355 μm, only 30-50 μm holes can be punched, and when the pore diameter is smaller than 30 μm, it is difficult to realize or the realization cost is extremely high. When the micro-holes are metallized, the infiltration and exchange of the liquid medicine are poor, the binding force between the copper layer and the hole wall is poor, and the thickness non-uniformity is increased.
The field has continuous demands for a circuit board and a carrier board processing method which are simple to implement, low in production cost, environment-friendly, micro-porous and high in binding force between high-precision circuits and base materials.
Disclosure of Invention
The invention aims to solve the technical problems that: the fine circuit board processing method is free from laser drilling, simple in implementation and capable of improving the binding force between the metal layer and the hole wall.
The technical scheme adopted by the invention for solving the technical problems is as follows: a fine circuit board processing method comprises the following steps:
s1, taking a single-layer or multi-layer circuit board as a core board substrate, and arranging a photosensitive heat-resistant insulating resin adhesive film on at least one surface of the core board substrate;
s2, forming holes at positions to be formed on the surface of a core board substrate with the photosensitive heat-resistant insulating resin adhesive film through film or direct exposure and then developing, and setting the photosensitive heat-resistant insulating resin adhesive films at other positions through photo-curing reaction and high-temperature curing; the holes comprise through holes and/or blind holes;
s3, simultaneously carrying out metal coating on the hole wall and other positions of the hole to form a conductive seed crystal layer;
s4, pasting a dry film or coating a liquid photoresist on the conductive seed crystal layer, and forming a corresponding loop pattern in an exposure and development mode, so that one part of the conductive seed crystal layer is covered by the dry film or the liquid photoresist, the other part of the conductive seed crystal layer is exposed, and the positions with holes are all exposed;
and S5, carrying out pattern and hole filling electroplating on the exposed conductive seed crystal layer, removing a dry film or a liquid photoresist after the electroplating is completed, and carrying out flash etching to complete circuit manufacture and hole interconnection, thereby obtaining the multilayer circuit board.
According to the scheme, the method further comprises the step of S6, wherein the multilayer circuit board obtained in the step of S5 is used as a core board base material, and the steps of S1-S5 are repeated one or more times to obtain the final multilayer circuit board.
According to the above scheme, the pore diameter of the pore described in S2 is 5-2000. Mu.m.
According to the scheme, the metal coating is carried out by the S3 through the processes of chemical plating, sputtering plating, arc ion plating or ion implantation coating.
According to the scheme, the thickness of the conductive seed crystal layer is 80nm-2000nm.
According to the scheme, in the step S3, when electroless plating is adopted, the metal is Pd+Cu or Ag+Cu;
when sputtering plating is adopted, other metals except Cu are selected as bottom metal, and are matched with Cu to form a two-layer or multi-layer structure, wherein the other metals are one or more of Ni, niCr, niCu alloy, ti, tiN compound, tiW alloy, ta, taN compound and Zr, cr, al, mo, moTi alloy.
According to the scheme, the photosensitive heat-resistant insulating resin adhesive film is a PSPI adhesive film or an acrylic/methacrylic resin photosensitive adhesive film.
According to the scheme, the thin conductive seed layer is formed by adopting sputtering plating in the step S3, and then the conductive seed layer is thickened to a certain thickness by electroplating in the step S5, wherein the certain thickness is prepared according to the productivity, the cost and the process window.
According to the scheme, the S3 is used for carrying out partial film plating, and only partial conductive seed crystal layers are formed; and S5, performing pattern + hole filling electroplating only in the area with the conductive seed crystal layer to finish partial layer adding.
A fine circuit board is obtained by the fine circuit board processing method.
The beneficial effects of the invention are as follows: the method adopts a photosensitive heat-resistant insulating resin adhesive film exposure development mode to replace the conventional laser drilling, so that the holes with metal hole walls with smaller apertures can be obtained, a circuit board with higher fineness can be manufactured, the circuit board can be molded at one time, the method is simple to implement, the generated waste is less, and the method is suitable for double-layer or multi-layer circuit boards with high fineness. The photosensitive heat-resistant insulating resin adhesive film is cured and shaped at high temperature, so that the adhesive film is attached to the surface of the core board base material, and the defect of poor bonding force is overcome.
Drawings
Fig. 1 is a flowchart of a method according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a product corresponding to the steps of the method shown in fig. 1.
In the figure: 1-substrate, 2-inner layer circuit, 3-photosensitive heat-resistant insulating resin film, 4-blind hole, 5-conductive seed layer, 6-dry film and 7-electroplated metal layer.
Detailed Description
The invention will be further described with reference to specific examples and figures.
Embodiment one:
the steps of this embodiment are specifically as follows:
confirming that a double-sided circuit board is to be manufactured, directly exposing PIC base material of a photosensitive development type cover film (Photo imageable Coverlay) through a film or LDI with a hole site, then developing and removing resin of a part to be formed with the hole, and forming a hole with the diameter of 5-2000 mu m; and further curing to make it completely react and form.
Coating a conductive seed crystal layer on the surface and the hole wall of the PIC substrate in an electroless copper plating or router mode or other film forming modes, wherein the thickness of the conductive seed crystal layer is 80-2000 nm; the thickness of the conductive seed layer has a large relation with pretreatment before electroplating in the post-process, electroplating and flash etching, and if the thickness is too thin, the conductive seed layer may be etched by electroplating pretreatment liquid medicine or electroplating technology, and cannot play a role in conducting electricity in the electroplating process, if the thickness is too thick, the final flash etching is not clean or the line width is out of standard, and in view of the fact that the thickness of the conductive seed layer is strongly related to the three-step technology, the thickness is limited in the range, and the thickness of the conductive seed layer can be preferably 800nm. The metal of the conductive seed layer can be Cu or Cu matched with one or more layers of Ta, taN/Ta alloy, tiN, tiW, cr, ti, mo, moTi alloy, ni, niCu and other metals. If a copper electroless plating method is adopted, a metal of Cu can be selected, if a Sputter or other dry plating methods are adopted, other metals except Cu can be selected as bottom metal to be matched with Cu to form a two-layer structure, the two-layer structure of the bottom Ni upper Cu can be selected as a preferable scheme, and the total thickness can be 800nm; considering the cost of the Sputter approach, it is also possible to deposit thinner Ni/Cu to 150nm and then thicken it to 800nm by electroplating, which can be tailored according to throughput and cost and process window.
And pasting a dry film or coating liquid photoresist on the surface of the conductive thickening layer, exposing and developing in sequence to expose the circuit part and the hole, and covering the rest by the dry film or the liquid photoresist. Pattern plating and plating Kong Zenghou, wherein the copper thickness of the exposed circuit part is increased to more than 15 mu m by electroplating, then the dry film is removed by alkali liquor, and the conductive layer which is not electroplated and thickened is etched off by differential etching, so that the circuit pattern is obtained.
Embodiment two:
as shown in fig. 1, the method of this embodiment includes the following steps:
s1, taking a single-layer or multi-layer circuit board as a core board substrate.
As shown in fig. 2 (a), in the present embodiment, the core substrate includes a BT substrate 1 and an inner layer wiring 2, the inner layer wiring 2 being provided on both upper and lower sides of the BT substrate 1. The core substrate may also be a two-layer, four-layer, six-layer or even more layer core.
S2, setting a photosensitive heat-resistant insulating resin adhesive film on at least one surface of the core board base material. The photosensitive heat-resistant insulating resin adhesive film belongs to a photosensitive polymerization reaction resin system, and is prepared by ultraviolet radiation curing to decompose an initiator to generate active free radicals or active ions capable of initiating polymerization, and initiating polymerization of monomers and oligomers to form an insoluble polymer layer. Representative examples thereof include an acrylic epoxy resin (PIC main component) and a bisbenzocyclobutene compound (PSPI main component) having an imide structure.
As shown in fig. 2 (b), a photosensitive heat-resistant insulating resin film 3 is vacuum-applied to both upper and lower surfaces. The photosensitive heat-resistant insulating resin adhesive film can be a dry film material with hot-pressing property, such as PIC adhesive film, and can be attached to the surface of the circuit board after exposure, development and heat drying; the photosensitive coating film can also be a photosensitive coating film, has the characteristics of coating and drying, such as PSPI slurry, can be attached to the surface of a circuit board after exposure, development and heat drying; the paste and dry film of photosensitive acrylic material can be used, and the material is also widely applied to display panels as a flat layer material or other organic materials which can be coated and cured.
S3, forming holes at positions to be formed by film or direct exposure and development on the surface of the core board substrate with the photosensitive heat-resistant insulating resin adhesive film, and curing and shaping the photosensitive heat-resistant insulating resin adhesive film at other positions except the holes at high temperature through a photo-curing reaction; the holes include through holes and/or blind holes. The high temperature means a temperature at which the cured product can be formed, and is not particularly limited.
In this embodiment, as shown in FIG. 2 (c), the hole site is directly exposed to light through a film or LDI, and then Na is used 2 CO 3 Removing resin of a part to be formed by development to form blind holes 4 with the diameter of 10-2000 mu m; and further curing at 150 ℃ to fully react and shape the photosensitive heat-resistant insulating resin adhesive film.
Here, the hole is set according to the actual situation, and may be a through hole or a blind hole. For example, holes communicated with the upper surface and the lower surface are required to be formed directly on the substrate, and the through holes can be formed on only one surface through exposure and development for the thickness of the substrate less than or equal to 50 mu m, or the holes can be formed on two surfaces through exposure and development at the same position at the same time for the thickness of the substrate more than 50 mu m, and then the holes are just communicated.
S4, simultaneously carrying out metal coating on the hole wall and other positions of the hole to form a conductive seed crystal layer.
In this embodiment, as shown in fig. 2 (d), the surface and the hole wall of the PIC substrate are coated with a conductive seed layer 5 having a thickness of 80nm to 2000nm by electroless copper plating or sputtering or other film forming methods. The thickness of the conductive seed layer 5 has a large relation with the pretreatment before the electroplating of the post-process, and the electroplating and the flash etching, and if the thickness is too thin, the conductive seed layer may be etched away by the electroplating pretreatment or the electroplating process, and cannot play a role in the electroplating process, if the thickness is too thick, the flash etching is too much to cause the flash etching to be incomplete or the line width and line spacing to be out of standard, and in view of the strong correlation of the thickness of the conductive seed layer 5 with the three steps, the thickness is limited in this range, and in this embodiment, the thickness of the conductive seed layer 5 may be preferably 800nm.
The metal of the conductive seed layer 5 may be Cu or Cu collocated with one or more layers of one or more metals of Ni, niCr, niCu alloy, ti, tiN compound, tiW alloy, ta, taN compound, zr, cr, al, mo, moTi alloy. If a copper electroless plating method is adopted, one metal of Cu, pd+Cu or Ag+Cu can be optimized, if a Sputter or other dry plating methods are adopted, other metals except Cu can be selected as bottom metal to be matched with Cu to form a two-layer structure, the two-layer structure of the upper Cu of the bottom Ni can be optimized as an optimized scheme, and the total thickness can be 1000nm; considering the cost of the Sputter approach, it is also possible to deposit thinner Ni/Cu to 200nm and then electroplate to thicken to 1000nm, which can be tailored according to throughput and cost and process window.
The sputtering plating can be magnetron sputtering plating and high-power pulse magnetron sputtering. In addition, arc ion plating and the like can be used.
Further preferably, the plating can be accomplished by ion implantation plating technology, and electroless copper plating or Sputer is not necessarily needed. I.e. first chemical bonds or interstitial structures are formed between the implanted ions of the conductive material and the molecules of the material of the insulating layer, thereby obtaining modified doping structures and active groups. And then carrying out high-power pulse magnetron sputtering on the ion-implanted modified surface through a magnetic filtration cathode vacuum arc, and obtaining the conductive seed crystal layer 5 with uniform and compact texture on the upper and lower surfaces of the PIC substrate subjected to ion implantation and the hole wall. This can avoid insufficient bonding force due to roughness or material.
S5, pasting a dry film or coating liquid photoresist on the conductive seed crystal layer.
As shown in fig. 2 (e), the dry film 6 is directly attached to the conductive seed layer 5, or alternatively, a liquid photoresist may be applied.
S6, as shown in fig. 2 (f), a corresponding loop pattern is formed by an exposure and development mode, so that one part of the conductive seed layer 5 is covered by the dry film 6 or the liquid photoresist, the other part of the conductive seed layer 5 is exposed, and the positions with holes are all exposed.
And S7, as shown in fig. 2 (g), performing pattern + hole filling electroplating on the exposed conductive seed layer 5 to obtain an electroplated metal layer 7, so that the copper thickness of the finally exposed circuit part is increased to be more than 15 mu m, and the thickness of the electroplated metal layer 7 is determined according to the process setting.
And S8, after electroplating is completed, removing the dry film 6 or the liquid photoresist, and performing flash etching to complete circuit manufacture and hole interconnection, thereby obtaining the multilayer circuit board.
On the basis, the multilayer circuit board obtained in the step S8 is used as a core board base material, and the steps S1-S7 are repeated one or more times, so that the circuit board with more layers can be obtained.
Of course, according to actual needs, only part of the plating film can be performed, and only part of the conductive seed crystal layer can be formed; and then, carrying out pattern + hole filling electroplating only in the area with the conductive seed crystal layer to finish partial layer adding.
The embodiment also provides the circuit board processed by the method.
The processing method does not need laser drilling, has one-step molding of a common semi-additive method, can well adhere to the substrate, and has strong binding force between the substrates. In addition, the method is simple to implement, generates less waste, and can manufacture a circuit board with very high fineness; moreover, a high-quality double-layer or multi-layer circuit board with metallized holes and a carrier plate can be formed; when the composite board is used for processing a multilayer board, the composite board can be used for a Core layer, and can be fully or partially added on the Core layer, so that the application is greatly widened.
It will be understood that modifications and variations will be apparent to those skilled in the art from the foregoing description, and it is intended that all such modifications and variations be included within the scope of the following claims.
Claims (10)
1. A fine circuit board processing method is characterized in that: the method comprises the following steps:
s1, taking a single-layer or multi-layer circuit board as a core board substrate, and arranging a photosensitive heat-resistant insulating resin adhesive film on at least one surface of the core board substrate;
s2, forming holes at positions to be formed on the surface of a core board substrate with the photosensitive heat-resistant insulating resin adhesive film through film or direct exposure and then developing, and setting the photosensitive heat-resistant insulating resin adhesive films at other positions through photo-curing reaction and high-temperature curing; the holes comprise through holes and/or blind holes;
s3, simultaneously carrying out metal coating on the hole wall and other positions of the hole to form a conductive seed crystal layer;
s4, pasting a dry film or coating a liquid photoresist on the conductive seed crystal layer, and forming a corresponding loop pattern in an exposure and development mode, so that one part of the conductive seed crystal layer is covered by the dry film or the liquid photoresist, the other part of the conductive seed crystal layer is exposed, and the positions with holes are all exposed;
and S5, carrying out pattern and hole filling electroplating on the exposed conductive seed crystal layer, removing a dry film or a liquid photoresist after the electroplating is completed, and carrying out flash etching to complete circuit manufacture and hole interconnection, thereby obtaining the multilayer circuit board.
2. The fine wiring circuit board processing method according to claim 1, characterized in that: and S6, repeating the steps S1-S5 once or more times by taking the multilayer circuit board obtained in the step S5 as a core board base material, so as to obtain the final multilayer circuit board.
3. The fine wiring circuit board processing method according to claim 1 or 2, characterized in that: the pore diameter of the pore described in S2 is 5-2000 μm.
4. The fine wiring circuit board processing method according to claim 1 or 2, characterized in that: and S3, performing metal coating through a chemical plating, sputtering plating, arc ion plating or ion implantation coating process.
5. The fine wiring circuit board processing method according to claim 1 or 2, characterized in that: the thickness of the conductive seed crystal layer is 80nm-2000nm.
6. The fine wiring circuit board processing method according to claim 4, wherein: in the step S3, when chemical plating is adopted, the metal is Pd+Cu or Ag+Cu;
when sputtering plating is adopted, other metals except Cu are selected as bottom metal, and are matched with Cu to form a two-layer or multi-layer structure, wherein the other metals are one or more of Ni, niCr, niCu alloy, ti, tiN compound, tiW alloy, ta, taN compound and Zr, cr, al, mo, moTi alloy.
7. The fine wiring circuit board processing method according to claim 1 or 2, characterized in that: the photosensitive heat-resistant insulating resin adhesive film is PSPI adhesive film or acrylic acid/methacrylic acid resin photosensitive adhesive film.
8. The fine wiring circuit board processing method according to claim 1 or 2, characterized in that: and S3, forming a thinner conductive seed crystal layer by adopting sputtering plating, and then electroplating and thickening to a certain thickness in S5, wherein the certain thickness is prepared according to the productivity, the cost and the process window.
9. The fine wiring circuit board processing method according to claim 1 or 2, characterized in that: s3, performing partial coating to form only a part of conductive seed crystal layer; and S5, performing pattern + hole filling electroplating only in the area with the conductive seed crystal layer to finish partial layer adding.
10. A fine line circuit board, characterized in that: obtained by the fine wiring circuit board processing method according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311141226.9A CN117082752A (en) | 2023-09-05 | 2023-09-05 | Fine circuit board processing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311141226.9A CN117082752A (en) | 2023-09-05 | 2023-09-05 | Fine circuit board processing method |
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| CN202311141226.9A Pending CN117082752A (en) | 2023-09-05 | 2023-09-05 | Fine circuit board processing method |
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