CN117081561A - Open drain output circuit and chip - Google Patents
Open drain output circuit and chip Download PDFInfo
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- CN117081561A CN117081561A CN202311115385.1A CN202311115385A CN117081561A CN 117081561 A CN117081561 A CN 117081561A CN 202311115385 A CN202311115385 A CN 202311115385A CN 117081561 A CN117081561 A CN 117081561A
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- 238000010586 diagram Methods 0.000 description 7
- 101100524516 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA2 gene Proteins 0.000 description 6
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- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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Abstract
The application discloses an open drain output circuit and a chip, the open drain output circuit comprises: the MOS transistor comprises a first MOS transistor, a current source and a first resistor, wherein a first end of the current source is connected with an input node VIN, a second end of the current source is connected with a first node A, a control end of the first MOS transistor is connected with the first node A, the first end of the first MOS transistor is connected with the ground potential, the second end of the first MOS transistor is connected with an output node PG, the first end of the first resistor is connected with a power supply voltage VCC, and the second end of the first resistor is connected with the output node PG; the first control unit is connected with the first node A; the first end of the second resistor is connected with the output node PG, the second end of the second resistor is connected with the second node B, the control end of the sixth MOS transistor is connected with the second node B, the first end of the sixth MOS transistor is connected with the ground potential, and the second end of the sixth MOS transistor is connected with the output node PG; and the second control unit is connected with the second node B. The application can pull the potential of PG down under the condition of smaller VIN in the power-on process, and control the potential of PG below the logic level, thereby avoiding the erroneous judgment caused by the later-stage circuit.
Description
Technical Field
The application belongs to the technical field of integrated circuits, and particularly relates to an open-drain output circuit and a chip.
Background
In an integrated circuit, an Open Drain (OD) circuit is often used, which refers to a circuit using a drain of a MOS transistor as an output end, and can convert a control signal under a certain power supply voltage into a signal under another power supply voltage, which is commonly used for transmitting signals between different power supply modules in a power management chip.
Referring to fig. 1, a schematic diagram of an open-drain output circuit in the prior art is shown, which mainly includes devices such as an NMOS transistor MN1, a current source I, a first resistor R1, etc., wherein a first end of the current source is connected to an input node VIN, a second end of the current source is connected to a first node a, a gate of the NMOS transistor MN1 is connected to the first node a, a drain is connected to an output node PG, a source is connected to a ground potential GND, the first resistor R1 is a pull-up resistor, a first end of the first resistor is connected to a power supply voltage VCC, a second end of the first resistor is connected to the output node PG, and an under-voltage locking signal UVLO is connected to the first node a through a buffer BUF1 and an NMOS transistor MN2 to form a gate driving signal of MN 1.
The output node PG of the open drain output circuit is used to indicate specific signals, such as good power, failure, etc. However, in this circuit, when vin=0v, the signal of the first node a goes low, NM1 is in the off state, and even if VIN is not ready (vin=0v or 0 to 1V), the PG signal goes high, and is higher than the Logic level (Logic level), which may cause erroneous judgment of the subsequent circuit.
Therefore, in order to solve the above-mentioned problems, it is necessary to provide an open-drain output circuit and a chip.
Disclosure of Invention
Accordingly, the present application is directed to an open drain output circuit and a chip.
In order to achieve the above object, an embodiment of the present application provides the following technical solution:
an open drain output circuit, the open drain output circuit comprising:
the MOS transistor comprises a first MOS transistor, a current source and a first resistor, wherein a first end of the current source is connected with an input node VIN, a second end of the current source is connected with a first node A, a control end of the first MOS transistor is connected with the first node A, the first end of the first MOS transistor is connected with the ground potential, the second end of the first MOS transistor is connected with an output node PG, the first end of the first resistor is connected with a power supply voltage VCC, and the second end of the first resistor is connected with the output node PG;
the first control unit is connected with the first node A and is used for generating a first driving signal of the first MOS tube according to the first input signal;
the first end of the second resistor is connected with the output node PG, the second end of the second resistor is connected with the second node B, the control end of the sixth MOS transistor is connected with the second node B, the first end of the sixth MOS transistor is connected with the ground potential, and the second end of the sixth MOS transistor is connected with the output node PG;
and the second control unit is connected with the second node B and is used for generating a second driving signal of the sixth MOS tube according to the second input signal.
In an embodiment, the first MOS transistor is an NMOS transistor MN1, the control end of which is a gate, the first end is a source, and the second end is a drain.
In an embodiment, the first control unit includes a second MOS transistor, where the second MOS transistor is an NMOS transistor MN2, a source thereof is connected to a ground potential, and a drain thereof is connected to the first node a.
In an embodiment, the first control unit further includes a first buffer, an input end of which is connected to the first input signal, and an output end of which is connected to the gate of the NMOS MN 2.
In one embodiment, the open drain output circuit further comprises a clamp connected between the first node a and ground potential.
In an embodiment, the clamp is one or more of a MOS transistor, a resistor, and a diode.
In an embodiment, the sixth MOS transistor is an NMOS transistor MN6, the control end of which is a gate, the first end is a source, and the second end is a drain.
In an embodiment, the second control unit includes a seventh MOS transistor, where the seventh MOS transistor is an NMOS transistor MN7, and a source thereof is connected to the ground potential, and a drain thereof is connected to the second node B.
In an embodiment, the second control unit further includes a second buffer, an input end of which is connected to the second input signal, and an output end of which is connected to the gate of the NMOS MN 7.
The technical scheme provided by the other embodiment of the application is as follows:
a chip comprises the open drain output circuit.
The application has the following beneficial effects:
according to the application, the potential of PG can be pulled down under the condition of smaller VIN in the power-on process through the second resistor and the sixth MOS tube, and the potential of PG is controlled below the logic level, so that the error judgment caused by a later-stage circuit is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a schematic diagram of a prior art open drain output circuit;
FIG. 2 is a timing diagram illustrating the operation of the prior art open drain output circuit;
FIG. 3 is a schematic diagram of an open drain output circuit according to an embodiment of the application;
FIG. 4 is a timing diagram illustrating the operation of the open drain output circuit according to an embodiment of the present application.
Detailed Description
In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
Referring to fig. 1, a schematic diagram of an open-drain output circuit in the prior art is shown, including:
NMOS tube MN1, current source I and first resistor R1, the first end of current source I couples to input node VIN, the second end couples to first node A, the grid of NMOS tube MN1 couples to first node A, the first end couples to ground potential, the second end couples to output node PG, the first end of the first resistor R1 couples to power supply voltage VCC, the second end couples to output node PG;
the first control unit is connected with the first node A and is used for generating a first driving signal of the first MOS tube according to a first input signal, the first control unit comprises a first buffer BUF1 and an NMOS tube MN2, the source electrode of the NMOS tube MN2 is connected with the ground potential, the drain electrode of the NMOS tube MN2 is connected with the first node A, the input end of the first buffer BUF1 is connected with a first input signal UVLO, and the output end of the first buffer BUF1 is connected with the grid electrode of the NMOS tube MN 2.
In addition, a clamp is further included between the first node A and the ground potential, specifically NMOS transistors MN 3-MN 5, the gate and the drain of the NMOS transistor MN3 are connected with the first node A after being short-circuited, the gate and the drain of the NMOS transistor MN4 are connected with the source of the NMOS transistor MN3 after being short-circuited, the gate and the drain of the NMOS transistor MN5 are connected with the source of the NMOS transistor MN4 after being short-circuited, and the source of the NMOS transistor MN5 is connected with the ground potential.
Referring to fig. 2, which shows a timing chart of the prior art of the open drain output circuit, it is seen that, during the power-up process, the voltage of the input node VIN gradually increases from 0V to 12V, when VIN is 0-1V (before time T1), the first node a is at a low level, MN1 is in an off state, and even if VIN is not ready (vin=0v or 0-1V), the PG signal also becomes high (3.3V) and is higher than the logic level (1V); when VIN is 1-4V (T1-T2 time), MN1 is in a conducting state, and the output node PG is pulled down to a low level; when VIN is 4-12V (after time T2), the first input signal UVLO is turned from low level to high level, the first node a is high level, and the PG signal goes high (3.3V).
In the prior art, before the time T1, the output node PG is at a high level and is higher than a logic level, so that the post-stage TTL or CMOS circuit causes erroneous judgment.
Referring to fig. 2, a schematic diagram of an open drain output circuit according to an embodiment of the application is shown, including:
the MOS transistor comprises a first MOS transistor, a current source I and a first resistor R1, wherein the first end of the current source I is connected with an input node VIN, the second end of the current source I is connected with a first node A, the control end of the first MOS transistor is connected with the first node A, the first end of the first MOS transistor is connected with the ground potential, the second end of the first MOS transistor is connected with an output node PG, the first end of the first resistor R1 is connected with a power supply voltage VCC, and the second end of the first resistor R1 is connected with the output node PG;
the first control unit is connected with the first node A and is used for generating a first driving signal of the first MOS tube according to a first input signal UVLO;
the first end of the second resistor R2 is connected with the output node PG, the second end of the second resistor R2 is connected with the second node B, the control end of the sixth MOS tube is connected with the second node B, the first end of the sixth MOS tube is connected with the ground potential, and the second end of the sixth MOS tube is connected with the output node PG;
and the second control unit is connected with the second node B and is used for generating a second driving signal of the sixth MOS tube according to the second input signal OK.
Specifically, the first MOS transistor in this embodiment is an NMOS transistor MN1, the control end of which is a gate, the first end is a source, and the second end is a drain; the sixth MOS transistor is an NMOS transistor MN6, the control end of which is a grid electrode, the first end is a source electrode, and the second end is a drain electrode.
In addition, a clamp is further included between the first node A and the ground potential, specifically NMOS transistors MN 3-MN 5, the gate and the drain of the NMOS transistor MN3 are connected with the first node A after being short-circuited, the gate and the drain of the NMOS transistor MN4 are connected with the source of the NMOS transistor MN3 after being short-circuited, the gate and the drain of the NMOS transistor MN5 are connected with the source of the NMOS transistor MN4 after being short-circuited, and the source of the NMOS transistor MN5 is connected with the ground potential.
The clamp in this embodiment is used to clamp the voltage of the first node a to a lower potential when VIN is higher, and in other embodiments, the clamp may also use a resistor or a diode, which will not be described herein.
In this embodiment, the first control unit includes a second MOS transistor and a first buffer BUF1, the second MOS transistor is an NMOS transistor MN2, a source thereof is connected to a ground potential, a drain thereof is connected to the first node a, an input terminal of the first buffer BUF1 is connected to a first input signal UVLO, and an output terminal thereof is connected to a gate of the NMOS transistor MN 2.
In this embodiment, the second control unit includes a seventh MOS transistor and a second buffer BUF2, the seventh MOS transistor is an NMOS transistor MN7, the source thereof is connected to the ground potential, the drain thereof is connected to the second node B, the input end of the second buffer BUF2 is connected to the second input signal OK, and the output end thereof is connected to the gate of the NMOS transistor MN 7.
Referring to fig. 4, a timing chart of the operation of the open drain output circuit in this embodiment is shown, and the working principle thereof is as follows:
the voltage at the input node VIN is increased from 0V before time T1Up to 1V, the first node a is low, UVLO is low, MN2 is off, OK is low, MN7 is off, the second resistor R2 can make the second node B equal to the voltage (3.3V) of PG upwards, MN6 is on, thereby keeping the voltage of PG equal to V of MN6 GS V of MN6 in the present embodiment GS 0.7V, below logic level (1V);
at times T1-T3, the voltage of the input node VIN increases from 1V to 4V, uvlo is low, PG is low, and the first node a increases from 0V to 5V, where at times T1-T2, OK is low, the second node B is high (0.7V), at times T2-T3, VIN has risen sufficiently, OK is high, and the second node B is low (0V), thereby turning off MN6.
It can be seen that the potential of PG can be controlled to V of MN6 by MN6 and R2 before time T1 in the present embodiment GS (about 0.7V) below the logic level, and will not cause misjudgment of the post-stage TTL or CMOS circuit.
Preferably, under normal operation, current will reach GND through R2, and R2 may be selected to have as large a resistance as possible to reduce power consumption.
The back-end circuit comprises a positive logic circuit (low level is 0, high level is 1) and a negative logic circuit (low level is 1, high level is 0), and the open-drain output circuit is only applicable to the back-end circuit which is the positive logic circuit.
As can be seen from the technical scheme, the application has the following advantages:
according to the application, the potential of PG can be pulled down under the condition of smaller VIN in the power-on process through the second resistor and the sixth MOS tube, and the potential of PG is controlled below the logic level, so that the error judgment caused by a later-stage circuit is avoided.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (10)
1. An open drain output circuit, the open drain output circuit comprising:
the MOS transistor comprises a first MOS transistor, a current source and a first resistor, wherein a first end of the current source is connected with an input node VIN, a second end of the current source is connected with a first node A, a control end of the first MOS transistor is connected with the first node A, the first end of the first MOS transistor is connected with the ground potential, the second end of the first MOS transistor is connected with an output node PG, the first end of the first resistor is connected with a power supply voltage VCC, and the second end of the first resistor is connected with the output node PG;
the first control unit is connected with the first node A and is used for generating a first driving signal of the first MOS tube according to the first input signal;
the first end of the second resistor is connected with the output node PG, the second end of the second resistor is connected with the second node B, the control end of the sixth MOS transistor is connected with the second node B, the first end of the sixth MOS transistor is connected with the ground potential, and the second end of the sixth MOS transistor is connected with the output node PG;
and the second control unit is connected with the second node B and is used for generating a second driving signal of the sixth MOS tube according to the second input signal.
2. The open drain output circuit of claim 1, wherein the first MOS transistor is an NMOS transistor MN1, the control terminal is a gate, the first terminal is a source, and the second terminal is a drain.
3. The open drain output circuit according to claim 2, wherein the first control unit includes a second MOS transistor, the second MOS transistor is an NMOS transistor MN2, a source thereof is connected to a ground potential, and a drain thereof is connected to the first node a.
4. The open drain output circuit of claim 3, wherein the first control unit further comprises a first buffer having an input coupled to the first input signal and an output coupled to the gate of the NMOS transistor MN 2.
5. The open drain output circuit of claim 1, further comprising a clamp connected between the first node a and ground potential.
6. The open drain output circuit of claim 5, wherein the clamp is one or more of a MOS transistor, a resistor, and a diode.
7. The open drain output circuit of claim 1, wherein the sixth MOS transistor is an NMOS transistor MN6, the control terminal of which is a gate, the first terminal is a source, and the second terminal is a drain.
8. The open drain output circuit of claim 7, wherein the second control unit comprises a seventh MOS transistor MN7, the source of which is connected to the ground potential and the drain of which is connected to the second node B.
9. The open drain output circuit of claim 8, wherein the second control unit further comprises a second buffer having an input coupled to the second input signal and an output coupled to the gate of the NMOS transistor MN 7.
10. A chip comprising the open drain output circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311115385.1A CN117081561A (en) | 2023-08-31 | 2023-08-31 | Open drain output circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311115385.1A CN117081561A (en) | 2023-08-31 | 2023-08-31 | Open drain output circuit and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117081561A true CN117081561A (en) | 2023-11-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311115385.1A Pending CN117081561A (en) | 2023-08-31 | 2023-08-31 | Open drain output circuit and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117081561A (en) |
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2023
- 2023-08-31 CN CN202311115385.1A patent/CN117081561A/en active Pending
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