CN117081510A - Low Noise Amplifier (LNA) with distortion and noise cancellation - Google Patents

Abstract

Low Noise Amplifiers (LNAs) with distortion and noise cancellation are disclosed. In one aspect, an LNA may have distortion cancellation implemented orthogonally with respect to noise cancellation such that changes in the distortion cancellation do not affect the noise cancellation. In further exemplary aspects, cancellation circuitry is added in parallel to the main LNA path or the main LNA path. The cancellation circuitry may include an initial impedance matching amplifier that achieves noise cancellation and a second amplifier that achieves distortion cancellation. Variations in placement and composition of the second amplifier are provided. By providing a second path that allows for independent control of noise and distortion cancellation, the overall performance of the LNA is improved.

Description

Low Noise Amplifier (LNA) with distortion and noise cancellation

Priority claim

The present application claims priority from U.S. provisional patent application No. 63/375,064, entitled "low noise amplifier with distortion and noise cancellation (LNA) (LOW NOISE AMPLIFIER (LNA) WITH DISTORTION AND NOISE CANCELLATION)", filed 9 at 2022, the contents of which are incorporated herein by reference in their entirety.

The present application claims priority from U.S. provisional patent application No. 63/342,678 entitled "COMPACT non-INDUCTOR LNA with two-way distortion cancellation and active INPUT matching with noise cancellation" (COMPACT INPUT-LESS LNA WITH DUAL-PATH DISTORTION CANCELLATION AND ACTIVE INPUT MATCH WITH NOISE CANCELLATION) "filed on 5 month 17 of 2022, the contents of which are incorporated herein by reference in their entirety.

The present application also claims priority from U.S. patent application Ser. No. 18/298,426, entitled "inductor-less self-tuning INPUT match LOW NOISE amplifier with very LOW NOISE figure and Gm boost (INDUCTORLESS SELF-TUNED INPUT LOW-NOISE AMPLIFIER WITH VERY LOW NOISE FIGURE AND Gm BOOST)" filed on month 4 of 2023. U.S. patent application Ser. No. 18/298,426 claims the benefit of U.S. provisional patent application Ser. No. 63/375,064, U.S. provisional patent application Ser. No. 63/400,502, U.S. provisional patent application Ser. No. 63/342,678, U.S. provisional patent application Ser. No. 2022, 9, and 24. The disclosures of all of these applications are hereby incorporated by reference in their entirety.

Technical Field

The technology of the present disclosure generally relates to low noise amplifiers that may be present in a receiver or transceiver, for example.

Background

In modern society, computing devices are of all kinds, and more particularly mobile communication devices are becoming more and more common. The popularity of these mobile communication devices is driven in part by the many functions that are currently enabled on such devices. The increase in processing power in such devices means that mobile communication devices have evolved from pure communication tools to complex mobile entertainment centers, enabling enhanced user experience. With the advent of the variety of functions available to such devices, there is increasing pressure to find ways to improve data transfer, for example by increasing the data transfer rate. One common way to increase the data transfer rate is by increasing the carrier frequency at which data is transferred compared to previous generations of cellular technology, as evidenced by the frequency range used by the fifth generation new radio (5G-NR) cellular technology. With these higher frequencies, additional demands are placed on the amplifiers in both the transmit and receive chains of the transceiver. These additional requirements provide room for innovation.

Disclosure of Invention

Aspects disclosed in the detailed description include a Low Noise Amplifier (LNA) with distortion and noise cancellation. In an exemplary aspect, the LNA may have distortion cancellation implemented orthogonally with respect to noise cancellation such that changes in distortion cancellation do not affect noise cancellation. In further exemplary aspects, cancellation circuitry is added in parallel to the main LNA path or the main LNA path. The cancellation circuitry may include an initial impedance matching amplifier that achieves noise cancellation and a second amplifier that achieves distortion cancellation. Variations in placement and composition of the second amplifier are provided. By providing a second path that allows for independent control of noise and distortion cancellation, the overall performance of the LNA is improved.

In this regard, in one aspect, a Power Amplifier (PA) module is disclosed. The PA module includes a first path coupling an input node and an output node, the first path including an LNA. The PA module further includes a second path that couples the input node and the output node. The second path is electrically parallel to the first path. The second path includes cancellation circuitry. The cancellation circuitry includes a noise cancellation circuit and a distortion cancellation circuit.

In another aspect, a low noise amplification system is disclosed. The low noise amplification system includes a first signal path including an amplification path. The low noise amplification system also includes a second signal path including a cancellation path configured to cancel noise and distortion independently. The means in the amplification path is configured to produce a distortion having a first value and a first sign, and the means in the second signal path is configured to produce a distortion having a substantially first value and a second sign opposite the first sign.

Drawings

FIG. 1 is a block diagram of an exemplary amplifier module having two paths, wherein a first path contains a Low Noise Amplifier (LNA) stage and a second path contains cancellation circuitry, according to an exemplary aspect of the present disclosure;

FIG. 2A is a more detailed diagram of the amplifier module of FIG. 1, showing noise cancellation circuitry and distortion cancellation circuitry in a second path and a summing point after the LNA stage;

FIG. 2B is a more detailed diagram of the amplifier module of FIG. 1, showing noise cancellation circuitry and distortion cancellation circuitry in a second path and summing points within the LNA stage;

FIG. 3 is a more detailed diagram of the amplifier module of FIG. 2A in which two distortion cancellation circuits are connected in series to cancel second and third order distortions;

FIG. 4 is a more detailed diagram of the amplifier module of FIG. 2A in which two distortion cancellation circuits are connected in parallel to cancel second and third order distortions;

FIG. 5 is a more detailed diagram of the amplifier module of FIG. 2A in which three distortion cancellation circuits are used to cancel second and third order distortions;

FIG. 6A is a first exemplary aspect of a noise cancellation circuit;

FIG. 6B is a second exemplary aspect of a noise cancellation circuit;

FIG. 7A is a first exemplary aspect of a distortion cancellation circuit;

FIG. 7B is a second exemplary aspect of a distortion cancellation circuit;

FIG. 8 is a block diagram of the amplifier module of FIG. 2B, showing how internal summing may be arranged;

FIG. 9 is a circuit diagram of the amplifier module of FIG. 3 provided to facilitate how this structure may be instantiated;

FIG. 10 is a block diagram of exemplary aspects in which additional distortion cancellation is provided by a cascode element within the LNA stage;

FIG. 11 is a block diagram highlighting an alternative aspect of the amplifier module of FIG. 8 for current reuse; and

fig. 12 is a block diagram illustrating details of an inductor-based summing circuit of the amplifier module of fig. 2A.

Detailed Description

The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "over" or "extending over" another element, it can extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly on" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Aspects disclosed in the detailed description include a Low Noise Amplifier (LNA) with distortion and noise cancellation. In an exemplary aspect, the LNA may have distortion cancellation implemented orthogonally with respect to noise cancellation such that changes in distortion cancellation do not affect noise cancellation. In further exemplary aspects, cancellation circuitry is added in parallel to the main LNA path or the main LNA path. The cancellation circuitry may include an initial impedance matching amplifier that achieves noise cancellation and a second amplifier that achieves distortion cancellation. Variations in placement and composition of the second amplifier are provided. By providing a second path that allows for independent control of noise and distortion cancellation, the overall performance of the LNA is improved.

It should be appreciated that LNAs typically have "low noise," overall linear operation over the frequencies of interest, and desired performance characteristics of an overall low power usage profile (particularly for mobile computing applications). Against these desirable performance characteristics are the inherent nonlinearity and noise of the transistors used to provide the main amplification within the LNA. Conventional approaches are typically current intensive and use relatively large inductors to compensate for noise. Such methods are expensive and may destroy the desired power consumption level. Similarly, such methods typically compensate for noise at the expense of distortion and vice versa, as the compensation circuits are shared, resulting in a tradeoff of cancellation.

Exemplary aspects of the present disclosure provide an inductor-less technique to provide independent or quadrature control of circuitry to provide distortion cancellation and noise cancellation. This cancellation circuitry is disposed in a path in parallel with the main LNA path, and may take various configurations.

In this regard, fig. 1 is a block diagram of an amplifier module 100 that may operate as an LNA stage within a receive chain of a transceiver or the like. The amplifier module 100 includes an input node 102 and an output node 104. The amplifier module 100 additionally includes a primary path, main path, or first path 106 between the input node 102 and the output node 104. The amplifier module 100 additionally includes a second path 108 between the input node 102 and the output node 104. The first path 106 and the second path 108 may be joined at the output node 104 by a summing circuit 110.

With continued reference to fig. 1, the first path 106 may include a main LNA 112. Similarly, the second path 108 may include cancellation circuitry 114. The use of the second path 108 and the cancellation circuitry 114 allows for the removal of off-chip sensors, thereby saving space and power. Furthermore, the use of the second path 108 allows current reuse, as will be explained in more detail below. Further details are provided in subsequent figures.

In this regard, fig. 2A provides some additional details regarding cancellation circuitry 114. In particular, the cancellation circuitry 114 may include a noise cancellation amplifier 200 (also referred to as Zamp in the figure) that provides impedance matching such that the main LNA 112 presents a standard impedance (e.g., 50 ohms (Ω)) at the input node 102. The cancellation circuitry 114 may additionally include a distortion cancellation amplifier 202 that may provide opposite sign distortion relative to the main LNA 112. As with fig. 1, the summing circuit 110 occurs after the main LNA 112.

In contrast, fig. 2B shows an alternative amplifier module 100' in which the summing circuit 110' is provided within the circuitry of the main LNA 112 '. Further details regarding this possible configuration are provided below with reference to fig. 8. Such use of the first path 106 and the second path 108 is consistent with the teachings of the present disclosure.

Fig. 3 provides more details regarding the amplifier module 100. In particular, the second path 108 may include the noise cancellation amplifier 200 previously described. The distortion cancellation amplifier 202 is instantiated by a distortion cancellation amplifier chain 300 in which a first distortion cancellation amplifier 302 is electrically connected in series with a second distortion cancellation amplifier 304. In a first exemplary aspect, the first distortion cancellation amplifier 302 may cancel second order distortion from the main LNA 112 and the second distortion cancellation amplifier 304 may cancel third order distortion from the main LNA 112. While it is contemplated that the first distortion cancellation amplifier 302 may cancel second order distortion, the first distortion cancellation amplifier 302 may instead cancel third order distortion and the second distortion cancellation amplifier 304 cancels second order distortion. By having two distortion canceling amplifiers 302, 304, both second and third order distortions can be resolved independently of each other (i.e., orthogonally) and independently of the noise canceling amplifier 200.

Fig. 4 provides another example of the second path 108. The distortion cancellation amplifier 202 is instantiated by a distortion cancellation amplifier chain 400 in which a first distortion cancellation amplifier 402 is electrically parallel to a second distortion cancellation amplifier 404. In a first exemplary aspect, the first distortion cancellation amplifier 402 may cancel second order distortion from the main LNA 112 and the second distortion cancellation amplifier 404 may cancel third order distortion from the main LNA 112.

Fig. 5 provides yet another example of the second path 108. The distortion cancellation amplifier 202 is instantiated by a distortion cancellation amplifier chain 500, wherein a first distortion cancellation amplifier 502 is electrically parallel to a second distortion cancellation amplifier 504 while both are electrically in series with a third distortion cancellation amplifier 506. In a first exemplary aspect, the first distortion cancellation amplifier 502 may cancel third order distortion from the main LNA 112 and the second distortion cancellation amplifier 504 may cancel second or third order distortion from the main LNA 112. The third distortion cancellation amplifier 506 may cancel the second or third order distortion from the main LNA 112, but it is understood that at least one of the second or third order distortion cancellation amplifiers 504, 506 cancels the second order distortion such that the distortion cancellation amplifier chain 500 cancels the second and third order distortion of the main LNA 112.

It should be appreciated that the noise cancellation amplifier 200 may be formed from a variety of different circuits, two of which are illustrated in fig. 6A and 6B as noise cancellation amplifiers 200A and 200B, respectively. The noise cancellation amplifier 200A is in a parallel feedback arrangement, wherein the resistor 600 provides a feedback loop for the parallel feedback amplifier 602. In contrast, noise cancellation amplifier 200B is a common-gate transistor arrangement in which gate 604 is coupled to ground 606. It should be appreciated that an n-type Field Effect Transistor (FET) (NFET) or a p-type FET (PFET) may be used, or a combination (i.e., complementary) may be used. Similarly, the present disclosure is not limited to a particular material, and may be silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), silicon (Si), germanium (Ge), or the like.

It should also be appreciated that the distortion cancellation amplifier 202 may similarly be formed from a variety of different circuits, two of which are illustrated in fig. 7A and 7B as distortion cancellation amplifiers 202A and 202B, respectively. The distortion cancellation amplifier 202A is a source follower amplifier 700, and the distortion cancellation amplifier 202B is a common source amplifier 702. Likewise, the particular materials or types of FETs may be varied as needed or desired without departing from the disclosure. Similarly, any of the amplifiers discussed herein may be single ended, differential, quadrature, etc.

In general, to achieve distortion cancellation, devices operate at different current levels. That is, a device with high gain, low noise has a high current density, and can be considered as a strong inverse. In contrast, devices that counteract such strong inversion devices should perform weak inversion and have relatively low current densities.

Fig. 8 provides a hybrid view of a particular embodiment of an amplifier module 800 based on the amplifier module 100' of fig. 2B. The main LNA 112 'is formed of cascode amplifiers 802 (1) -802 (2) with a node 804 therebetween that acts as a summing circuit 110' in which currents are summed. More specifically, the cancellation current Icancel is provided to the node 804 by the second path 108 and summed with the cascode current of the main LNA 112'.

With continued reference to fig. 8, the second path 108 includes the noise cancellation amplifier 200B, with the gate 604 coupled to ground 606 through a bias network 806. Further, the noise distortion cancellation amplifier 200B may be an Alternating Current (AC) coupled through a capacitor 808. The drain 810 of the noise cancellation amplifier 200B is coupled to the variable Zload 812 and the gate of the distortion cancellation amplifier 202A. The distortion cancellation amplifier 202A generates a cancellation current Icancel that is provided to the main LNA 112'. As shown, noise cancellation amplifier 200B may be in a high inversion state while distortion cancellation amplifier 202A is in a weak inversion state. This arrangement also allows current to be reused between the amplifiers 200B, 202A. Similarly, the current used by the second path 108 is substantially less than the current used by the first path 106 (e.g., a division of 90-10 is contemplated). Such current splitting is desirable because most of the current is used to support the signal of interest and not to cancel noise and distortion.

Fig. 9 is a circuit level diagram of an amplifier module 100 using the arrangement of the distortion cancellation amplifier chain 300 of fig. 3. Although specific circuitry is shown, it should be appreciated that there are other ways of achieving the same functionality. Fig. 9 is included to show the occupation of the operating circuit.

It should be noted that it is also possible to use some cascode amplifiers of the main LNA 112 to provide additional distortion (e.g., third order distortion), as better seen in fig. 10, where the main LNA 112 includes a cascode amplifier 1000 in addition to the main amplifier 1002 and the other cascode amplifier 1004. The second path 108 has a noise cancellation amplifier 200 and a distortion cancellation amplifier 202 that may, for example, cancel second order distortion. The cascode amplifier 1000 may also be considered part of the second path 108 and may provide additional distortion cancellation.

As better seen in fig. 11, more current reuse may be provided by changing the noise cancellation amplifier from a grounded gate to a floating gate. In most respects, the amplifier module 1100 of fig. 11 is identical to the amplifier module 800 of fig. 8, but the gate 604 is also coupled to the summing circuit 110' through a capacitor 1102, thereby forming a feedback of the input impedance of the noise cancellation amplifier 200B. By providing this connection, the current is reused within noise cancellation amplifier 200B, again reducing the overall current usage of second path 108. It should be noted that additional cascode amplifiers 802 (3) may be added without departing from the disclosure.

While aspects discussed above have contemplated summing circuits 110, 110' based on current summation, the present disclosure is not so limited. It is also possible to sum by means of a transformer, as shown in fig. 12. In particular, the power amplifier module 1200 includes a noise cancellation amplifier 200, which may be a parallel feedback amplifier 602 with an additional capacitor 1202 in parallel with a resistor 600. Equivalently, parallel feedback amplifier 602 may be replaced with circuit 1204. The output from the distortion cancellation amplifier 202B is summed in a summing circuit 110 "that is an inverting converter. Alternatively, the summing circuit 110 "may be replaced with an inductor 110'".

Although not specifically shown, aspects of the present disclosure may incorporate some form of temperature compensation to help bias the amplifier appropriately. That is, the amplifier may operate in different ways at different temperatures. Thus, having, for example, a bandgap temperature reference may allow for adjustments to operation as needed to maintain desired operation.

It should also be noted that the operational steps described in any of the exemplary aspects herein are described for purposes of providing examples and discussion. The described operations may be performed in a number of different orders than that illustrated. Furthermore, operations described in a single operational step may actually be performed in many different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It will be appreciated that the operational steps shown in the flow diagrams may be susceptible to many different modifications as will be readily apparent to those of skill in the art. Those of skill in the art would also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (16)

1. A Power Amplifier (PA) module, comprising:

a first path coupling an input node and an output node, the first path comprising a Low Noise Amplifier (LNA); and

a second path coupling the input node and the output node, the second path being electrically parallel to the first path, the second path including cancellation circuitry, the cancellation circuitry comprising:

a noise cancellation circuit; and

a distortion cancellation circuit.

2. The PA module of claim 1, wherein the noise cancellation circuit includes a noise cancellation amplifier configured to adjust an impedance presented at the input node.

3. The PA of claim 2, wherein the noise cancellation amplifier comprises a common gate transistor.

4. The PA of claim 2, wherein the noise cancellation amplifier comprises a parallel feedback amplifier.

5. The PA of claim 1, wherein the distortion cancellation circuit includes a distortion cancellation amplifier electrically in series after the noise cancellation circuit.

6. The PA of claim 1, wherein the distortion cancellation circuit comprises a first distortion cancellation amplifier electrically in parallel with a second distortion cancellation amplifier, wherein the first distortion cancellation amplifier cancels second order distortion in the LNA and the second distortion cancellation amplifier cancels third order distortion in the LNA.

7. The PA of claim 6, wherein the distortion cancellation circuit includes a third distortion cancellation amplifier electrically in series with the first and second distortion cancellation amplifiers and electrically in parallel with the noise cancellation circuit.

8. The PA of claim 1, wherein the distortion cancellation circuit comprises a first distortion cancellation amplifier electrically in series with a second distortion cancellation amplifier, wherein the first distortion cancellation amplifier is electrically in parallel with the noise cancellation circuit.

9. The PA of claim 1, further comprising a summing circuit that sums current from the first path with current from the second path.

10. The PA of claim 1, further comprising a summing circuit within the LNA that sums current from the first path with current from the second path.

11. The PA of claim 1, wherein the LNA comprises an n-type Field Effect Transistor (FET) (NFET) configured to be biased in a strong inversion.

12. The PA of claim 11, wherein the second path includes one or more p-type FETs (PFETs) configured to be biased in a weak inversion to produce opposite sign distortion.

13. The PA of claim 11, wherein the second path uses one or more NFETs biased in a weak inversion to produce opposite sign distortion.

14. A low noise amplification system, comprising:

a first signal path including an amplification path; and

a second signal path comprising a cancellation path configured to cancel noise and distortion independently,

wherein the means in the amplification path is configured to produce a distortion having a first value and a first sign and the means in the second signal path is configured to produce a distortion having substantially the first value and a second sign opposite to the first sign.

15. The low noise amplification system of claim 14, wherein the second signal path comprises two or more separate stages to achieve independent noise and distortion cancellation.

16. The low noise amplification system of claim 14, wherein the second signal path comprises a first stage configured to cancel second order distortion of the amplification path and a second stage configured to cancel third order distortion of the amplification path.