CN117079943A - On-chip transformer based on through silicon vias - Google Patents
On-chip transformer based on through silicon vias Download PDFInfo
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- CN117079943A CN117079943A CN202310997645.6A CN202310997645A CN117079943A CN 117079943 A CN117079943 A CN 117079943A CN 202310997645 A CN202310997645 A CN 202310997645A CN 117079943 A CN117079943 A CN 117079943A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 146
- 239000010703 silicon Substances 0.000 title claims abstract description 146
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 109
- 239000002184 metal Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 13
- 230000008569 process Effects 0.000 abstract description 12
- 238000004088 simulation Methods 0.000 description 9
- 238000004804 winding Methods 0.000 description 9
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000001939 inductive effect Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 239000000696 magnetic material Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F21/00—Variable inductances or transformers of the signal type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/29—Terminals; Tapping arrangements for signal inductances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
- H01F2027/2809—Printed windings on stacked layers
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Abstract
The application provides an on-chip transformer based on silicon through holes, which comprises a silicon substrate, a plurality of silicon through holes arranged in an array manner in the silicon substrate, a top rewiring layer, a bottom rewiring layer, an input port and two output ports, wherein the top rewiring layer and the bottom rewiring layer are respectively arranged on the top surface and the bottom surface of the silicon substrate, and metal columns and medium rings surrounding the metal columns are arranged in the silicon through holes. The device has the characteristics of high space utilization rate and convenient arrangement of input and output ports, and is wide in frequency band and excellent in phase amplitude. Therefore, the problems of huge volume, low space utilization rate, complex process, single input and output port arrangement form, narrow bandwidth and the like of an on-chip transformer and an on-chip balun in the prior art can be avoided.
Description
Technical Field
The application relates to the field of on-chip passive devices, in particular to an on-chip transformer based on a through silicon via.
Background
In recent years, along with the rapid development of wireless communication technology, a radio frequency front-end device plays a vital role in a wireless communication system, and a duplexer, a filter and a balun filter are microwave devices which are necessary for connecting a radio frequency front-end transmitter and a receiver and are widely applied to the fields of Bluetooth, wiFi, wireless local area networks and the like. The balun filter is used as a balun, is widely applied to devices such as an antenna, a mixer, a phase shifter and the like, is used as a three-port device, comprises an unbalanced input port and two balanced output ports, can output signals of the unbalanced input port from the two balanced output ports respectively, has the same amplitude and 180-degree phase difference, and is widely applied to a differential circuit, so that the anti-interference capability of an electronic system can be improved. In recent years, radio frequency devices are developed towards miniaturization and high performance, and the use amount of the radio frequency devices is also increasing as passive devices which are indispensable in wireless communication products. The ratio of active devices to passive devices used in a general electronic system is 1:10, so that the development of a miniaturized radio frequency passive device with high performance is of great practical significance.
Most of the current transformers adopt a laminated sheet-type upper transformer, and adopt a laminated differential structure, so that the primary coil and the secondary coil are completely overlapped up and down. The transformer structure mainly adopts a planar spiral inductance coupling mode to realize voltage transformation. The planar spiral transformer structure has the advantages of multiple winding turns, large volume and limited power improvement of the transformer.
Some transformers adopt a through silicon via structure, but the positions of input and output ports are fixed, the arrangement is single, the process is complex, the space utilization rate is low, and the bandwidth is narrow.
Disclosure of Invention
The application aims to provide an on-chip transformer based on a through silicon via, which can avoid the problems of huge volume, low space utilization rate, complex process, single input/output port arrangement form, narrow bandwidth and the like of the on-chip transformer in the prior art.
In order to achieve the above object, the present application provides an on-chip transformer based on through silicon vias, comprising a silicon substrate, a plurality of through silicon vias arranged in an array in the silicon substrate, a top rewiring layer and a bottom rewiring layer respectively arranged on the top surface and the bottom surface of the silicon substrate, an input port, and two output ports, wherein metal columns and dielectric rings surrounding the metal columns are arranged in the through silicon vias;
n is a positive integer, the through silicon vias are arranged in 2 rows and N columns, the top rewiring layer comprises N-2 sections of top interconnecting wires, two input port connecting wires and two output port connecting wires, and the bottom rewiring layer comprises N sections of bottom interconnecting wires;
the top ends of the metal columns in the through silicon vias of one of the 1 st row, the 1 st column and the 1 st row and the 2 nd column are connected with the input port through one input port connecting line, and the top ends of the metal columns in the through silicon vias of the other of the 1 st row, the 1 st column and the 1 st row and the 2 nd column are connected with the system ground through the other input port connecting line; the top ends of the metal columns in the 2 nd row, the N-1 th column and the 2 nd row and the N th column of through silicon vias are respectively connected with two output ports through two output port connecting wires;
the top ends of the metal columns in the through holes of the 1 st row and the 3 rd column are connected with the top ends of the metal columns in the through holes of the 2 nd row and the 1 st column through a 1 st section top interconnecting wire, the top ends of the metal columns in the through holes of the 1 st row and the 4 th column are connected with the top ends of the metal columns in the through holes of the 2 nd row and the 2 nd column through a 2 nd section top interconnecting wire, and so on, the top ends of the metal columns in the through holes of the 1 st row and the N th column are connected with the top ends of the metal columns in the through holes of the 2 nd row and the N2 th column through an N-2 section top interconnecting wire;
the N-th bottom interconnecting wire is connected with the bottom ends of the metal posts in the two through silicon vias of the N-th column.
In some embodiments of the present application, based on the foregoing, the method further comprises a magnetic body disposed inside the silicon substrate and between the two rows of through silicon vias.
In some embodiments of the application, the shape of the magnetic body is rectangular, annular or elliptical based on the foregoing.
In some embodiments of the application, the thickness of the magnetic body ranges from 1 to 20 μm based on the foregoing.
In some embodiments of the present application, based on the foregoing, the plurality of through silicon vias are arranged in a shape of a straight line, a ring, or a circle.
In some embodiments of the present application, based on the foregoing scheme, the input port and the two output ports are located on two sides of the two rows of through silicon vias, respectively.
In some embodiments of the present application, based on the foregoing scheme, the input port and the two output ports are located on the same side of the two rows of through silicon vias.
In some embodiments of the application, the thickness of the silicon substrate ranges from 100 to 200 μm and the diameter of the metal posts ranges from 10 to 20 μm based on the foregoing scheme.
In some embodiments of the application, the dielectric ring is silica in a thickness ranging from 0.2 to 0.5 μm based on the foregoing scheme.
In some embodiments of the present application, based on the foregoing scheme, the spacing between two adjacent through-silicon vias in the same row ranges from 20 μm to 100 μm, and the spacing between two through-silicon vias in the same column ranges from ≡20 μm.
According to the technical scheme, the plurality of through silicon vias are divided into two groups, the two groups are connected through the top rewiring layer and the bottom rewiring layer to form two independent winding groups to form two groups of mutually coupled inductive links, the two inductive links are subjected to complex coupling energy through capacitance and inductance, the coupling energy is adjusted according to the through silicon vias, the top rewiring layer and the bottom rewiring layer, the input port and the output port are positioned on two sides of the two winding groups, the energy of the input port can be coupled to the output port in an unequal mode, and the transformer structure is formed and has the characteristics of high space utilization rate, convenience in arrangement of the input port and the output port, wide frequency band and excellent phase amplitude. Therefore, the problems of huge volume, low space utilization rate, complex process, single input and output port arrangement form, narrow bandwidth and the like of an on-chip transformer and an on-chip balun in the prior art can be avoided.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art. In the drawings:
fig. 1 is a schematic perspective view of a through-silicon via-based on-chip transformer of the present application;
FIG. 2 is a schematic plan view of a through-silicon via-based on-chip transformer of the present application;
FIG. 3 is a schematic perspective view of an on-chip transformer with two output ports on the same side of two rows of through silicon vias according to the present application;
FIG. 4 is a schematic plan view of a through silicon via of the present application;
FIG. 5 is a schematic perspective view of bonding an upper silicon substrate and a lower silicon substrate according to the present application;
FIG. 6 is a schematic plan view of a through-silicon-via-based on-chip transformer of the present application in a toroidal configuration;
FIG. 7 is a graph of data simulation results of the on-chip balun based on through silicon vias with balanced return loss at the input port and amplitude at the output port;
FIG. 8 is a graph of data simulation results of phase balancing of output ports of a through-silicon via based on-chip balun of the present application;
FIG. 9 is a graph of data simulation results of the input port return loss and output port amplitude balance of the through-silicon-via-based on-chip transformer of the present application;
fig. 10 is a graph of data simulation results of phase balancing of output ports of the through-silicon via based on-chip transformer of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1 and 2, the present application provides an on-chip transformer based on through silicon vias, which includes a silicon substrate 2, a plurality of through silicon vias (Through Silicon Via, TSVs) 1 arranged in an array in the silicon substrate 2, top and bottom redistribution layers (Re-distributed layer, RDL) and bottom redistribution layers respectively disposed on top and bottom surfaces of the silicon substrate 2, an input port 9, and two output ports 10, wherein metal pillars 3 and dielectric rings 4 surrounding the metal pillars 3 are disposed in the through silicon vias 1;
n is a positive integer, the plurality of through silicon vias 1 are arranged in 2 rows and N columns, the top rewiring layer comprises N-2 segments of top interconnecting lines 61, two input port connecting lines 62 and two output port connecting lines 63, and the bottom rewiring layer comprises N segments of bottom interconnecting lines 64;
the top ends of the metal posts 3 in the through-silicon vias 1 of one of the 1 st row, 1 st column and 1 st row, 2 nd column are connected with the input port 9 through one input port connecting line 62, and the top ends of the metal posts 3 in the through-silicon vias 1 of the other of the 1 st row, 1 st column and 1 st row, 2 nd column are connected with the system ground through the other input port connecting line 62; the top ends of the metal columns 3 in the through silicon vias 1 of the 2 nd row, the N-1 th column and the 2 nd row and the N column are respectively connected with two output ports 10 through two output port connecting lines 63;
the top ends of the metal pillars 3 in the through-silicon vias 1 of the 1 st row and the 3 rd column are connected with the top ends of the metal pillars 3 in the through-silicon vias 1 of the 2 nd row and the 1 st column through the 1 st segment top interconnecting line 61, the top ends of the metal pillars 3 in the through-silicon vias 1 of the 1 st row and the 4 th column are connected with the top ends of the metal pillars 3 in the through-silicon vias 1 of the 2 nd row and the 2 nd column through the 2 nd segment top interconnecting line 61, and so on, the top ends of the metal pillars 3 in the through-silicon vias 1 of the 1 st row and the N2 th column are connected with the top ends of the metal pillars 3 in the through-silicon vias 1 of the 2 nd row and the N2 column through the N2 segment top interconnecting line 61;
the nth segment bottom interconnect line 64 connects the bottom ends of the metal pillars 3 in the two through-silicon vias 1 of the nth column.
Specifically, the silicon substrate 2 may be a conventional low-resistance silicon wafer, but since a high-resistance silicon wafer has a lower dielectric loss than a low-resistance silicon wafer, the silicon substrate 2 is preferably a high-resistance silicon wafer, and if the on-chip transformer is used for a high-frequency band, the silicon substrate 2 is preferably a high-resistance silicon wafer.
As shown in FIG. 2, the interval X between two adjacent through-silicon vias 1 in the same row is 20-100 μm, and the interval Y between two through-silicon vias 1 in the same column is not less than 20 μm. It should be noted that, depending on the process conditions, Y is related to the operating frequency of the transformer, and the lower the frequency is, the larger Y is, and theoretically, Y may be infinite.
As shown in fig. 4, the dielectric ring 4 separates the metal pillar 3 from the silicon substrate 2, and the dielectric ring 4 may be made of silicon dioxide which can perform an insulating function. The thickness of the dielectric ring 4 may range from 0.2 to 0.5 μm.
Specifically, the ratio of the depth to the width (aspect ratio) of the through-silicon via 1 is relatively high in process requirements, and when the process conditions are normal, the through-silicon via 1 with a relatively small aspect ratio can be selected. In order to avoid overlarge processing difficulty caused by overlarge depth-to-width ratio of the through silicon via 1, the practical processing is convenient, the thickness range of the silicon substrate 2 is 100-200 mu m, and the diameter range of the metal column 3 is 10-20 mu m.
It should be noted that, the top redistribution layer and the bottom redistribution layer are respectively disposed on the top surface and the bottom surface of the silicon substrate 2, the top surface and the bottom surface of the silicon substrate 2 may be respectively deposited with a metal layer by a conventional semiconductor process, the metal layer is patterned to form a top redistribution layer and a bottom redistribution layer, and then dielectric layers (not shown in the figure, the dielectric layers play a role of protecting the top redistribution layer and the bottom redistribution layer) are respectively deposited, so as to form a redistribution layer disposed on the top surface and the bottom surface of the silicon substrate 2, and have corresponding metal wirings, and the input/output ports of the chip are rearranged on a loose area outside the chip. The application divides a plurality of through silicon vias 1 into two groups, and is connected with a bottom rewiring layer through a top rewiring layer to form two independent winding groups, so as to form two groups of mutually coupled inductive links, the two inductive links are mutually coupled with energy through capacitance and inductance, and meanwhile, the two inductive links are used as circuits of an input port 9 and an output port 10 to provide ports for subsequent packaging and other components connection.
Specifically, the widths of the top interconnect lines 61 and the bottom interconnect lines 64 may be the same as the diameters of the metal posts 3, and the top and bottom re-wiring layers are wired according to actual design requirements.
In some embodiments, the on-chip transformer further comprises a magnetic body 11 disposed inside the silicon substrate 2 and between the two rows of through silicon vias 1. The magnetic body 11 may be located at the center of the silicon substrate 2, and when the magnetic body 11 is provided, an on-chip balun based on a through silicon via is formed. Of course, if the magnetic body 11 is not provided, the on-chip transformer is a through-silicon via, but if the amplitude balance is not required to be high, the balun may be a low-end balun.
When the magnetic body 11 is provided, as shown in fig. 5, the manufacturing method may be: the silicon substrate 2 is divided into an upper silicon substrate 12 and a lower silicon substrate 13, a magnetic material is grown on the bottom of the upper silicon substrate 12 and the top of the lower silicon substrate 13, a magnetic material grown on the bottom of the upper silicon substrate 12 forms an upper magnetic core 16, a magnetic material grown on the top of the lower silicon substrate 13 forms a lower magnetic core 17, the upper magnetic core 16 and the lower magnetic core 17 are symmetrical about a horizontal plane, the upper silicon substrate 12 and the lower silicon substrate 13 are bonded by a wafer bonding process, the upper magnetic core 16 and the lower magnetic core 17 are aligned with each other, a magnetic body 11 is formed, and finally a through silicon via-based on-chip balun is formed.
Specifically, the thickness of the magnetic body 11 is in the range of 1 to 20 μm. In the actual process, the thinner the thickness of the magnetic body 11 is, the easier the processing is, and therefore, in order to facilitate the processing of the magnetic body 11, the thinner the thickness of the magnetic body 11 is generally required to be.
Specifically, the input port 9 and the two output ports 10 are led out by adopting an input port connecting line 62 and two output port connecting lines 63 of the top rewiring layer respectively, and because the on-chip transformer and the on-chip balun are on-chip passive devices and the ports are reciprocal, one port on one side of the two winding groups can be designated as the input port 9, and the other port is connected with the system ground, and then the two ports on the other side of the two winding groups are designated as the output ports 10. As shown in fig. 1, the input port 9 and the two output ports 10 are located on two sides of the two rows of through silicon vias 1, respectively. As shown in fig. 3, the input port 9 and the two output ports 10 are located on the same side of the two rows of through silicon vias 1.
Specifically, the plurality of through silicon vias 1 are arranged in a shape of a straight line, a ring (sector), or a circle. The magnetic body 11 has a rectangular, annular (circular arc) or elliptical shape. In fig. 1, a plurality of through silicon vias 1 are arranged in a straight line, and a magnetic body 11 is rectangular in shape. In fig. 6, the plurality of through silicon vias 1 are arranged in a ring shape, and the magnetic body 11 is in a ring shape, thereby forming an on-chip balun in a ring structure.
Fig. 7 is a graph of data simulation results of the on-chip balun based on through silicon vias, wherein the data simulation results show that the return loss of an input port and the amplitude of an output port are balanced, the standing wave is good in a frequency range of 2.7-5.5 GHz, the relative bandwidth reaches 70%, and the amplitude balance degree, namely the maximum power ratio of the two output ports, is 1.16dB in the frequency range of 2.7-5.5 GHz. Fig. 8 is a graph of data simulation results of phase balance of output ports of a through-silicon via-based on-chip balun of the present application, showing that the phase difference phase of two output ports is 7.4 degrees at maximum in the frequency range of 2.7-5.5 GHz. FIG. 9 is a graph of data simulation results of the input port return loss and output port amplitude balance of the on-chip transformer based on the through silicon vias, showing that standing waves are good in the frequency range of 1-5 GHz, the relative bandwidth reaches 130%, and the amplitude balance, namely the power ratio of two output ports is basically constant in the frequency range of 1-3.5 GHz and is 3.5-4 dB. Fig. 10 is a graph of data simulation results of phase balancing of output ports of the through-silicon via-based on-chip transformer of the present application, showing that the phase difference between the two output ports is 10 degrees at maximum in the frequency range of 3-5 GHz.
The on-chip transformer and the on-chip balun of the application have the following characteristics:
1. the same-layer transformer and balun structure design of two winding groups are formed by adopting the silicon through holes, and the planar spiral structure and the transformer and balun structure formed by the multilayer silicon through holes are avoided, so that the integrated circuit is not limited by a two-dimensional plane, has more degrees of freedom, has good reliability in the aspects of mechanical strength, thermal stress, heat dissipation and the like, avoids the complexity of a process, and improves the yield of devices.
2. The silicon through holes and the interconnecting lines of the rewiring layers form a symmetrical three-dimensional balun structure which is uniformly distributed between the inner part of the silicon substrate and the upper and lower layers, so that the on-chip balun has good common-mode rejection performance.
3. The on-chip transformer and the balun have adjustable shape, changeable structure and wider application range.
4. The input port and the output port can be positioned at the same side or two sides of the two rows of silicon through holes, can be flexibly adjusted according to the ports of the used devices, and is convenient to use.
In summary, the on-chip transformer based on the through silicon via provided by the application forms an on-chip balun when a magnetic body is arranged, can be used as an independent device to realize the conversion from an unbalanced input signal to a balanced output signal, and can also be integrated in a radio frequency/microwave integrated circuit to realize the functions of push-pull amplification, double balanced mixing and balanced amplification. The on-chip transformer based on the silicon through holes comprises a silicon substrate, a plurality of silicon through holes which are arranged in the silicon substrate in an array manner, a top rewiring layer, a bottom rewiring layer, an input port and two output ports which are respectively arranged on the top surface and the bottom surface of the silicon substrate, wherein metal columns and dielectric rings surrounding the metal columns are arranged in the silicon through holes. The plurality of through silicon vias are divided into two groups, the two groups are connected through the top rewiring layer and the bottom rewiring layer to form two independent winding groups, two groups of mutually coupled inductance links are formed, the two inductance links are subjected to complex coupling energy through capacitance and inductance, the coupling energy is adjusted according to the through silicon vias, the top rewiring layer and the bottom rewiring layer, the input ports and the output ports are positioned on two sides of the two winding groups, and the two groups of through silicon vias are arranged on the same side or different sides according to the practical application of the device. The application can couple the energy of the input port to the output port in an unequal mode to form a transformer structure, and can also realize the balun circuit function of converting a single-ended unbalanced input signal into a double-ended balanced output signal. Compared with the prior art, the device has the characteristics of high space utilization rate and convenient arrangement of the input and output ports, and the arrangement shape of the silicon through holes and the shape of the magnetic body are adjustable, for example, the device can be annular or linear, and has wide frequency band and excellent phase amplitude. Therefore, the problems of huge volume, low space utilization rate, complex process, single input and output port arrangement form, narrow bandwidth and the like of an on-chip transformer and an on-chip balun in the prior art can be avoided.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. The on-chip transformer based on the silicon through holes is characterized by comprising a silicon substrate, a plurality of silicon through holes arranged in an array manner in the silicon substrate, a top rewiring layer, a bottom rewiring layer, an input port and two output ports, wherein the top rewiring layer and the bottom rewiring layer are respectively arranged on the top surface and the bottom surface of the silicon substrate, and metal columns and medium rings surrounding the metal columns are arranged in the silicon through holes;
n is a positive integer, the plurality of through silicon vias are arranged in 2 rows and N columns, the top rerouting layer comprises N-2 sections of top interconnecting lines, two input port connecting lines and two output port connecting lines, and the bottom rerouting layer comprises N sections of bottom interconnecting lines;
the top ends of the metal columns in the through silicon vias of one of the 1 st row, the 1 st column and the 1 st row and the 2 nd column are connected with the input port through one input port connecting line, and the top ends of the metal columns in the through silicon vias of the other of the 1 st row, the 1 st column and the 1 st row and the 2 nd column are connected with the system ground through the other input port connecting line; the top ends of the metal columns in the 2 nd row, the N-1 th column and the 2 nd row and the N th column of through silicon vias are respectively connected with two output ports through two output port connecting wires;
the top ends of the metal columns in the through holes of the 1 st row and the 3 rd column are connected with the top ends of the metal columns in the through holes of the 2 nd row and the 1 st column through a 1 st section top interconnecting wire, the top ends of the metal columns in the through holes of the 1 st row and the 4 th column are connected with the top ends of the metal columns in the through holes of the 2 nd row and the 2 nd column through a 2 nd section top interconnecting wire, and so on, the top ends of the metal columns in the through holes of the 1 st row and the N th column are connected with the top ends of the metal columns in the through holes of the 2 nd row and the N2 th column through an N-2 section top interconnecting wire;
the N-th bottom interconnecting wire is connected with the bottom ends of the metal posts in the two through silicon vias of the N-th column.
2. The through-silicon via based on-chip transformer of claim 1, further comprising a magnetic body disposed inside the silicon substrate between two rows of through-silicon vias.
3. The through-silicon via based on-chip transformer of claim 2, wherein the magnetic body is rectangular, annular or elliptical in shape.
4. The through-silicon via based on-chip transformer according to claim 2, wherein the thickness of the magnetic body ranges from 1 to 20 μm.
5. The through-silicon via based on-chip transformer of claim 1, wherein the plurality of through-silicon vias are arranged in a shape of a straight line, a ring, or a circle.
6. The through-silicon via based on-chip transformer of claim 1, wherein the input port and the two output ports are located on either side of two rows of through-silicon vias, respectively.
7. The through-silicon via based on-chip transformer of claim 1, wherein the input port and the two output ports are on the same side of two rows of through-silicon vias.
8. The through-silicon via based on-chip transformer of claim 1, wherein the silicon substrate has a thickness ranging from 100 to 200 μm and the metal pillars have a diameter ranging from 10 to 20 μm.
9. The through-silicon via based on-chip transformer of claim 1, wherein the dielectric ring is of silicon dioxide and has a thickness in the range of 0.2-0.5 μm.
10. The through-silicon via based on-chip transformer of claim 1, wherein the spacing between two adjacent through-silicon vias of the same row is in the range of 20-100 μm and the spacing between two through-silicon vias of the same column is in the range of ≡20 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202310997645.6A CN117079943A (en) | 2023-08-09 | 2023-08-09 | On-chip transformer based on through silicon vias |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310997645.6A CN117079943A (en) | 2023-08-09 | 2023-08-09 | On-chip transformer based on through silicon vias |
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| CN202310997645.6A Pending CN117079943A (en) | 2023-08-09 | 2023-08-09 | On-chip transformer based on through silicon vias |
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2023
- 2023-08-09 CN CN202310997645.6A patent/CN117079943A/en active Pending
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