CN117063275A - 功率半导体封装 - Google Patents
功率半导体封装 Download PDFInfo
- Publication number
- CN117063275A CN117063275A CN202280024442.2A CN202280024442A CN117063275A CN 117063275 A CN117063275 A CN 117063275A CN 202280024442 A CN202280024442 A CN 202280024442A CN 117063275 A CN117063275 A CN 117063275A
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- source
- circuit
- power
- power semiconductor
- copper cladding
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 148
- 239000000758 substrate Substances 0.000 claims abstract description 156
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 123
- 229910052802 copper Inorganic materials 0.000 claims abstract description 121
- 239000010949 copper Substances 0.000 claims abstract description 121
- 238000005253 cladding Methods 0.000 claims abstract description 93
- 238000002955 isolation Methods 0.000 description 28
- 230000008901 benefit Effects 0.000 description 21
- 238000010586 diagram Methods 0.000 description 14
- 230000003071 parasitic effect Effects 0.000 description 11
- 238000003466 welding Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000001965 increasing effect Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 150000001879 copper Chemical class 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000011859 microparticle Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000003134 recirculating effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
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Abstract
本发明涉及一种功率半导体封装(150),其包括:第一基板组件(201;202),其包括多个功率半导体管芯(301;401);第二基板组件(202;201),其基本上平行于第一基板组件(201;202)布置,并且包括限定具有键合区(450;350)的源极铜覆层电路(407b;407c;306b;306c)的铜覆层(202c;201c),所述键合区(450;350)被配置成被机械地接触,以提供至源极铜覆层电路(407b;407c;306b;306c)的电连接;以及多个源极触点(QH1‑QH5;QL1‑QL5),所述源极触点中的每一个在第一基板组件(201;202)的功率半导体管芯(301;401)之一的源极连接与第二基板组件(202;201)的源极铜覆层电路(407b;407c;306b;306c)之间提供电连接,所述源极触点(QH1‑QH5;QL1‑QL5)被布置在距源极铜覆层电路(407b;407c;306b;306c)的键合区(450、350)的不同距离处。由于源极铜覆层电路(407b;407c;306b;306c)设有布置在最靠近源极铜覆层电路(407b;407c;306b;306c)的键合区(450、350)的源极触点(QH1;QL1)与源极铜覆层电路(407b;407c;306b;306c)的键合区(450、350)之间的电隔离槽(701;501;502),因此本发明的功率半导体封装(150)能够可靠且高效地开关较高的电功率。
Description
技术领域
本发明涉及一种功率半导体封装,尤其涉及一种具有第一基板组件和第二基板组件的功率半导体封装,所述第一基板组件包括多个功率半导体管芯,所述第二基板组件基本上平行于第一基板组件布置,并且包括限定具有键合区的源极铜覆层电路的铜覆层,该键合区被配置成被机械接触,以提供至源极铜覆层电路的电连接。
本公开涉及一种多个功率半导体管芯的高功率密度封装,所述高功率密度封装具有低功率回路电感、平衡的并联源极电感、高电流处理能力、高电压爬电隔离,并且可以使用标准半导体封装材料、设备和工艺以低成本制造。
背景技术
功率半导体发展的总体目标是提高它们的功率密度。这可以通过减小这种封装的尺寸和体积和/或通过提高功率半导体封装的电流和电压额定值来实现。但是,在增加额定电流和额定电压的同时实现尺寸和体积的减小会引入对立的限制。减小封装会导致功率半导体封装的功率端子的可用空间缩小。这通常会导致功率端子导体横截面积减小,从而导致更高的功率端子电阻。由于相邻功率端子之间、高压信号端子之间以及高压功率或信号端子与半导体封装冷却表面和与其键合的散热器之间的爬电距离减小,功率端子的可用空间的减少通常还会限制高压运行。
功率半导体晶体管技术的改进已经导致几纳秒内数十安培数量级的极快晶体管开关速度。但是,由功率半导体封装的寄生功率回路电感引起的关断电压过冲可能会限制能够实现的开关速度。
此外,并联功率半导体晶体管之间的寄生共源电感的不匹配会在导通和关断开关瞬变期间导致并联晶体管之间的源极-漏极电流不平衡,这会导致并联晶体管之间不一致的开关损耗和不一致的结点温度。不一致的开关损耗导致效率降低,不一致的晶体管结点温度严重降低功率半导体封装的热性能。并联晶体管之间的源极-漏极电流的巨大不平衡还可能引起振荡,导致运行不稳定。
发明内容
因此,本发明的目的是提供一种允许较高电功率的可靠和高效开关的功率半导体封装。
这个目的通过具有权利要求1的特征的功率半导体封装实现的。
本发明的功率半导体封装设有两个基板组件,这两个基板组件彼此叠置,从而第二基板组件基本上平行于第一基板组件布置。
第一基板组件设有多个功率半导体管芯,这些功率半导体管芯彼此并联电连接以限定功率开关。每个功率半导体管芯包括半导体开关,例如金属氧化物半导体场效应晶体管(MOSFET)、绝缘栅双极晶体管(IGBT)或高电子迁移率晶体管(HEMT)。每个功率半导体管芯包括通常位于功率半导体管芯的顶面处的输入连接、通常位于功率半导体管芯的底面处的输出连接、以及控制连接。输入连接例如与MOSFET的源极连接、IGBT的发射极连接或HEMT的源极连接对应。输出连接例如与MOSFET的漏极连接、IGBT的集电极连接或HEMT的漏极连接对应。控制连接例如与MOSFET的栅极连接、IGBT的基极连接或HEMT的栅极连接对应。
为了简单起见,在下文中,输入连接被称为功率半导体管芯的源极,输出连接被称为功率半导体管芯的漏极,控制连接被称为功率半导体管芯的栅极。
将功率半导体管芯相互并联电连接意味着通过源极电路将所有这些功率半导体管芯的源极电互连,通过漏极电路将所有这些功率半导体管芯的漏极电互连,并且通过电子门电路将所有这些功率半导体管芯的栅极电互连。
第二基板组件在面向第一基板组件的一侧上设有铜覆层,其中该铜覆层限定源极铜覆层电路。所述源极铜覆层电路设有键合区,该键合区被配置成被机械地接触,以提供至源极铜覆层电路的电连接。所述键合通常基本上是矩形和细长的。
本发明的功率半导体封装还设有多个源极触点,每个源极触点从第一基板组件延伸至第二基板组件,并在第一基板组件的功率半导体管芯之一的源极触点与第二基板组件的源极铜覆层电路之间提供电连接。因此,第一基板组件的功率半导体管芯的源极连接经由第二基板组件的源极触点和源极铜覆层电路电互连。源极触点布置在距源极铜覆层电路的键合区的不同距离处,并且通常基本上垂直于所述两个基板组件的平行表面延伸。源极触点优选被布置在一条直线上,其中所述直线优选基本上垂直于键合区的纵向尺寸。源极触点通常是由具有较高电导率的材料制成的独立元件,并且连接至(典型地键合至)相应功率半导体管芯的源极以及源极铜覆层电路。
通常可能的是所述两个基板组件均设有多个功率半导体和限定源极铜覆层电路的铜覆层。在这种情况下,源极触点在一个基板组件的功率半导体管芯的源极触点与相应的另一个基板组件的源极铜覆层电路之间提供电连接。
根据本发明,所述源极铜覆层电路设有布置在最靠近源极铜覆层电路的键合区的源极触点与源极铜覆层电路的键合区之间的电隔离槽。所述最靠近源极铜覆层电路的键合区的源极触点在下文中被称为最靠近的源极触点。本文中的术语“在……之间”指电隔离槽被布置成打断键合区与具有大致相同的形状但不具有电隔离槽的“虚拟”源极铜覆层电路的最靠近的源极触点之间的最短源极铜覆层电路路径。结果,电隔离槽增加了键合区与最靠近的源极触点之间的有效电流路径长度,即,延长了电流在键合区与最靠近的源极触点之间流动的路径。电隔离槽通常是“空的”,即,填充有空气,但是一般可以填充有任何具有较低电导率的材料。所述电隔离槽优选是通过从铜覆层有选择性地去除材料来产生的。
本发明的电隔离槽增加了键合区与最靠近的源极触点之间的有效电流路径长度,导致键合区与各个源极触点之间更一致的有效电流路径长度。这减少了各个功率半导体管芯的源极的寄生电感之间的失配,从而实现了并联连接的功率半导体管芯的更一致的开关。因此,本发明的半导体封装能够可靠且高效地开关较高的电功率。
在本发明的一个优选实施例中,在第二基板组件的设有源极铜覆层电路的表面上设置在平面图中基本上为U形的电隔离槽,其中所述电隔离槽被布置成使得它在三侧围绕最靠近的源极触点。本文中的术语“侧”是指平面图中的物体的四个面内侧,即,前面、后面和两个侧面。本文中的术语“围绕”指电隔离槽沿着最靠近的源极触点的相应侧延伸,但是不一定必须沿着相应侧的整个宽度延伸。U形电隔离槽的封闭端通常面向键合区。U形电隔离槽的两个分叉位于最靠近的源极触点的相对侧,并且优选基本上平行于布置有源极触点的直线延伸。U形电隔离槽的两个分叉优选具有不同的长度。在三侧围绕最靠近的源极触点的U形电隔离槽允许在键合区与各个源极触点之间实现特别一致的有效电流路径长度,由此允许并联连接的功率半导体管芯的特别一致的开关。
优选地,所述电隔离槽围绕至少两个源极触点,这意味着所述电隔离槽邻近两个源极触点延伸。所述电隔离槽优选在两个相对侧围绕两个触点中的每一个。这允许在键合区与各个源极触点之间实现特别一致的有效电流路径长度,由此允许并联连接的功率半导体管芯的特别一致的开关。
在本发明的一个优选实施例中,所述源极铜覆层电路设有至少一个附加的电隔离槽,即,所述源极铜覆层电路总共设有至少两个电隔离槽。由于设有多个电隔离槽,因此能够以较简单的方式实现键合区与各个源极触点之间的特别一致的有效电流路径长度。
优选地,源极铜覆层电路的所述至少一个电隔离槽被配置成使得并联连接的功率半导体管芯的最大峰值导通电流与最小峰值导通电流之比不超过1.1。在本文中,功率半导体管芯的峰值导通电流指在功率半导体管芯导通之后的瞬态阶段中流经相应功率半导体管芯的最大电流。最大峰值导通电流是具有最高峰值导通电流的单个功率半导体管芯的峰值导通电流,最小峰值导通电流是具有最低峰值导通电流的单个功率半导体管芯的峰值导通电流。不超过1.1的最大峰值导通电流与最小峰值导通电流之比确保了并联连接的功率半导体管芯的非常一致的开关,使得所述半导体封装能够非常可靠且高效地开关较高的电功率。
包括对多个并联半导体功率管芯的封装的改进的本公开说明了使得功率半导体管芯能够以最佳性能、功率密度和成本运行的实施例。
附图说明
下面将参照附图说明本发明的实施例,在附图中:
图1示出了本发明的功率半导体封装的示意性电路图和透视图;
图2示出了图1的功率半导体封装的部件和子组件的分解图;
图3A示出了图1的功率半导体封装的第一基板组件的第一实施例的内侧的俯视图;
图3B示出了图1的功率半导体封装的第一基板组件的替代第二实施例的内侧的俯视图;
图4示出了图1的功率半导体封装的第二基板组件的内侧的俯视图;
图5示出了在组装后图1的半导体封装的第一基板组件、第二基板组件、信号端子引线框和功率端子组件相对于彼此的对准;
图6A示出了图1的功率半导体封装的第一基板组件的铜覆层布局的不同实施例;
图6B示出了图1的半导体封装的低侧功率开关的功率半导体管芯的示例性导通电流开关波形;
图7A示出了图1的半导体封装的第二基板组件的铜覆层布局的不同实施例;
图7B示出了图1的半导体封装的高侧功率开关的功率半导体管芯的示例性导通电流开关波形;
图8示出了图1的半导体封装的功率端子组件的两个透视图,其中示出了功率端子组件的顶部侧和底部侧;
图9示出了图1的半导体封装的功率端子基板塑料封装主体的两个透视图,其中示出了功率端子基板塑料封装主体的顶部侧和底部侧;
图10示出了图1的示意性电路图,其中示出了图1的半导体封装的低侧功率开关的漏极-源极电压和漏极-源极电流,并且示出了低侧功率开关的漏极-源极电压和漏极-源极电流的示例性关断波形,以及
图11示出了封装图1的半导体封装的多个信号端子的信号端子塑料封装主体的透视图和俯视图。
具体实施方式
通过参考下文的详细说明,能够最佳地理解本公开的实施例及其优点。应理解,相同的附图标记用于标识在一个或多个附图中示出的相同元件,附图中的图示是为了说明本公开的实施例,而不是为了限制本公开。
本发明涉及半导体功率晶体管的封装以及用于在最大限度地减小功率模块封装内的并联功率半导体晶体管之间的寄生功率回路电感和匹配源极电感的同时最大限度地提高功率密度的装置和方法。
本公开提供了解决上述问题中的一个或更多个问题的实施例。说明对封装和冷却结构的改进的本公开说明了使得半导体功率晶体管封装更高效、更可靠、具有更高功率密度和更具成本效益的实施例。
图1示意性地示出了高侧功率开关101和低侧功率开关102的半桥电气配置100。在某些实施例中,两个功率开关101和102中的每一个都包括多个并联连接的功率半导体管芯,还包括一个或更多个功率半导体晶体管和一个或更多个功率半导体二极管。在某些实施例中,所述多个并联连接的半导体管芯中的每一个可以包括具有固有的反并联二极管的晶体管。在其它实施例中,所述多个并联连接的功率半导体管芯中的一些可以包括晶体管,而其它并联连接的功率半导体管芯可以包括反并联二极管。在某些实施例中,所述半导体晶体管包括金属氧化物半导体场效应晶体管MOSFET、绝缘栅双极晶体管IGBT或高电子迁移率晶体管HEMT。在某些实施例中,MOSFET、IGBT和HEMT晶体管以及反并联二极管可以由硅、碳化硅、氮化镓、另一种III-V半导体或其它半导体材料形成。与MOSFET晶体管的漏极、HEMT晶体管的漏极、IGBT晶体管的集电极和反并联二极管的阴极对应的底部侧功率半导体管芯表面在下文中将被称为每个管芯的漏极连接。所述多个包括高侧功率开关101的功率半导体管芯的漏极连接并联地电连接至高侧功率开关101的漏极101d。所述多个包括高侧功率开关101的功率半导体管芯的源极连接并联地电连接至高侧功率开关101的源极101s。与MOSFET晶体管的源极、HEMT晶体管的源极、IGBT晶体管的发射极和反并联二极管的阳极对应的顶部侧功率半导体管芯表面的暴露的焊盘区在下文中将被称为每个管芯的源极连接。所述多个包括低侧功率开关102的功率半导体管芯的漏极连接并联地电连接至低侧功率开关102的漏极101d。所述多个包括低侧功率开关102的功率半导体管芯的源极连接并联地电连接至低侧功率开关102的源极102s。在某些示例性实施例中,高侧开关101d的漏极电连接至高侧漏极功率端子121和信号端子129。在某些示例性实施例中,低侧开关102s的源极电连接至低侧功率端子121和信号端子126。在某些示例性实施例中,高侧开关101s的源极和低侧开关102d的漏极电连接至中点功率端子123和高侧源极/低侧漏极信号端子130。包括高侧开关101的功率半导体晶体管管芯的公共栅极电路101g电连接至信号引脚132。在某些示例性实施例中,包括高侧开关101的功率半导体管芯的公共开尔文源极电路在101s与信号引脚131之间形成电连接。低侧开关102g的功率半导体晶体管管芯的公共栅极电路电连接至信号引脚124。在某些示例性实施例中,包括低侧开关101的功率半导体管芯的公共开尔文源极电路在101s与信号引脚131之间形成电连接。在某些示例性实施例中,本公开的半导体封装包括热敏电阻104,该热敏电阻104的第一端子电连接至信号端子127,该热敏电阻104的第二端子电连接至信号端子128。在某些示例性实施例中,本公开的半导体封装包括多个阻容RC缓冲器件103,所述阻容RC缓冲器件103的端子电连接在高侧开关漏极电路101d与低侧开关源极电路102s之间。最终的功率半导体封装结构150的一个示例性实施例包括位于该封装的一侧的多个信号端子、位于该封装的相反侧上的多个功率端子124-132、塑料封装主体142、底部侧散热器140和顶部侧散热器141。
图2示出了构成本公开的半导体封装结构的子组件和部件,不包括塑料封装主体142。所述半导体封装包括第一基板组件201、第二基板组件202、信号端子引线框220、功率端子组件210、下散热器140和上散热器131。这样的第一基板组件201具有示例性外部铜覆层201a、示例性内部铜覆层201c,这样的外部铜覆层和内部铜覆层被电隔离层201b隔开。这样的第二基板组件202具有示例性外部铜覆层202a、示例性内部铜覆层202c,这样的外部铜覆层和内部铜覆层被电隔离层202b隔开。这样的信号端子引线框架包括由铜或铜合金材料制成的多个信号端子124-132。这样的示例性功率端子组件210包括功率端子基板211,该功率端子基板211具有被电隔离层211b隔开的示例性第一铜覆层211a和示例性第二铜覆层211c、以及多个键合至这样的第一铜覆层和第二铜覆层的铜或铜合金端子121-123。
图3A示出了示例性第一基板组件201。示例性铜覆层电路307形成高侧功率开关101的漏极电路101d。示例性铜覆层电路306形成低侧功率开关102的源极电路102s。
示例性高侧功率开关101包括五个并联的具有固有的反并联二极管301的功率半导体晶体管管芯,每个管芯的漏极连接键合至漏极电路101d的铜覆层电路。其它示例性实现方案可以使用更少或更多的并联管芯。竖向源极触点302键合至每个这样的示例性功率半导体晶体管管芯301的源极连接。
示例性铜覆层电路308形成高侧功率开关101的公共电子门电路101g,具有用于每个功率晶体管管芯301的示例性独立键合线连接。示出了用于将外部栅极信号端子132键合至公共栅极电路铜覆层电路308的示例性键合区132a。
示例性铜覆层电路309形成包括高侧功率开关101的功率半导体的公共开尔文源极电路。这样的公共开尔文源极电路的一种示例性实现方案包括多个限流电阻303,每个限流电阻301具有键合至公共开尔文源极铜覆层电路309的一个端子和键合至每个功率半导体晶体管管芯301的源极焊盘的第二端子线。示出了用于将外部开尔文信号端子131键合至公共开尔文源极电路铜覆层电路309的示例性键合区131a。在某些示例性实施例中,可能需要使用限流电阻来防止并联功率半导体晶体管之间的过大再循环开尔文源极电流熔化开尔文源极键合线。在具有高di/dt开关瞬变以及并联连接的功率晶体管管芯301之间的大阈值电压失配的应用中,这种再循环电流的幅度可能过高。示例性键合区128m支持第二热敏电阻信号端子与第一基板201的机械键合。没有铜覆层104x的示例性区域为组装在第二基板上的热敏电阻104提供竖向机械键合线间隙。示例性键合区127m支持第二热敏电阻信号端子与第一基板201的机械键合。示例性键合区126a支持低侧源极信号端子126至第一基板201的电气和机械键合。示例性键合区125m支持低侧开尔文源极信号端子125至第一基板201的机械键合。示例性键合区124m支持低侧栅极信号端子124至第一基板201的机械键合。
本公开的第一个信号端子124m和最后一个信号端子132a的键合区分别相对于其它信号端子键合区水平偏移,并且被置于与基板的信号端子侧垂直的基板侧上。这种布置方式的优点是:i)不需要增加第一基板201或第二基板202的宽度来支持示例性信号端子的数量,以及ii)示例性热敏电阻可以放置在引线框键合宽度内,而不需要使用第一基板201或第二基板202的额外区域。
在第一基板201上有用于第二基板202的每个功率半导体晶体管管芯源极连接的多个竖向源极触点402的示例性电气和机械键合位置。
本公开的某些示例性实施例结合有多个阻容RC缓冲电容103,每个电容具有电气和机械键合至形成低侧功率开关102的源极电路102s的铜覆层电路306的第一底部侧端子、以及引线键合至形成高侧功率开关101的漏极电路101d的铜覆层电路307的第二顶部侧端子。本公开的优点在于,所述多个RC缓冲电容103中的每一个使用独立的最小长度的键合线,这导致最大限度地减小寄生电感并提高滤波性能。其它示例性实施例可以省略这样的RC缓冲电容103。
示例性的多个竖向功率触点304在第一基板201与第二基板202之间电连接和机械连接高侧电力开关101的漏极101d电路。
一种示例性电气和机械键合区350,有在第一基板201上的低侧功率开关102的源极电路102s,以及在功率端子基板211的第二铜覆层211c上的相应电路。
图3B示出了栅极和开尔文源极电路的键合线配置的一个替代示例性实施例。外部栅极控制信号可以连接至信号端子131,该信号端子131具有来自每个电阻303的键合线,该键合线连接至每个相应的功率晶体管管芯301的栅极焊盘。在这样的替代实施例中,与每个功率半导体晶体管管芯301的源极焊盘相关联的键合线可以键合至铜覆层电路308,并且进一步连接至外部信号端子132,形成公共开尔文源极返回电路。在使用具有低栅极-漏极对栅极-源极电容比的功率半导体晶体管管芯301时,这种替代引线键合配置会为每个功率半导体晶体管管芯提供增大的栅极电阻,以减轻寄生栅极-漏极振荡。其它示例性实施例可以完全省略电阻303。
高侧公共源极信号端子130机械键合至第一基板201上的键合区130m。信号端子130的相反侧电气和机械键合至第二基板上的高侧电公共源极电路101s。开尔文源极以及公共源极-栅极返回电路都连接至本公开的示例性半导体封装的外部信号端子。对于部分地硬切换和软切换的应用电路,优选在信号端子130上使用公共源极返回信号,而在硬切换应用电路中优选使用开尔文源极信号端子131。本发明的栅极控制和源极返回电路的优点包括支持具有相同半导体封装的开尔文源极和公共源极应用电路。另一个优点包括使用相同的信号端子和基板材料实现了用于限流或补充栅极电阻适配的电阻的简单键合线配置,从而提高了规模经济性。
图4示出了示例性第二基板组件202。示例性铜覆层电路407形成低侧功率开关102的漏极电路102d和高侧功率开关101的源极电路101s。示例性铜覆层电路410通过竖向功率触点304将高侧电力开关101的漏极电路101d从第一基板组件201连接至示例性电气和机械键合区451,再连接至功率端子基板211的第一铜覆层211c上的相应电路。
示例性低侧功率开关102包括五个并联的具有固有的反并联二极管401的功率半导体晶体管管芯,每个管芯的漏极连接键合至漏极电路102d的铜覆层电路407。其它示例性实现例可以使用更少或更多的并联管芯。竖向源极触点402键合至每个这样的示例性功率半导体晶体管管芯401的源极连接。
示例性铜覆层电路408形成用于低侧功率开关102的公共电子门电路102g,具有用于每个功率晶体管管芯401的示例性独立键合线连接。示出了用于将外部栅极信号端子124键合至公共栅极电路铜覆层电路408的示例性键合区124a。
示例性铜覆层电路409形成包括低侧功率开关102的功率半导体的公共开尔文源极电路。这样的公共开尔文源极电路的一种示例性实现方案包括多个限流电阻403,每个限流电阻403具有键合至公共开尔文源极铜覆层电路409的一个端子和键合至每个功率半导体晶体管管芯301的源极焊盘的第二端子线。示出了用于将外部开尔文信号端子125键合至公共开尔文源极电路铜覆层电路409的示例性键合区125a。低侧公共源极信号端子126机械键合至第二基板202上的键合区126m。信号端子126的相反侧电气和机械键合至第一基板上的低侧电公共源极电路102s。该第二基板上的示例性栅极电路、开尔文源极电路、公共源极电路与针对第一基板公开的图3A和图3B中的示例性电路对称。针对第一基板上的相应电路配置公开的所有示例性实施例和优点直接适用于第二基板。
铜覆层电路411上的示例性键合区127a支持第一热敏电阻信号端子至第二基板202的电气和机械键合。示例性热敏电阻104底部的第一端子键合至铜覆层电路411。示例性键合线将示例性热敏电阻104顶部的第二端子连接至铜覆层电路412。铜覆层电路411上的示例性键合区128a支持第二热敏电阻信号端子至第二基板202的电气和机械键合。形成热敏电阻的键合和信号引脚连接的示例性结构的优点在于这种结构与所述半导体封装的高压电路电隔离。这种结构的另一个优点是这样的热敏电阻104在几何上靠近低侧功率半导体晶体管管芯401布置,导致热敏电阻104和半导体晶体管管芯401的温度相关性提高。示例性键合区129m支持高侧漏极信号端子129至第二基板202的机械键合。示例性键合区130a支持低侧源极信号端子130至第二基板202的电气和机械键合。在本公开的一些实施例中,示例性键合区131m支持低侧开尔文源极信号端子131至第二基板202的机械键合。在本公开的一些实施例中,示例性键合区132m支持低侧栅极信号端子132至第二基板201的机械键合。
本公开的用于将第一个信号端子124m和最后一个信号端子132a键合至第二基板202的键合区分别相对于其它信号端子键合区水平偏移,并且布置在与基板的信号端子侧垂直的基板侧上。这种布置方式的优点是:i)不需要增加第一基板201或第二基板202的宽度来支持示例性信号端子的数量,以及ii)示例性热敏电阻可以放置在引线框键合宽度内,而不需要使用第一基板201或第二基板202的额外区域。
在第二基板202上有用于第一基板201的每个功率半导体晶体管管芯源极连接的多个竖向源极触点302的示例性电气和机械键合位置。
第一基板201的示例性多个竖向功率触点304将高侧电力开关101的漏极电路101d从第一基板201电气和机械地连接至第二基板202上的铜覆层电路410。
铜覆层电路410上的示例性电气和机械键合区451将第二基板202上的高侧功率开关101的漏极电路101d连接至功率端子基板211的相应铜覆层211a。
示例性键合区450支持低侧功率开关102的漏极电路102d至功率端子基板211的相应铜覆层211a的电气和机械键合。
图5示出了第一基板组件201、第二基板组件202、信号端子引线框220和功率端子组件210当组装在本发明的一个示例性实施例中时如何相对于彼此对准。
图示501示出了信号端子引线框220、第一基板组件201和功率端子组件210的示例性水平x-y平面对准。
图示502示出了信号端子引线框220、第二基板组件201和功率端子组件210的示例性水平x-y维度对准。
图示503示出了信号端子引线框220、第一基板组件201、第二基板组件202和功率端子组件210的示例性组装。箭头510-517示意性地示出了在组装期间形成的各种键合点的大致位置。键合位置510示出了在信号端子引线框220的上表面和下表面与第一基板和第二基板上的相应多个键合区125a-131a和125m-131m之间形成的键合点。键合位置511示出了在信号端子124和132的上表面和下表面与第一基板和第二基板上的相应多个键合区124a、124m、132a和132m之间形成的键合点。键合位置511还示出了在i)第一基板组件201的最左边的源极触点302及其在第二基板组件202上的相应键合位置与ii)第二基板组件202的最左边的源极触点402及其在第一基板组件201上的相应键合位置之间形成的键合点。键合位置512-515示出了在i)第一基板组件201的剩余源极触点302及其在第二基板组件202上的相应键合位置与ii)第二基板组件202的剩余源极触点402及其在第一基板组件201上的相应键合位置之间形成的键合点。键合位置516示出了在第一基板组件201的竖向功率触点304与其在第二基板组件202上的相应键合位置之间形成的键合点。键合位置517示出了在i)第一基板组件201的键合区350和功率端子组件210的相应键合区350a与ii)第二基板组件202的键合区450和451和功率端子组件210的相应键合区450a和451a之间形成的键合点。
本公开的功率半导体封装结构的与组装工艺相关的优点包括:i)第一基板组件201和第二基板组件202的组装仅需要在水平x-y维度上的组装公差控制,这样的公差完全在行业标准功率半导体封装设备和工艺的能力范围之内;ii)与组装第一基板201和第二基板202的组装公差相比,第一基板组件201、第二基板组件202、信号端子引线框组件220和功率端子组件210的组装已经显著降低了水平x-y维度的公差要求;以及iii)组装第一基板组件201、第二基板组件202、信号端子引线框组件220和功率端子组件210所需的严格的竖向z维度的组装公差很容易通过信号端子引线框组件220、功率半导体管芯301和401、竖向源极触点302和402以及竖向功率触点304的行业标准厚度公差来实现。只有功率端子基板211需要非标准处理来满足所需的厚度公差。
图6A示出了形成低侧功率开关102的源极电路102s的第一基板201的铜覆层电路306的三个示例性实施例。
示例性实施例601的图示示出了键合至示例性铜覆层电路306a的五个竖向源极触点402,所述多个竖向源极触点402基本上与功率基板211的键合区350成直线地组装,如604所示。每个竖向源极触点的位置被标记为QL1-QL5,其中QL1在几何上最靠近键合区350,QL5在几何上最远离键合区350。
示例性实施例602的图示示出了一种经过改进的具有电隔离槽501的源极电路102s的铜覆层电路306b,该电隔离槽501具有围绕竖向源极触点402中在几何上最靠近键合区350的QL1的三个侧面的外周的连续跨度。这样的隔离槽501的优点是改善了功率基板211的键合区350与所述多个竖向源极触点QL1-QL5之间的并联寄生源极电感匹配。
示例性实施例603的图示示出了一种经过改进的具有两个电隔离槽的源极电路102s的铜覆层电路306c。第一电隔离槽502具有围绕竖向源极触点402中在几何上最靠近键合区350的QL1的三个侧面的外周的连续跨度,该隔离槽跨度在一侧延伸至QL4,在第二侧延伸至QL2。第二电隔离槽503具有从QL2至QL3的跨度。这样的隔离槽502和503的优点是进一步改善了功率基板211的键合区350与所述多个竖向源极触点QL1-QL5之间的并联寄生源极电感匹配。
图6B示出了图6A的每个示例性铜覆层几何结构306a、306b和306c的键合至竖向源极触点QL1-QL5的每个并联功率半导体管芯的导通电流的电路模拟结果。
图示601a示出了铜覆层电路306a的QL1-QL5的导通电流。QL1在由线610指示的时刻呈现最高峰值电流。在时刻610,QL1的最高导通电流与QL5的最低导通电流之比为1.93。
图示602a示出了铜覆层电路306b的QL1-QL5的导通电流。QL1在由线610指示的时刻仍呈现最高峰值电流。在时刻610,QL1的最高导通电流与QL5的最低导通电流之比减小为1.59。
图示603a示出了铜覆层电路306c的QL1-QL5的导通电流。QL5现在在由线610指示的时刻呈现最高峰值电流。在时刻610,QL5的最高导通电流与QL1的最低导通电流之比减小为1.05。
结合了本发明的示例性隔离槽501、502和503的本发明的示例性实施例在动态开关条件期间在示例性并联功率半导体晶体管管芯301之间提供了平衡的电流共享。平衡的电流共享最大限度地减小了示例性晶体管管芯301之间的差异开关损耗,从而导致一致的晶体管管芯301温度和更高的效率。
图7A示出了形成高侧功率开关101的源极电路101s的第二基板202的铜覆层电路407的三个示例性实施例。
示例性实施例701的图示示出了键合至示例性铜覆层电路407a的五个竖向源极触点302。所述多个竖向源极触点302基本上与功率基板211的键合区450成对角线地组装,如704所示。每个竖向源极触点的位置被标记为QH1-QH5,其中QH1在几何上最靠近键合区450,而QH5在几何上最远离键合区450。
示例性实施例702的图示示出了一种经过改进的具有电隔离槽701的源极电路101s的铜覆层电路407b,该电隔离槽701具有由705示出的从邻近键合区450的铜覆层的边缘穿过竖向源极触点302中在几何上最靠近键合区450的QH1的宽度的连续跨度。这样的隔离槽501的优点是改善了功率基板211的键合区450与所述多个竖向源极触点QH1-QH5之间的并联寄生源极电感匹配。
示例性实施例703的图示示出了一种经过改进的具有三个电隔离槽的源极电路101s的铜覆层电路407c。第一电隔离槽701具有从邻近键合区450的铜覆层的边缘穿过竖向源极触点302中在几何上最靠近键合区450的QH1的宽度的连续跨度。第二电隔离槽702邻近QH4。第三电隔离槽703邻近QH5。这样的隔离槽701、702和703的优点是进一步改善了功率基板211的键合区450与所述多个竖向源极触点QH1-QH5之间的并联寄生源极电感匹配。
图7B示出了图7A的每个示例性铜覆层几何结构407a、407b和407c的键合至竖向源极触点QH1-QH5的每个并联功率半导体管芯的导通电流的电路模拟结果。
图示701a示出了铜覆层电路407a的QH1-QH5的导通电流。QH1在由线710指示的时刻呈现最高峰值电流。在时刻710,QH1的最高导通电流与QH5的最低导通电流之比为1.15。
图示702a示出了铜覆层电路407b的QH1-QH5的导通电流。在时刻710,QH1的最高导通电流与QH5的最低导通电流之比减小为1.10。
图示703a示出了铜覆层电路407c的QH1-QH5的导通电流。在时刻610,QH1的最高导通电流与QH1的最低导通电流之比减小为1.06。
结合了本发明的示例性隔离槽701、702和703的本发明的示例性实施例在动态开关条件期间在示例性并联功率半导体晶体管管芯401之间提供了平衡的电流共享。平衡的电流共享最大限度地减小了示例性晶体管管芯401之间的差异开关损耗,从而导致一致的晶体管管芯401温度和更高的效率。
图8示出了本发明的某些实施例的功率端子组件210的示例性结构的顶部侧800和底部侧820。功率端子组件210包括功率端子基板211和三个功率端子121-123。
在某些示例性实施例中,这样的功率端子基板211可以是直接敷铜(DBC)基板、活性金属钎焊(AMB)基板、直接镀铜(DPC)基板或双面金属芯印刷电路板(MCPCB)。
在某些示例性实施例中,用于这样的功率端子121-123的材料可以是铜或铜合金。
示例性铜覆层电路801将高侧功率开关101的源极电路101s和低侧功率开关102的漏极电路102d连接至中点功率端子123。键合区450a电气和机械地键合至第二基板202的键合区450。中点功率端子123电气和机械地键合至键合区123a。
示例性铜覆层电路804将高侧功率开关101的漏极电路101d连接至高侧漏极功率端子122。键合区451a电气和机械地键合至第二基板202的键合区451。高侧漏极功率端子123电气和机械地键合至键合区122a。
示例性铜覆层电路804将低侧功率开关102的源极电路102s连接至低侧功率端子121。键合区350a电气和机械地键合至第一基板201的键合区350。低侧功率端子121电气和机械地键合至键合区121a。
功率端子基板211的材料的典型制造厚度公差在±100微米的量级。当在大规模生产中组装本发明时,期望实现±30微米量级的厚度公差,以实现高制造产量。在本发明的一个示例性实施例中,可以对铜覆层电路801的厚度进行加工,以在键合区350a的整个宽度804b上实现基板211的期望厚度公差。
铜覆层区域830与所述功率半导体封装中的所有电路电隔离。在本公开的某些实施例中,这样的区域830可用于使用文字、二维条形码或二维数据矩阵码来压印制造可追溯性信息。
在本发明的某些示例性实施例中,可以使用烧结方式将示例性功率端子121-123键合至功率端子基板211。烧结键合可以使用包含银、铜、铂、钯或金颗粒、微米颗粒或纳米颗粒的浆料或薄膜来形成。在其它示例性实施例中,可以使用超声波焊接、激光焊接或电子束焊接来形成这种键合。
本公开的功率端子121-123的示例性实施例分别包括用于利用螺栓将这种功率端子连接至外部母线的孔121b、122b、123b。这样的功率端子的其它示例性实施例可以省略这种孔,使用超声波焊接、激光焊接或电子束焊接来形成与外部母线的键合。在本发明的其它示例性实施例中,可以从功率半导体封装中省略功率端子121-123。在这样的实施例中,外部母线可以使用超声波焊接、激光焊接或电子束焊接直接键合至铜覆层键合区121a、122a和123a。
图9示出了本发明的某些实施例的示例性功率端子基板211的塑料封装主体142的结构。
图示900a示出了本发明的这种塑料封装主体142的顶部侧的一个示例性实施例。第二基板202的外部铜覆层202a的表面、功率端子键合区122a和123a的表面没有被封装主体142封装。封装主体表面142a相对于铜覆层202a的表面凹陷,以支持散热器与铜覆层202a的无障碍键合。
示例性封装主体142形成横跨功率半导体封装的宽度的脊901a。这样的脊901a相对于封装主体142的表面142a升高。这样的示例性脊901a的优点是扩展了暴露的铜覆层202a与功率端子基板211的暴露的功率端子键合区122a和123a之间的爬电距离911a和912a。
示例性封装主体142在功率端子键合区122a和123a之间形成第二脊903a。这样的示例性脊903a的优点是扩展了功率端子基板211的暴露的键合区122a和123a之间的爬电距离913a。
示例性封装主体142在功率端子基板211的外周周围形成附加的脊904a、905a、906a和907a。这样的示例性脊904a~907a的优点是扩展了功率端子基板211的顶部侧和底部侧上的暴露的铜覆层之间的爬电距离914a、915a、916a和917a。
图示900b示出了这样的塑料封装主体142的底部侧的示意图。封装主体142的底部侧与封装主体142的顶部侧对称。表面142b与图示900a中的表面142a互补。脊901b和903b与图示900a中的脊901a和903a互补。爬电距离911b、912b和913b与图示900a中的尺寸911a、912a和912a互补。
封装主体142的示例性脊901a、903a、904a、905a、906a、907a、901b和903b的另一个优点是改善了对功率端子基板211的机械支撑。
图10示出了本发明的某些实施例的示例性功率模块的低侧开关漏极-源极电压和电流关断波形。
本发明的功率端子组件210的示例性实施例的其它优点包括低寄生功率回路电感和低功率半导体封装电阻。
向高侧开关101d的漏极传导电流的第一铜覆层电路802与向低侧开关102s的源极传导电流的第二铜覆层电路804基本上重叠。电路802和804被非常薄的功率端子基板211的绝缘层211b进一步分开。电路802和804的这种重叠和紧密的几何接近导致电路802和804之间的强互感耦合,从而导致功率回路电感的减小。
三个功率端子中的两个功率端子122和123键合至功率端子基板211的一侧,第三个功率端子键合至功率端子基板211的相反侧。这种布置方式的效果是,对于给定的功率半导体封装宽度,与具有彼此相邻的三个功率端子的功率半导体封装相比,每个功率端子可以宽33%。根据本发明的示例性实施例,能够将功率端子宽度增加33%,这导致功率端子的电阻降低。对于所公开的示例性实施例,这种功率端子电阻的减小与在功率环路中没有任何键合线的本发明相结合导致小于0.075毫欧的非常低的功率半导体封装电阻。
图10的图示1000示出了本公开的功率半导体半桥电路100的简化示意图。对于850A的漏极-源极电流和800V的漏极-源极电压,用功率端子122和123之间的感性负载模拟低侧开关102关断切换瞬变。在信号端子130和126上测量低侧开关102的漏极-源极电压1002。在功率端子121处测量漏极-源极电流1003。图示1010示出了在这种关断切换瞬变期间低侧开关102的漏极-源极电压和漏极-源极电流。在峰值电压出现时测得的电压过冲幅度1004和测得的电流变化率1005与4.6纳亨的功率回路电感1006对应。
图11示出了本发明的某些实施例的示例性信号端子引线框220的塑料封装主体142的结构。
图示1100a示出了本发明的这种塑料封装主体142的一侧的一个示例性实施例。塑料封装主体142部分地封装示例性信号端子124-132,以机械地支撑这样的信号端子并提供爬电隔离。第二基板202的外部铜覆层202a的表面、第一基板201的外部铜覆层201a(未示出)未被封装主体142封装。封装主体表面142a相对于铜覆层202a表面凹陷,以支持散热器与铜覆层202a的无障碍键合。
示例性封装主体142形成基本上横跨功率半导体封装的宽度的脊1101a。这样的脊1101a相对于封装主体142的表面142a升高。这样的示例性脊1101a的优点是扩展了暴露的铜覆层202a与暴露的信号端子123-132之间的示例性爬电距离1102a。在某些实施例中,封装主体142的结构在功率半导体封装的相反侧是对称的(未示出)。由本公开的功率半导体封装的相反侧上的封装主体形成的脊1101b在结构上与脊1101a对称。
图示1100b示出了相对于封装主体142的边缘1010凹陷的多个示例性凹口1004、1006和1008。
示例性凹口1104扩展了低侧源极电路102s的信号端子126与热敏电阻104的信号端子127之间的爬电距离1105,这是热敏电阻电路的安全高压电隔离所需要的。
示例性凹口1106扩展了高侧漏极电路101d的信号端子129与热敏电阻104的信号端子128之间的爬电距离1107,这是热敏电阻电路的安全高压电隔离所需要的。
示例性凹口1108扩展了高侧漏极电路101d的信号端子129与高侧源极电路101s的端子130之间的爬电距离1109,这是热敏电阻电路的安全高压电隔离所需要的。
本发明的具有多个这样的封装主体142凹口1105、1107和1109的示例性实施例的优点是,相对于没有凹口的封装,所需的功率半导体封装宽度减小了16%,导致更小和更高功率密度的功率半导体封装。
在本文中所用的术语“包括”、“包含”、“具有”或它们的任何上下文变化形式意图涵盖非排他性的包含。例如,包括一系列元素的过程、产品、物品或装置不一定仅限于这些元素,还可以包括未明确列出的或者这种过程、产品、物品或装置所固有的其它元素。此外,除非另有明确说明,否则“或”指包含性的而不是排他性的或者。例如,以下任何一项都满足条件“A或B”:A为真(或存在)、B为假(或不存在)、A为假(或不存在)且B为真(或存在)、以及A和B均为真(或存在)。
还应理解,附图中描绘的一个或更多个元件也可以以更加分离或集成的方式实施,或者甚至在某些情况下被去除或变得不可操作,这对于特定应用来说是有用的。
Claims (5)
1.一种功率半导体封装(150),包括:
-第一基板组件(201;202),其包括多个功率半导体管芯(301;401),
-第二基板组件(202;201),其基本上平行于第一基板组件(201;202)布置,并且包括限定具有键合区(450;350)的源极铜覆层电路(407b;407c;306b;306c)的铜覆层(202c;201c),所述键合区(450;350)被配置成被机械地接触,以提供至源极铜覆层电路(407b;407c;306b;306c)的电连接,以及
-多个源极触点(QH1-QH5;QL1-QL5),这些源极触点中的每一个在第一基板组件(201;202)的功率半导体管芯(301;401)之一的源极连接与第二基板组件(202;201)的源极铜覆层电路(407b;407c;306b;306c)之间提供电连接,所述源极触点(QH1-QH5;QL1-QL5)被布置在距源极铜覆层电路(407b;407c;306b;306c)的键合区(450、350)的不同距离处,
其中所述源极铜覆层电路(407b;407c;306b;306c)设有布置在最靠近源极铜覆层电路(407b;407c;306b;306c)的键合区(450、350)的源极触点(QH1;QL1)与源极铜覆层电路(407b;407c;306b;306c)的键合区(450、350)之间的电隔离槽(701;501;502)。
2.如权利要求1所述的功率半导体封装(150),其中所述电隔离槽(501;502)基本上是U形的,并围绕着在三个侧面最靠近源极铜覆层电路(407b;407c;306b;306c)的键合区(450、350)的源极触点(QH1;QL1)。
3.如前述权利要求之一所述的功率半导体封装(150),其中所述电隔离槽(501;502)围绕至少两个源极触点(QL1-QL4)。
4.如前述权利要求之一所述的功率半导体封装(150),其中所述源极铜覆层电路(407b;407c;306b;306c)设有至少一个附加的电隔离槽(702、703;503)。
5.如前述权利要求之一所述的功率半导体封装(150),其中所述至少一个电隔离槽(701-703;502、503)被配置成使得功率半导体管芯(301;401)的最大峰值导通电流与最小峰值导通电流之比不超过1.1。
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