CN117063236A - Antifuse device with cup-shaped insulator - Google Patents
Antifuse device with cup-shaped insulator Download PDFInfo
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- CN117063236A CN117063236A CN202280025031.5A CN202280025031A CN117063236A CN 117063236 A CN117063236 A CN 117063236A CN 202280025031 A CN202280025031 A CN 202280025031A CN 117063236 A CN117063236 A CN 117063236A
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Abstract
An integrated circuit device is disclosed that includes an antifuse device. The antifuse device includes: a cup-shaped bottom antifuse electrode; a cup-shaped antifuse insulator formed in an opening defined by the cup-shaped bottom antifuse electrode; and a top antifuse electrode formed in an opening defined by the cup-shaped antifuse insulator. The cup-shaped antifuse insulator has a thickness less than
Description
Related patent application
The present application claims priority from commonly owned U.S. provisional patent application No. 63/222,367 filed on 7/15 of 2021, the entire contents of which are hereby incorporated by reference for all purposes.
Technical Field
The present disclosure relates to antifuses formed in Integrated Circuit (IC) structures, and more particularly to antifuses formed by a damascene process.
Background
Antifuse is an electrically programmable two-terminal device. The antifuse has a high resistance in an unprogrammed state, and a low resistance in a programmed state. Programming the antifuse converts the antifuse from a high-resistance state to a state with a permanent low-resistance conductive path. Typically, programming is performed when the voltage across the antifuse exceeds a certain level.
Antifuses are commonly used in FPGA (field programmable gate array) applications. Antifuse FPGAs can provide various advantages, for example, compared to FPGAs based on SRAM (static random access memory) or flash memory. For example, an antifuse FPGA is non-volatile and efficient at power up, may exhibit a shorter latency due to routing, may use less power than SRAM or flash memory, and may be more secure. Antifuses-based FPGAs may be particularly useful in radiation-resistant applications, such as space and military applications.
One type of conventional antifuse comprises a polysilicon layer separated from an n+ doped region by an oxide-nitride-oxide (ONO) dielectric layer. The antifuse is capable of programming between (a) an unprogrammed high-resistance state and (b) a programmed state in which a conductive antifuse chain is formed across the ONO dielectric layer, thereby defining a low-resistance state.
Typical antifuse FPGAs have various drawbacks or shortcomings. For example, conventional antifuses typically require complex non-standard manufacturing processes (which may result in lower yields and slower technological evolution), e.g., compared to SRAM FPGAs. As another example, conventional antifuse designs are typically implemented between an active region and a polysilicon region, which may result in relatively high series resistance and low packing density (e.g., compared to antifuses implemented on metal interconnects, as well as compared to multi-layer designs). As another example, some conventional antifuses are not effectively surrounded such that a blown fuse that can release energy that may damage nearby circuitry can lead to yield or reliability problems for surrounding integrated circuit structures.
Disclosure of Invention
An integrated antifuse device and a method of forming an integrated antifuse device are provided. An integrated antifuse device may be formed between adjacent metal layers. The antifuse device may comprise a metal-insulator-metal (MIM) structure formed by a damascene process, the damascene process comprising: a tub opening is formed in the dielectric region, a cup-shaped bottom antifuse electrode is formed in the tub opening, a cup-shaped antifuse insulator is formed in the opening defined by the cup-shaped bottom antifuse electrode, and a top antifuse electrode is formed in the opening defined by the cup-shaped antifuse insulator.
The thickness of the cup-shaped antifuse insulator may define or affect the breakdown voltage of the antifuse device, i.e., the voltage required to program the antifuse device. Thus, the cup-shaped antifuse insulator may be formed with a defined thickness that provides a desired breakdown voltage of the antifuse device. For example, the cup-shaped antifuse insulator may be formed with a predetermined thickness that provides a breakdown voltage of less than 15V, less than 10V, less than 7V, or less than 5V. In some examples, the cup-shaped antifuse insulator has a thickness less thanFor example in->To->Within (1) or>To->Within a range of (2).
One aspect provides an integrated circuit device that includes an antifuse device. An antifuse device includes: cup with cup bodyA bottom antifuse electrode; a cup-shaped antifuse insulator formed in an opening defined by the cup-shaped bottom antifuse electrode; and a top antifuse electrode formed in an opening defined by the cup-shaped antifuse insulator. The cup-shaped antifuse insulator has a thickness less than
In some examples, the cup-shaped antifuse insulator has a thickness ofTo->Within a range of (2). In some examples, the thickness of the cup-shaped antifuse insulator is +.>To->Within a range of (2).
In some examples, the antifuse device has a breakdown voltage below 15V. In some examples, the antifuse device has a breakdown voltage below 7V.
In some examples, the cup-shaped antifuse insulator comprises silicon oxide (SiO 2 ) Oxide-nitride-oxide (ONO), nitride-oxide-nitride (NON) or alumina (Al) 2 O 3 )。
In some examples, an integrated circuit device includes: a bottom antifuse electrode contact formed in the lower metal interconnect layer, wherein the bottom antifuse electrode contact is electrically connected to the cup-shaped bottom antifuse electrode; and a top antifuse electrode contact formed in the upper metal interconnect layer, wherein the top antifuse electrode contact is electrically connected to the top antifuse electrode.
In some examples, an integrated circuit device includes a transistor including a doped source region and a doped drain region, wherein a cup-shaped bottom antifuse electrode is electrically connected to a silicide region of the transistor formed over the source region or a silicide region formed over the drain region.
Another aspect provides an integrated circuit device that includes an interconnect structure and an antifuse device. The interconnection structure comprises: a lower interconnect element formed in the lower metal layer; an upper interconnect element formed in the upper metal layer; and an interconnect via formed in the dielectric region between the lower metal layer and the upper metal layer, the interconnect via electrically connecting the upper interconnect element to the lower interconnect element. An antifuse device includes: a cup-shaped bottom antifuse electrode formed in the dielectric region; a cup-shaped antifuse insulator formed in an opening defined by the cup-shaped bottom antifuse electrode; and a top antifuse electrode formed in an opening defined by the cup-shaped antifuse insulator. The cup-shaped antifuse insulator has a thickness less than
In some examples, the cup-shaped antifuse insulator has a thickness ofTo->Within a range of (2). In some examples, the thickness of the cup-shaped antifuse insulator is +.>To->Within a range of (2).
In some examples, the antifuse device has a breakdown voltage below 15V. In some examples, the antifuse device has a breakdown voltage below 7V.
In some examples, the cup-shaped antifuse insulator comprises silicon oxide (SiO 2 ) Oxide-nitride-oxide (ONO), nitride-oxide-nitride (NON) or alumina (Al) 2 O 3 )。
In some examples, the cup-shaped bottom antifuse electrode and the interconnect via are formed of the same conformal material.
In some examples, the lower interconnect element and the bottom antifuse electrode contact are formed in a lower metal interconnect layer, and the upper interconnect element and the top antifuse electrode contact are formed in an upper metal interconnect layer.
In some examples, an integrated circuit device includes a transistor including a doped source region and a doped drain region, wherein a cup-shaped bottom antifuse electrode is electrically connected to a silicide region of the transistor formed over the source region or a silicide region formed over the drain region.
Another aspect provides a method of forming an antifuse device. The method comprises the following steps: forming a tub opening in the dielectric region; depositing a conformal metal over the dielectric region and extending into the tub opening to form a cup-shaped bottom antifuse electrode in the tub opening; depositing a metal layer with a thickness less thanTo define a cup-shaped antifuse insulator in an opening defined by the cup-shaped bottom antifuse electrode, the cup-shaped antifuse insulator comprising: a laterally extending antifuse insulator base, and vertically extending antifuse insulator sidewalls extending upward from the laterally extending antifuse insulator base; depositing a top electrode metal over the insulator layer and extending into an opening defined by the cup-shaped antifuse insulator; and performing a planarization process to remove upper portions of the conformal metal, insulator layer, and top electrode metal outside the tub opening.
In some examples, the layer thickness is atTo->Within a range of (2).
In some examples, the layer thickness is atTo->Within a range of (2).
In some examples, the cup-shaped antifuse insulator comprises silicon oxide (SiO 2 ) Oxide-nitride-oxide (ONO), nitride-oxide-nitride (NON) or alumina (Al) 2 O 3 )。
In some examples, the method includes: depositing a dielectric barrier layer over a planarized upper surface defined by a planarization process, the dielectric barrier layer extending over vertically extending sidewalls of the cup-shaped bottom antifuse electrode, vertically extending antifuse insulator sidewalls, and the top antifuse electrode; depositing an upper dielectric layer over the dielectric barrier layer; etching the upper dielectric layer and the dielectric barrier layer to form a top antifuse electrode contact opening exposing an upper surface of the top antifuse electrode, wherein the dielectric barrier layer acts as an etch stop; and filling the top antifuse electrode contact opening to form a top antifuse electrode contact electrically connected to the top antifuse electrode.
In some examples, the antifuse device is formed without adding any photomask processes to the background integrated circuit fabrication process.
Drawings
Exemplary aspects of the disclosure are described below in conjunction with the following drawings, in which:
FIG. 1A is a top view and FIG. 1B is a side cross-sectional view of an exemplary IC structure including an exemplary antifuse device and an exemplary interconnect structure that may be formed simultaneously, according to an example;
fig. 2 illustrates a side cross-sectional view of the exemplary antifuse device shown in fig. 1A and 1B;
fig. 3A-3I illustrate an exemplary process for forming the integrated circuit structure shown in fig. 1A and 1B, including an exemplary antifuse device and an exemplary interconnect structure;
FIG. 4 illustrates an exemplary integrated circuit device including a plurality of antifuse devices formed at different depths in the integrated circuit device; and is also provided with
Fig. 5 illustrates an exemplary integrated circuit device including an exemplary antifuse device and an exemplary interconnect structure formed between a silicided active region including a MOSFET transistor and a first metal interconnect layer.
It will be appreciated that the reference numerals of any illustrated element appearing in a plurality of different figures have the same meaning in the plurality of figures, and that any illustrated element mentioned or discussed herein in the context of any particular figure is also applicable to every other figure (if any), where the same illustrated element is shown.
Detailed Description
An integrated antifuse device and a method of forming an integrated antifuse device are provided. An integrated antifuse device may be formed between adjacent metal layers. The antifuse device may include a MIM structure comprising: a cup-shaped bottom antifuse electrode formed in a tub opening in the dielectric region; a cup-shaped antifuse insulator formed in an opening defined by the cup-shaped bottom antifuse electrode; and a top antifuse electrode formed in an opening defined by the cup-shaped antifuse insulator.
The thickness of the antifuse insulator may define or affect the breakdown voltage of the antifuse device. Thus, the antifuse insulator may be formed with a defined thickness that provides a desired breakdown voltage of the antifuse device. For example, the cup-shaped antifuse insulator may be formed with a predetermined thickness that provides a breakdown voltage of less than 15V, less than 10V, less than 7V, or less than 5V. In some examples, the cup-shaped antifuse insulator has a thickness less thanFor example in->To->Within (2) or within (1)To->Within a range of (2).
As used herein, a "metal layer" may include any metal or metallization layer, including:
(a) A metal interconnect layer comprising, for example, copper, aluminum, or other metal formed by a damascene process or by a subtractive patterning process (e.g., deposition, patterning, and etching of a metal layer), or
(b) A silicided active region comprising a plurality of silicided structures (structures having a metal silicide layer formed thereon), such as a silicided source region, drain region or polysilicon gate of a MOSFET.
For example, as discussed below with reference to fig. 1A-1B, 3A-3I, and 4, an antifuse device may be constructed at any depth in an integrated circuit device at two adjacent metal interconnect layers M x And M x+1 Between them. As another example, as discussed below with reference to fig. 5, an antifuse device may be constructed over a silicided active region, such as on a silicon transistor having a metal silicide layer formed over selected transistor features, and under a first metal interconnect layer (commonly referred to as metal-1); in such an example, the silicided active region defines a lower metal layer Mx, where x=0 (i.e., M 0 ) And the first metal interconnection layer (metal-1) defines an upper metal layer M x+1 (i.e., M 1 )。
In some examples, the antifuse device may be formed concurrently with certain interconnect structures (e.g., interconnect vias) separate from the antifuse device. For example, as shown in the methods of fig. 3A-3I discussed below, the cup-shaped bottom antifuse electrode of the antifuse device may be formed concurrently with the interconnect via by depositing a conformal metal layer (e.g., tungsten) into the respective openings for the cup-shaped bottom antifuse electrode and the interconnect via.
In other examples, the antifuse device may be formed separately from the interconnect structure, i.e., not simultaneously with the interconnect structure. For example, fig. 2 illustrates an exemplary antifuse device that may be formed separately from an interconnect structure, or alternatively, may be formed concurrently with an interconnect structure (e.g., an interconnect via).
As discussed below with reference to fig. 3A-3I, the antifuse device may be constructed using a damascene process and without adding any masking operations to the background integrated circuit fabrication process.
Fig. 1A and 1B illustrate an exemplary integrated circuit device 100 including an exemplary antifuse device 102 and an exemplary interconnect structure 104. Specifically, FIG. 1A shows a top view of integrated circuit device 100, and FIG. 1B shows a side cross-sectional view of integrated circuit device 100 through scribe line 1B-1B shown in FIG. 1A. As shown, exemplary antifuse device 102 has a lower metal layer Mx and an upper layer M formed thereon x+1 A three-dimensional (3D) metal/insulator/metal (MIM) structure in between. In the example shown in fig. 1A to 1B, the lower metal layer M x And upper layer M x+1 Representing two adjacent metal interconnect layers such that antifuse device 102 is formed at the two adjacent metal interconnect layers M x And M is as follows x+1 Between via layers V x Is a kind of medium. In other examples, for example, as shown in fig. 5 discussed below, an antifuse device may be formed between a silicided active region (including one or more silicon-based transistors including a silicided structure) and a first metal interconnect layer (commonly referred to as metal-1).
As shown in fig. 1A-1B, the exemplary interconnect structure 104 includes: formed on the lower metal layer M x Lower interconnection element 110 of (a), upper metal layer M x+1 Upper interconnection element 112 of (1), formed in the viaPore layer V x And electrically connects the upper interconnect element 112 to at least one interconnect via 114 of the lower interconnect element 110.
Each of the lower interconnect element 110 and the upper interconnect element 112 may include: wires or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, substantially square, or substantially circular shape in the x-y plane), or any other suitable shape and structure.
Exemplary antifuse device 102 is formed in a tub opening 129 formed in via layer V x In the dielectric region 108. Antifuse device 102 includes: a cup-shaped bottom antifuse electrode 120, a cup-shaped antifuse insulator 122 formed in an opening 136 defined by the cup-shaped bottom antifuse electrode 120, and a top antifuse electrode 124 formed in an opening 144 defined by the cup-shaped antifuse insulator 122.
As discussed below with reference to the method shown in fig. 3A-3I, cup-shaped bottom antifuse electrode 120 may be formed simultaneously with interconnect via 114 by depositing a conformal metal into via opening 115 and barrel opening 129 formed in dielectric region 108. In some examples, the conformal metal forming cup-shaped bottom antifuse electrode 120 and interconnect via 114 may comprise tungsten, cobalt, aluminum, or other conformal metal. In some examples, liner 138 (e.g., comprising titanium nitride (TiN)) is deposited in tub opening 129 and via opening 115 prior to the conformal metal to improve adhesion between the conformal metal and dielectric region 108.
The cup-shaped bottom antifuse electrode 120 includes: (a) A laterally extending bottom antifuse electrode base 130 formed over and electrically connected to underlying bottom antifuse electrode contact 116, and (b) vertically extending bottom antifuse electrode sidewalls 132 extending upward from laterally extending bottom antifuse electrode base 130. In the illustrated example, the laterally extending bottom antifuse electrode base 130 has a rectangular shape, and the vertically extending bottom antifuse electrode sidewalls 132 have a closed loop rectangular shape extending laterally upward from a lateral perimeter of the laterally extending bottom antifuse electrode base 130 (as shown in fig. 1A).
Cup-shaped antifuse insulator 122 is formed in an opening 136 defined by cup-shaped bottom antifuse electrode 120, and includes: a laterally extending insulator base 140 formed on the bottom antifuse electrode base 130, and a vertically extending insulator sidewall 142 extending upward from the laterally extending insulator base 140, wherein the vertically extending insulator sidewall 142 is formed on the vertically extending bottom antifuse electrode sidewall 132.
The thickness of cup-shaped antifuse insulator 122 may define or affect the breakdown voltage of antifuse device 102. Thus, in some examples, cup-shaped antifuse insulator 122 may be formed with a predetermined thickness that provides a pre-specified breakdown voltage of antifuse device 102. For example, cup-shaped antifuse insulator 122 may be formed with a defined thickness that provides a breakdown voltage of antifuse device 102 below 15V, below 10V, below 7V, or below 5V. As used herein, the thickness of the cup-shaped antifuse insulator refers to the minimum thickness of: (a) Minimum vertical thickness T of laterally extending insulator base 140 140 And (b) a minimum lateral thickness T of the vertically extending insulator sidewall 142 142 。
In some examples, cup-shaped antifuse insulator 122 has a thickness less thanFor example, according to a particular example, the thickness of cup-shaped antifuse insulator 122 may be +.>To->Within (1) or>To->Within a range of (2).
In some examples, cup-shaped antifuse insulator 122 comprises silicon oxide (SiO 2 ) An ONO layer stack or a NON layer stack or alumina (Al 2 O 3 )。
The top antifuse electrode 124 of the exemplary antifuse device 102 is formed in an opening 144 defined by a cup-shaped antifuse insulator 122. In some examples, top antifuse electrode 124 may comprise titanium nitride (TiN), titanium (Ti), tungsten (W), or a combination thereof. Thus, in some examples, both bottom antifuse electrode 120 and top antifuse electrode 124 may be formed of a refractory metal (e.g., W, tiN or Ti), which may reduce or eliminate hillock generation, which may provide a tight programming voltage window (e.g., in the range of a few volts without outliers) and thereby avoid uncontrolled (unintended) low voltage programming of the antifuse.
A dielectric barrier 150 may be formed over top antifuse electrode 124, vertically extending insulator sidewalls 142, vertically extending bottom antifuse electrode sidewalls 132, and interconnect via 114. In some examples, the dielectric barrier 150 may be included withTo->Silicon nitride (SiN) or silicon carbide (SiC) in a thickness in the range of (a). Dielectric barrier 150 may act as a diffusion barrier (e.g., to prevent or reduce diffusion from top antifuse electrode 124 formed of, for example, copper or other diffusive material) and seal the top side of antifuse device 102, which may cooperate with cup-shaped bottom antifuse electrode 120 (e.g., formed of tungsten) to define a sealed enclosure for antifuse device 102 to accommodate the physical effect of breaking the fuse link (commonly referred to as "blowing the fuse"), and thereby prevent or reduce collateral damage to nearby structures in integrated circuit device 100 caused by associated energy release.
Formed on the via layer V x An upper metal layer over (in which the antifuse device 102 and interconnect via 114 are constructed)(M x+1 ) Comprising the following steps: a top antifuse electrode contact 158 electrically connected to top antifuse electrode 124, and an upper interconnect element 112 electrically connected to interconnect via 114. In some implementations, a damascene process (e.g., using copper, tungsten, or aluminum) is used to form top antifuse electrode contact 158 and upper interconnect element 112. For example, top antifuse electrode contact 158 and upper interconnect element 112 may comprise a copper element formed over barrier layer 159 (e.g., a TaN/Ta bilayer). In some examples, dielectric barrier 150 may be at upper metal layer M in addition to sealing the topside of antifuse device 102 as described above x+1 Acts as an etch stop during construction (e.g., during an etch process that forms respective openings for upper interconnect element 158 and top antifuse electrode contact 112).
In some examples, antifuse device 102 is formed concurrently with interconnect structure 104. For example, as described below, cup-shaped bottom antifuse electrode 120 may be formed concurrently with interconnect via 114. As described above, in other examples, antifuse device 102 may be formed independently of interconnect structure 104 (not at the same time).
Fig. 2 illustrates a side cross-sectional view of the exemplary antifuse device 102 described above. As described above, antifuse device 102 may include: a cup-shaped bottom antifuse electrode 120 formed in dielectric region 108, a cup-shaped antifuse insulator 122 formed in an opening defined by cup-shaped bottom antifuse electrode 120, and a top antifuse electrode 124 formed in an opening defined by cup-shaped antifuse insulator 122. In some examples, cup-shaped antifuse insulator 122 has a thickness less thanFor example, according to a particular example, the thickness of cup-shaped antifuse insulator 122 may be +.>To->Within (1) or>To the point ofWithin a range of (2). As described above, in some examples, antifuse device 102 may be formed separately from an interconnect structure (e.g., an interconnect via), or alternatively may be formed concurrently with an interconnect structure (e.g., an interconnect via formed in dielectric region 108).
Fig. 3A-3I illustrate an exemplary process for forming the integrated circuit device 100 (including the exemplary antifuse device 102 and the exemplary interconnect structure 104) shown in fig. 1. Those skilled in the art will recognize that the same process (without reference to interconnect structure 104) may be used to form integrated circuit structure 102 shown in fig. 2.
First, as shown in FIG. 3A (top view) and FIG. 3B (cross-sectional side view through line 3B-3B shown in FIG. 3A), a metal layer M is formed on the lower portion x Dielectric region 108 is formed thereon, lower metal layer M x Including lower interconnect element 110 and bottom antifuse electrode contact 116. Dielectric region 108 may include an inter-metal dielectric (IMD) region, for example, comprising silicon oxide, fluorinated Silicate Glass (FSG), organosilicate glass (OSG), or porous OSG. The lower interconnect element 110 and the bottom antifuse electrode contact 116 may comprise copper elements formed by a damascene process. The lower interconnect element 110 and the bottom antifuse electrode contact 116 may comprise: corresponding conductive lines or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, substantially square, or substantially circular shape in the x-y plane), or any other suitable shape and structure.
A photoresist layer 302 is deposited and patterned to form photoresist openings, and underlying dielectric region 108 is etched through the photoresist openings to form tub openings 129 for forming antifuse device 102 and via openings 115 in dielectric region 108. The via opening 115 may have a square, circular, or other suitable shape, as viewed from a top view (x-y plane), or, for example, wherein the width (or diameter or Critical Dimension (CD)) W Through hole In the range of 0.1 μm to 0.35 μm in both the x-direction and the y-direction.
In contrast, the tub opening 129 may have a significantly larger width W in the x-direction than the via opening 115 Bucket_x And width W in y direction Bucket_y . Accordingly, the drum opening 129 may be referred to as a "drum" opening. The shape and size of the tub opening 129 may be selected based on various parameters, for example, for efficient fabrication and/or desired performance characteristics of the antifuse device 102 being formed. In one example, the tub opening 129 may have a square or rectangular shape in the x-y plane. In other examples, the drum opening 129 may have a circular or oval shape in the x-y plane.
As described above, the width (W Bucket_x ) Width in y direction (W Bucket_y ) Or width in both x-direction and y-direction (W Bucket_x And W is Bucket_y ) May be substantially greater than the width W of the via opening 115 in the x-direction Through hole And width W of the via opening 115 in the y direction Through hole Both of which are located in the same plane. For example, in some examples, W of drum opening 129 Bucket_x And W is Bucket_y Is the width W of the via opening 115 Through hole At least twice as many as (a). In a particular example, each width W of the tub opening 129 Bucket_x And W is Bucket_y Width W of the via opening 115 Through hole Is at least five times larger. Each width (W) of the tub opening 129 Bucket_x And W is Bucket_y ) It may be sufficient to allow for the construction of antifuse device 102 within barrel opening 129 by a damascene process, for example, to allow for the construction of cup-shaped bottom antifuse electrode 120, cup-shaped antifuse insulator 122 formed in opening 136 of cup-shaped bottom antifuse electrode 120, and top antifuse electrode 124 formed in opening 144 of cup-shaped antifuse insulator 122. In some examples, W Bucket_x And W is Bucket_y Each in the range of 0.5 μm to 10 μm, for example in the range of 0.5 μm to 2 μm.
In addition, the tub opening 129 may be formed with an aspect ratio in both the x-direction and the y-direction of less than or equal to 2.0, for example, to allow the tub opening 129 to be efficiently filled with a conformal material. For example, barrelsThe openings 129 may be formed with an aspect ratio H each in the range of 0.1 to 2.0 (e.g., in the range of 0.5 to 2.0) Barrel (barrel) /W Bucket_x And H Barrel (barrel) /W Bucket_y . In some examples, aspect ratio H Barrel (barrel) /W Bucket_x And H Barrel (barrel) /W Bucket_y Each less than or equal to 1.5, for example, for effectively filling the tub opening 129 with a conformal material (e.g., tungsten, cobalt, or aluminum). For example, the tub openings 129 may be formed with aspect ratios H each in the range of 0.5 to 1.5 (or more specifically in the range of 0.8 to 1.2) Barrel (barrel) /W Bucket_x And H barrel/W Bucket_y 。
As shown in fig. 3C, photoresist layer 302 is removed and liner 138 (e.g., comprising TiN) is deposited over dielectric region 108 and extends down into tub opening 129 and via opening 115. The liner 138 may be deposited using a Physical Vapor Deposition (PVD) process or a Chemical Vapor Deposition (CVD) process. In some examples, liner 138 may be present inTo->Within a range of (2).
Conformal metal 312 may be deposited over liner 138 and extend down into tub opening 129 and via opening 115. As shown, deposited conformal metal 312 (a) fills via opening 115 to form interconnect via 114 and (b) covers the interior surface of tub opening 129 to form cup-shaped bottom antifuse electrode 120 of antifuse device 102 defining opening 136. As described above, cup-shaped bottom antifuse electrode 120 includes a vertically extending bottom antifuse electrode sidewall 132 extending upward from a laterally extending bottom antifuse electrode cup base 130, and in one example, vertically extending bottom antifuse electrode sidewall 132 extends upward from a lateral side or perimeter of laterally extending bottom antifuse electrode cup base 130. In one example, the conformal metal 312 includes a layer deposited withTo->Tungsten of a thickness in the range of (a). In other examples, the conformal metal 312 may comprise cobalt, aluminum, or other conformal metals. The conformal metal 312 may be deposited by a conformal Chemical Vapor Deposition (CVD) process or other suitable deposition process. Liner 138 (e.g., comprising TiN) may increase or enhance adhesion of conformal metal 312 to the interior surfaces of tub opening 129 (including the vertical sidewall surfaces of tub opening 129) to facilitate formation of cup-shaped bottom antifuse electrode 120.
As shown in fig. 3D, an insulator layer 320 is deposited over the conformal metal 312 and extends down into the opening 136 defined by the cup-shaped bottom antifuse electrode 120 to define a cup-shaped antifuse insulator 122 in the opening 136. The cup-shaped antifuse insulator 122 comprises: a laterally extending insulator base 140, and vertically extending insulator sidewalls 142 extending upwardly from the lateral sides of the laterally extending insulator base 140. Cup-shaped antifuse insulator 122 defines an opening 144.
In some examples, insulator layer 320 (including cup-shaped antifuse insulator 122) is deposited with less than(e.g. in->To->Within (a) or in some examples +.>To->Within a range of (2) layer thickness T 320 . In some examples, insulator layer 320 includes: (a) By Plasma Enhanced Chemical Vapor Deposition (PECVD) or otherSuitable deposition processes deposit silicon oxide (SiO 2 ) An oxide-nitride-oxide (ONO) layer stack or a nitride-oxide-nitride (NON) layer stack, or (b) aluminum oxide (Al) deposited by Atomic Layer Deposition (ALD) or other suitable deposition process 2 O 3 ) Or (c) other suitable insulator materials.
As shown in fig. 3E, top electrode metal 330 may be deposited over insulator layer 320 and extend down into openings 144 defined by cup-shaped antifuse insulator 122 to define top antifuse electrode 124 in openings 144. The top electrode metal 330 may comprise titanium nitride (TiN), titanium (Ti), tungsten (W), tantalum nitride, copper, or combinations thereof, and may be deposited by a PVD process with sufficient thickness to fill the openings 144.
As shown in fig. 3F (top view) and 3G (cross-sectional side view through line 3G-3G shown in fig. 3F), a planarization process may be performed to remove upper portions of conformal metal 312, insulator layer 320, and top electrode metal 330 outside of tub opening 129 and via opening 115, leaving cup-shaped bottom antifuse electrode 120, cup-shaped antifuse insulator 122, and top antifuse electrode 124 in tub opening 129. In some examples, the planarization process includes a Chemical Mechanical Planarization (CMP) process. The planarization process effectively planarizes the top surfaces of cup-shaped bottom antifuse electrode 120, cup-shaped antifuse insulator 122, top antifuse electrode 124, via 114, and surrounding dielectric region 108.
According to the above process, the antifuse device 102 may be formed by a damascene process, which includes: (a) A planarization process that deposits the conformal metal 312, insulator layer 320, and top electrode metal 330 over the dielectric region 108 and extends down into the tub opening 129, and (b) removes the upper portion of the conformal metal 312, insulator layer 320, and top electrode metal 330 outside (above) the tub opening 129. The planarization process may be applicable to a variety of electrode materials for the conformal metal 312 and/or the top electrode metal 330, including without limitation, for example W, WO 3 、Al 2 O 3 TiW, ta, taN or Cu.
As shown in fig. 3H, a dielectric barrier 150 may be depositedOn integrated circuit device 100 to completely enclose and seal the exposed top surface of antifuse device 102. In some examples, the dielectric barrier 150 may be included withTo->Within (e.g. in +.>To->In the range of (c), such as silicon nitride (SiN) or silicon carbide (SiC). The dielectric barrier 150 and cup-shaped bottom antifuse electrode 120 may together define a sealed enclosure for the antifuse device 102 that may accommodate physical forces caused by a blown fuse condition and thereby prevent or reduce collateral damage to nearby structures in the integrated circuit device 100. Dielectric barrier 150 may also act as a diffusion barrier to prevent or reduce metal diffusion from top antifuse electrode 124 formed, for example, of copper or other diffusible material.
As shown in fig. 3I, an upper metal layer M x+1 (including top antifuse electrode contact 158 and upper interconnect element 112) may be formed over via layer Vx (including antifuse device 102 and interconnect via 114), for example, using a damascene process. In one example, an upper metal layer M x+1 Including copper interconnect layers formed by a copper damascene process.
To form the upper metal layer M x+1 A dielectric layer 156 is first deposited over the dielectric barrier 150. In some examples, the dielectric layer 156 may include silicon oxide (SiO 2 ) FSG (fluorosilicate glass), OSG (organosilicate glass), or porous OSG. Dielectric layer 156 may be patterned and etched to form top antifuse electrode contact opening 350 over top antifuse electrode 124, and interconnect opening 352 (exampleSuch as trench openings) where etching first stops on dielectric barrier 150 and then proceeds through the dielectric barrier through top antifuse electrode contact opening 350 and interconnect opening 352. Dielectric barrier 150 may act as an etch stop layer for forming top antifuse electrode contact opening 350 and interconnect opening 352 to improve the etching process margin.
A barrier layer 159 (e.g., a TaN/Ta bilayer) and a copper seed layer may be deposited over the dielectric layer 156 and extend down into the etched top antifuse electrode contact opening 350 and interconnect opening 352. A copper plating process may then be performed that fills the top antifuse electrode contact opening 350 and interconnect opening 352 with copper. A copper anneal may be performed followed by a copper CMP process to remove the copper portion over dielectric layer openings 350 and 352, thereby defining top antifuse electrode contact 158 electrically connected to top antifuse electrode 124, and upper interconnect element 112 electrically connected to via 114.
Forming an upper metal layer M as discussed above x+1 Thereafter, the process may be continued to build additional interconnect structures, for example, by building additional metal layers separated by respective dielectric layers.
As described above, in some examples, an integrated antifuse device may be built on two interconnect layers M x And M is as follows x+1 Between, or between the active region and the first metal interconnect layer (metal-1). In other examples, multiple antifuse devices may be formed at different depths in an integrated circuit device, which may provide higher packing density of the antifuse devices.
Fig. 4 illustrates an exemplary IC structure 400, which includes: two exemplary antifuse devices 402a and 402b formed at different depths in integrated circuit structure 400, and an exemplary interconnect structure 404. First antifuse device 402a is formed in metal interconnect layer M x And M is as follows x+1 A first via layer V between x And a second antifuse device 402b is formed in the metal interconnect layer M x+1 And M is as follows x+2 A second via layer V therebetween x+1 Is a kind of medium. First antifuse device 402a is conductively connected to a metal interconnect layer formed on the metal interconnect layerM x Lower metal contact 404 of (a) x And formed on the metal interconnection layer M x+1 Upper metal contact 404 of (a) x+1 And a second antifuse device 402b is conductively connected to a metal interconnect layer M formed therein x+1 Lower metal contact 406 of (a) x+1 And formed on the metal interconnection layer M x+2 Upper metal contact 406 in (a) x+2 Between them.
Exemplary first antifuse device 402a and second antifuse device 402b may be similar to exemplary antifuse device 102 described above, e.g., formed of similar materials as disclosed above and formed according to the exemplary process shown in fig. 3A-3I. Thus, the first antifuse device 402a includes: a cup-shaped lower electrode 420a formed over liner 438a (similar to liner 138 described above), a cup-shaped antifuse insulator 422a formed in an opening defined by cup-shaped lower electrode 420a, and a top antifuse electrode 424a formed in an opening defined by cup-shaped antifuse insulator 422 a. Similarly, the second antifuse device 402b includes: a cup-shaped lower electrode 420b formed over liner 438b, a cup-shaped antifuse insulator 422b formed in an opening defined by cup-shaped lower electrode 420b, and a top antifuse electrode 424b formed in an opening defined by cup-shaped antifuse insulator 422 b.
Exemplary interconnect structure 404 includes: metal interconnect element 410 x 、410 x+1 And 410 x+2 And interconnect via 414 x And 414 x+1 . In this example, first antifuse device 402a may be in communication with interconnect via 414 x Simultaneously forming, for example, cup-shaped bottom antifuse electrode 420a and interconnect via 414 x Can be formed on the first through hole layer V x Dielectric material 408 in (a) x Tungsten or other conformal material is deposited in the corresponding openings in the substrate to be formed simultaneously. Similarly, antifuse device 402b may be in communication with interconnect via 414 x+1 Simultaneously forming, for example, cup-shaped bottom antifuse electrode 420b and interconnect via 414 x+1 Can be formed on the second through hole layer V x+1 Dielectric material 408 in (a) x+1 Tungsten or other conformal material is deposited in the corresponding openings in the substrate to be formed simultaneously.
Fig. 5 illustrates an exemplary integrated circuit device 500 including an exemplary antifuse device 502 and an exemplary interconnect structure 504. Antifuse device 502 may be similar to antifuse device 102 described above. However, unlike the example shown in fig. 1A to 1B (in which the antifuse device 102 is formed in two adjacent metal interconnect layers M x And M is as follows x+1 Between), antifuse device 502 is formed in (a) a silicided active region M comprising silicided structures (e.g., silicided transistor elements) 0 (i.e., M x Where x=0) and (b) a first metal interconnect layer M, commonly referred to as metal-1 1 (i.e., M x+1 Where x=0).
As shown in fig. 5, the active region M is silicided 0 Including a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 510 formed on a silicon substrate 512. MOSFET 510 may include: a polysilicon gate 514 formed over and separated from the silicon substrate 512 by a gate oxide layer 516, and doped source and drain regions 520, 522 formed in the silicon substrate 512. In this example, polysilicon gate 514 and doped drain region 522 include silicide structures 524. Specifically, a metal silicide layer 530 is formed on the top surface of the doped drain region 522, and a metal silicide layer 532 is formed on the top surface of the polysilicon gate 514. Metal silicide layers 530 and 532 may be includedTo->Any suitable metal silicide layer, such as titanium silicide (TiSi 2), cobalt silicide (CoSi 2), or nickel silicide (NiSi), of a thickness within the range of (a) or other suitable thickness. For purposes of this disclosure, metal silicide layers 530 and 532 define a metal structure such that active region M is silicided 0 May be considered a metal layer.
In the example shown in fig. 5, antifuse device 502 is formed on a metal silicide layer 530 on top of doped drain region 522 to provide a conductive connection between antifuse device 502 and doped drain region 522. Antifuse device 502 passes through the topAntifuse electrode contact 158 is contacted from above, as described above. In addition, vias 114 (also referred to as contacts) are formed on the metal silicide layer 532 on top of the polysilicon gate 514 to provide a conductive connection between the polysilicon gate 514 and the upper interconnect element 112. Top antifuse electrode contact 158 and upper interconnect element 112 comprise a metal formed in a first metal interconnect layer M, such as by a damascene process 1 Is a metal element of the group (C).
Claims (16)
1. An integrated circuit device, the integrated circuit device comprising:
an antifuse device, the antifuse device comprising:
a cup-shaped bottom antifuse electrode formed in a dielectric region;
a cup-shaped antifuse insulator formed in an opening defined by the cup-shaped bottom antifuse electrode;
wherein the cup-shaped antifuse insulator has a thickness less thanAnd
a top antifuse electrode formed in an opening defined by the cup-shaped antifuse insulator.
2. The integrated circuit device of claim 1, wherein the thickness of the cup-shaped antifuse insulator is atTo->Within a range of (2).
3. The integrated circuit device of claim 1, wherein the thickness of the cup-shaped antifuse insulator is atTo->Within a range of (2).
4. The integrated circuit device of any of claims 1-3, wherein the antifuse device has a breakdown voltage of less than 15V.
5. The integrated circuit device of any of claims 1-3, wherein the antifuse device has a breakdown voltage below 7V.
6. The integrated circuit device of any of claims 1-5, wherein the cup-shaped antifuse insulator comprises silicon oxide (SiO 2 ) Oxide-nitride-oxide (ONO), nitride-oxide-nitride (NON) or alumina (Al) 2 O 3 )。
7. The integrated circuit device of any of claims 1 to 6, comprising:
a bottom antifuse electrode contact formed in a lower metal interconnect layer, wherein the bottom antifuse electrode contact is electrically connected to the cup-shaped bottom antifuse electrode; and
a top antifuse electrode contact formed in an upper metal interconnect layer, wherein the top antifuse electrode contact is electrically connected to the top antifuse electrode.
8. The integrated circuit device of any of claims 1-7, comprising a transistor comprising a doped source region and a doped drain region;
wherein the cup-shaped bottom antifuse electrode is electrically connected to a silicide region of the transistor formed over the source region or a silicide region formed over the drain region.
9. An integrated circuit device, the integrated circuit device comprising:
an interconnect structure, the interconnect structure comprising:
a lower interconnect element formed in the lower metal layer;
an upper interconnect element formed in the upper metal layer; and
an interconnect via formed in a dielectric region between the lower metal layer and the upper metal layer, the interconnect via electrically connecting the upper interconnect element to the lower interconnect element; and
an antifuse device comprising any one of the antifuse devices as claimed in claims 1 to 8.
10. The integrated circuit device of claim 9, wherein:
the lower interconnect element and the bottom antifuse electrode contact are formed in the lower metal interconnect layer; and
the upper interconnect element and the top antifuse electrode contact are formed in the upper metal interconnect layer.
11. A method of forming an antifuse device, the method comprising:
forming a tub opening in the dielectric region;
depositing a conformal metal over the dielectric region and extending into the tub opening to form a cup-shaped bottom antifuse electrode in the tub opening;
depositing a metal layer with a thickness less thanTo define a cup-shaped antifuse insulator in an opening defined by the cup-shaped bottom antifuse electrode, an insulating layer of layer thickness ofThe cup-shaped antifuse insulator comprises: a laterally extending antifuse insulator base, and vertically extending antifuse insulator sidewalls extending upward from the laterally extending antifuse insulator base;
depositing a top electrode metal over the insulator layer and extending into an opening defined by the cup-shaped antifuse insulator; and
a planarization process is performed to remove upper portions of the conformal metal, insulator layer, and top electrode metal outside the tub opening.
12. The method according to claim 11, the method comprising: depositing the belt onTo->The insulator layer having a layer thickness within the range of (1).
13. The method according to claim 11, the method comprising: depositing the belt onTo->The insulator layer having a layer thickness within the range of (1).
14. The method according to any one of claims 11 to 13, the method comprising:
depositing a dielectric barrier layer over a planarized upper surface defined by the planarization process, the dielectric barrier layer extending over vertically extending sidewalls of the cup-shaped bottom antifuse electrode, the vertically extending antifuse insulator sidewalls, and the top antifuse electrode;
depositing an upper dielectric layer over the dielectric barrier layer;
etching the upper dielectric layer and the dielectric barrier layer to form a top antifuse electrode contact opening exposing an upper surface of the top antifuse electrode, wherein the dielectric barrier layer acts as an etch stop; and
the top antifuse electrode contact opening is filled to form a top antifuse electrode contact electrically connected to the top antifuse electrode.
15. The method of any of claims 11-15, wherein the antifuse device is formed without adding any photomask process to a background integrated circuit fabrication process.
16. An anti-fuse device prepared by any one of the methods of claims 1 to 15.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63/222,367 | 2021-07-15 | ||
| US17/862,693 US20230021192A1 (en) | 2021-07-15 | 2022-07-12 | Anti-fuse device with a cup-shaped insulator |
| US17/862,693 | 2022-07-12 | ||
| PCT/US2022/037076 WO2023287955A1 (en) | 2021-07-15 | 2022-07-14 | Anti-fuse device with a cup-shaped insulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117063236A true CN117063236A (en) | 2023-11-14 |
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ID=88669671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202280025031.5A Pending CN117063236A (en) | 2021-07-15 | 2022-07-14 | Antifuse device with cup-shaped insulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117063236A (en) |
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2022
- 2022-07-14 CN CN202280025031.5A patent/CN117063236A/en active Pending
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