CN117060715A

CN117060715A - Switching capacitor type voltage conversion circuit and switching capacitor converter control method

Info

Publication number: CN117060715A
Application number: CN202211164236.XA
Authority: CN
Inventors: 刘国基; 杨大勇
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2022-05-04
Filing date: 2022-09-23
Publication date: 2023-11-14
Also published as: TWI818731B; TW202345503A

Abstract

A switched capacitor voltage conversion circuit and a control method of the switched capacitor voltage conversion circuit are provided, wherein the switched capacitor voltage conversion circuit comprises a switched capacitor converter and a control circuit. The switched capacitor converter comprises at least one resonant capacitor, a plurality of switches and at least one inductor. The control circuit generates a pulse width modulation signal according to the first voltage or the second voltage, and generates a control signal according to the pulse width modulation signal and the zero current detection signal to control the switched capacitor converter to operate the corresponding switches so as to switch the electric connection relation of the corresponding inductors, thereby converting the first voltage into the second voltage or converting the second voltage into the first voltage.

Description

Switching capacitor type voltage conversion circuit and switching capacitor converter control method

Technical Field

The present invention relates to a switched capacitor voltage conversion circuit and a method for controlling a switched capacitor converter, and more particularly, to a switched capacitor voltage conversion circuit and a method for controlling a switched capacitor converter controlled by a pulse width modulation signal and a zero current detection signal.

Background

A paper by the Institute of Electrical and Electronics Engineers (IEEE) application power electronics seminar in 2005: "Three-level buck converter for packet trace of an rf power amplifier" ("Three-Level Buck Converter for Envelope Tracking in RF Power Amplifiers"), a Three-level buck converter is proposed for packet trace applications, such as packet trace in an rf power amplifier; to achieve high efficiency and high power density, the flying capacitor (flying capacitor) voltage across must be regulated to half the input voltage.

Fig. 1A shows a conventional switched slot converter (switched tank converter, STC) of U.S. Pat. No. 9,917,517B 1. This known STC can achieve high efficiency power conversion but it is a voltage divider that does not regulate voltage regulation; when the input voltage increases, the output voltage increases, and the output voltage cannot be regulated stably.

Fig. 1B shows a conventional buck converter circuit 10. The inductor L of the buck converter 10 is subjected to voltage stress of the input voltage level, so that it requires a larger size inductor and a higher inductance value. In general, a higher switching frequency can enable a conversion circuit with a smaller size of inductance. However, switching power loss also increases significantly with high switching frequencies and high input voltages to the switch.

In view of the above, the present invention provides an innovative switched capacitor voltage conversion circuit and a control method of the switched capacitor converter.

Disclosure of Invention

In one aspect, the present invention provides a switched capacitor voltage conversion circuit for converting a first voltage to a second voltage or vice versa, the switched capacitor voltage conversion circuit comprising: a switched capacitor converter coupled between the first voltage and the second voltage; the control circuit is used for generating a pulse width modulation signal according to the first voltage or the second voltage, and generating a control signal according to the pulse width modulation signal and a zero current detection signal to control the switched capacitor converter so as to convert the first voltage into the second voltage or convert the second voltage into the first voltage; wherein the switched capacitor converter comprises: at least one resonant capacitor; a plurality of switches coupled to the at least one resonant capacitor; and at least one inductor; when the first voltage is converted into the second voltage, the control signal comprises a unidirectional conduction operation signal, a first operation signal and a second operation signal, so as to respectively correspond to a unidirectional conduction program, a first program and a second program, and further be used for operating the corresponding switches to switch the electric connection relation of the corresponding inductors; when the first voltage is converted into the second voltage, the control circuit generates the pulse width modulation signal according to the second voltage, and the operation modes of the one-way conduction program, the first program and the second program are as follows: in the unidirectional conduction program, the unidirectional conduction operation signals control the switching of the switches so as to form a unidirectional conduction path between a first direct current potential and the second voltage, and an inductance current flowing through the inductance flows to the second voltage through the unidirectional conduction path; in the first procedure, the switching of the switches is controlled by the first operation signal, so that the corresponding resonant capacitor and the corresponding inductor are connected in series between the second voltage and a second direct current potential to form a first current path, and the inductor current flowing through the inductor and flowing to the second voltage is a resonant current with a first resonant frequency; in the second procedure, the switching of the switches is controlled by the second operation signal, so that the corresponding resonant capacitor and the corresponding inductor are connected in series between the first voltage and the second voltage to form a second current path, and the inductor current flowing through the inductor and flowing to the second voltage is a resonant current with a second resonant frequency; the unidirectional conduction operation signal, the first operation signal and the second operation signal are respectively switched to an enabling level in a corresponding enabling period, and the enabling periods of the segments are not overlapped with each other, so that the unidirectional conduction program, the first program and the second program are not overlapped with each other; the unidirectional conduction program, the first program and the second program are sequentially ordered into a combination, and then the combination is repeated, so that the inductor performs inductive power conversion switching among the unidirectional conduction program, the first program and the second program, and further converts the first voltage into the second voltage; the control circuit also generates the zero current detection signal according to the time point when the inductance current reaches zero current.

In another aspect, the present invention provides a method for controlling a switched capacitor converter, which is used for converting a first voltage into a second voltage or converting the second voltage into the first voltage, the method comprising: generating a pulse width modulation signal according to the first voltage or the second voltage; generating a zero current detection signal according to the time point when an inductance current reaches zero current; generating a control signal to control a switched capacitor converter according to the pulse width modulation signal and the zero current detection signal, so as to convert the first voltage into the second voltage or convert the second voltage into the first voltage; when the first voltage is converted into the second voltage, the pulse width modulation signal is generated according to the second voltage, and the control signal comprises a unidirectional conduction operation signal, a first operation signal and a second operation signal, so as to respectively correspond to a unidirectional conduction program, a first program and a second program, and further be used for operating a plurality of corresponding switches to switch the electric connection relation of a corresponding inductor; when the first voltage is converted into the second voltage, the unidirectional conduction procedure, the first procedure and the second procedure are operated as follows: in the unidirectional conduction program, the unidirectional conduction operation signals control the switching of the switches so as to form a unidirectional conduction path between a first direct current potential and the second voltage, and the inductive current flowing through the inductor flows to the second voltage through the unidirectional conduction path; in the first procedure, the switching of the switches is controlled by the first operation signal, so that a corresponding resonant capacitor and a corresponding inductor are connected in series between the second voltage and a second direct current potential to form a first current path, and the inductor current flowing through the inductor and flowing to the second voltage is a resonant current with a first resonant frequency; in the second procedure, the switching of the switches is controlled by the second operation signal, so that the corresponding resonant capacitor and the corresponding inductor are connected in series between the first voltage and the second voltage to form a second current path, and the inductor current flowing through the inductor and flowing to the second voltage is a resonant current with a second resonant frequency; the unidirectional conduction operation signal, the first operation signal and the second operation signal are respectively switched to an enabling level in a corresponding enabling period, and the enabling periods of the segments are not overlapped with each other, so that the unidirectional conduction program, the first program and the second program are not overlapped with each other; the unidirectional conduction program, the first program and the second program are sequentially ordered into a combination, and then the combination is repeated, so that the inductor performs inductive power conversion switching among the unidirectional conduction program, the first program and the second program, and further converts the first voltage into the second voltage.

In one embodiment, the control circuit includes: the pulse width modulation circuit is used for generating the pulse width modulation signal according to the second voltage when the first voltage is converted into the second voltage, and generating the pulse width modulation signal according to the first voltage when the second voltage is converted into the first voltage; a zero current detection circuit for generating the zero current detection signal when the inductance current reaches the zero current; and a control signal generating circuit for generating the control signal according to the pulse width modulation signal and the zero current detection signal, and generating a plurality of switch operation signals corresponding to the plurality of switches in the unidirectional conduction program, the first program and the second program according to the control signal.

In an embodiment, the unidirectional current process, the first process and the second process form a switching period, the arrangement sequence of the unidirectional current process, the first process and the second process in the switching period can be arbitrarily combined, the ending time of the earliest process in the switching period is determined by the pulse width modulation signal, and the ending time of other processes except the earliest process in the switching period is determined by the zero current detection signal.

In one embodiment, the inductor current is one of the following: the inductance current is a resonance current with a third resonance frequency; or the inductor current is a non-resonant current; wherein when the inductor current is the non-resonant current, the inductor current is a linear ramp current that gradually decreases or another linear ramp current that gradually increases.

In an embodiment, in the unidirectional current conduction procedure, the inductor current is a non-resonant current and is the linear ramp current that gradually decreases, and the unidirectional current conduction path includes a body diode (body diode) in at least one of the switches in a non-conductive state through which the inductor current flows.

In one embodiment, in the unidirectional conduction process, the unidirectional conduction path includes at least one of the switches in a conduction state through which the inductor current flows.

In one embodiment, the first dc potential is the first voltage or a ground potential, and the second dc potential is the first voltage or the ground potential.

In one embodiment, the pulse width modulation circuit includes: a locking circuit for locking the second voltage to a reference voltage to generate a voltage locking signal; a ramp circuit for generating a ramp signal; and a comparison circuit for comparing the voltage locking signal and the ramp signal to generate the pulse width modulation signal.

In one embodiment, the ramp circuit includes a reset circuit for resetting the ramp signal according to the control signal or a clock signal.

In one embodiment, the control signal adjusts the enabling period of the first program and/or the second program to achieve zero voltage switching or zero current switching of soft switching (soft switching).

In one embodiment, the switching period is a fixed period.

In one embodiment, after the unidirectional current process, the first process and the second process of the switching cycle are all completed, the switches are kept not to conduct a zero current period until the fixed period is completed.

In an embodiment, the switched capacitor voltage conversion circuit further includes a non-resonant capacitor coupled to the resonant capacitor, wherein a voltage across the non-resonant capacitor is maintained at a constant dc voltage during the first and second processes.

In an embodiment, when the second voltage is converted into the first voltage, the control circuit generates the pulse width modulation signal according to the first voltage to generate the control signal, so as to convert the second voltage into the first voltage; when the second voltage is converted into the first voltage, the control signal comprises an inverse unidirectional conduction operation signal, a third operation signal and a fourth operation signal, so as to respectively correspond to an inverse unidirectional conduction program, a third program and a fourth program, and operate the corresponding switches to switch the electric connection relation of the corresponding inductors; when the second voltage is converted into the first voltage, the reverse unidirectional current process, the third process and the fourth process are operated as follows: in the reverse unidirectional conduction process, the switching of the switches is controlled by the reverse unidirectional conduction operation signal so as to form a reverse unidirectional conduction path between a third direct current potential and the first voltage, and the inductance current flowing through the inductance flows to the first voltage through the reverse unidirectional conduction path; in the third procedure, the switching of the switches is controlled by the third operation signal, so that the corresponding resonant capacitor and the corresponding inductor are connected in series between the first voltage and a fourth direct current potential to form a third current path, and the inductor current flowing through the inductor and flowing to the first voltage is a resonant current with a fourth resonant frequency; in the fourth procedure, the switching of the switches is controlled by the fourth operation signal, so that the corresponding resonant capacitor and the corresponding inductor are connected in series between the first voltage and the second voltage to form a fourth current path, and the inductor current flowing through the inductor and flowing to the first voltage is a resonant current with a fifth resonant frequency; the reverse unidirectional operation signal, the third operation signal and the fourth operation signal are respectively switched to the enabling level in a corresponding enabling period, and the enabling periods of the segments are not overlapped with each other, so that the reverse unidirectional operation program, the third program and the fourth program are not overlapped with each other; the reverse one-way conduction program, the third program and the fourth program are sequentially ordered into a combination, and then the combination is repeated, so that the reverse one-way conduction program, the third program and the fourth program are subjected to inductive power conversion switching, and the second voltage is converted into the first voltage.

In one embodiment, the switched capacitor converter includes a distributed switched capacitor converter (distributed switched capacitor converter), a series-parallel switched capacitor converter (series-parallel switched capacitor converter), a Dixon switched capacitor converter (Dickson switched capacitor converter), a stepped switched capacitor converter (ladder switched capacitor converter), a voltage-doubler switched capacitor converter (doubler switched capacitor converter), a fibonacci switched capacitor converter (Fibonacci switched capacitor converter), a pipelined switched capacitor converter (pipelined switched capacitor converter), or a switched cavity converter (switched tank converter).

In one embodiment, the series-parallel switched capacitor converter (series-parallel switched capacitor converter) includes one-half of the series-parallel switched capacitor converter (2-to-1 series-parallel switched capacitor converter), one-third of the series-parallel switched capacitor converter (3-to-1 series-parallel switched capacitor converter), or one-fourth of the series-parallel switched capacitor converter (4-to-1 series-parallel switched capacitor converter).

In one embodiment, the third dc potential is the second voltage or a ground potential, and the fourth dc potential is the second voltage or the ground potential.

In one embodiment, the zero current detection circuit comprises: a current sensing circuit for sensing a current flowing through the at least one inductor to generate at least one corresponding current sensing signal; and a comparator coupled to the current sensing circuit for comparing the at least one current sensing signal with a reference signal to generate at least one corresponding zero current detection signal to indicate a time point when the at least one inductor current reaches the zero current.

In an embodiment, the combination includes two unidirectional conducting programs, the first program and the second program, wherein the two unidirectional conducting programs, the first program and the second program form a switching period, the arrangement sequences of the two unidirectional conducting programs, the first program and the second program in the switching period can be arbitrarily combined, the ending time point of the earliest program in the switching period is determined by the pulse width modulation signal, and the ending time points of other programs except the earliest program in the switching period are determined by the zero current detection signal.

In an embodiment, the reverse unidirectional current process, the third process and the fourth process form a switching period, the arrangement sequence of the reverse unidirectional current process, the third process and the fourth process in the switching period can be arbitrarily combined, the ending time of the earliest process in the switching period is determined by the pulse width modulation signal, and the ending time of other processes except the earliest process in the switching period is determined by the zero current detection signal.

In one embodiment, the inductor current is one of the following in the reverse unidirectional current process: the inductance current is a resonance current with a sixth resonance frequency; or the inductor current is a non-resonant current; wherein when the inductor current is the non-resonant current, the inductor current is a linear ramp current that gradually decreases or another linear ramp current that gradually increases.

In one embodiment, the switching cycle is a fixed period, wherein after the reverse unidirectional current process, the third process and the fourth process of the switching cycle are all completed, the switches are kept not conducting for a zero current period until the fixed period is completed.

The invention has the advantages that the invention can realize zero-current switching and zero-voltage switching without balancing the resonant capacitor voltage with half of the input voltage so as to reduce switching power loss, can use smaller inductor so as to reduce the inductor size, can achieve lower voltage stress on a switch, a resonant capacitor and the inductor, can adjust the output voltage compared with a resonant switching capacitor type conversion circuit with fixed voltage conversion ratio, and can have higher efficiency.

The objects, technical contents, features and effects achieved by the present invention will be more readily understood by the following detailed description of specific embodiments.

Drawings

Fig. 1A shows a conventional switching slot converter of U.S. Pat. No. 9,917,517B 1.

Fig. 1B is a schematic diagram of a known buck conversion circuit.

Fig. 2A is a circuit diagram of a switched capacitor voltage conversion circuit according to an embodiment of the invention.

Fig. 2B is a circuit block diagram of a control circuit for a switched capacitor voltage conversion circuit according to an embodiment of the invention.

Fig. 2C is a circuit diagram showing a switched capacitor voltage conversion circuit according to an embodiment of the invention.

Fig. 2D is a circuit diagram showing a logic circuit in the control signal generating circuit 2013 according to an embodiment of the present invention.

Fig. 3A is a circuit diagram showing a pulse width modulation circuit in a control circuit of a switched capacitor voltage converting circuit according to an embodiment of the invention.

Fig. 3B is a signal waveform diagram showing signals related to a pulse width modulation circuit in a control circuit of a switched capacitor voltage converting circuit according to an embodiment of the invention.

FIG. 3C is a block diagram of a zero current detection circuit in a control circuit of a switched capacitor voltage conversion circuit according to an embodiment of the present invention.

Fig. 3D-3E are circuit block diagrams illustrating a zero current detection circuit in a control circuit of a switched capacitor voltage conversion circuit according to several embodiments of the present invention.

Fig. 3F is a circuit diagram showing a zero current detection circuit in a control circuit of a switched capacitor voltage converting circuit according to an embodiment of the invention.

Fig. 3G is a signal waveform diagram showing signals related to the zero current detection circuit in the control circuit of the switched capacitor voltage conversion circuit according to an embodiment of the invention.

Fig. 3H is a circuit diagram showing a control signal generating circuit in a control circuit of a switched capacitor voltage converting circuit according to an embodiment of the invention.

Fig. 3I-3K are operational waveforms of several embodiments of the switched capacitor voltage converting circuit according to the present invention.

Fig. 3L is a signal waveform diagram showing related signals of the switched capacitor voltage conversion circuit of fig. 2A when using the pulse width modulation circuit of fig. 3A according to an embodiment of the present invention.

Fig. 4A is a circuit diagram showing a pulse width modulation circuit in a control circuit of a switched capacitor voltage converting circuit according to another embodiment of the present invention.

Fig. 4B is a signal waveform diagram showing signals related to the pwm circuit in the control circuit of the switched capacitor voltage converting circuit of fig. 4A according to an embodiment of the present invention.

Fig. 4C is a circuit diagram showing a control signal generating circuit in a control circuit of a switched capacitor voltage converting circuit according to another embodiment of the invention.

Fig. 4D is a signal waveform diagram showing related signals of the switched capacitor voltage conversion circuit of fig. 2A when using the pulse width modulation circuit of fig. 4A according to an embodiment of the present invention.

Fig. 4E is a signal waveform diagram showing related signals when the switched capacitor voltage conversion circuit of fig. 2A uses the pulse width modulation circuit of fig. 3A and the unidirectional conduction procedure adopts unidirectional conduction to the ground potential according to another embodiment of the present invention.

Fig. 4F is a signal waveform diagram showing related signals when the switched capacitor voltage conversion circuit of fig. 2A uses the pulse width modulation circuit of fig. 4A and the unidirectional conduction procedure adopts unidirectional conduction to the ground potential according to another embodiment of the present invention.

Fig. 5 is a circuit diagram of a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 6 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 7 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention.

Fig. 8 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention.

Fig. 9 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 10 is a circuit diagram of a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 11 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 12 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention.

Fig. 13 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 14 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention.

Fig. 15 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 16 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention.

Fig. 17 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 18A is a circuit diagram of a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 18B is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 19 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the invention.

Fig. 20 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 21 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the invention.

Fig. 22 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 23 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention.

Fig. 24 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Fig. 25 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the invention.

Fig. 26 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention.

Description of the symbols in the drawings

10: known buck conversion circuits

20 40, 50, 60, 70, 80, 90, 100, 110, 120b,130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240: switching capacitor type voltage conversion circuit

201, 201',201",201"',401, 501, 601, 701, 801, 901, 1001, 1101, 1201, 1301, 1401, 1501, 1601, 1701, 1801, 1901, 2001, 2101, 2201, 2301, 2401: control circuit

2011, 3011: pulse width modulation circuit

20111, 30111: locking circuit

20112, 30112: ramp circuit

20113, 30113: comparison circuit

20114, 30114: reset circuit

201141, 301141: OR gate

201142, 301142: pulse generator

201143: NOT gate

2012: zero current detection circuit

2012',2012": zero current estimation circuit

20121: current sensing circuit

20121': voltage detecting circuit

20121": peak-to-valley detection circuit

20122, 20124': comparator with a comparator circuit

20122': timing circuit

20123': ramp circuit

2013, 3013: control signal generating circuit

20131a,20131b,20131c,30131a,30131b,30131c,30131d: flip-flop

20132a,20132b,20132c,20132d,30132a,30132b,30132c,30132d,30132e,30132f: AND gate

20133a,20133b,20133c,30133a,30133b,30133c,30133d: pulse generator

20134 30134a,30134b: NOT gate

20135a,20135b,30135a,30135b: OR gate

20136a,20136b,20136c,20136d,30136a,30136b,30136c,30136d: buffer device

2014: logic circuit

202, 402, 502, 602, 702, 1602, 1702, 1802, 1902, 2002, 2102, 2202, 2302, 2402: switched capacitor converter

5021, 5022, 8021, 8022, 8031, 8032, 12021, 12022, 12031, 12032, 16021, 16022: resonant tank

5023, 5024, 8023, 8024, 8033, 8034, 12023, 12024, 12033, 12034, 16023: closed loop

7021: transformer

802 A, 902, 1002, 1102, 1202, 1200 b,1302, 1402, 1502: first switched capacitor converter

803 903, 1003, 1103, 1203b,1303, 1403, 1503: second switched capacitor converter

C1 C11, C12, C13, C2, C3: (non) resonant capacitance/capacitance

C21: upper layer resonant capacitor

CINT, crp: capacitance device

CLK: clock signal

CV1, CV2: non-resonant capacitor

EAO: voltage lock signal

GA: a first operation signal

GB: a second operation signal

Gu, gu1, gu2: unidirectional conduction operation signal

I1: first current

I2: second current

IC1: resonant capacitive current

IL, IL1, IL11, IL12, IL2, IL3, ILo1, ILo11, ILo12, ILo2, ILo3: inductor current

Is, is1, is2: current source

L, L1, L11, L12, L2, L3: inductance

Lgc-H: signal signal

LX: switching node

LX1, LX11: first switching node

LX2, LX12: second switching node

Q1 to Q21, Q28, srp: switch

S1 to S21, S28: switch operation signal

Spwm: pulse width modulated signal

Szc: zero current detection signal

t0 to t5: time point

T1: time period of

T2, T3, td: delay time

TG1, TG2, TG3, TGA1, TGA2, TGA3, TGA4: intermediate signal

TN: during negative voltage

TP: during positive voltage

Tsw: switching cycle

V1: first voltage

V2: second voltage

V2': second voltage related signal

VC1, VC2, VC3: cross-over pressure

VD: voltage detection signal

VL: voltage difference

VLa, VLb: voltage (V)

Vramp, VT: ramp signal

Vref1: reference voltage

Vref2: reference signal

Vth0: zero current threshold

Vx: voltage (V)

Detailed Description

The drawings in the present invention are schematic and are mainly intended to represent coupling relationships between circuits and relationships between signal waveforms, which are not drawn to scale.

Fig. 2A is a circuit diagram of a switched capacitor voltage conversion circuit according to an embodiment of the invention. Fig. 2B is a circuit block diagram of a control circuit for a switched capacitor voltage conversion circuit according to an embodiment of the invention. As shown in fig. 2A, the switched capacitor voltage converting circuit 20 is configured to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1. The switched capacitor voltage conversion circuit 20 includes a control circuit 201 and a switched capacitor converter 202. The switched capacitor converter 202 is coupled between the first voltage V1 and the second voltage V2. As shown in fig. 2B, the control circuit 201 generates a pulse width modulation signal Spwm according to the first voltage V1 or the second voltage V2, and the control circuit 201 generates a control signal to control the switched capacitor converter 202 according to the pulse width modulation signal Spwm and the zero current detection signal Szc, so as to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1. The switched capacitor converter 202 includes at least one resonant capacitor C1, a plurality of switches Q1-Q4, and at least one inductor L. The inductor L is coupled to the resonant capacitor C1. The plurality of switches Q1 to Q4 are coupled to the resonance capacitor C1.

Referring to fig. 2A and fig. 3B, the control circuit 201 is configured to generate a control signal, where the control signal includes a unidirectional conduction operation signal Gu, a first operation signal GA, and a second operation signal GB, so as to respectively correspond to the unidirectional conduction program, the first program, and the second program, and further generate switch operation signals S1 to S4, and operate a plurality of switches Q1 to Q4 corresponding to the unidirectional conduction program, so as to switch the electrical connection relationship of the corresponding inductor L.

When the first voltage V1 is converted into the second voltage V2, the pwm circuit 2011 in the control circuit 201 generates the pwm signal Spwm according to the second voltage V2, and the operation modes of the unidirectional current process, the first process and the second process are as follows:

in the unidirectional conduction program, the unidirectional conduction operation signal Gu controls the switches Q1 to Q4 to switch so as to form a unidirectional conduction path between the first dc potential and the second voltage V2, so that the inductor current IL flowing through the inductor L flows to the second voltage V2 through the unidirectional conduction path. In the present embodiment, the first direct current voltage is, for example, but not limited to, a first voltage V1; in other embodiments, the first direct current potential is, for example, a ground potential. The unidirectional current operation signal Gu is used for operating the switches Q1 and Q3 of the plurality of switches Q1 to Q4 to be turned on during a first enabling period Ten1 in the unidirectional current process, and the switches Q2 and Q4 are not turned on, that is, during the unidirectional current process, the unidirectional current operation signal Gu is switched to an enabling level (e.g., a high level shown in fig. 3B) for a first enabling period Ten1, so that the switch operation signals S1 and S3 are switched to a conducting level and the switch operation signals S2 and S4 are switched to a non-conducting level, so as to electrically connect one end (voltage Vx end) of the inductor L to the first voltage V1.

In a first procedure, the first operation signal GA controls the switches Q1 to Q4 to switch, so that the corresponding resonant capacitor C1 and the corresponding inductor L are connected in series between the second voltage V2 and the second dc potential to form a first current path, so that the inductor current IL flowing through the inductor L and flowing through the second voltage V2 is a resonant current with a first resonant frequency. In this embodiment, the second dc potential is, for example and without limitation, a ground potential; in other embodiments, the second dc potential is, for example, the first voltage V1. The first operation signal GA is used for operating the switches Q3 and Q4 of the switches Q1 to Q4 to be conductive and the switches Q1 and Q2 to be non-conductive during a second enabling period Ten2 in the first process, that is, in the first process, the first operation signal GA is switched to an enabling level for a second enabling period Ten2 to enable the switch operation signals S3 and S4 to be switched to a conductive level and the switch operation signals S1 and S2 to be switched to a non-conductive level, so as to connect the resonant capacitor C1 and the corresponding inductor L in series between the second voltage V2 and the ground potential.

In the second procedure, the switching of the switches Q1 to Q4 is controlled by the second operation signal GB, so that the corresponding resonant capacitor C1 and the corresponding inductor L are connected in series between the first voltage V1 and the second voltage V2 to form a second current path, so that the inductor current IL flowing through the inductor L and flowing through the second voltage V2 has a resonant current with a second resonant frequency. The second operation signal GB is used for operating the switches Q1 and Q2 of the switches Q1 to Q4 to be conductive and the switches Q3 and Q4 to be non-conductive during a third enabling period Ten3 in the second process, that is, in the second process, the second operation signal GB is switched to the enabling level for a third enabling period Ten3 to enable the switch operation signals S1 and S2 to be switched to the conductive level and the switch operation signals S3 and S4 to be switched to the non-conductive level, so as to connect the resonant capacitor C1 and the corresponding inductor L in series between the first voltage V1 and the second voltage V2.

In this embodiment, the unidirectional operation signal Gu, the first operation signal GA and the second operation signal GB are respectively switched to the enable level in a corresponding one of the enable periods, and the enable periods of the segments are not overlapped with each other, so that the unidirectional operation process, the first process and the second process are not overlapped with each other, as shown in fig. 3B.

In this embodiment, as shown in fig. 3B, the unidirectional conduction process, the first process and the second process are sequentially ordered into a combination, and then the combination is repeated, so that the inductor L performs inductive power switching between the unidirectional conduction process, the first process and the second process, and further converts the first voltage V1 into the second voltage V2. As shown in fig. 3B, the control circuit 201 further generates the zero current detection signal Szc according to the time point when the inductor current IL reaches zero current.

In one-way conduction procedure, in one embodiment, the inductor current IL flowing toward the second voltage V2 is a resonant current having a third resonant frequency, wherein the third resonant frequency may be different from or the same as the first resonant frequency in the first procedure and the second resonant frequency in the second procedure. The first resonant frequency and the second resonant frequency may be the same or different, depending on the inductance and capacitance to which the first current path and the second current path are coupled, respectively.

In the unidirectional current-conducting process, in another embodiment, the inductor current IL flowing toward the second voltage V2 is a non-resonant current. In an embodiment in which the inductor current IL is a non-resonant current, the inductor current IL flowing toward the second voltage V2 is a linear ramp current that gradually decreases. In another embodiment, the inductor current IL is a non-resonant current, and the inductor current IL flowing toward the second voltage V2 is a gradually rising linear ramp current.

In one embodiment, the unidirectional conduction program, the first program and the second program form a switching period Tsw, and the arrangement sequence of the unidirectional conduction program, the first program and the second program in the switching period Tsw can be arbitrarily combined (for example, the arrangement sequence of the unidirectional conduction program, the first program and the second program in this embodiment is sequentially the unidirectional conduction program, the first program and the second program), and the end point of the earliest program (for this embodiment, the unidirectional conduction program) in the switching period Tsw is determined by the pwm signal Spwm as shown in fig. 3B; the end point of the switching period Tsw, except for the earliest one, is determined by the zero current detection signal Szc as shown in fig. 3B. It should be noted that, in the switching period Tsw, the number of times of the unidirectional conduction process, the first process and the second process is not limited, and the arrangement is not limited, so long as the ending point of the earliest process is determined by the pulse width modulation signal Spwm, and the ending point of the later process is determined by the zero current detection signal Szc.

Referring to fig. 2A, 2B and 3B, the control circuit 201 includes a pulse width modulation circuit 2011, a zero current detection circuit 2012 and a control signal generation circuit 2013. The pwm circuit 2011 is configured to generate a pwm signal Spwm according to the first voltage V1 or the second voltage V2. The zero current detection circuit 2012 is configured to generate a zero current detection signal Szc when the inductor current IL reaches zero current. The control signal generating circuit 2013 is coupled to the zero current detecting circuit 2012 for generating a control signal according to the pulse width modulation signal Spwm and the zero current detecting signal Szc, and generating a plurality of switch operation signals S1-S4 corresponding to the plurality of switches Q1-Q4 in the unidirectional conduction process, the first process and the second process according to the control signal.

Fig. 2C is a circuit diagram of a switched capacitor voltage conversion circuit 20 according to an embodiment of the invention. Referring to fig. 2C, in the unidirectional conduction procedure, the switches Q1 to Q4 are controlled to switch (e.g. the switches Q1 and Q3 are turned on and the switches Q2 and Q4 are not turned on) by the unidirectional conduction operation signal Gu, so that a unidirectional conduction path is formed between the first voltage V1 and the second voltage V2, and the inductor current IL flowing toward the second voltage V2 flows to the second voltage V2 through the unidirectional conduction path (as shown by the dotted broken line arrow in fig. 2C), wherein the inductor current IL is a gradually rising linear ramp current.

Referring to fig. 2C and 3B, in the first procedure, the first operation signal GA controls the switches Q1 to Q4 (e.g. the switches Q3 and Q4 are turned on and the switches Q1 and Q2 are turned off), and a first current path is formed between the ground potential and the second voltage V2, so that the inductor current IL flowing toward the second voltage V2 flows to the second voltage V2 through the first current path (as shown by the dashed-dotted arrow in fig. 2C), wherein the inductor current IL is a resonant current with the first resonant frequency.

Referring to fig. 2C and 3B, in the second procedure, the switches Q1 to Q4 are controlled to switch (e.g. the switches Q1 and Q2 are turned on and the switches Q3 and Q4 are turned off) by the second operation signal GB, and a second current path is formed between the first voltage V1 and the second voltage V2, so that the inductor current IL flowing toward the second voltage V2 flows toward the second voltage V2 through the second current path, wherein the inductor current IL is a resonant current with a second resonant frequency, and in the present embodiment, the first resonant frequency is equal to the second resonant frequency.

For example, referring to fig. 2C and 4E, in the unidirectional conduction process (as shown in fig. 4E, during the period of time t1-t 2), the unidirectional conduction operation signal Gu controls the switching of the plurality of switches, for example, the switches Q1, Q2, Q3 and Q4 are all non-conductive, and the inductor current IL flowing through the corresponding inductor L flows to the second voltage V2 through the unidirectional conduction path of at least one switch, for example, the body diode (body diode) in the switches Q2 and Q4, so that the inductor current IL flowing to the second voltage V2 is a gradually decreasing linear ramp current. The unidirectional conduction path includes a body diode (body diode) in the switches Q2 and Q4 in a non-conductive state.

In another embodiment of the unidirectional conduction path, for example, referring to fig. 2C and 4E, in the unidirectional conduction procedure, when the unidirectional conduction operation signal Gu controls the switching of the plurality of switches Q1 to Q4 (for example, the switches Q1 and Q3 are turned off and the switches Q2 and Q4 are turned on), the inductor current IL flowing through the corresponding inductor L flows to the second voltage V2 through the turned-on switches Q2 and Q4, and the inductor current IL flowing toward the second voltage V2 is a linear ramp current that gradually decreases. The unidirectional conduction path includes switches Q2 and Q4 in a conduction state.

In still another embodiment of the unidirectional conduction path, for example, referring to fig. 2C and 3B, in the unidirectional conduction procedure, when the unidirectional conduction operation signal Gu controls the switching of the plurality of switches Q1 to Q4 (for example, the switches Q1 and Q3 are both turned on and the switches Q2 and Q4 are both turned off), the inductor current IL flowing through the corresponding inductor L flows to the second voltage V2 through the turned-on switches Q1 and Q3 (as indicated by dashed-dotted broken line arrows in fig. 2C), and the inductor current IL flowing toward the second voltage V2 is a gradually rising linear ramp current. The unidirectional conduction path includes switches Q1 and Q3 in a conduction state.

Fig. 2D is a circuit diagram showing a logic circuit in the control signal generating circuit 2013 according to an embodiment of the present invention. As shown in fig. 2A-2C and referring to the embodiment shown in fig. 3B, the control circuit 201 generates a control signal according to the pwm signal Spwm and the zero current detection signal Szc, and the control signal includes a unidirectional conduction operation signal Gu, a first operation signal GA and a second operation signal GB, so as to generate switch operation signals S1-S4, and operate a plurality of corresponding switches Q1-Q4. The logic circuit 2014 is configured to convert the unidirectional operation signal Gu, the first operation signal GA, and the second operation signal GB into the switching operation signals S1 to S4. As shown in fig. 2D, after the unidirectional conduction operation signal Gu and the second operation signal GB perform a logic or gate operation, a switching operation signal S1 is generated through a buffer; the second operation signal GB passes through the buffer to generate a switch operation signal S2; after logical OR gate operation is carried out on the unidirectional conduction operation signal Gu and the first operation signal GA, a switch operation signal S3 is generated through a buffer; the first operation signal GA passes through the buffer to generate a switch operation signal S4. It should be noted that, the embodiment of the logic circuit 2014 is not limited to the embodiment shown in fig. 2D, and only the unidirectional operation signal Gu, the first operation signal GA and the second operation signal GB need to be converted into the switching operation signals S1 to S4 according to the requirements, and the corresponding conversion requirements are different, and the embodiment of the logic circuit 2014 is also different, which is well known to those skilled in the art and is not repeated herein.

Fig. 3A is a circuit diagram showing a pulse width modulation circuit in a control circuit of a switched capacitor voltage converting circuit according to an embodiment of the invention. As shown in fig. 3A, the pulse width modulation circuit 2011 includes a lock circuit 20111, a ramp circuit 20112, a comparison circuit 20113, and a reset circuit 20114. The locking circuit 20111 is configured to lock the second voltage-related signal V2' related to the second voltage V2 to a reference voltage Vref1 to generate a voltage locking signal EAO. The ramp circuit 20112 is used for generating a ramp signal Vramp. In one embodiment, the ramp 20112 includes a current source Is and a capacitor Crp. The current source Is used for charging the capacitor Crp to generate the ramp signal Vramp. The comparing circuit 20113 is used for comparing the voltage locking signal EAO and the ramp signal Vramp to generate the pwm signal Spwm. The reset circuit 20114 is configured to reset the ramp signal Vramp according to a control signal such as the first operation signal GA or a clock signal CLK. In one embodiment, the reset circuit 20114 includes a switch Srp, an or gate 201141, a pulse generator 201142 and an not gate 201143. When the first operation signal GA is at the disable level or the clock signal CLK is at the enable level, the switch Srp is turned on for a short period of time by the or gate 201141 and the pulse generator 201142, so that the level of the ramp signal Vramp is pulled down to zero.

Fig. 3B is a signal waveform diagram showing signals related to a pulse width modulation circuit in a control circuit of a switched capacitor voltage converting circuit according to an embodiment of the invention. The clock signal CLK, the ramp signal Vramp, the voltage locking signal EAO, the pulse width modulation signal Spwm, the zero current detection signal Szc, the inductor current IL, the first operation signal GA, the second operation signal GB, the unidirectional conduction operation signal Gu and the switching period Tsw are shown in fig. 3B. As shown in fig. 3B, the first operation signal GA, the second operation signal GB and the unidirectional operation signal Gu are respectively switched to an enable level for an enable period, and the enable periods of the segments are not overlapped with each other, so that the first program, the second program and the unidirectional operation signal Gu are not overlapped with each other.

As shown in fig. 3B, when the voltage locking signal EAO is lower than the ramp signal Vramp, the pulse width modulation signal Spwm is triggered to switch to the disable level, and the unidirectional operation signal Gu is triggered to switch to the disable level, and the first operation signal GA is caused to switch to the enable level. When the zero current detection signal Szc is switched to the enable level, the first operation signal GA is triggered to be switched to the disable level, and the second operation signal GB is caused to be switched to the enable level. When the voltage locking signal EAO is higher than the ramp signal Vramp, the pulse width modulation signal Spwm is enabled to be switched to the enable level, and when the zero current detection signal Szc is enabled to be switched to the enable level, the second operation signal GB is enabled to be switched to the disable level, the unidirectional conduction operation signal Gu is triggered to be switched to the enable level. As shown in fig. 3B, the present embodiment adopts the sequence of the unidirectional conduction procedure, the first procedure, and the second procedure to form the switching period Tsw. In another embodiment, the switching period Tsw may also be formed by sequentially performing the unidirectional conduction procedure, the second procedure and the first procedure.

FIG. 3C is a block diagram of a zero current detection circuit in a control circuit of a switched capacitor voltage conversion circuit according to an embodiment of the present invention. The switched capacitor voltage conversion circuit 20 of fig. 3C includes a switched capacitor converter 202 and a control circuit 201', the configuration of the switched capacitor converter 202 is the same as that of the switched capacitor converter 202 of fig. 2A, the control circuit 201' is configured to generate control signals (and further generate switch operation signals S1-S4) to control a plurality of switches (e.g. switches Q1-Q4) of the switched capacitor converter 202, and the control circuit 201' includes a zero current detection circuit 2012, a control signal generation circuit 2013 and a pulse width modulation circuit 2011. The zero current detection circuit 2012 is configured to generate a zero current detection signal Szc according to the inductor current IL flowing through the inductor L, and in this embodiment, the zero current detection circuit 2012 is configured to detect the inductor current IL.

With continued reference to fig. 3C, in one embodiment, the zero current detection circuit 2012 includes a current sense circuit 20121 and a comparator 20122, wherein the current sense circuit 20121 is configured to sense the inductor current IL to generate the current sense signal Vis. The comparator 20122 is configured to compare the current sensing signal Vis with a reference signal Vref2 to generate a zero current detection signal Szc to indicate a time point when the inductor current IL reaches 0 current. The control signal generating circuit 2013 and the pulse width modulation circuit 2011 of fig. 3C are similar to the control signal generating circuit 2013 and the pulse width modulation circuit 2011 of fig. 2B, so a detailed description thereof is omitted.

Fig. 3D-3E are circuit block diagrams illustrating a zero current detection circuit in a control circuit of a switched capacitor voltage conversion circuit according to several embodiments of the present invention. The control circuit 201″ shown in fig. 3D generates the zero current detection signal Szc according to another embodiment, wherein the switched capacitor converter 202 of the present embodiment corresponds to the switched capacitor converter 202 of fig. 2A.

The control circuit 201″ includes a zero current estimation circuit 2012' coupled to the inductor L for estimating a time point when the inductor current IL is 0 according to a voltage difference between two ends of the inductor L, and is used for generating a zero current detection signal Szc, and then the control signal generation circuit 2013 generates control signals (and thus generates the switch operation signals S1 to S4) to control the operation of the plurality of switches according to the zero current detection signal Szc, which can refer to the embodiment of fig. 3C.

Referring to fig. 3D and fig. 3G, in one embodiment, the zero current estimation circuit 2012 'includes a voltage detection circuit 20121' and a timing circuit 20122', wherein the voltage detection circuit 20121' is configured to generate a voltage detection signal VD according to, for example, a voltage difference VL across the inductor L, so as to indicate a positive voltage period TP during which the voltage difference VL across the inductor L exceeds zero voltage. The timing circuit 20122 'is coupled to the output end of the voltage detection circuit 20121' for estimating a negative voltage period TN in which the voltage difference VL between the two ends of the inductor L does not exceed zero voltage according to the voltage detection signal VD, so as to generate a zero current detection signal Szc to indicate a time point when the inductor current IL is zero.

It should be noted that, the operation mode for generating the voltage detection signal VD according to the voltage difference between the two ends of the inductor L and estimating the time point when the inductor current IL is zero is not limited to the switch capacitor converter 202 shown in fig. 3D, and in another embodiment, the operation mode may be applied to, for example, the embodiment corresponding to fig. 5, etc., in the embodiment (fig. 5) where the resonant capacitor has the corresponding inductors (e.g., L1 and L2), the voltage detection circuit may be used to respectively sense the inductor currents IL1 and IL2 of the inductors L1 and L2, respectively, and respectively estimate the time points when the inductor currents IL1 and IL2 reach 0, so as to perform the subsequent control operation, which is not described herein.

The control circuit 201' "shown in fig. 3E generates the zero current detection signal Szc according to another embodiment, wherein the switched capacitor converter 202 of the present embodiment corresponds to the switched capacitor converter 202 of fig. 2A.

In this embodiment, the control circuit 201' "includes a zero current estimation circuit 2012″ coupled to the resonant capacitor C1 for estimating a time point when the inductor current IL is 0 according to a voltage difference (voltage across VC 1) between two ends of the resonant capacitor C1, and is used for generating a zero current detection signal Szc, and then the control signal generation circuit 2013 generates control signals (e.g. switch operation signals S1-S4) according to the zero current detection signal Szc to control the operation of the plurality of switches, which can refer to the embodiment of fig. 3C.

Referring to fig. 3E and fig. 3G, in the present embodiment, the zero current estimation circuit 2012 "includes a peak-to-valley detection circuit 20121", the peak-to-valley detection circuit 20121 "is configured to generate a voltage detection signal according to a voltage difference (voltage across VC 1) between two ends of the resonant capacitor C1, so as to illustrate a peak time point (time point t2 shown in fig. 3G) of a peak of the voltage difference between two ends of the resonant capacitor C1 and a valley time point (time point t4 shown in fig. 3G) of a valley thereof, and generate a zero current detection signal Szc accordingly, wherein the peak time point and the valley time point both correspond to a time point when the inductor current IL is 0. There are many different embodiments for detecting the peaks and valleys of the voltage difference, which are well known to those skilled in the art and will not be described herein.

Fig. 3F is a circuit diagram showing a zero current detection circuit in a control circuit of a switched capacitor voltage converting circuit according to an embodiment of the invention. FIG. 3F is a schematic diagram of a switching capacitor type switching circuit corresponding to FIG. 3D, showing a zero current estimation circuit according to a more specific embodiment. The zero current estimation circuit 2012' of the present embodiment includes a comparator (corresponding to the voltage detection circuit 20121 '), a ramp circuit 20123', and a comparator 20124', wherein the ramp circuit 20123' and the comparator 20124' correspond to the timing circuit 20122'.

Referring to fig. 3F and 3G, the comparator 20121' is configured to compare the voltages VLa and VLb at the two ends of the inductor L to generate the voltage detection signal VD, so as to indicate a positive voltage period TP in which the voltage difference between the two ends of the inductor L exceeds the zero voltage.

Referring to fig. 3F and 3G, the ramp circuit 20123' Is configured to generate a first ramp (e.g., a rising ramp of fig. 3G) of the ramp signal VT according to the voltage detection signal VD during the positive voltage period TP, and to generate a second ramp (e.g., a falling ramp of fig. 3G) of the ramp signal VT after the positive voltage period TP Is ended, wherein the slopes of the first ramp and the second ramp are opposite to each other, and the absolute values of the slopes of the first ramp and the second ramp are equal, and in one embodiment, the current sources Is1 and Is2 are configured to charge and discharge the integrating capacitor (capacitor CINT) with equal current values.

Referring to fig. 3F and 3G, the comparator 20124' is configured to indicate a time point when the inductor current IL is 0 when the ramp signal VT (especially, the second ramp) reaches the zero current threshold Vth0, so as to generate the zero current detection signal Szc. It should be noted that, in other embodiments, the absolute values of the slopes of the first slope and the second slope may be other ratios, and in this case, the same effect may be obtained by adjusting the zero current threshold.

Fig. 3H is a circuit diagram showing a control signal generating circuit in a control circuit of a switched capacitor voltage converting circuit according to an embodiment of the invention. As shown in fig. 3H, in one embodiment, the control signal generating circuit 2013 includes, but is not limited to, flip-flops 20131a, 20131b and 20131c, and gates 20132a, 20132b, 20132c and 20132d, pulse generators 20133a, 20133b and 20133c, not gates 20134, or gates 20135a and 20135b, and buffers 20136a, 20136b, 20136c and 20136d. The control signal generating circuit 2013 may be implemented in other embodiments than the one shown in fig. 3H.

Fig. 3I-3K are operational waveforms of several embodiments of the switched capacitor voltage converting circuit according to the present invention. In fig. 3I, when the inductor current IL is 0, the switch operation signals S1 and S2 and the switch operation signals S3 and S4 are respectively turned to the inverted level to control the switches Q1 to Q4 to switch to the respective inverted states. In one embodiment, as shown in fig. 3I, 50% of the switching period is corresponding between any two adjacent 0-current time points of IL, so that the on period of the first program is equal to the on period of the second program, so as to achieve zero-current switching of soft switching (soft switching).

In the embodiment of fig. 3J, the reference signal Vref2 may be adjusted such that, for example, the switching signals S1 and S2 turn to low level (i.e., not conducting) earlier, for example, in fig. 3J, the switching signals S1 and S2 turn to low level earlier than the point of time when the inductor current IL reaches 0 by the period T1, and the inductor current IL is still positive, for example, thereby achieving zero voltage switching of the switch Q4.

In an embodiment, as shown in fig. 3K, after the inductor current IL reaches 0, a delay time T2 is further elapsed, so that the inductor current IL freewheels to, for example, a negative current, the switch operation signals S3 and S4 are turned off, and then after the delay time T3, the switch operation signals S1 and S2 are turned on, thereby realizing, for example, zero voltage switching of the switch Q1.

Fig. 3L is a signal waveform diagram showing related signals of the switched capacitor voltage conversion circuit of fig. 2A when using the pulse width modulation circuit of fig. 3A according to an embodiment of the present invention. The first voltage V1, the second voltage V2, the second current I2, the voltage across VC1, the inductor current IL, the switch operation signals S1 to S4, the voltage Vx, and the switching period Tsw are shown in fig. 3I. As shown in fig. 3I, between time t0 and time t1, the inductor current IL exhibits a gradually increasing linear ramp current. The inductor current IL exhibits a resonance current between the time t1 and the time t2 and between the time t2 and the time t 3.

Fig. 4A is a circuit diagram showing a pulse width modulation circuit in a control circuit of a switched capacitor voltage converting circuit according to another embodiment of the present invention. The pwm circuit 3011 of this embodiment is similar to the pwm circuit 2011 of fig. 3A, except that the reset circuit 30114 of this embodiment does not include an nor gate and the or gate 301141 has three inputs, namely, the clock signal CLK, the intermediate signals TGA2 and TGA4. When one of the clock signal CLK, the intermediate signal TGA2 or the intermediate signal TGA4 is switched to the enable level, the switch Srp is turned on for a short period of time by the or gate 301141 and the pulse generator 301142, so that the level of the ramp signal Vramp is pulled down to zero.

Fig. 4B is a signal waveform diagram showing signals related to the pwm circuit in the control circuit of the switched capacitor voltage converting circuit of fig. 4A according to an embodiment of the present invention. The clock signal CLK, the ramp signal Vramp, the voltage locking signal EAO, the pulse width modulation signal Spwm, the zero current detection signal Szc, the inductor current IL, the first operation signal GA, the second operation signal GB, the unidirectional conduction operation signals Gu1 and Gu2, and the switching period Tsw are shown in fig. 4B.

As shown in fig. 4B, when the voltage locking signal EAO is lower than the ramp signal Vramp, the pulse width modulation signal Spwm is triggered to switch to the disable level, and the unidirectional operation signal Gu1 is triggered to switch to the disable level, and the first operation signal GA is caused to switch to the enable level. When the voltage locking signal EAO is higher than the ramp signal Vramp, the pulse width modulation signal Spwm is enabled to switch to the enable level, and when the zero current detection signal Szc is enabled to switch to the disable level, the unidirectional operation signal Gu2 is triggered to switch to the enable level. When the voltage locking signal EAO is lower than the ramp signal Vramp, the pulse width modulation signal Spwm is triggered to switch to the disable level, and the unidirectional operation signal Gu2 is triggered to switch to the disable level, and the second operation signal GB is caused to switch to the enable level. When the voltage locking signal EAO is higher than the ramp signal Vramp, the pulse width modulation signal Spwm is enabled to be switched to the enable level, and when the zero current detection signal Szc is enabled to be switched to the enable level, the second operation signal GB is enabled to be switched to the disable level, the unidirectional operation signal Gu1 is triggered to be switched to the enable level. As shown in fig. 4B, the switching period Tsw is formed by the sequence of the unidirectional conduction process, the first process, the unidirectional conduction process, and the second process. In another embodiment, the switching period Tsw may also be formed by a sequence of the unidirectional conduction process, the second process, the unidirectional conduction process, and the first process.

Fig. 4C is a circuit diagram showing a control signal generating circuit in a control circuit of a switched capacitor voltage converting circuit according to another embodiment of the invention. The control signal generation circuit 3013 of the present embodiment can cooperate with the pulse width modulation circuit 3011 of fig. 4A. As shown in fig. 4C, in one embodiment, the control signal generating circuit 3013 includes, but is not limited to, flip-flops 30131a, 30131b, 30131C and 30131d, and gates 30132a, 30132b, 30132C, 30132d, 30132e and 30132f, pulse generators 30133a, 30133b, 30133C and 30133d, not gates 30134a and 30134b, or gates 30135a and 30135b, and buffers 30136a, 30136b, 30136C and 30136d. The control signal generation circuit 3013 may be implemented in other embodiments than those shown in fig. 4C.

Fig. 4D is a signal waveform diagram showing related signals of the switched capacitor voltage conversion circuit of fig. 2A when using the pulse width modulation circuit of fig. 4A according to an embodiment of the present invention. The first voltage V1, the second voltage V2, the second current I2, the voltage across VC1, the inductor current IL, the switch operation signals S1 to S4, the voltage Vx, and the switching period Tsw are shown in fig. 4D. As shown in fig. 4D, the inductor current IL shows a gradually increasing linear ramp current between the time t0 to the time t1 and the time t3 to the time t 4. The inductor current IL exhibits a resonant current between the time t1 and the time t2 and between the time t4 and the time t 5. The delay time Td is between the time t2 and the time t 3. The delay time Td can adjust the non-conductive periods of the switches (e.g., the switches Q2, Q3, Q4) so that the control circuit 201 operates at a fixed switching frequency (i.e., the switching period Tsw is a fixed period). It should be noted that the delay time Td may be inserted after the first process and/or the second process and/or the unidirectional current-conducting process, that is, after the inductor current IL decreases to 0 in the first process and/or the second process and/or the unidirectional current-conducting process, the switches may remain non-conductive for a zero current period (i.e., the delay time Td).

Fig. 4E is a signal waveform diagram showing related signals when the switched capacitor voltage conversion circuit of fig. 2A uses the pulse width modulation circuit of fig. 3A and the unidirectional conduction procedure adopts unidirectional conduction to the ground potential according to another embodiment of the present invention. Fig. 4E shows signal waveforms of the clock signal CLK, the switching operation signals S1 to S4, and the inductor current IL. As shown in fig. 4E, between time t1 and time t2, the inductor current IL exhibits a gradually decreasing linear ramp current. The inductor current IL exhibits a resonant current having a resonant frequency between the time t0 and the time t1 and between the time t2 and the time t 3. In this embodiment, the time t0 to the time t1 are the first program of the switching period Tsw, i.e., the period of the first program, and the ending time t1 (or the length of the period of the first program) is determined according to the pwm signal Spwm. The end points t2 and t3 of the unidirectional conduction process and the second process are determined according to the zero current detection signal Szc. As shown in fig. 4E, the present embodiment adopts the sequence of the first procedure, the unidirectional conduction procedure, and the second procedure to compose the switching period Tsw. In another embodiment, the switching period Tsw may be combined in the order of the second procedure, the unidirectional conduction procedure, and the first procedure.

In detail, in the embodiment shown in fig. 4E, during the first procedure, the switching of the switches Q1 to Q4 is controlled by the first operation signal GA during the real time t0 to t1, including making the switches Q3 and Q4 conductive and making the switches Q1 and Q2 non-conductive, so that the corresponding resonant capacitor C1 and the corresponding inductor L are connected in series between the second voltage V2 and the second dc potential (e.g. the ground potential or the first voltage V1, in this embodiment, the ground potential) to form a first current path. In the first procedure, the inductor current IL flowing toward the second voltage V2 is a resonant current having a first resonant frequency.

Then, the unidirectional conduction operation signal Gu is used to operate the switches Q2 and Q4 of the switches (e.g. the switches Q1 to Q4) to conduct and the switches Q1 and Q3 to not conduct during the unidirectional conduction process in the real time period t1 to t2, i.e. the unidirectional conduction operation signal Gu is switched to the enable level for a first enable period to enable the switch operation signals S2 and S4 to switch to the conduction level and the switch operation signals S1 and S3 to switch to the non-conduction level in the unidirectional conduction process to electrically connect one end of the inductor L to the dc potential (the ground potential in the present embodiment). In the unidirectional conduction procedure, the unidirectional conduction operation signal Gu controls the switching of the plurality of switches (the switches Q1 and Q3 are not turned on, and the switches Q2 and Q4 are turned on), so that the inductor current IL flowing through the corresponding inductor L flows to the second voltage V2 through a unidirectional conduction path.

Then, in the second procedure, the switching of the switches Q1 to Q4 is controlled by the second operation signal GB, including making the switches Q1 and Q2 conductive and the switches Q3 and Q4 non-conductive, so that at least one resonant capacitor C1 and the corresponding inductor L are connected in series between the first voltage V1 and the second voltage V2 to form a second current path. In the second procedure, the inductor current IL flowing toward the second voltage V2 has a resonant current with a second resonant frequency. In this embodiment, the first resonant frequency is the same as the second resonant frequency.

Fig. 4F is a signal waveform diagram showing related signals when the switched capacitor voltage conversion circuit of fig. 2A uses the pulse width modulation circuit of fig. 4A and the unidirectional conduction procedure adopts unidirectional conduction to the ground potential according to another embodiment of the present invention. The clock signal CLK, the switching operation signals S1 to S4, and the inductor current IL are shown in fig. 4F. As shown in fig. 4F, the inductor current IL shows a gradually decreasing linear ramp current between the time t1 to the time t2 and the time t3 to the time t 4. The inductor current IL exhibits a resonance current between the time t0 and the time t1 and between the time t2 and the time t 3. In this embodiment, the length of the second program time period from the time t0 to the time t1 is determined according to the pwm signal Spwm. As shown in fig. 4F, the switching period Tsw is formed by the sequence of the second program, the unidirectional conduction program, the first program, and the unidirectional conduction program. In another embodiment, the switching period Tsw may also be formed by a sequence of the first procedure, the unidirectional conduction procedure, the second procedure, and the unidirectional conduction procedure.

Fig. 5 is a circuit diagram of a switched capacitor voltage conversion circuit according to another embodiment of the invention. The switched capacitor voltage conversion circuit 40 is used for converting the first voltage V1 into the second voltage V2 or converting the second voltage V2 into the first voltage V1. In the present embodiment, the switched capacitor voltage conversion circuit 40 includes a control circuit 401 and a switched capacitor converter 402. The switched capacitor converter 402 includes a non-resonant capacitor C1, a resonant capacitor C2, a resonant capacitor C3, and a plurality of switches (e.g., switches Q1-Q10) coupled to each other. It should be noted that when the capacitance of the capacitor C1 is much larger than the capacitance of the capacitors C2 and C3, the capacitor C1 can be regarded as a non-resonant capacitor.

In an embodiment, in the second procedure, the switches (e.g., the switches Q1-Q10) control the non-resonant capacitor C1 and the resonant capacitor C3 to be connected in series between the first voltage V1 and the second voltage V2, and control the resonant capacitor C2 to be connected in parallel with the second voltage V2, and the other end of the resonant capacitor C2 is controlled to be coupled to the ground potential. Specifically, the switches Q1, Q2 and Q3 are turned on to control the non-resonant capacitor C1 and the resonant capacitor C3 to be connected in series between the first voltage V1 and the second voltage V2, the switches Q4 and Q5 are turned on to control the resonant capacitor C2 and the second voltage V2 to be connected in parallel, and the switches Q6 to Q10 are turned off. In the second procedure, the switch operation signals S1 to S5 are enabled to turn on the switches controlled by the switch operation signals S6 to S10, and are disabled to turn off the switches controlled by the switch operation signals S6 to S10.

In the first procedure, the switches (e.g., the switches Q1 to Q10) control the resonant capacitor C2 and the non-resonant capacitor C1 to be connected in series between the second voltage V2 and the ground potential, and control the resonant capacitor C3 to be connected in parallel with the second voltage V2. In the first procedure, the resonant capacitor C2 and the non-resonant capacitor C1 are connected in anti-series between the second voltage V2 and the ground potential. Specifically, the switches Q6, Q7 and Q8 are turned on to control the resonant capacitor C2 and the non-resonant capacitor C1 to be connected in series between the second voltage V2 and the ground potential, the switches Q9 and Q10 are turned on to control the resonant capacitor C3 to be connected in parallel with the second voltage V2, and the switches Q1 to Q5 are turned off. In the present embodiment, in the first procedure, the switch operation signals S1 to S5 are disabled, the switch controlled by the switch operation signals S6 to S10 are enabled, and the switch controlled by the switch operation signals S1 to S5 is turned on.

The switched capacitor voltage conversion circuit 40 performs power conversion between the first voltage V1 and the second voltage V2 by the above-described periodic operation. In this embodiment, the ratio of the first voltage V1 to the second voltage V2 is 4.

It should be noted that, in the first procedure, the "reverse" series connection of the resonant capacitor C2 and the non-resonant capacitor C1 means that the voltage across the resonant capacitor C2 and the voltage across the non-resonant capacitor C1 are opposite (i.e. opposite to the positive and negative directions).

In the embodiment for converting the first voltage V1 into the second voltage V2, in the second process, the first voltage V1 charges the non-resonant capacitor C1 and the resonant capacitor C3 connected in series, and the resonant capacitor C2 discharges to supply the second voltage V2, i.e. the resonant capacitor C2 charges the non-resonant capacitor CV2 coupled to the second voltage V2. In the first procedure, the non-resonant capacitor C1 charges the resonant capacitor C2 and the second voltage V2.

In addition, in the embodiment of converting the second voltage V2 into the first voltage V1, in the second procedure, the second voltage V2 charges the non-resonant capacitor C1 and the resonant capacitor C3 connected in series with each other, and the second voltage V2 charges the resonant capacitor C2. In the first procedure, the second voltage V2 charges the resonant capacitor C3, and the second voltage V2 charges the non-resonant capacitor C1 through the resonant capacitor C2.

Through the above-mentioned periodic operation, in the present embodiment, in a steady state, the ratio of the voltage across VC1 of the non-resonant capacitor C1 to the second voltage V2 is 2, the ratio of the voltage across VC3 of the resonant capacitor C3 to the second voltage V2 is 1, and the ratio of the voltage across VC2 of the resonant capacitor C2 to the second voltage V2 is 1. In the embodiment where the second voltage V2 is 12V, both the voltage across VC3 of the resonant capacitor C3 and the voltage across VC2 of the resonant capacitor C2 are 12V in the steady state, and it is noted that, since the voltage across the capacitor can be maintained at a lower voltage in the steady state, the capacitor can maintain a higher effective capacitance value, so that the voltage withstand and the volume required by the capacitor can be effectively reduced, and the resonant frequency is stable, and the transient response is better. It is also noted that the output current (e.g., corresponding to the second current I2) of the present invention is provided by two channels, thereby reducing ripple.

The non-resonant capacitors CV1 and CV2 respectively coupled to the first voltage V1 and the second voltage V2 respectively correspond to the input capacitor and the output capacitor in the embodiment of converting the first voltage V1 into the second voltage V2, or correspond to the output capacitor and the input capacitor in the embodiment of converting the second voltage V2 into the first voltage V1.

The switched capacitor converter 402 further includes an inductor L1 and an inductor L2, wherein the inductor L1 is coupled between the second voltage V2 and the first switching node LX1, and the inductor L2 is coupled between the second voltage V2 and the second switching node LX 2. In the second procedure, the switches (e.g., the switches Q1 to Q10) control the non-resonant capacitor C1 and the resonant capacitor C3 to be connected in series between the first voltage V1 and the second voltage V2 after being connected in series with the inductor L1 through the first switching node LX1, and control the resonant capacitor C2 to be connected in parallel with the second voltage V2 after being connected in series with the inductor L2 through the second switching node LX 2. On the other hand, in the first procedure, the switches (e.g., the switches Q1 to Q10) control the resonant capacitor C2 and the non-resonant capacitor C1 to be connected in series between the second voltage V2 and the ground potential through the second switching node LX2 and the inductor L2, and control the resonant capacitor C3 to be connected in parallel with the second voltage V2 after being connected in series with the inductor L1 through the first switching node LX 1. In one embodiment, both the inductor L1 and the inductor L2 are operated in the continuous conduction mode, thereby further reducing the surge current and the ripple current.

In an embodiment, the capacitance of the non-resonant capacitor C1 is much larger than the capacitance of the resonant capacitor C3 and the resonant capacitor C2, so that the first resonant frequency of the resonant capacitor C3 and the inductor, and the second resonant frequency of the resonant capacitor C2 and the inductor are much higher than the third resonant frequency of the non-resonant capacitor C1 and the inductor, and in a preferred embodiment, the first resonant frequency and the second resonant frequency are both greater than or equal to 10 times the third resonant frequency.

The control circuit 401 of this embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

In one embodiment. When the unidirectional current is applied to the first voltage, the unidirectional current, the second program and the first program may sequentially form the switching period Tsw, or the unidirectional current, the first program and the second program may sequentially form the switching period Tsw. In another embodiment, when the unidirectional current process is unidirectional current to the first voltage, the unidirectional current process, the second process, the unidirectional current process and the first process may sequentially form the switching period Tsw, or the unidirectional current process, the first process, the unidirectional current process and the second process sequentially form the switching period Tsw. In yet another embodiment, when the unidirectional current process is conducted to a dc potential (e.g. a ground potential), the switching period Tsw may be formed by the sequence of the second process, the unidirectional current process, and the first process, or the switching period Tsw may be formed by the sequence of the first process, the unidirectional current process, and the second process. In yet another embodiment, when the unidirectional current process is conducted to a dc potential (e.g., a ground potential), the switching period Tsw may be formed by the sequence of the first process, the unidirectional current process, the second process, and the unidirectional current process, or the switching period Tsw may be formed by the sequence of the second process, the unidirectional current process, the first process, and the unidirectional current process.

Fig. 6 is a circuit diagram of a switched capacitor voltage conversion circuit according to another embodiment of the invention. The switching capacitance converter 502 in the present embodiment is similar to the switching capacitance converter 302 of fig. 4, in that the inductor L1 of the switching capacitance converter 502 is directly connected in series with the resonant capacitor C3 to form the resonant tank 5021, and the inductor L2 of the switching capacitance converter 502 is directly connected in series with the resonant capacitor C2 to form the resonant tank 5022. In one embodiment, in the second process, the switches (e.g., the switches Q1-Q10) control the resonant tank 5021 and the non-resonant capacitor C1 to be connected in series between the first voltage V1 and the second voltage V2, and control the resonant tank 5022 to be connected in parallel with the second voltage V2. On the other hand, in the first procedure, the switches (e.g., the switches Q1-Q10) control the resonant tank 5022 and the non-resonant capacitor C1 to be connected in series between the second voltage V2 and the ground potential, and control the resonant tank 5021 to be connected in parallel with the second voltage V2, and the switched capacitor converter 502 is operated in a resonant manner to realize the power conversion between the first voltage V1 and the second voltage V2 through the above-mentioned periodic operation. Details of the control of the plurality of switches (e.g., switches Q1-Q10) described above may be found in the embodiment of fig. 4.

The control circuit 501 of the present embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C.

As shown in fig. 6, in the unidirectional conduction process, when the switches are controlled to switch (e.g., the switches Q1 to Q10 are turned off) by the switch operation signals S1 to S10, the inductor currents IL1 and IL2 flowing through the corresponding inductors L1 and L2 are turned on by at least one of the switches (e.g., the switches Q9 and Q3 and the internal diodes (as shown by the dashed lines in fig. 6)) respectively, and the closed loops 5023 and 5024 formed by the resonant tanks 5021 and 5022 and at least one of the switches (e.g., the switches Q9 and Q3 and the internal diodes (as shown by the dashed lines in fig. 6) respectively, so that the inductor currents ILo1 and ILo2 stop flowing toward the second voltage V2 in the second state. As shown in fig. 6, at least one resonant capacitor C3 and at least one inductor L1 form a resonant tank 5021, and at least one resonant capacitor C2 and at least one inductor L2 form a resonant tank 5022. In this case, no net current flows into or out of the non-resonant capacitor (also referred to as output capacitor) CV2 by the closed loop currents (i.e., inductor currents IL1 and IL 2).

For example, the inductor current IL1 flowing through the corresponding inductor L1 is turned on by the internal diode of the switches Q9 and Q3, and freewheels through the closed loop 5023 formed by the resonant tank 5021 and the internal diode of the switches Q9 and Q3, so that the inductor current ILo1 stops flowing toward the second voltage V2 in the second state. The inductor current IL2 flowing through the corresponding inductor L2 is turned on by the internal diode of the switches Q4 and Q6, and freewheels through the closed loop 5024 formed by the resonant tank 5022 and the internal diode of the switches Q4 and Q6, so that the inductor current ILo2 stops flowing toward the second voltage V2 in the second state. In another embodiment, the switches Q9 and Q3 and the switches Q4 and Q6 are turned on to form a closed loop, so that the inductor currents ILo1 and ILo2 stop flowing toward the second voltage V2 in the second state.

In another embodiment, when the unidirectional conduction process adopts unidirectional conduction to the first voltage V1, for example, the switch operation signals S1 to S10 control the switching of the switches (for example, the switches Q1, Q7, Q6 are all turned on and the switches Q2 to Q5, Q8 to Q10 are all turned off), the inductor L2 and the resonant capacitor C2 are turned on through at least one switch (for example, the switches Q1, Q7, Q6) (shown by dotted lines in fig. 6) and connected in series between the first voltage V1 and the second voltage V2, so that the inductor current ILo flowing toward the second voltage V2 is a resonant current having a third resonant frequency, wherein the third resonant frequency is different from the first resonant frequency of the first process and the second resonant frequency of the second process.

In one embodiment. When the unidirectional current is applied to the first voltage V1, the unidirectional current, the second program and the first program may sequentially form the switching period Tsw, or the unidirectional current, the first program and the second program sequentially form the switching period Tsw. In another embodiment, when the unidirectional current is applied to the first voltage V1, the unidirectional current, the second procedure, the unidirectional current and the first procedure may sequentially form the switching period Tsw, or the unidirectional current, the first procedure, the unidirectional current and the second procedure sequentially form the switching period Tsw. In yet another embodiment, when the unidirectional conduction procedure adopts the closed loop formation, the switching period Tsw may be formed by the sequence of the second procedure, the unidirectional conduction procedure, and the first procedure, or the switching period Tsw may be formed by the sequence of the first procedure, the unidirectional conduction procedure, and the second procedure. In still another embodiment, when the unidirectional current-conducting process adopts the closed loop, the switching period Tsw may be formed by the sequence of the first process, the unidirectional current-conducting process, the second process, and the unidirectional current-conducting process, or the switching period Tsw may be formed by the sequence of the second process, the unidirectional current-conducting process, the first process, and the unidirectional current-conducting process.

Fig. 7 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention. The difference between the switched capacitor converter 602 in the present embodiment and the switched capacitor converter 402 in fig. 5 is that the switched capacitor converter 602 shares an inductance L, the inductance L is coupled between the second voltage V2 and the switching node LX, and in the second procedure, the plurality of switches (e.g., the switches Q1-Q10) control the non-resonant capacitor C1 and the resonant capacitor C3 to be connected in series between the first voltage V1 and the second voltage V2 after being connected in series with the inductance L through the switching node LX, and control the resonant capacitor C2 to be connected in parallel with the second voltage V2 after being connected in series with the inductance L through the switching node LX. On the other hand, in the first procedure, the switches (e.g., the switches Q1 to Q10) control the resonant capacitor C2 and the non-resonant capacitor C1 to be connected in series between the second voltage V2 and the ground potential through the switching node LX and the inductor L, and control the resonant capacitor C3 to be connected in parallel with the second voltage V2 after being connected in series with the inductor L through the switching node LX. In the present embodiment, the non-resonant capacitor C1, the resonant capacitor C2 and the resonant capacitor C3 are all resonant with the inductor L to perform the conversion between the first voltage V1 and the second voltage V2. Details of the control of the plurality of switches (e.g., switches Q1-Q10) described above may be found in the embodiment of fig. 5.

The control circuit 601 of the present embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

It should be noted that the process of charging and discharging the capacitor and the inductor in this embodiment are performed in a resonant manner, so that the surge current of the capacitor during charging and discharging can be effectively reduced, and the zero-current switching control or the zero-voltage switching control can be realized through the resonance characteristic.

Fig. 8 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention. The switched capacitor converter 702 shown in fig. 8 is similar to the switched capacitor converter 402 shown in fig. 5, in this embodiment, the inductors L1 and L2 of the switched capacitor converter 702 have mutual inductance, so that the inductor current IL1 and the inductor current IL2 of the switched capacitor converter 702 have better current balance, and at the same time, the resonant capacitors C3 and C2 have better voltage balance.

The control circuit 701 of the present embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

In one embodiment, the inductors L1 and L2 may be configured as, for example, mutual inductors (coupled inductors) or as a transformer (e.g., transformer 7021).

Fig. 9 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention. In an embodiment, the switched capacitor voltage converting circuit 80 includes a first switched capacitor converter 802 and a second switched capacitor converter 803, and the first switched capacitor converter 802 and the second switched capacitor converter 803 are coupled in parallel between the first voltage V1 and the second voltage V2, in this embodiment, the first switched capacitor converter 802 and the second switched capacitor converter 803 correspond to the switched capacitor converter 502 of fig. 6, for example, in this embodiment, the output power can be improved or the ripple current and the ripple current can be reduced by a plurality of switched capacitor converters operating in parallel. It should be noted that, the "parallel connection" of the switching capacitor converters means that the input ends of the switching capacitor converters are electrically connected to each other, for example, the first voltage V1, and the output ends of the switching capacitor converters are electrically connected to each other, for example, the second voltage V2.

In one embodiment, the first switched capacitor converter 802 and the second switched capacitor converter 803 switch the corresponding switches in each switched capacitor converter in opposite phases to each other to perform power conversion in an interleaved manner, specifically, as shown in fig. 9, the switch operation signals S1 to S10 of the switches Q1 to Q10 of the first switched capacitor converter 802 are in phase with the switched capacitor converter 502 of fig. 6, and the switch operation signals S11 to S20 of the switches Q11 to Q20 of the second switched capacitor converter 803 are in phase with the switched capacitor converter 502 of fig. 6 (thus also in phase with the first switched capacitor converter 802).

The first switched capacitor converter 802 and the second switched capacitor converter 803 include inductors L1, L2, L11, L12, and are respectively connected in series with the resonant capacitors C3, C2, C13, C12 to form resonant tanks 8021, 8022, 8031, and 8032. In this embodiment, the first switched capacitor converter 802 and the second switched capacitor converter 803 are operated in an interleaved manner to perform power conversion, and the first switched capacitor converter 802 and the second switched capacitor converter 803 are respectively similar to the switched capacitor converter 502 in fig. 6 and perform power conversion in a resonant manner.

The control circuit 801 of this embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the unidirectional conduction process is similar to that of fig. 6, please refer to the detailed description of fig. 6.

Fig. 10 is a circuit diagram of a switched capacitor voltage conversion circuit according to another embodiment of the invention. The switched capacitor voltage conversion circuit 90 of fig. 10 is similar to the switched capacitor voltage conversion circuit 80 of fig. 9, and the switched capacitor voltage conversion circuit 90 includes a first switched capacitor converter 902 and a second switched capacitor converter 903, wherein the first switched capacitor converter 902 shares an inductance L1, and the second switched capacitor converter 903 shares an inductance L11, and is connected in series with the inductance L1 after the resonant capacitors C3 and C2 are connected in parallel in a similar manner to the embodiment of fig. 7, and is connected in series with the inductance L11 after the resonant capacitors C13 and C12 are connected in parallel in a similar manner to the embodiment of fig. 7. Like the switched capacitor voltage converting circuit 80 of fig. 9, the first switched capacitor converter 902 and the second switched capacitor converter 903 are operated in an interleaved manner to perform power conversion, and the first switched capacitor converter 902 and the second switched capacitor converter 903 are respectively similar to the switched capacitor converter 602 of fig. 7 and perform power conversion in a resonant manner.

The control circuit 901 of this embodiment may be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

Fig. 11 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention. The switched capacitor voltage conversion circuit 100 of fig. 11 is similar to the switched capacitor voltage conversion circuit 80 of fig. 9, and the switched capacitor voltage conversion circuit 100 includes a first switched capacitor converter 1002 and a second switched capacitor converter 1003, wherein the difference is that the inductances L1, L2, L11, L12 of the first switched capacitor converter 1002 and the second switched capacitor converter 1003 are not directly connected in series with the resonance capacitances C3, C2, C13, C12, respectively, but are connected in series with the resonance capacitances C3, C2, C13, C12 through a first switching node LX1, a second switching node LX2, a first switching node LX11, and a second switching node LX12, respectively. Like the switched capacitor voltage converting circuit 80 of fig. 9, the first switched capacitor converter 1002 and the second switched capacitor converter 1003 are operated in an interleaved manner to perform power conversion, and the first switched capacitor converter 1002 and the second switched capacitor converter 1003 are similar to the switched capacitor converter 402 of fig. 5, respectively, to perform power conversion in a resonant manner.

The control circuit 1001 of this embodiment may be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

Fig. 12 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention. The switched capacitor voltage conversion circuit 110 of fig. 12 is similar to the switched capacitor voltage conversion circuit 100 of fig. 11, and the inductors L1, L2, L11, L12 in the switched capacitor voltage conversion circuit 110 have mutual inductance, so that the inductor current IL1, the inductor current IL2, the inductor current IL11, and the inductor current IL12 of the switched capacitor voltage conversion circuit 110 have better current balance, and at the same time, the resonant capacitors C3, C2, C13, and C12 have better voltage balance. In one embodiment, the switched capacitor voltage converting circuit 110 may be configured with the inductors L1, L2, L11, L12 having mutual inductance therebetween or with only a portion of the inductors having mutual inductance therebetween, as desired. In one embodiment, the inductors L1, L2, L11, L12 may be configured as at least one transformer.

The control circuit 1101 of this embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

Fig. 13 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention. The switched capacitor voltage conversion circuit 120 shown in fig. 13 includes a first switched capacitor converter 1202 and a second switched capacitor converter 1203, an upper resonant capacitor C21 and a plurality of upper switches (e.g. switches Q21, Q28), wherein the first switched capacitor converter 1202 and the second switched capacitor converter 1203 may correspond to the switched capacitor converter 502 of fig. 6, for example. In one aspect, the switched capacitor voltage conversion circuit 120 shown in fig. 13 is configured as a switched capacitor voltage conversion circuit having more layers based on, for example, the switched capacitor converter 502 of fig. 6, specifically, the upper resonant capacitor C21, the plurality of upper switches (switches Q21, Q28), the first switched capacitor converter 1202 and the second switched capacitor converter 1203 are coupled to each other in a basic topology, and in one embodiment, the "basic topology" refers to the basic coupling relationship of the upper resonant capacitor C21, the plurality of upper switches (switches Q21, Q28), the first switched capacitor converter 1202 and the second switched capacitor converter 1203, as described in detail below.

The control circuit 1201 of this embodiment may be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the unidirectional conduction process is similar to that of fig. 6, please refer to the detailed description of fig. 6.

In an embodiment, according to the basic topology described above, the input terminal of the first switched capacitor converter 1202 (corresponding to the first switched capacitor converter 1202b, fig. 14) and one end of the upper resonant capacitor C21 are electrically connected to each other, and the input terminal of the second switched capacitor converter 1203 (corresponding to the second switched capacitor converter 1203b, fig. 14) and the other end of the upper resonant capacitor C21 are electrically connected to each other, and furthermore, the output terminal of the first switched capacitor converter 1202, the output terminal of the second switched capacitor converter 1203 and the second voltage V2 are electrically connected to each other.

In a second procedure (for example, the switch operation signals S1-S5, S16-S20, S28 are disabled, and the switch operation signals S6-S10, S11-S15, S21 are enabled), the upper switches (for example, the switches Q21, Q28) and the switches (for example, the switches Q11-Q20) of the first switched capacitor converter 1202 control the upper resonant capacitor C21 to be connected in series with the first switched capacitor converter 1202 and establish at least one current path between the first voltage V1 and the second voltage V2, and the upper switches (for example, the switches Q21, Q28) and the switches (for example, the switches Q1-Q10) of the second switched capacitor converter 1203 control the upper resonant capacitor C21 to be disconnected, and control the second switched capacitor converter 1203 to establish at least one current path between the second voltage V2 and the ground potential.

On the other hand, in the first procedure (for example, when the switch operation signals S1 to S5, S16 to S20, S28 are enabled, the switch operation signals S6 to S10, S11 to S15, S21 are disabled), the plurality of upper switches (switches Q21, Q28) and the plurality of switches (for example, the switches Q1 to Q10) of the second switched capacitor converter 1203 control the second switched capacitor converter 1203 and the upper resonant capacitor C21 to be connected in series between the second voltage V2 and the ground potential, and establish at least one current path between the second voltage V2 and the ground potential, and the plurality of upper switches (switches Q21, Q28) and the plurality of switches (for example, the switches Q11 to Q20) of the first switched capacitor converter 1202 control the upper resonant capacitor C21 and the first switched capacitor converter 1202 to be disconnected, and control the first switched capacitor converter 1202 to establish at least one current path between the second voltage V2 and the ground potential.

The current paths are, for example, current paths established by the switches which are turned on when the switch operation signals S1 to S5, S16 to S20, and S28 are enabled, or when the switch operation signals S6 to S10, S11 to S15, and S21 are enabled, respectively.

The first switched capacitor converter 1202 and the second switched capacitor converter 1203 are further configured with resonant tanks, i.e., the resonant tanks 12021, 12022, 12031, 12032 in the embodiment of fig. 6, so as to perform the conversion between the first voltage V1 and the second voltage V2 in a resonant manner through the resonant tanks 12021, 12022, 12031, 12032.

In this embodiment, the ratio of the first voltage V1 to the second voltage V2 shown in fig. 13 is 8. In detail, in the steady state, the voltage across the upper layer resonant capacitor C21 is 4×v2, the voltage across the non-resonant capacitors C1 and C11 (both correspond to the non-resonant capacitors in the previous embodiment) is 2×v2, and the voltage across the resonant capacitors C3 and C13 (both correspond to the resonant capacitors in the previous embodiment) and the voltage across the resonant capacitors C2 and C12 (both correspond to the resonant capacitors in the previous embodiment) is V2.

With continued reference to fig. 14, according to the present invention, the number of layers of the pipelined switched capacitor voltage converting circuit can be recursively extended by the basic topology of fig. 14, thereby achieving a higher conversion ratio between the first voltage V1 and the second voltage V2. As shown in fig. 14, any of the pipeline-type switched capacitor voltage converting circuits having the basic topology according to fig. 14 may be used to replace the first switched capacitor converter 1202 and the second switched capacitor converter 1203 (for example, the first switched capacitor converter 1202b and the second switched capacitor converter 1203b in the figure may be corresponding to an N-layer pipeline-type switched capacitor voltage converting circuit, where N is an integer greater than or equal to 2), so as to obtain a pipeline-type switched capacitor voltage converting circuit with a higher layer number, that is, the pipeline-type switched capacitor voltage converting circuit 120b will be an n+1 layer pipeline-type switched capacitor voltage converting circuit.

For example, if the pipelined switched capacitor voltage converting circuit 120 of fig. 13 is substituted into the first switched capacitor converter 1202b and the second switched capacitor converter 1203b of fig. 14, the pipelined switched capacitor voltage converting circuit 120b of fig. 14 is configured as 16:1, the same substitution configuration can continuously and repeatedly increase the layer number, thereby continuously increasing the conversion multiple of the power supply.

In this embodiment (16:1 switched capacitor voltage converting circuit), the first switched capacitor converter 1202 and the second switched capacitor converter 1203 of fig. 13 can be regarded as the bottom layer (1 layer) of the pipelined switched capacitor voltage converting circuit, the structure corresponds to the switched capacitor converter 502 of fig. 6, the pipelined switched capacitor voltage converting circuit 120 of fig. 13 can be regarded as the 2 layer of the pipelined switched capacitor voltage converting circuit, and further, the 2 layer of the pipelined switched capacitor voltage converting circuit 120 of fig. 13 is substituted into the first switched capacitor converter 1202b and the second switched capacitor converter 1203b of fig. 14, the pipelined switched capacitor voltage converting circuit 120b of fig. 14 can be regarded as the 3 layer of the pipelined switched capacitor voltage converting circuit.

Fig. 15 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention. The switched capacitor voltage conversion circuit 130 shown in fig. 15 is similar to the switched capacitor voltage conversion circuit 120 shown in fig. 13, in that the first switched capacitor converter 1302 shares the inductance L11, and the second switched capacitor converter 1303 shares the inductance L1, and is connected in series with the inductance L1 after the resonant capacitors C3 and C2 are connected in parallel in a similar manner to the embodiment of fig. 7, and is connected in series with the inductance L11 after the resonant capacitors C13 and C12 are connected in parallel in a similar manner to the embodiment of fig. 7. Like the switched capacitor voltage converting circuit 120 of fig. 13, the first switched capacitor converter 1302 and the second switched capacitor converter 1303 are operated in an interleaved manner to perform power conversion, and the first switched capacitor converter 1302 and the second switched capacitor converter 1303 are similar to the switched capacitor converter 602 of fig. 7, respectively, to perform power conversion in a resonant manner.

The control circuit 1301 of this embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. The embodiment of the unidirectional conduction process is similar to that of fig. 2C and 6, please refer to the detailed description of fig. 2C and 6.

Fig. 16 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention. The switched capacitor voltage converting circuit 140 shown in fig. 16 is similar to the switched capacitor voltage converting circuit 120 shown in fig. 13, in which the difference is that the inductors L1, L2, L11, L12 of the first switched capacitor converter 1402 and the second switched capacitor converter 1403 are not directly connected in series with the resonance capacitors C3, C2, C13, C12 respectively, but are connected in series with the resonance capacitors C3, C2, C13, C12 respectively through the first switching node LX1, the second switching node LX2, the first switching node LX11, the second switching node LX12 respectively, in other words, the switched capacitor voltage converting circuit 140 performs a switching operation in a manner similar to the switched capacitor voltage converting circuit 120, and further performs a conversion between the first voltage V1 and the second voltage V2 through the inductors L1, L2, L11, L12 and the corresponding resonance capacitors in a resonance manner as in the embodiment of fig. 5, and the ratio of the first voltage V1 to the second voltage V2 is also 8.

The control circuit 1401 of this embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. The embodiment of the unidirectional conduction process is similar to that of fig. 2C and 6, please refer to the detailed description of fig. 2C and 6.

Fig. 17 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the invention. The switched capacitor voltage conversion circuit 150 of fig. 17 is similar to the switched capacitor voltage conversion circuit 140 of fig. 16, and the inductors L1, L2, L11, L12 in the switched capacitor voltage conversion circuit 150 have mutual inductance, so that the inductor current IL1, the inductor current IL2, the inductor current IL11, and the inductor current IL12 of the switched capacitor voltage conversion circuit 150 have better current balance, and at the same time, the resonant capacitors C3, C2, C13, and C12 have better voltage balance. In one embodiment, the switched capacitor voltage conversion circuit 150 may be configured with the inductors L1, L2, L11, L12 having mutual inductance therebetween or with only a portion of the inductors having mutual inductance therebetween, as desired. In one embodiment, the inductors L1, L2, L11, L12 may be configured as at least one transformer.

The control circuit 1501 of this embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. The embodiment of the unidirectional conduction process is similar to that of fig. 2C and 6, please refer to the detailed description of fig. 2C and 6.

Fig. 18A is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention. As shown in fig. 18A, the switched capacitor voltage conversion circuit 160 includes resonant capacitors C1 and C3, at least one non-resonant capacitor C2, switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, resonant inductors L1 and L2, and a control circuit 1601.

As shown in fig. 18A, the control circuit 1601 is configured to generate switch operation signals S1, S3, S5, S8, S9 and switch operation signals S2, S4, S6, S7, S10, respectively, corresponding to the second program and the first program, and operate a plurality of corresponding switches (e.g. switches Q1 to Q10) to switch the electrical connection relationship between the corresponding resonant capacitors C1, C3 and the non-resonant capacitor C2. The switched capacitor voltage conversion circuit 160 includes at least one resonant tank, such as resonant tanks 1602 and 1603, the resonant tank 1602 has a resonant capacitor C1 and a resonant inductor L1 connected in series, and the resonant tank 1603 has a resonant capacitor C3 and a resonant inductor L2 connected in series. The switches Q1-Q10 are correspondingly coupled to at least one of the resonance slots 1602, 1603, and respectively correspond to the second program and the first program according to the corresponding switch operation signals S1, S3, S5, S8, S9 and the switch operation signals S2, S4, S6, S7, S10 to switch the electrical connection relationship of the corresponding resonance slots 1602, 1603. In the second process, the corresponding resonance grooves 1602 and 1603 are resonantly charged, and in the first process, the corresponding resonance grooves 1602 and 1603 are resonantly discharged. The at least one non-resonant capacitor C2 is coupled to the at least one resonant tank 1602, 1603, and the switch operation signals S1, S3, S5, S8, S9 and the switch operation signals S2, S4, S6, S7, S10 switch the electrical connection relationship between the non-resonant capacitor C2 and the at least one resonant tank 1602, 1603. The voltage across the non-resonant capacitor C2 is maintained at a fixed ratio to the first voltage V1, for example, half the first voltage V1 in the present embodiment. The first and second processes are sequentially ordered into a combination, and the combination is repeated to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1. The switch operation signals S1, S3, S5, S8, S9 and the switch operation signals S2, S4, S6, S7, S10 are respectively switched to the on level for a conduction period, and the conduction periods of the switch operation signals S1, S3, S5, S8, S9 and the conduction periods of the switch operation signals S2, S4, S6, S7, S10 are not overlapped with each other so that the first program and the second program are not overlapped with each other.

In the second procedure, according to the switch operation signals S1, S3, S5, S8, S9 and the switch operation signals S2, S4, S6, S7, S10, the switches Q1, Q3, Q5, Q8, Q9 are turned on, the switches Q2, Q4, Q6, Q7, Q10 are turned off, so that the resonant capacitor C1 and the resonant inductor L1 of the resonant tank 1602 are connected in series between the first voltage V1 and the second voltage V2, and the resonant capacitor C3 and the resonant inductor L2 of the non-resonant capacitor C2 and the resonant tank 1603 are connected in series between the ground potential and the second voltage V2, and the resonant capacitors C1 and C3 are charged, and the non-resonant capacitor C2 is discharged. In the first procedure, according to the switch operation signals S1, S3, S5, S8, S9 and the switch operation signals S2, S4, S6, S7, S10, the switches Q2, Q4, Q6, Q7, Q10 are turned on, the switches Q1, Q3, Q5, Q8, Q9 are turned off, so that the non-resonant capacitor C2 and the resonant capacitor C1 and the resonant inductor L1 of the resonant tank 1602 are connected in series between the ground potential and the second voltage V2, and the resonant capacitor C3 and the resonant inductor L2 of the resonant tank 1603 are connected in series between the ground potential and the second voltage V2, and the resonant capacitors C1 and C3 are discharged, and the non-resonant capacitor C2 is charged.

The operation of the switched capacitor voltage conversion circuit 160 having the resonant tanks 1602 and 1603 shown in fig. 18A and 18B is well known to those skilled in the art and will not be described herein.

The control circuit 1601 of the present embodiment may be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. As shown in fig. 18A, in the unidirectional conduction process, when the switches Q1 to Q10 are not turned on by the switch operation signals S1 to S10, one end of the corresponding inductor L1 is electrically connected to the dc potential via at least one switch (e.g., a body diode (shown by a dotted line in fig. 18A)) so that the inductor current ILo1 flowing toward the second voltage V2 is a resonant current having a third resonant frequency, wherein the third resonant frequency is different from the first resonant frequency of the first process and the second resonant frequency of the second process. For example, the inductor L1 is connected in series between the second voltage V2 and the ground potential via the inscribed diodes in the switches Q8, Q2 and Q5, so that the inductor current IL1 is freewheeled according to the current direction shown by the dashed arrow in fig. 18A, for example. Referring to fig. 18A again, in the unidirectional conduction procedure, when the switches are controlled to switch (e.g. the switches Q1 to Q10 are turned off) by the switch operation signals S1 to S10, the inductor current IL2 flowing through the corresponding inductor L2 is conducted through the body diode (shown by the dotted line in fig. 18A) in at least one switch (e.g. the switches Q4 and Q9), and the closed loop 16023 formed through the resonant tank 16022 and the body diode (shown by the dotted line in fig. 18A) in at least one switch (e.g. the switches Q4 and Q9) is freewheeled, so that the inductor current ILo2 stops flowing toward the second voltage V2 in the second state. In this case, no net current flows into or out of the non-resonant capacitor (also referred to as the output capacitor) CV2 by the closed loop current (i.e., inductor current IL 2).

Referring to fig. 18B, in the unidirectional conduction process, when the switches are controlled to switch (e.g. the switches Q1 to Q10 are turned off) by the switch operation signals S1 to S10, one end of the corresponding inductor L2 is electrically connected to the dc potential via at least one switch (e.g. a body diode (shown by a dotted line in fig. 18B)) in the switch Q10, so that the inductor current ILo2 flowing toward the second voltage V2 is a resonant current with a third resonant frequency, wherein the third resonant frequency is different from the first resonant frequency of the first process and the second resonant frequency of the second process. For example, the inductor L2 is connected in series between the second voltage V2 and the ground potential via the inscribed diodes in the switches Q10, Q3 and Q7, so that the inductor current IL2 is freewheeled according to the current direction shown by the dashed arrow in fig. 18B, for example. In another embodiment, when the unidirectional conduction process adopts unidirectional conduction to the first voltage V1, the unidirectional conduction process is similar to that of fig. 6, please refer to the detailed description of fig. 6.

Fig. 19 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the invention. As shown in fig. 19, the switched capacitor voltage conversion circuit 170 of the present invention includes resonance capacitors C1 to C3, switches Q1 to Q10, and inductors L1 to L3. The switches Q1-Q3 are respectively connected in series with the corresponding resonant capacitors C1-C3, and the resonant capacitors C1-C3 are respectively connected in series with the corresponding inductors L1-L3. It should be noted that the number of capacitors in the power conversion circuit of the present invention is not limited to three in the present embodiment, but may be two or more, and the number of inductors is not limited to three in the present embodiment, but may be two or more.

The switches Q1-Q10 can switch the electric connection relation between the corresponding resonant capacitors C1-C3 and the inductors L1-L3 according to the corresponding operation signals. In the second procedure, the switches Q1-Q4 are conductive, and the switches Q5-Q10 are non-conductive, so that the resonant capacitors C1-C3 and the inductors L1-L3 are connected in series between the first voltage V1 and the second voltage V2 to form a second current path for performing the charging procedure. In the first procedure, the inductors L1-L3 can be used as discharge inductors, the switches Q5-Q10 are turned on, and the switches Q1-Q4 are turned off, so that the resonant capacitor C1 and the corresponding inductor L1 are connected in series between the second voltage V2 and the ground potential, the resonant capacitor C2 and the corresponding inductor L2 are connected in series between the second voltage V2 and the ground potential, and the resonant capacitor C3 and the corresponding inductor L3 are connected in series between the second voltage V2 and the ground potential, thereby forming a plurality of first current paths for performing the discharge procedure. It should be noted that the first process and the second process are performed alternately in different time periods, not simultaneously, so as to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1. The first and second programs are sequentially ordered into a combination, and the combination is repeated to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1. In this embodiment, the dc bias voltage of each of the resonant capacitors C1, C2, and C3 is the second voltage V2, so the resonant capacitors C1, C2, and C3 in this embodiment need to withstand a lower rated voltage, and therefore a smaller capacitor can be used.

The control circuit 1701 of this embodiment may be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. As shown in fig. 19, in the unidirectional conduction process, when the switches are controlled to switch (e.g., the switches Q1 to Q10 are turned off) by the switch operation signals S1 to S10, one ends of the corresponding inductors L2 and L3 are electrically connected to the dc potential via at least one switch (e.g., the body diode (shown by the dotted line in fig. 19) among the switches Q8 and Q2 and the switches Q9 and Q3), so that the inductor currents ILo2 and ILo3 flowing toward the second voltage V2 are the resonant current having the third resonant frequency and the resonant current having the fourth resonant frequency, wherein the third resonant frequency and the fourth resonant frequency are different from the first resonant frequency of the first process and the second resonant frequency of the second process. For example, the inductor L2 is connected in series between the second voltage V2 and the ground potential via the inscribed diodes of the switches Q8, Q2, Q3 and Q4, and the inductor L3 is connected in series between the second voltage V2 and the ground potential via the inscribed diodes of the switches Q9, Q3 and Q4, so that the inductor current IL2 and the inductor current IL3 can freewheel according to the current directions shown by the dashed arrows in fig. 19, respectively. In another embodiment, when the unidirectional conduction process adopts unidirectional conduction to the first voltage V1, the unidirectional conduction process is similar to that of fig. 6, please refer to the detailed description of fig. 6.

In one embodiment, the first process has a first resonant frequency and the second process has a second resonant frequency. In a preferred embodiment, the first resonant frequency is the same as the second resonant frequency.

Fig. 20 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention. The difference between this embodiment and the previous embodiment is that the plurality of resonance capacitors share a charging inductance or a discharging inductance, so that only one charging inductance and one discharging inductance are needed no matter how many resonance capacitors are, and the number of the inductors can be further reduced. As shown in fig. 20, the switched capacitor voltage conversion circuit 180 of the present invention includes resonance capacitors C1 to C3, switches Q1 to Q10, and inductors L1 to L2. Switches Q1-Q3 are connected in series with corresponding resonant capacitors C1-C3, respectively, while switch Q4 is connected in series with inductor L1. It should be noted that the number of capacitors in the switched capacitor voltage conversion circuit of the present invention is not limited to three in the present embodiment, but may be two or more than four.

The switches Q1-Q10 can switch the electric connection relation between the corresponding resonant capacitors C1-C3 and the inductors L1 and L2 according to the corresponding operation signals. In the second procedure, the switches Q1 to Q4 are turned on and the switches Q5 to Q10 are turned off according to the switch operation signals S1 to S4 and S5 to S10, so that the resonant capacitors C1 to C3 are connected in series with each other and then connected in series with the inductor L1 between the first voltage V1 and the second voltage V2 to form a second current path for performing the charging procedure. In the first procedure, according to the switch operation signals S1 to S4 and S5 to S10, the switches Q5 to Q10 are turned on, the switches Q1 to Q4 are turned off, the resonance capacitors C1 to C3 are connected in parallel, and then the series inductor L2 is connected between the second voltage V2 and the ground potential, so as to form a plurality of first current paths for performing a discharging procedure. It should be noted that the first process and the second process are performed alternately in different time periods, not simultaneously, so as to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1. In this embodiment, the dc bias voltage of each of the resonant capacitors C1, C2, and C3 is the second voltage V2, so the resonant capacitors C1, C2, and C3 in this embodiment need to withstand a lower rated voltage, and therefore a smaller capacitor can be used.

The control circuit 1801 of the present embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

In one embodiment, the first process has a first resonant frequency and the second process has a second resonant frequency. In a preferred embodiment, the first resonant frequency is the same as the second resonant frequency. In another embodiment, the first resonant frequency is different from the second resonant frequency. In one embodiment, the inductance value of the inductor L1 is equal to the inductance value of the inductor L2. In another embodiment, the inductance value of the inductor L1 is different from the inductance value of the inductor L2.

Fig. 21 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the invention. In this embodiment, the charging inductor and the discharging inductor may be the same inductor L, and the number of inductors may be further reduced by such arrangement. As shown in fig. 21, the switched capacitor voltage conversion circuit 190 of the present invention includes resonance capacitors C1 to C3, switches Q1 to Q10, and an inductance L. Switches Q1-Q3 are connected in series with corresponding resonant capacitors C1-C3, respectively, while switch Q4 is connected in series with inductor L. It should be noted that the number of capacitors in the switched capacitor voltage conversion circuit of the present invention is not limited to three in the present embodiment, but may be two or more than four.

It should be noted that, in the present embodiment, the charging inductance and the discharging inductance are the same inductance L, and in the first procedure, the resonant capacitors C1-C3 are connected in parallel to each other and then connected in series to the same inductance L through the switching of the switches Q1-Q10. The charging inductance and the discharging inductance are the same inductance L, which means that in the second process (which may be referred to as a charging process) and the first process (which may be referred to as a discharging process), the inductance current IL in the charging process and the discharging process flows through only the single inductance L, and no other inductance element.

The switches Q1-Q10 can switch the electric connection relation between the corresponding resonant capacitors C1-C3 and the inductor L according to the corresponding operation signals. In the second procedure, the switches Q1 to Q4 are turned on and the switches Q5 to Q10 are turned off according to the switch operation signals S1 to S4 and S5 to S10, so that the resonant capacitors C1 to C3 are connected in series with each other and then connected in series with the inductor L between the first voltage V1 and the second voltage V2 to form a second current path for performing the charging procedure. In the first procedure, according to the switch operation signals S1 to S4 and S5 to S10, the switches Q5 to Q10 are turned on, the switches Q1 to Q4 are turned off, the resonance capacitors C1 to C3 are connected in parallel, and then the series inductance L is connected between the second voltage V2 and the ground potential, so as to form a plurality of first current paths for performing a discharging procedure. It should be noted that the first and second processes are repeatedly performed in a staggered manner in different time periods, instead of being performed simultaneously, so as to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1. In the present embodiment, the dc bias voltage of each of the resonant capacitors C1 to C3 is the second voltage V2, so the resonant capacitors C1 to C3 in the present embodiment need to withstand a lower rated voltage, and thus a smaller capacitor can be used.

The control circuit 1901 of this embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

Fig. 22 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention. As shown in fig. 22, the switched capacitor voltage conversion circuit 200 of the present invention includes resonance capacitors C1 to C2, switches Q1 to Q7, and an inductance L. The switches Q1-Q2 are connected in series with the corresponding resonant capacitors C1-C2, respectively, while the switch Q3 is connected in series with the inductor L.

The switches Q1-Q7 can switch the electric connection relation between the corresponding resonant capacitors C1-C2 and the inductor L according to the corresponding operation signals. In the second procedure, the switches Q1-Q3 are turned on and the switches Q4-Q7 are turned off according to the switch operation signals S1-S3 and S4-S7, so that the resonant capacitors C1-C2 are connected in series with each other and then connected in series with the inductor L between the first voltage V1 and the second voltage V2 to form a second current path for performing the charging procedure. In the first procedure, according to the switch operation signals S1-S3 and S4-S7, the switches Q4-Q7 are conducted, the switches Q1-Q3 are not conducted, the resonance capacitors C1-C2 are connected in parallel, and then the series inductance L is connected between the second voltage V2 and the ground potential, so as to form a plurality of first current paths, and a discharging procedure is performed. It should be noted that the first and second processes are repeatedly performed in a staggered manner in different time periods, instead of being performed simultaneously, so as to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1. In the present embodiment, the dc bias voltage of each of the resonant capacitors C1 to C2 is the second voltage V2, so the resonant capacitors C1 to C2 in the present embodiment need to withstand a lower rated voltage, and thus a smaller capacitor can be used.

The control circuit 2001 of the present embodiment may be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

Fig. 23 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the present invention. As shown in fig. 23, the switched capacitor voltage conversion circuit 210 of the present invention includes a resonant capacitor C3, non-resonant capacitors C1 to C2, switches Q1 to Q8, and an inductance L.

The switches Q1-Q8 can switch the electric connection relation between the corresponding resonant capacitor C3, the corresponding non-resonant capacitors C1-C2 and the inductor L according to the corresponding operation signals. In the second procedure, according to the switch operation signals S1 to S8, the switches Q1, Q3, Q5, Q7 are turned on, and the switches Q2, Q4, Q6, Q8 are turned off, so that the non-resonant capacitor C1, the resonant capacitor C3, and the inductor L are connected in series between the first voltage V1 and the second voltage V2, and one end of the non-resonant capacitor C2 is coupled between the non-resonant capacitor C1 and the resonant capacitor C3, while the other end of the non-resonant capacitor C2 is coupled to the ground potential, so as to form a second current path for performing the charging procedure. In the first procedure, according to the switch operation signals S1 to S8, the switches Q2, Q4, Q6, Q8 are turned on, and the switches Q1, Q3, Q5, Q7 are turned off, so that the resonant capacitor C3 and the inductor L are connected in series between the second voltage V2 and the ground potential to form a first current path for performing the discharging procedure. It should be noted that the first and second processes are repeatedly performed in a staggered manner in different time periods, instead of being performed simultaneously, so as to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1.

The control circuit 2101 of the present embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

Fig. 24 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention. As shown in fig. 24, the switched capacitor voltage conversion circuit 220 of the present invention includes a resonant capacitor C3, non-resonant capacitors C1 to C2, switches Q1 to Q6, and an inductance L.

The switches Q1-Q6 can switch the electric connection relation between the corresponding resonant capacitor C3, the corresponding non-resonant capacitors C1-C2 and the inductor L according to the corresponding operation signals. In the second procedure, according to the switch operation signals S1 to S6, the switches Q1, Q3, Q5 are turned on, and the switches Q2, Q4, Q6 are turned off, so that the non-resonant capacitor C2 and the resonant capacitor C3 are connected in parallel, and then the non-resonant capacitor C1 and the inductor L are connected in series between the first voltage V1 and the second voltage V2, so as to form a second current path for performing the charging procedure. In the first procedure, according to the switch operation signals S1 to S6, the switches Q2, Q4, Q6 are turned on, and the switches Q1, Q3, Q5 are turned off, so that the resonant capacitor C3 and the inductor L are connected in series between the second voltage V2 and the ground potential to form a first current path for performing the discharging procedure. It should be noted that the first and second processes are repeatedly performed in a staggered manner in different time periods, instead of being performed simultaneously, so as to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1.

The control circuit 2201 of this embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

Fig. 25 is a circuit diagram showing a switched capacitor voltage conversion circuit according to still another embodiment of the invention. As shown in fig. 25, the switched capacitor voltage conversion circuit 230 of the present invention includes a resonant capacitor C3, non-resonant capacitors C1 to C2, switches Q1 to Q8, and an inductance L.

The switches Q1-Q8 can switch the electric connection relation between the corresponding resonant capacitor C3, the corresponding non-resonant capacitors C1-C2 and the inductor L according to the corresponding operation signals. In the second procedure, according to the switch operation signals S1-S8, the switches Q1, Q2, Q5, Q6 are turned on, and the switches Q3, Q4, Q7, Q8 are turned off, so that the non-resonant capacitor C1, the resonant capacitor C3, and the inductor L are connected in series between the first voltage V1 and the second voltage V2, and one end of the non-resonant capacitor C2 is coupled between the non-resonant capacitor C1 and the resonant capacitor C3, while the other end of the non-resonant capacitor C2 is coupled to the ground potential, so as to form a second current path for performing the charging procedure. In the first procedure, according to the switch operation signals S1 to S8, the switches Q3, Q4, Q7, Q8 are turned on, and the switches Q1, Q2, Q5, Q6 are turned off, so that the resonant capacitor C3 and the inductor L are connected in series between the second voltage V2 and the ground potential to form a first current path for performing the discharging procedure. It should be noted that the first and second processes are repeatedly performed in a staggered manner in different time periods, instead of being performed simultaneously, so as to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1.

The control circuit 2301 of the present embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

Fig. 26 is a circuit diagram showing a switched capacitor voltage conversion circuit according to another embodiment of the invention. As shown in fig. 26, the switched capacitor voltage conversion circuit 240 of the present invention includes resonance capacitors C1 to C3, switches Q1 to Q10, and an inductance L.

The switches Q1-Q10 can switch the electric connection relation between the corresponding resonant capacitors C1-C3 and the inductor L according to the corresponding operation signals. In the second procedure, according to the switch operation signals S1 to S10, the switches Q1, Q3, Q5, Q8, Q9 are turned on, and the switches Q2, Q4, Q6, Q7, Q10 are turned off, so that the resonant capacitor C1, the resonant capacitor C3, and the inductor L are connected in series between the first voltage V1 and the second voltage V2, and one end of the resonant capacitor C2 is coupled between the resonant capacitor C1 and the resonant capacitor C3, and the other end of the resonant capacitor C2 is coupled to the ground potential to form a second current path for performing the charging procedure. In the first procedure, according to the switch operation signals S1 to S10, the switches Q2, Q4, Q6, Q7, Q10 are turned on, and the switches Q1, Q3, Q5, Q8, Q9 are turned off, so that the resonant capacitor C1 and the resonant capacitor C2 are connected in series, then connected in parallel with the resonant capacitor C3, and then connected in series with the inductor L between the second voltage V2 and the ground potential, thereby forming a first current path for performing the discharging procedure. It should be noted that the first and second processes are repeatedly performed in a staggered manner in different time periods, instead of being performed simultaneously, so as to convert the first voltage V1 into the second voltage V2 or convert the second voltage V2 into the first voltage V1.

The control circuit 2401 of this embodiment can be implemented by using the control circuit architecture of fig. 2B in combination with fig. 3A, 3C-3F, 3H, 4A or 4C, please refer to the detailed description of fig. 2B, 3A, 3C-3F, 3H, 4A or 4C. An embodiment of the one-way conduction process is similar to that of fig. 2C, please refer to the detailed description of fig. 2C.

The present invention provides a switched capacitor voltage conversion circuit that does not require balancing the resonant capacitor voltage to one half of the input voltage, that can achieve zero current switching and zero voltage switching to reduce switching power loss, that can use smaller inductors to reduce inductor size, that can achieve lower voltage stress on switches, resonant capacitors, and inductors, that can adjust the output voltage as compared to a resonant switched capacitor conversion circuit with a fixed voltage conversion ratio, and that can have higher efficiency.

The present invention has been described in terms of the preferred embodiments, but the above description is only for the purpose of facilitating the understanding of the present invention to those skilled in the art, and is not intended to limit the scope of the invention in its broadest form. The embodiments described are not limited to single applications but may be combined, for example, two or more embodiments may be combined, and portions of one embodiment may be substituted for corresponding components of another embodiment. In addition, various equivalent changes and various combinations will be apparent to those skilled in the art, and for example, the term "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the processing or calculating based on the signal itself, but includes performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling conversion of the signal, if necessary, and then processing or calculating based on the converted signal to generate an output result. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described herein, embody the principles of the invention and are thus equally well suited to the particular use contemplated. Accordingly, the scope of the invention should be assessed as that of the above and all other equivalent variations.

Claims

1. A switched capacitor voltage conversion circuit for converting a first voltage to a second voltage or vice versa, the switched capacitor voltage conversion circuit comprising:

a switched capacitor converter coupled between the first voltage and the second voltage; and

the control circuit is used for generating a pulse width modulation signal according to the first voltage or the second voltage, and generating a control signal according to the pulse width modulation signal and a zero current detection signal to control the switched capacitor converter so as to convert the first voltage into the second voltage or convert the second voltage into the first voltage;

wherein the switched capacitor converter comprises:

at least one resonant capacitor;

a plurality of switches coupled to the at least one resonant capacitor; and

at least one inductor;

when the first voltage is converted into the second voltage, the control signal comprises a unidirectional conduction operation signal, a first operation signal and a second operation signal, so as to respectively correspond to a unidirectional conduction program, a first program and a second program, and further be used for operating the corresponding switches to switch the electric connection relation of the corresponding inductors;

When the first voltage is converted into the second voltage, the control circuit generates the pulse width modulation signal according to the second voltage, and the operation modes of the one-way conduction program, the first program and the second program are as follows:

in the unidirectional conduction program, the unidirectional conduction operation signals control the switching of the switches so as to form a unidirectional conduction path between a first direct current potential and the second voltage, and an inductance current flowing through the inductance flows to the second voltage through the unidirectional conduction path;

in the first procedure, the switching of the switches is controlled by the first operation signal, so that the corresponding resonant capacitor and the corresponding inductor are connected in series between the second voltage and a second direct current potential to form a first current path, and the inductor current flowing through the inductor and flowing to the second voltage is a resonant current with a first resonant frequency;

in the second procedure, the switching of the switches is controlled by the second operation signal, so that the corresponding resonant capacitor and the corresponding inductor are connected in series between the first voltage and the second voltage to form a second current path, and the inductor current flowing through the inductor and flowing to the second voltage is a resonant current with a second resonant frequency;

The unidirectional conduction operation signal, the first operation signal and the second operation signal are respectively switched to an enabling level in a corresponding enabling period, and the enabling periods of the segments are not overlapped with each other, so that the unidirectional conduction program, the first program and the second program are not overlapped with each other;

the unidirectional conduction program, the first program and the second program are sequentially ordered into a combination, and then the combination is repeated, so that the inductor performs inductive power conversion switching among the unidirectional conduction program, the first program and the second program, and further converts the first voltage into the second voltage;

the control circuit also generates the zero current detection signal according to the time point when the inductance current reaches zero current.

2. The switched capacitor voltage conversion circuit of claim 1 wherein the control circuit comprises:

the pulse width modulation circuit is used for generating the pulse width modulation signal according to the second voltage when the first voltage is converted into the second voltage, and generating the pulse width modulation signal according to the first voltage when the second voltage is converted into the first voltage;

a zero current detection circuit for generating the zero current detection signal when the inductance current reaches the zero current; and

And the control signal generating circuit is used for generating the control signal according to the pulse width modulation signal and the zero current detection signal and generating a plurality of switch operation signals corresponding to the plurality of switches in the one-way conduction program, the first program and the second program respectively according to the control signal.

3. The switched capacitor voltage converting circuit of claim 1 wherein said unidirectional current flowing process, said first process and said second process form a switching cycle, and the sequence of said unidirectional current flowing process, said first process and said second process in said switching cycle can be arbitrarily combined, and the end point of the earliest process in said switching cycle is determined by said pwm signal, and the end points of the other processes in said switching cycle except the earliest process are determined by said zero current detection signal.

4. The switched capacitor voltage conversion circuit of claim 1 wherein the inductor current is one of:

the inductance current is a resonance current with a third resonance frequency; or (b)

The inductance current is non-resonant current;

wherein when the inductor current is the non-resonant current, the inductor current is a linear ramp current that gradually decreases or another linear ramp current that gradually increases.

5. The switched capacitor voltage conversion circuit of claim 4 wherein, in the unidirectional current conduction process, when the inductor current is the non-resonant current and the linearly ramp current is gradually decreasing, the unidirectional current conduction path comprises an internal diode of at least one of the switches in a non-conductive state through which the inductor current flows.

6. The switched capacitor voltage conversion circuit of claim 4 wherein in the unidirectional conduction process, the unidirectional conduction path comprises at least one of the switches in a conductive state through which the inductor current flows.

7. The switched capacitor voltage conversion circuit of claim 1 wherein the first dc voltage is the first voltage or a ground voltage and the second dc voltage is the first voltage or the ground voltage.

8. The switched capacitor voltage conversion circuit of claim 1 wherein the pulse width modulation circuit comprises:

a locking circuit for locking the second voltage to a reference voltage to generate a voltage locking signal;

a ramp circuit for generating a ramp signal; and

a comparing circuit for comparing the voltage locking signal and the ramp signal to generate the pulse width modulation signal.

9. The switched capacitor voltage conversion circuit of claim 8 wherein the ramp circuit comprises a reset circuit for resetting the ramp signal according to the control signal or a clock signal.

10. The switched capacitor voltage conversion circuit of claim 1, wherein the control signal adjusts the enabling period of the first and/or second program to achieve soft switching zero voltage switching or zero current switching.

11. The switched capacitor voltage conversion circuit of claim 3 wherein the switching period is a fixed period.

12. The switched capacitor voltage conversion circuit of claim 11 wherein after the unidirectional current sequence, the first sequence and the second sequence of the switching cycle are all completed, the plurality of switches remain non-conductive for a zero current period to the end of the fixed period.

13. The switched capacitor voltage conversion circuit of claim 1 further comprising a non-resonant capacitor coupled to the resonant capacitor, wherein a voltage across the non-resonant capacitor is maintained at a constant dc voltage during the first and second processes.

14. The switched capacitor voltage conversion circuit of claim 1 wherein when the second voltage is converted to the first voltage, the control circuit generates the pulse width modulation signal according to the first voltage to generate the control signal to convert the second voltage to the first voltage;

When the second voltage is converted into the first voltage, the control signal comprises an inverse unidirectional conduction operation signal, a third operation signal and a fourth operation signal, so as to respectively correspond to an inverse unidirectional conduction program, a third program and a fourth program, and operate the corresponding switches to switch the electric connection relation of the corresponding inductors;

when the second voltage is converted into the first voltage, the reverse unidirectional current process, the third process and the fourth process are operated as follows:

in the reverse unidirectional conduction process, the switching of the switches is controlled by the reverse unidirectional conduction operation signal so as to form a reverse unidirectional conduction path between a third direct current potential and the first voltage, and the inductance current flowing through the inductance flows to the first voltage through the reverse unidirectional conduction path;

in the third procedure, the switching of the switches is controlled by the third operation signal, so that the corresponding resonant capacitor and the corresponding inductor are connected in series between the first voltage and a fourth direct current potential to form a third current path, and the inductor current flowing through the inductor and flowing to the first voltage is a resonant current with a fourth resonant frequency;

In the fourth procedure, the switching of the switches is controlled by the fourth operation signal, so that the corresponding resonant capacitor and the corresponding inductor are connected in series between the first voltage and the second voltage to form a fourth current path, and the inductor current flowing through the inductor and flowing to the first voltage is a resonant current with a fifth resonant frequency;

the reverse unidirectional operation signal, the third operation signal and the fourth operation signal are respectively switched to the enabling level in a corresponding enabling period, and the enabling periods of the segments are not overlapped with each other, so that the reverse unidirectional operation program, the third program and the fourth program are not overlapped with each other;

the reverse one-way conduction program, the third program and the fourth program are sequentially ordered into a combination, and then the combination is repeated, so that the reverse one-way conduction program, the third program and the fourth program are subjected to inductive power conversion switching, and the second voltage is converted into the first voltage.

15. The switched capacitor voltage conversion circuit of claim 1 wherein the switched capacitor converter comprises a distributed switched capacitor converter, a series-parallel switched capacitor converter, a dixon switched capacitor converter, a stepped switched capacitor converter, a voltage doubler switched capacitor converter, a fibonacci switched capacitor converter, a pipelined switched capacitor converter, or a switched cavity converter.

16. The switched capacitor voltage conversion circuit of claim 15 wherein the series-parallel switched capacitor converter comprises a half series-parallel switched capacitor converter, a third series-parallel switched capacitor converter, or a quarter series-parallel switched capacitor converter.

17. The switched capacitor voltage converting circuit of claim 14 wherein said third dc voltage is said second voltage or a ground voltage and said fourth dc voltage is said second voltage or said ground voltage.

18. The switched capacitor voltage conversion circuit of claim 2 wherein the zero current detection circuit comprises:

a current sensing circuit for sensing a current flowing through the at least one inductor to generate at least one corresponding current sensing signal; and

and a comparator coupled to the current sensing circuit for comparing the at least one current sensing signal with a reference signal to generate at least one corresponding zero current detection signal to indicate a time point when the at least one inductor current reaches the zero current.

19. The switched capacitor voltage converting circuit of claim 1 wherein said combination comprises two of said unidirectional current-carrying processes, said first process and said second process, wherein said two of said unidirectional current-carrying processes, said first process and said second process form a switching cycle, and the order of said two of said unidirectional current-carrying processes, said first process and said second process in said switching cycle can be arbitrarily combined, and the end point of the earliest process in said switching cycle is determined by said pwm signal, and the end points of the other processes in said switching cycle other than the earliest process are determined by said zero current detection signal.

20. A control method of a switched capacitor converter is used for converting a first voltage into a second voltage or converting the second voltage into the first voltage, and comprises the following steps:

generating a pulse width modulation signal according to the first voltage or the second voltage;

generating a zero current detection signal according to the time point when an inductance current reaches zero current; and

generating a control signal to control a switched capacitor converter according to the pulse width modulation signal and the zero current detection signal, so as to convert the first voltage into the second voltage or convert the second voltage into the first voltage;

when the first voltage is converted into the second voltage, the pulse width modulation signal is generated according to the second voltage, and the control signal comprises a unidirectional conduction operation signal, a first operation signal and a second operation signal, so as to respectively correspond to a unidirectional conduction program, a first program and a second program, and further be used for operating a plurality of corresponding switches to switch the electric connection relation of a corresponding inductor;

when the first voltage is converted into the second voltage, the unidirectional conduction procedure, the first procedure and the second procedure are operated as follows:

In the unidirectional conduction program, the unidirectional conduction operation signals control the switching of the switches so as to form a unidirectional conduction path between a first direct current potential and the second voltage, and the inductive current flowing through the inductor flows to the second voltage through the unidirectional conduction path;

in the first procedure, the switching of the switches is controlled by the first operation signal, so that a corresponding resonant capacitor and a corresponding inductor are connected in series between the second voltage and a second direct current potential to form a first current path, and the inductor current flowing through the inductor and flowing to the second voltage is a resonant current with a first resonant frequency;

The unidirectional conduction program, the first program and the second program are sequentially ordered into a combination, and then the combination is repeated, so that the inductor performs inductive power conversion switching among the unidirectional conduction program, the first program and the second program, and further converts the first voltage into the second voltage.

21. The method of claim 20, wherein when the second voltage is converted into the first voltage, the pwm signal is generated according to the first voltage, and the control signal includes a reverse unidirectional operation signal, a third operation signal and a fourth operation signal, so as to respectively correspond to a reverse unidirectional operation program, a third program and a fourth program, and operate the corresponding switches to switch the electrical connection relationship of the corresponding inductors;

22. The method of claim 20, wherein the unidirectional current-carrying process, the first process and the second process form a switching cycle, the arrangement sequence of the unidirectional current-carrying process, the first process and the second process in the switching cycle can be arbitrarily combined, the end point of the earliest process in the switching cycle is determined by the pulse width modulation signal, and the end points of the other processes except the earliest process in the switching cycle are determined by the zero current detection signal.

23. The method of claim 21, wherein the reverse unidirectional current process, the third process and the fourth process form a switching cycle, the arrangement sequence of the reverse unidirectional current process, the third process and the fourth process in the switching cycle can be arbitrarily combined, the end point of the earliest process in the switching cycle is determined by the pwm signal, and the end points of the other processes except the earliest process in the switching cycle are determined by the zero current detection signal.

24. The method of claim 20, wherein the inductor current is one of the following in the unidirectional current flowing process:

The inductance current is non-resonant current;

25. The method of claim 21, wherein the inductor current is one of the following in the reverse unidirectional current process:

the inductance current is a resonance current with a sixth resonance frequency; or (b)

The inductance current is non-resonant current;

26. The method of claim 20, wherein the first dc voltage is the first voltage or a ground voltage, and the second dc voltage is the first voltage or the ground voltage.

27. The method of claim 21, wherein the third dc voltage is the second voltage or a ground voltage, and the fourth dc voltage is the second voltage or the ground voltage.

28. The method of claim 22, wherein the switching cycle is a fixed period, and wherein the switches remain non-conductive for a zero current period to the fixed period after the unidirectional current process, the first process, and the second process of the switching cycle are all completed.

29. The method of claim 23, wherein the switching cycle is a fixed period, and wherein the switches remain non-conductive for a period of zero current until the fixed period ends after the reverse unidirectional conducting process, the third process, and the fourth process of the switching cycle are all completed.

30. The method of claim 20, wherein the combination includes two unidirectional conduction programs, the first program and the second program, wherein the two unidirectional conduction programs, the first program and the second program form a switching period, the arrangement sequence of the two unidirectional conduction programs, the first program and the second program in the switching period can be arbitrarily combined, the end time point of the earliest program in the switching period is determined by the pulse width modulation signal, and the end time points of other programs except the earliest program in the switching period are determined by the zero current detection signal.