CN117059544A

CN117059544A - Semiconductor processing device

Info

Publication number: CN117059544A
Application number: CN202210489064.7A
Authority: CN
Inventors: 王吉
Original assignee: Wuxi Huaying Microelectronics Technology Co Ltd
Current assignee: Wuxi Huaying Microelectronics Technology Co Ltd
Priority date: 2022-05-06
Filing date: 2022-05-06
Publication date: 2023-11-14

Abstract

The present invention provides a semiconductor processing apparatus, comprising: a first chamber portion; a second chamber portion movable relative to the first chamber portion between an open position and a closed position; and the positioning mechanisms are arranged on the first cavity part and/or the second cavity part, each positioning mechanism comprises a positioning column and a driving mechanism for driving the positioning column to move between a positioning position and an initial position, the positioning column is provided with a positioning side surface perpendicular to the surface of the semiconductor wafer, and when the positioning column is positioned at the positioning position, the positioning side surface of the positioning column can position the edge of the semiconductor wafer. The semiconductor wafer can be centrally positioned by the mutual matching of the positioning sides of the positioning columns of the positioning mechanisms.

Description

Semiconductor processing device

[ field of technology ]

The present invention relates to the field of processing semiconductor wafers, and more particularly, to a semiconductor processing apparatus.

[ background Art ]

The precise edge etching process of semiconductor wafers is a challenging process. It is required to achieve accurate corrosion of the wafer edge micron level without damaging or contaminating the film of the remaining portion. In epitaxial wafer processing and advanced integrated circuit processing, wafer edge etching is an important step for ensuring film formation quality and improving chip yield.

Please refer to fig. 1a to 1d, wherein: FIG. 1a shows a schematic structure of a semiconductor wafer 400, and FIG. 1b is a cross-sectional E-E view of FIG. 1 a; FIG. 1c is a partial cross-sectional view of the outer edge of a semiconductor wafer prior to outer edge processing; fig. 1d is a cross-sectional view of the outer edge portion of the semiconductor wafer after outer edge processing. As shown in fig. 1a to 1d, the semiconductor wafer 400 includes a substrate layer 401 and a thin film layer 402 formed on a first edge surface and a second edge surface of the substrate layer 401. After the selective etching treatment for the first edge surface 404, the second wafer surface 406 and the outer end bevel 408 of the outer edge portion of the semiconductor wafer 400, the thin film layer 402 of the outer edge portion of the semiconductor wafer 400 is removed, and the first edge surface and the second edge surface of the base material layer 401 are exposed.

Existing wafer edge etching equipment can be divided into two main types, namely dry method and wet method. The dry method is mainly divided into a plasma method and a polishing method. The plasma edge etching method has high equipment cost and complex method, and is mainly applied to the integrated circuit chip manufacturing process. The polishing method is to remove the contacted film by rotating the wafer and utilizing physical friction and chemical gas-liquid combination. The polishing method has lower equipment cost, but is easy to cause the damage and pollution of the reserved film part, and is mainly applied to the wafer manufacturing process below 200 mm. The wet method mainly comprises a film pasting method and a vacuum adsorption method. The film pasting method adopts pure and anti-corrosion plastic films such as PTFE, PE and the like to protect the part of the film to be reserved, and then the film is wholly exposed in a chemical corrosive gas environment or soaked in chemical corrosive liquid to corrode the exposed part. The film pasting method has a plurality of process steps and needs to be completed by using various equipment, wherein the equipment comprises film pasting, wet etching, cleaning, film removing and the like. The vacuum adsorption method uses a vacuum suction head to suck a wafer, the vacuum suction head has the function of sucking the wafer to protect the part of the film to be kept in the vacuum suction head, exposing the part of the film to be removed outside the vacuum suction head, and then soaking the vacuum suction head and the wafer together in a chemical etching solution to etch away the part of the film exposed outside the vacuum suction head. The vacuum adsorption method has simple process steps and lower equipment cost, but is easy to cause the damage and pollution of the reserved film part, and is mainly applied to the wafer manufacturing process below 200 mm.

The chinese patent application No. 201821459515.8 entitled "a semiconductor processing apparatus" discloses an edge processing scheme for semiconductor wafers. For this edge processing scheme, the accuracy of the centering of the semiconductor wafer is important, and if the centering is inaccurate, there is a large error in the result of the edge processing.

In view of this, there is a need for an improved semiconductor processing apparatus that can improve the accuracy of the centering of the semiconductor wafer.

[ invention ]

The invention aims to provide a semiconductor processing device which can flexibly and accurately adjust the position of a wafer and realize the accurate positioning of the wafer.

To achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor processing apparatus comprising: a first chamber portion; a second chamber portion movable between an open position and a closed position with respect to the first chamber portion, wherein a micro chamber is formed between the first chamber portion and the second chamber portion when the second chamber portion is located at the closed position with respect to the first chamber portion, wherein a semiconductor wafer can be accommodated in the micro chamber, and wherein the semiconductor wafer can be taken out or put in when the second chamber portion is located at the open position with respect to the first chamber portion; and the positioning mechanisms are arranged on the first cavity part and/or the second cavity part, each positioning mechanism comprises a positioning column and a driving mechanism for driving the positioning column to move between a positioning position and an initial position, the positioning column is provided with a positioning side surface perpendicular to the surface of the semiconductor wafer, and when the positioning column is positioned at the positioning position, the positioning side surface of the positioning column can position the edge of the semiconductor wafer.

Compared with the prior art, the invention comprises a plurality of positioning mechanisms arranged on the first chamber part or the second chamber part, and the semiconductor wafer can be centrally positioned by adjusting the positioning side surfaces of the positioning columns of the positioning mechanisms.

[ description of the drawings ]

The invention will be more readily understood by reference to the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:

FIG. 1a is a schematic diagram of a semiconductor wafer;

FIG. 1b is a cross-sectional E-E view of FIG. 1 a;

fig. 1c is a cross-sectional view of an outer edge portion of a semiconductor wafer prior to outer edge processing;

FIG. 1d is a cross-sectional view of the outer edge portion of a semiconductor wafer after outer edge processing;

FIG. 2a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a first embodiment;

FIG. 2b is an enlarged schematic view of circle A in FIG. 2 a;

FIG. 3a is a bottom view of a first chamber portion of the semiconductor processing apparatus of FIG. 2 a;

FIG. 3b is a top view of a second chamber portion of the semiconductor processing apparatus of FIG. 2 a;

FIG. 4 is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a second embodiment;

FIG. 5 is an enlarged schematic view of circle B in FIG. 4;

fig. 6a is a bottom view of a first chamber portion of the semiconductor processing apparatus of fig. 4;

fig. 6b is a top view of a second chamber portion of the semiconductor processing apparatus of fig. 4;

fig. 7a is a top view showing a part of the structure of a semiconductor processing apparatus according to a third embodiment of the present invention;

FIG. 7b is a schematic cross-sectional view of FIG. 7a along line H-H;

FIG. 7c is an enlarged schematic view of circle I of FIG. 7 b;

FIG. 7d is a schematic view of the structure of circle I in FIG. 7c in another state, wherein the positioning post is retracted;

FIG. 8 is a schematic view of the structure in the ring I shown in FIG. 7c with the positioning post replaced;

fig. 9 is a schematic view of a positioning column in an embodiment.

[ detailed description ] of the invention

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. The terms "plurality" and "a plurality" as used herein mean two or more. "and/or" in the present invention means "and" or ".

First embodiment:

referring to fig. 2a to 3b, a schematic structural diagram of a semiconductor processing apparatus 100 according to a first embodiment of the present invention is shown, wherein: FIG. 2a is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a first embodiment; FIG. 2b is an enlarged schematic view of circle A in FIG. 2 a; FIG. 3a is a bottom view of a first chamber portion of the semiconductor processing apparatus of FIG. 2 a; fig. 3b is a top view of the second chamber portion of the semiconductor processing apparatus of fig. 2 a.

Referring to fig. 2a to 3b, the semiconductor processing apparatus 100 includes a first chamber portion 110 and a second chamber portion 120. The first chamber portion 110 includes a first chamber plate 119 and a flange 118 extending from a periphery of the first chamber plate 119. The second chamber portion 120 includes a second chamber plate 129 and a flange 128 extending around the periphery of the second chamber plate 129.

The first chamber portion 110 is movable relative to the second chamber portion 120 between an open position and a closed position. It should be noted that the movement of the first chamber portion 110 and the second chamber portion 120 are opposite, the first chamber portion 110 may be fixed so that the second chamber portion 120 is moved relatively, the second chamber portion 120 may be fixed so that the first chamber portion 110 is moved relatively, and both the first chamber portion 110 and the second chamber portion 120 may be moved at the same time, as long as the first chamber portion 110 and the second chamber portion 120 are able to move relatively. With the first chamber portion 110 in a closed position relative to the second chamber portion 120, the flange 118 cooperates with the flange 128 to form a micro chamber 140 between the first chamber plate 118 and the second chamber plate 128, and a semiconductor wafer 400 to be processed can be accommodated within the micro chamber 140 awaiting subsequent processing. The flange 118 is separated from the flange 128 when the first chamber portion 110 is in an open position relative to the second chamber portion 120, and the semiconductor wafer 400 to be processed can be removed from or placed into the micro-chamber 140.

An annular first channel 116 is formed on the side of the first chamber portion 110 facing the micro chamber 140, and a second channel 126 is formed on the side of the second chamber portion 120 facing the micro chamber 140. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is received in the micro-chamber, the first channel 116 and the second channel 126 together form an edge micro-processing space 130, and an outer edge of the semiconductor wafer 400 received in the micro-chamber protrudes into the edge micro-processing space 130.

As shown in fig. 2a to 3b, in this embodiment, the first channel 116 and the second channel 126 are annular channels. When the second chamber portion 120 is located at the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is accommodated in the micro chamber, the wall surface 117 of the first chamber portion 110 located inside the first channel 116 abuts against the first edge surface of the semiconductor wafer 400 to be processed, the wall surface 127 of the second chamber portion 120 located inside the second channel 126 abuts against the second edge surface of the semiconductor wafer 400 to be processed, the first channel 116 and the second channel 126 are surrounded to form a closed, annular outer edge micro processing space 130, and the outer edge portion of the semiconductor wafer 400 to be processed is accommodated in the outer edge micro processing space 130.

Therefore, in the present embodiment, the edge micro-process space 130 can implement selective processing of the entire outer edge portion of the semiconductor wafer 400 to be processed.

Of course, the first channel 116 and the second channel 126 may be configured as arc-shaped channels having an arc less than 360 degrees. At this time, the first channel 116 and the second channel 126 form the closed outer edge micro-processing space 130 having an arc shape with an arc less than 360 degrees. Accordingly, a partial arc of the outer edge of the semiconductor wafer 400 to be processed is accommodated in the edge micro-processing space 130. Thus, the edge micro-processing space 130 only enables selective processing of a portion of the arc segment of the outer edge of the semiconductor wafer 400 to be processed at this time.

The first chamber part 110 has at least two edge processing through holes 112 penetrating the first chamber part 110 from the outside to communicate with the edge micro-processing space 130, wherein: at least one edge-treated through-hole serves as a fluid inlet and at least one edge-treated through-hole serves as a fluid outlet. In this embodiment, 4 edge processing through holes are provided. Of course, an edge processing through hole communicating with the edge micro-processing space 130 may be provided in the second chamber 120.

In use, a processing fluid can enter the edge micro-processing space 130 through one edge processing through-hole 112, the fluid entering the edge micro-processing space 130 can flow in the edge micro-processing space 130, at this time, the processing fluid can contact and process the outer edge portion of the semiconductor wafer 400 to be processed contained in the edge micro-processing space 130, and the fluid processed by the semiconductor wafer 400 to be processed can flow out through another edge processing through-hole 112 or flow out through an edge processing through-hole provided on the second chamber portion 120 and communicating with the edge micro-processing space 130. During processing, processing fluid can be introduced into the edge micro-processing space 130 through an edge processing through-hole 112 continuously or at intervals, and the fluid in the edge micro-processing space 130 can flow during processing, so that the processing speed can be increased.

Of course, the treatment may be etching treatment of the outer edge of the semiconductor wafer 400 to remove the thin film layer of the outer edge portion of the semiconductor wafer 400, selective cleaning of only the outer edge of the semiconductor wafer 400, or the like.

Taking as an example the etching removal of the thin film layer at the outer edge portion of the semiconductor wafer 400 to be processed. Referring to fig. 1a to 1d and 2a to 3b in combination, when it is required to etch away the thin film layers of the first and second sides of the outer edge of the semiconductor wafer 400 to be processed. Only the corresponding processing fluid having an etching effect on the thin film layer is introduced into the edge micro-processing space 130 through one edge processing through hole 112, and the processing fluid flows in the edge micro-processing space 130 and directly contacts the outer edge portion of the semiconductor wafer 400 to be processed. The processing fluid flows along the edge of the semiconductor wafer 400 to be processed, and chemically or physically reacts with the wafer surface of the wafer to be processed which is accommodated in the edge micro-processing space, so that the first edge surface, the second edge surface and the thin film layer 402 on the bevel edge of the semiconductor wafer 400 to be processed are continuously etched away. After the process is completed, as shown in fig. 1d, the thin film layer 402 of the portion of the outer edge of the semiconductor wafer 400 accommodated in the edge micro-process space 130 is etched away, and the first edge surface, the second edge surface and the outer end bevel edge of the substrate layer 401 of the outer edge of the semiconductor wafer 400 are exposed. The fluid processed by the semiconductor wafer 400 is flowed out through other edge processing vias.

It can be seen that, based on the edge micro-processing space 130, the semiconductor processing apparatus 100 in this embodiment consumes only a small amount of processing fluid to achieve selective etching treatment on the outer edge of one piece of the semiconductor wafer 400 to be processed, which greatly reduces the processing cost and the amount of production waste liquid. In addition, the semiconductor processing apparatus 100 in the present embodiment has the remarkable advantages of simple structure, convenient use, and low requirement on the operation skills of operators, as compared with the dry process apparatus in the related art.

It can be seen that the semiconductor processing apparatus 100 provided in this embodiment can implement selective processing on the outer edge of the semiconductor wafer 400 to be processed. In addition, by controlling the flow rate of the processing fluid within the semiconductor wafer 400 to be processed, the amount of processing fluid can be saved while ensuring the processing effect. With continued reference to fig. 2 a-2 b, in the present embodiment, the first chamber portion 110 further has a first recess 115 formed on an inner wall surface of the first chamber portion 110 facing the micro chamber, the first recess being located inside the first channel 116, and the second chamber portion 120 further has a second recess 125 formed on an inner wall surface of the second chamber portion 120 facing the micro chamber, the second recess being located inside the second channel 126. The first recess 115 and the second recess 125 are also annular. When the second chamber portion 120 is located at the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 to be processed is accommodated in the micro-chamber, a partial area of the second edge surface of the semiconductor wafer 400 to be processed covers the top of the second recess 125 to form a second inner micro-space, a partial area of the first edge surface of the semiconductor wafer 400 to be processed covers the top of the first recess 115 to form a first inner micro-space, and the first inner micro-space and the second inner micro-space are located inside the edge micro-processing space 130.

Correspondingly, the first chamber portion 110 has a first inner processing through hole communicating with the first recess portion 115, and the second chamber portion 120 has a second inner processing through hole communicating with the second recess portion 125. When the edge of the semiconductor wafer 400 is etched using the edge micro-process space 130, a liquid or gas, such as water or nitrogen, may be introduced into the first recess 115 and the second recess 125, that is, into the first inner micro-space and the second inner micro-space, to prevent the liquid in the edge micro-process space 130 from penetrating inward.

Likewise, the first recess 115 and the second recess 125 may be arc-shaped.

With continued reference to fig. 2a to 2b, in the present embodiment, when the second chamber portion 120 and the first chamber portion 110 are in the closed position, the micro chamber 140 is further formed in the middle thereof, the second chamber portion 120 has a middle processing through hole 123 communicating with the micro chamber 140, and the first chamber portion 110 has a middle processing through hole 113 communicating with the micro chamber 140.

Referring to fig. 2b, the first chamber portion 110 has a sealing engagement portion 210 thereon located outside the first channel 116, and the second chamber portion 120 has an engagement groove 122 thereon corresponding to the sealing engagement portion 210. The sealing joint 210 includes a guide surface 211 at the distal end and an inner side surface 212 at the inner side. When the second chamber portion 120 is located at the closed position with respect to the first chamber portion 110, the tip end of the seal engaging portion 210 protrudes into the engaging groove 122, the tip end portion of the inner side surface 212 thereof is in seal engagement with the groove wall of the engaging groove 122, and the upper end portion of the inner side surface 212 thereof forms the outer side surface of the outer-edge micro-processing space 130. Further, the sealing surface of the distal end portion of the inner side surface 212 of the seal joint 210 and the groove wall of the joint groove 122 is located below the outer edge micro processing space 130 and perpendicular to the extending direction of the semiconductor wafer 400, and this arrangement makes it possible to make the wall surface 117 of the first chamber portion 110 located inside the first groove 116 abut against the first edge surface of the semiconductor wafer 400 to be processed more closely, and the wall surface 127 of the second chamber portion 120 located inside the second groove 126 abuts against the second edge surface of the semiconductor wafer 400 to be processed more closely, avoiding the penetration of the etching liquid inward.

In the embodiment of fig. 2b, the inner side surface 212 of the sealing joint 210 may effect centering of the semiconductor wafer 400 during closing of the second chamber part 120 with respect to the first chamber part 110, i.e. if the center of the semiconductor wafer 400 when placed deviates from the desired center, the inner edge surface 212 of the sealing joint 210 may also be corrected to the desired center by pressing against the semiconductor wafer 140. In one example, when edge processing is performed, it is required that the center deviation of the semiconductor wafer 400 does not exceed 0.2mm, and in this way, the center deviation can be adjusted to within 0.1 mm. The guide surface 211 may guide the sealing engagement portion 210 into the engagement groove 122 when the first and second chamber portions 110 and 120 are closed. The sealing engagement portion 210 may be caught in the engagement groove 122.

Referring to fig. 2a, the first chamber portion 110 includes a chamber locating slot 114 and the second chamber portion 120 includes a chamber locating feature 124 that enables the first chamber portion 110 and the second chamber portion 120 to be properly located when closed. During the closing of the first and second chamber portions 110, 120, the chamber positioning means 124 is first in a positioning engagement with the chamber positioning groove 114 to achieve an initial positioning, and then the end of the sealing engagement portion 210 protrudes into the engagement recess 122.

In one embodiment, the silicon oxide wafer edge etching process performed using the semiconductor processing apparatus 100 of the present invention may include a closed chamber, an HF acid etch, a DIW rinse, an IPA rinse, a nitrogen gas dry, and an open chamber. The specific processes in which the HF acid etch, DIW (deionized water) rinse, and IPA (isopropyl alcohol) rinse are all operated with reference to the above-described procedure. In particular, during the HF acid etching, a liquid or gas, such as water or nitrogen, may be introduced into the first recess 115 and the second recess 125 to prevent the liquid in the edge micro-process space 130 from penetrating inward.

Second embodiment

Referring to fig. 4 to 6b, a schematic structural diagram of a semiconductor processing apparatus 200 according to a second embodiment of the present invention is shown, wherein: FIG. 4 is a schematic cross-sectional view of a semiconductor processing apparatus of the present invention in a first embodiment; FIG. 5 is an enlarged schematic view of circle B in FIG. 4; fig. 6a is a bottom view of a first chamber portion of the semiconductor processing apparatus of fig. 4; fig. 6b is a top view of a second chamber portion of the semiconductor processing apparatus of fig. 4.

The semiconductor processing apparatus 200 in the second embodiment is largely identical in structure to the semiconductor processing apparatus 100 in the first embodiment, and therefore identical parts thereof are denoted by the same reference numerals, and the difference therebetween is mainly that: the seal joint 310 of the semiconductor processing apparatus 200 and the seal joint 210 of the semiconductor processing apparatus 100 are somewhat different in structure.

As shown in fig. 5, the first chamber portion 110 has the seal engaging portion 310 located outside the first channel 116, and the second chamber portion 120 has the engaging groove 122 corresponding to the seal engaging portion 210.

The seal joint 310 includes a guide surface 311 at the distal end, an inner side surface 312 at the inner side upper end, and a projection 313 at the inner side distal end. When the second chamber portion 120 is located at the closed position relative to the first chamber portion 110, the tip of the seal engaging portion 310 protrudes into the engaging groove 122, the projection 313 thereof is in sealing engagement with the groove wall of the engaging groove 122, and the inner side surface 312 thereof forms the outer side surface of the outer-edge micro-processing space 130. The inner side surface 312 is spaced a distance from the outer edge of the semiconductor wafer 400.

The sealing surface formed by the protrusion 313 of the sealing joint 310 and the groove wall of the joint groove 122 is located below the outer edge micro-processing space 130 and perpendicular to the extending direction of the semiconductor wafer 400, and this arrangement can make the wall surface 117 of the first chamber portion 110 located inside the first groove 116 abut against the first side surface of the semiconductor wafer 400 to be processed more tightly, and the wall surface 127 of the second chamber portion 120 located inside the second groove 126 abuts against the second side surface of the semiconductor wafer 400 to be processed more tightly, so that the etching liquid is prevented from penetrating inward.

In the embodiment of fig. 2b, the bump 313 of the sealing joint 310 may achieve a centering of the semiconductor wafer 140 during closing of the second chamber part 120 with respect to the first chamber part 110, i.e. if the center of the semiconductor wafer 140 is offset from the desired center when placed, the bump 313 of the sealing joint 310 may also be corrected to the desired center by pressing against the semiconductor wafer 140.

There is still a distance between the inner side surface 312 and the outer edge of the semiconductor wafer 400. Such that the semiconductor wafer 400 may not be easily pinched by the seal joint 310 when the second chamber portion 120 is disengaged from the first chamber portion 110.

In another embodiment, the bump 313 may not be used to center the semiconductor wafer 400, i.e., the bump 313 does not contact the edge of the semiconductor wafer 400. While the centering of the semiconductor wafer 400 may be achieved with the wall edges of the first channel 116.

Third embodiment

Fig. 7a is a top view showing a part of the structure of a semiconductor processing apparatus according to a third embodiment of the present invention. FIG. 7b is a schematic cross-sectional view of FIG. 7a along line H-H; fig. 7c is an enlarged schematic view of circle I in fig. 7 b. FIG. 7d is a schematic view of the structure of circle I in FIG. 7c in another state, wherein the positioning post is retracted; FIG. 8 is a schematic view of the structure in the ring I shown in FIG. 7c with the positioning post replaced; fig. 9 is a schematic view of a positioning column in an embodiment.

The semiconductor processing apparatus also includes a first chamber section and a second chamber section 120. The second chamber portion 120 is movable relative to the first chamber portion between an open position in which a micro chamber is formed between the first chamber portion and the second chamber portion, and a closed position in which the semiconductor wafer 400 can be received and removed or placed in the second chamber portion relative to the first chamber portion. For simplicity, in fig. 7a-7c, only the second chamber portion 120 and the semiconductor wafer 400 are shown, and the first chamber portion is not shown. The structure of the first chamber portion may be referred to as the above-mentioned structure of the first chamber portion or may be adaptively modified.

As shown in fig. 7a-7c, the semiconductor processing apparatus in the third embodiment is different from the semiconductor processing apparatus in the previous two embodiments in that: which includes a plurality of positioning mechanisms 600 mounted on the second chamber portion. Each positioning mechanism 600 includes a positioning post 610 and a driving mechanism that drives the positioning post 610 between a positioning position (the position of the positioning post 610 shown in fig. 7 c) and an initial position (the position of the positioning post 610 shown in fig. 7 d). The positioning column 610 has a positioning side 6121 perpendicular to a surface of the semiconductor wafer 400 (e.g., an upper surface or a lower surface of the semiconductor wafer 400), and the positioning side 6121 of the positioning column 610 is capable of positioning an edge of the semiconductor wafer when the positioning column 610 is located at the positioning position.

The semiconductor wafer 400 is centered by the cooperation of the positioning sides 6121 of the positioning posts of the plurality of positioning mechanisms 600. Four positioning mechanisms 600 are shown in fig. 7a, but in other embodiments, three, five or more may be used. Specifically, each positioning structure 600 abuts against an edge of the semiconductor wafer 400, so that a central axis of the semiconductor wafer 400 is aligned with a central axis of a supporting region of the second chamber 120 supporting the semiconductor wafer, that is, the central positioning of the semiconductor wafer 400 is achieved.

In one embodiment, the driving mechanism drives the movement of the positioning column 610 by air pressure, when the positioning column 610 is located at the positioning position, the positioning column 610 is moved to the initial position by decreasing the air pressure, and when the positioning column 610 is located at the initial position, the positioning column 610 is moved to the positioning position by increasing the air pressure.

As shown in fig. 7a-7c, the first chamber portion 120 is provided with a plurality of positioning through holes, and each positioning mechanism is mounted in a corresponding positioning through hole. Each positioning mechanism 600 further includes an air tube connector 630 mounted at an outer end of the positioning through hole, and a sleeve 620 having a through hole mounted in the positioning through hole, the outer end of the air tube connector 630 being connected to an air tube (not shown), and the inner end of the air tube connector 630 being spaced apart from the sleeve 620 by a predetermined distance. As shown in fig. 9 and 7c, the positioning post 610 includes a guide rod 611, a positioning head 612 located at one end of the guide rod 611, and a limiting end 613 located at the other end of the guide rod 611, the positioning side of the positioning post 610 is an outer side 6121 of the positioning head 612, wherein the guide rod 611 of the positioning post 610 is slidably disposed in the inner hole of the sleeve 620, and the limiting end 613 of the positioning post is defined to move between the sleeve 620 and the tracheal joint 630.

As shown in fig. 7d, when the positioning column 610 is in the initial position, the limiting end 613 of the positioning column 710 contacts the inner end of the air pipe joint 630, and the positioning head 612 of the positioning column 610 is retracted, so that the positioning side 6121 of the positioning head 612 is no longer at the same height as the edge of the semiconductor wafer 400, and at this time, the positioning head 612 no longer positions the edge of the semiconductor wafer 400.

As shown in fig. 7c, when the positioning column 610 is located at the positioning position, the limiting end 613 of the positioning column 610 contacts with one end of the sleeve 620, and the positioning head 610 of the positioning column 610 extends out, so that the positioning side surface of the positioning head 612 is located at the same height as the semiconductor wafer 400, and further, the positioning side surface 6121 of the positioning head 612 can position the edge of the semiconductor wafer 400. At this time, the semiconductor wafer 400 is centered by the mutual engagement of the positioning sides 6121 of the positioning posts of the plurality of positioning mechanisms 600.

In one embodiment, the limiting end 613, the guide rod 611 and the positioning head 612 are cylindrical, the limiting end 613 has an outer diameter greater than an inner diameter of the inner bore of the sleeve 620, and the positioning head 612 has an outer diameter less than an outer diameter of the guide rod 611 of the positioning post 610. When the positioning column 610 is located at the initial position, the limiting end 613 of the positioning column 610 is tightly matched with the inner end of the air pipe joint 630 to prevent air leakage, and at this time, the air pressure difference drives the positioning column 610 to move from the initial position to the positioning position by increasing the air pressure in the air pipe joint 630. When the positioning column 610 is located at the positioning position, the limiting end 613 of the positioning column 610 is tightly matched with one end of the sleeve 620 to prevent air leakage, and at this time, the air pressure difference drives the positioning column 610 to move from the positioning position to the initial position by reducing the air pressure in the air pipe joint 630.

As shown in fig. 7c and 7d and fig. 9, the positioning column 610 further includes a guide head 614 at the end of the positioning head 612, the guide head 614 having an inclined guide surface that guides the edge of the semiconductor wafer 400 when the positioning column 610 moves from the initial position to the positioning position.

In another embodiment, a plurality of positioning mechanisms 600 may be disposed on the first chamber portion, and the principle thereof is the same, which will not be described herein. Of course, the positioning mechanism 600 may be disposed on both the first chamber portion and the second chamber portion.

However, most materials have a certain temperature expansion coefficient. The semiconductor wafer edge processing device manufactured by adopting the material with higher temperature expansion coefficient can cause the accurate center positioning of the wafer when the semiconductor wafer edge processing device is moved to another using place due to the difference between the manufacturing temperature and the using temperature and the temperature difference change in the transportation process or the change of other unknown factors, and the device is required to be subjected to very complex and high-precision re-modification, so that great problems are brought to popularization and application of the semiconductor wafer edge processing device. In addition, in order to enable the semiconductor wafer to be precisely centered, it is also necessary to improve the processing accuracy of the lower chamber and the upper chamber, increasing the manufacturing cost.

In order to solve this problem, the positioning column 610 of each positioning mechanism 600 in the present invention can be replaced, and the distance between the positioning side 6121 of the positioning column 610 and the central axis S1 of the positioning column 610 before and after replacement may be different or the same. In one example, the outer diameter of the positioning head 612 shown in fig. 8 is smaller than the outer diameter of the positioning head 612 shown in fig. 7c, i.e. the distance between the positioning side 6121 of the positioning post 610 and the central axis S1 of the positioning post 610 shown in fig. 8 is smaller than the distance between the positioning side 6121 of the positioning post 610 and the central axis S1 of the positioning post 610 shown in fig. 7 c. Thus, even if the positioning accuracy of the positioning mechanism is not satisfactory due to various reasons such as processing accuracy, expansion with heat, and contraction with cold, the accurate center positioning of the semiconductor wafer can be achieved by selecting the positioning column 610 having the appropriate spacing distance, or by selecting the positioning column 610 having the positioning head 612 having the appropriate outer diameter.

In this embodiment, the related structure of the positioning mechanism 600 is mainly described, and the semiconductor processing apparatus in the first embodiment and the second embodiment may also use the positioning mechanism 600 to perform the centering of the semiconductor wafer 400, so long as a plurality of positioning mechanisms 600 are disposed at different positions, the principle of centering will not be repeated.

In the embodiment of the present invention, the semiconductor processing apparatus is used for performing edge processing, however, it will be understood by those skilled in the art that the semiconductor processing apparatus may not perform edge processing, and may not provide related structures such as an edge micro-processing space, and may process the entire surface of the semiconductor wafer.

By the positioning mechanism 600 in the present invention, the accuracy of the center positioning of the semiconductor wafer 400 is improved, and in addition, the center positioning effect can be readjusted, so that the processing accuracy requirement is greatly reduced. Meanwhile, the influence of temperature or other position factors on the center positioning effect is overcome.

The foregoing description has fully disclosed specific embodiments of this invention. It should be noted that any modifications to the specific embodiments of the invention may be made by those skilled in the art without departing from the scope of the invention as defined in the appended claims. Accordingly, the scope of the claims of the present invention is not limited to the specific embodiments.

Claims

1. A semiconductor processing apparatus, comprising:

a first chamber portion;

a second chamber portion movable between an open position and a closed position with respect to the first chamber portion, wherein a micro chamber is formed between the first chamber portion and the second chamber portion when the second chamber portion is located at the closed position with respect to the first chamber portion, wherein a semiconductor wafer can be accommodated in the micro chamber, and wherein the semiconductor wafer can be taken out or put in when the second chamber portion is located at the open position with respect to the first chamber portion;

and the positioning mechanisms are arranged on the first cavity part and/or the second cavity part, each positioning mechanism comprises a positioning column and a driving mechanism for driving the positioning column to move between a positioning position and an initial position, the positioning column is provided with a positioning side surface perpendicular to the surface of the semiconductor wafer, and when the positioning column is positioned at the positioning position, the positioning side surface of the positioning column can position the edge of the semiconductor wafer.

2. The semiconductor processing apparatus according to claim 1, wherein the driving mechanism drives the movement of the positioning column by air pressure, the positioning column is moved to the initial position by decreasing the air pressure when the positioning column is located at the positioning position, the positioning column is moved to the positioning position by increasing the air pressure when the positioning column is located at the initial position,

and the semiconductor wafer is centrally positioned through the mutual matching of the positioning side surfaces of the positioning columns of the positioning mechanisms.

3. A semiconductor processing apparatus according to claim 2, wherein the first chamber portion and/or the second chamber portion is provided with a plurality of positioning through holes, each positioning mechanism is mounted in a corresponding positioning through hole,

each positioning mechanism also comprises an air pipe joint arranged at the outer end of the positioning through hole and a sleeve pipe arranged in the positioning through hole and provided with a penetrating inner hole, the outer end of the air pipe joint is connected with an air pipe, the inner end of the air pipe joint is separated from the sleeve pipe by a preset distance,

the positioning column comprises a guide rod, a positioning head part positioned at one end of the guide rod and a limiting end part positioned at the other end of the guide rod, the positioning side surface of the positioning column is the outer side surface of the positioning head part, the guide rod of the positioning column is arranged in the inner hole of the sleeve in a sliding way, the limiting end part of the positioning column is limited between the sleeve and the tracheal joint to move,

when the locating column is located the initial position, spacing tip of locating column with the inner contact of tracheal joint, the location head of locating column is retracted, when the locating column is located the locating position, spacing tip of locating column with sheathed tube one end contact, the location head of locating column stretches out for the location side of location head with semiconductor wafer is located same height, and then makes the location side of location head can be right the edge of semiconductor wafer is fixed a position.

4. The semiconductor processing apparatus of claim 3, wherein the spacing end, the guide rod and the positioning head are cylindrical, the outer diameter of the spacing end is larger than the inner diameter of the inner bore of the sleeve, the outer diameter of the positioning head is smaller than the outer diameter of the guide rod of the positioning column,

when the positioning column is located at the initial position, the limiting end of the positioning column is tightly matched with the inner end of the air pipe joint to prevent air leakage, and when the positioning column is located at the positioning position, the limiting end of the positioning column is tightly matched with one end of the sleeve to prevent air leakage.

5. The semiconductor processing apparatus of claim 2, wherein the positioning column further comprises a guide head at an end of the positioning head, the guide head having an inclined guide surface that guides an edge of the semiconductor wafer as the positioning column moves from an initial position to a positioning position.

6. The semiconductor processing apparatus of claim 1, wherein the positioning columns of each positioning mechanism can be replaced with different or the same spacing distances between the positioning sides of the positioning columns and the central axes of the positioning columns before and after replacement, and accurate centering of the semiconductor wafer is achieved by selecting the positioning columns having the appropriate spacing distances.

7. The semiconductor processing apparatus according to any one of claims 1 to 6, wherein,

the first chamber part is provided with a first channel, the second chamber part is provided with a second channel, when the second chamber part is positioned at the closed position relative to the first chamber part and the micro chamber is internally provided with a semiconductor wafer, the first channel and the second channel are communicated and form an edge micro-processing space together with the edge of the semiconductor wafer, the outer edge of the semiconductor wafer accommodated in the micro chamber stretches into the edge micro-processing space, the edge micro-processing space is communicated with the outside through an edge processing through hole, fluid enters or flows out of the edge micro-processing space through the edge processing through hole,

the first chamber part is provided with a sealing joint part positioned outside the first channel, the second chamber part is provided with an joint groove corresponding to the sealing joint part,

the first edge surface, the second edge surface, and the outer end bevel surface of the outer edge of the semiconductor wafer are exposed to the edge micro-processing space, one or more of the edge processing through holes serves as a fluid inlet, one or more of the edge processing through holes serves as a fluid outlet,

the edge micro-processing space is annular or arc-shaped, the outer edge of the semiconductor wafer stretches into the edge micro-processing space, and the edge micro-processing space is a closed space and is communicated with the outside through an edge processing through hole;

the inner sidewall portion top surface of the first channel abuts against a first edge surface of the semiconductor wafer adjacent the first chamber portion, and the inner sidewall portion top surface of the second channel abuts against a second edge surface of the semiconductor wafer adjacent the second chamber portion.

8. The semiconductor processing apparatus according to claim 7, wherein the first chamber portion further has a first recess formed in an inner wall surface of the first chamber portion facing the micro chamber, the first recess being located inside the first channel, the second chamber portion further has a second recess formed in an inner wall surface of the second chamber portion facing the micro chamber, the second recess being located inside the second channel, a partial region of a second edge surface of the semiconductor wafer covering a top of the second recess to form a second inner micro-space, a partial region of a first edge surface of the semiconductor wafer covering a top of the first recess to form a first inner micro-space, the first inner micro-space and the second inner micro-space being located inside the edge micro-processing space, the first chamber portion having a first recess surface communicating with a second through-hole communicating with the second chamber portion when the second chamber portion is located at the closed position with respect to the first chamber portion,

the first concave part and the second concave part are annular or arc-shaped, and when the edge of the semiconductor wafer is corroded by utilizing the edge micro-processing space, liquid or gas is introduced into the first concave part and the second concave part so as to prevent the liquid in the edge micro-processing space from penetrating inwards.

9. The semiconductor processing apparatus according to claim 7, wherein the seal engaging portion includes an inner edge surface located on an inner side, a tip end of the seal engaging portion extending into the engaging recess when the second chamber portion is located at the closed position with respect to the first chamber portion, a tip end portion of the inner edge surface thereof being in sealing engagement with a wall of the engaging recess, and an upper end portion of the inner edge surface thereof forming an outer side face of the outer edge micro-processing space.

10. The semiconductor processing apparatus according to claim 9, wherein a sealing surface of a distal end portion of an inner edge surface of the seal joint and a groove wall of the joint groove is located below the outer edge micro-processing space, and the sealing surface is perpendicular to an extending direction of the semiconductor wafer.