CN117059151A - PUF circuit and chip based on random breakdown of reverser and application method - Google Patents

Abstract

The invention discloses a PUF circuit based on random breakdown of an inverter, a chip and an application method. The invention aims to realize a simple high-stability on-off type PUF circuit which is based on random fusing of NMOS (N-channel metal oxide semiconductor) tubes or PMOS (P-channel metal oxide semiconductor) tubes in an inverter, is compatible with a standard CMOS (complementary metal oxide semiconductor) process and has low cost, avoid the use of transistors with special structures and improve the stability of a PUF key after both transistors are broken down.

Description

PUF circuit and chip based on random breakdown of reverser and application method

Technical Field

The invention relates to a secure chip key generation technology in the field of chip security, in particular to a Physical Unclonable Function (PUF) circuit based on random breakdown of an inverter, a chip and an application method.

Background

In a security chip, a physical unclonable function (Physically Unclonable Function, PUF) is typically used to provide the key required by the security chip, the PUF detects random variations in the physical characteristics of the materials that make up the circuit device during the production of the integrated circuit, and even the chip manufacturer and circuit designer cannot copy the exact same key using the same circuit, so that an attacker cannot deduce the original key by reverse engineering. Various PUF structures exist nowadays, such as transient effect ring oscillator type PUFs based on delay units and Arbiter type PUFs, RO type PUFs based on ring oscillator oscillation frequency difference, SRAM PUFs based on minimum data holding voltage detection, PUFs based on resistance random access memories and magnetic random access memories and the like, but the traditional PUFs sample mismatching among characteristics of noise, resistance, oscillation frequency, delay, threshold voltage and the like of devices or circuits, are extremely easy to be influenced by voltage and temperature, and novel memories such as novel magnetic random access memories are incompatible with standard CMOS processes, special treatment is needed, and chip cost is greatly increased. In addition, the manner of post-production trimming of unstable PUF cells using hand voting and error correction codes (Error Correction Code, ECC) also introduces significant digital circuit overhead. Therefore, the conventional PUF has the problems of low stability, high correction hardware cost and the like.

In order to avoid the problem of low stability caused by sampling the analog characteristics of a circuit or a device by using a conventional PUF, an On-Off (On-Off) PUF has been proposed, and a very simple design scheme is to reduce the distance between two metal interconnection lines to be smaller than the minimum distance allowed by a process. The PUF implementation is not affected by temperature and environment, whether the interconnection line is on or off is permanently determined after chip production, has 100% stability, and has very low implementation cost without an additional correction circuit. However, it should be noted that, in this implementation manner, it is difficult to control the bias characteristic of the PUF key, the connection state between the interconnection lines is very easily affected by the distance, the two interconnection lines are largely disjointed if the distance is slightly far, and are largely intersected if the distance is slightly close, it is very difficult to obtain 50% intersection probability, multiple analysis and iteration are required to obtain a proper spacing on the process itself, and the situation of each piece is different, so that convergence under different process conditions is very difficult to design, and is very easily affected by the process.

In order to obtain better bias characteristics, another effective on-off PUF implementation is to obtain a permanently stable PUF key by means of breakdown of an on-chip MOS transistor. In the prior art [ PUF Value Generation Using an Anti-Fuse Memory Array, WO 2017/117663 Al ] proposes a PUF circuit based on random breakdown of two NMOS transistors inside a chip, as shown in fig. 1, NMOS1 and NMOS2 are N-type MOS transistors with smaller size, and NMOS1 and NMOS2 are connected in series. The whole PUF is divided into two phases: (1) PUF key generation phase. At this time, the source and drain of NMOS1 are connected to the source and drain of NMOS2, respectively, and the gates are all connected to external input high voltage signals. When the input high voltage signal is as large as the breakdown voltage of the MOS transistor, since the NMOS1 and NMOS2 dimensions are completely identical to the external environment, the probability of breakdown of both transistors is equal to 50%. After breakdown of the transistor, the PUF enters the key extraction stage. (2) PUF key extraction phase. At this time, the gates of the two transistors are connected to the sampling voltage Vsense and the ground GND, respectively. If the gate-source of the NMOS1 is broken down in the stage (1), the Vsense is directly communicated with the broken down source end, the NMOS2 is cut off, the output point is the Vsense voltage, and the output is logic '1' after comparison by the comparator; on the contrary, if the gate-source of the NMOS2 is broken down in the stage (1), GND is directly connected to the broken down source, and even if the NMOS1 is in a conductive state, the output point is still GND voltage, and after comparison by the comparator, the output point is logic "0".

This implementation enables the acquisition of bias characteristics that are less affected by the process, but at the same time also suffers from the following problems:

(1) The circuit structure needs a special MOS transistor structure, cannot be compatible with a standard CMOS process, and has high realization cost. In order to realize gate-source breakdown when high voltage is applied to the gate of the transistor, avoid breakdown of the gate-drain and the gate-substrate, so as to realize direct connection of Vsense or GND and an output point in a PUF key extraction stage, a special antifuse structure is required to be adopted for the MOS transistor, a thick field oxide layer is required to be added in a range close to a drain end so as to enable a breakdown threshold between the gate and the drain to be higher, avoid the breakdown of the gate-drain from occurring first, and the gate-source breakdown can be ensured to occur before the gate-substrate breakdown by controlling the gate voltage.

(2) Such a structure is prone to unstable units. Although the MOS transistor is either broken down or not broken down, there is no third state, and there is a high stability, the PUF key may be unstable because it may happen that all 2 transistors are broken down. For example, if the high voltage applied to the gate electrode is large in the PUF key generation stage, resulting in breakdown of both NMOS1 and NMOS2, vsense and GND are directly connected together through the breakdown resistor, so that there is first a large leakage, more importantly, the output voltage may be any voltage between Vsense and GND, and at this time, after comparing with VREF, the output value may be "1" or "0", which results in unstable PUF key in this case.

(3) In addition, the circuit structure needs to adopt a comparator and a reference voltage generating circuit, and the circuit cost is high.

To sum up, it can be seen that the existing on-off PUF based on transistor breakdown has the problems of requiring special process, high circuit cost, easily generating unstable units and the like, and a circuit structure with low cost and high stability needs to be found, so that the use of transistors with special structures is avoided, and the stability of PUF keys after both transistors are broken down is improved.

Disclosure of Invention

The invention aims to solve the technical problems: aiming at the problems in the prior art, the invention provides a PUF circuit, a chip and an application method based on random breakdown of an inverter, and aims to realize a simple high-stability on-off PUF circuit which is based on random fusing of an NMOS tube or a PMOS tube in the inverter, is compatible with a standard CMOS process, has low cost, avoids the use of a transistor with a special structure and improves the stability of a PUF key after both transistors are broken down.

In order to solve the technical problems, the invention adopts the following technical scheme:

the utility model provides a PUF circuit based on random breakdown of inverter, includes the breakdown inverter that constitutes by NMOS transistor and PMOS transistor that the size, gate thickness are the same, NMOS transistor and PMOS transistor's grid is common as the input of breakdown inverter, and PMOS transistor and NMOS transistor's drain terminal are as the output of breakdown inverter, and PMOS transistor's source terminal is as the power supply of breakdown inverter, and NMOS transistor's source terminal ground, the input of breakdown inverter is connected with the first high-voltage inverter that is used for selecting between grid high voltage VHV and ground GND, the power supply of breakdown inverter is connected with the second high-voltage inverter that is used for selecting between power VDD and ground GND, and when input terminal input grid high voltage VHV, both NMOS transistor and PMOS transistor take place grid-substrate random breakdown in order to produce the PUF key of random "0" and "1".

Optionally, when the input terminal inputs the gate high voltage VHV, the NMOS transistor and the PMOS transistor both break down randomly, if only the gate-substrate of the NMOS transistor breaks down, the PUF key of the breakdown inverter is "1", if only the gate-substrate of the PMOS transistor breaks down, the PUF key of the breakdown inverter is "0", and if the gate-substrate of the NMOS transistor and the PMOS transistor both break down, the PUF key of the breakdown inverter is "0".

Optionally, the distance between the substrate potential clamping point of the PMOS transistor and the PMOS channel is larger than a set value, so as to prevent leakage current formed between the low potential of the gate and the power supply VDD connected to the PMOS substrate from being smaller than the set value when the gate-substrate of the PMOS transistor is broken down.

Optionally, a third high-voltage inverter for reversely shaping and outputting the PUF key is connected to the output end of the breakdown inverter.

Optionally, the third high voltage inverter is composed of a third NMOS transistor and a third PMOS transistor connected in series between the power supply VDD and the ground GND through source and drain terminals, gates of the third NMOS transistor and the third PMOS transistor are used as input terminals of the third high voltage inverter, drain terminals of the third NMOS transistor and the third PMOS transistor are used as output terminals of the third high voltage inverter, and a width-to-length ratio of the third NMOS transistor is smaller than that of the third PMOS transistor.

Optionally, the first high voltage inverter is composed of a first NMOS transistor and a first PMOS transistor connected in series between the gate high voltage VHV and the ground GND through source and drain terminals, gates of the first NMOS transistor and the first PMOS transistor are connected as an input terminal of the first high voltage inverter to the control signal prog_en, and drain terminals of the first NMOS transistor and the first PMOS transistor are connected as an output terminal of the first high voltage inverter to output the final PUF key PUFOUT.

Optionally, the second high voltage inverter is composed of a second NMOS transistor and a second PMOS transistor connected in series between the power supply VDD and the ground GND through source and drain terminals, gates of the second NMOS transistor and the second PMOS transistor are used as input terminals of the second high voltage inverter to be connected with the control signal prog_en1, and drain terminals of the second NMOS transistor and the second PMOS transistor are used as output terminals of the second high voltage inverter.

In addition, the invention also provides a PUF circuit, which comprises N PUF circuits based on random breakdown of the reverser and used for generating N bits of PUF keys in a combined mode.

In addition, the invention also provides a chip, which comprises a chip body and the PUF circuit arranged in the chip body, wherein the PUF circuit is the PUF circuit.

In addition, the invention also provides an application method of the PUF circuit based on the random breakdown of the reverser, which comprises the following steps:

s101, in a PUF key generation stage, setting a control signal PROG_EN to be 0, connecting an input end of a breakdown inverter to a grid high voltage VHV through a first high voltage inverter, setting a control signal PROG_EN1 to be 1, enabling a power end of the breakdown inverter to be connected to a ground GND through a second high voltage inverter, enabling a grid-substrate random breakdown to occur on both an NMOS transistor and a PMOS transistor to generate PUF keys with random 0 and 1;

s102, in the PUF key extraction stage, setting a control signal PROG_EN to be '1', connecting the input end of the breakdown inverter to the ground GND, setting a control signal PROG_EN1 to be '0', enabling the power supply end of the breakdown inverter to be connected to the power supply VDD through a second high-voltage inverter, and obtaining different PUF keys according to different types of broken MOS tubes in the breakdown inverter: (1) If only the grid electrode-substrate of the NMOS transistor is broken down, enabling the PUF key of the breakdown inverter to be 1, reversing and shaping the PUF key through the third high-voltage inverter, and outputting a final PUF key PUFOUT to be 0; (2) If only the grid electrode-substrate of the PMOS transistor is broken down, enabling the PUF key of the breakdown inverter to be 0, reversing and shaping the PUF key through the third high-voltage inverter, and outputting a final PUF key PUFOUT to be 1; (3) If the grid electrode-substrate of the NMOS transistor and the grid electrode-substrate of the PMOS transistor are broken down, the PUF key of the breakdown inverter is 0, and the final PUF key PUFOUT is 1 after the third high-voltage inverter inverts and shapes;

s103, after the key extraction is finished, the control signal PROG_EN and the control signal PROG_EN1 are both set to 0, so that the input end and the power end of the breakdown inverter are grounded to prevent electric leakage between the power end and the input end when the PMOS transistor in the breakdown inverter is broken down.

Compared with the prior art, the invention has the following advantages: the invention comprises a breakdown inverter composed of NMOS transistors and PMOS transistors with the same size and gate thickness, wherein the gates of the NMOS transistors and the PMOS transistors are commonly used as the input end of the breakdown inverter, the drain ends of the PMOS transistors and the NMOS transistors are used as the output ends of the breakdown inverter, the source ends of the PMOS transistors are used as the power ends of the breakdown inverter, the source ends of the NMOS transistors are grounded, the input ends of the breakdown inverter are connected with a first high-voltage inverter used for selecting between a gate high voltage VHV and a ground GND, the power ends of the breakdown inverter are connected with a second high-voltage inverter used for selecting between a power supply VDD and the ground GND, and when the gate high voltage VHV is input to the input end, the gate-substrate random breakdown occurs to generate PUF keys which are randomly 0 and 1, the invention realizes a simple PUF on-off type circuit which is based on random fusing of the NMOS transistors or the PMOS transistors, is compatible with a standard CMOS (complementary metal oxide semiconductor) technology, has low cost and has no special PUF technology, and is compatible with the standard CMOS technology; the output is a determined "0" or "1", and no intermediate state exists; and reference voltage generation circuit and analog comparator are not needed, the circuit is simple, the realization cost is low, the use of transistors with special structures can be avoided, and the stability of the PUF key after the two transistors are broken down is improved. The invention utilizes the characteristic that the possibility of breakdown of PMOS or NMOS by the gate-liner in the inverter is the same to obtain the PUF key with the probability of 50% of both 0 and 1, and simultaneously, even if the NMOS and the PMOS are broken down, the PUF key can be stably extracted, and the PMOS or the NMOS is the most commonly used CMOS transistor, no special process is needed, no reference voltage and analog comparator are needed, and the invention has the characteristics of low cost and high stability.

Drawings

Fig. 1 is a schematic circuit diagram of a PUF circuit in which two NMOS transistors are randomly broken down in the prior art.

Fig. 2 is a schematic circuit diagram of a PUF circuit based on random breakdown of an inverter in an embodiment of the present invention.

Fig. 3 is a diagram of equivalent devices and circuits when an NMOS transistor is broken down in a PUF circuit according to an embodiment of the present invention.

Fig. 4 is a diagram of equivalent devices and circuits when a PMOS transistor is broken down in a PUF circuit according to an embodiment of the present invention.

Fig. 5 is an equivalent device and a circuit diagram of the PUF circuit according to the embodiment of the invention when both NMOS and PMOS transistors are broken down.

Detailed Description

The present invention is further described below with reference to the drawings and specific examples of embodiments, examples of which are illustrated in the drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below are exemplary and intended to illustrate the present invention and should not be construed as limiting the invention, but any modifications, equivalent substitutions or improvements made within the spirit and principles of the present invention should be included within the scope of the claims of the present invention, which are not described in detail in the present technical solution.

As shown in fig. 2, the PUF circuit based on random breakdown of the inverter in this embodiment includes a breakdown inverter composed of NMOS transistors and PMOS transistors having the same size and gate thickness, gates of the NMOS transistors and PMOS transistors are commonly used as input terminals of the breakdown inverter, drain terminals of the PMOS transistors and NMOS transistors are used as output terminals of the breakdown inverter, source terminals of the PMOS transistors are used as power terminals of the breakdown inverter, source terminals of the NMOS transistors are grounded, an input terminal of the breakdown inverter is connected with a first high voltage inverter for selecting between a gate high voltage VHV and a ground GND, a power terminal of the breakdown inverter is connected with a second high voltage inverter for selecting between the power supply VDD and the ground GND, and when the gate high voltage VHV is input to the input terminal, both the NMOS transistors and the PMOS transistors generate random breakdown of the gate-substrate to generate PUF keys of random "0" and "1". The PUF circuit also includes two phases: in the PUF key generation stage, the channel between the source end of the PMOS transistor and the power supply VDD is disconnected, the NMOS transistor, the PMOS transistor substrate and the source electrode are not at potential, if the grid electrode inputs high voltage, the grid electrode high voltage can lead the grid electrode-substrate between the NMOS transistor and the PMOS transistor to break down as the NMOS transistor and the PMOS transistor adopt common CMOS structures; in the PUF key extraction stage, the input end of the inverter is disconnected from a high-voltage input channel and then connected to the ground GND, and the channel between the source end of the PMOS transistor and the power supply VDD is communicated, and the PUF circuit output determines whether the PUF key value is "1" or "0" according to the breakdown state of the NMOS transistor or the PMOS transistor, so that no intermediate state exists; and a reference voltage generating circuit and an analog comparator are not needed, so that the circuit is simple and the implementation cost is low.

Since the NMOS transistor and the PMOS transistor have the same size and the same gate thickness, the possibility of gate-liner breakdown is the same, and the PUF key obtains different key values according to the breakdown condition of the NMOS transistor and the PMOS transistor. In the PUF key extraction phase, the inverter input is grounded, and the power supply is connected with a normal power supply. If the NMOS transistor gate-liner breaks down, the output will be pulled up to "1" by the PMOS transistor. If the PMOS transistor gate-liner breaks down, the output clamps the PN junction formed by the PMOS transistor substrate-drain to ground, i.e., the output is "0", because the inverter input is grounded at this time. If both the NMOS transistor and the PMOS transistor break down, the characteristics are similar to just PMOS transistor breakdown, the output will still clamp the PN junction formed by the PMOS transistor substrate-drain to ground, i.e., the output is "0". Therefore, in this embodiment, when the gate high voltage VHV is input to the input terminal, the gate-substrate random breakdown occurs in both the NMOS transistor and the PMOS transistor, if only the gate-substrate of the NMOS transistor is broken down, the PUF key of the breakdown inverter is "1", if only the gate-substrate of the PMOS transistor is broken down, the PUF key of the breakdown inverter is "0", and if both the gate-substrates of the NMOS transistor and the PMOS transistor are broken down, the PUF key of the breakdown inverter is "0".

As an alternative implementation manner, in this embodiment, the distance between the substrate potential clamping point of the PMOS transistor and the PMOS channel is larger than a set value, so as to prevent the leakage current formed between the low gate potential and the power supply VDD connected to the PMOS substrate when the gate-substrate of the PMOS transistor is broken down from being smaller than the set value, so as to prevent a large leakage current from being formed between the low gate potential and the VDD connected to the PMOS substrate when the gate-substrate of the PMOS transistor is broken down.

As an alternative embodiment, as shown in fig. 2, the output end of the breakdown inverter in this embodiment is connected to a third high-voltage inverter for inversely shaping and outputting the PUF key.

As shown in fig. 2, in this embodiment, the third high-voltage inverter is composed of a third NMOS transistor and a third PMOS transistor connected in series between the power supply VDD and the ground GND through source and drain terminals, gates of the third NMOS transistor and the third PMOS transistor serve as input terminals of the third high-voltage inverter, drain terminals of the third NMOS transistor and the third PMOS transistor serve as output terminals of the third high-voltage inverter, and a width-to-length ratio of the third NMOS transistor is smaller than that of the third PMOS transistor, so that the output point can still be effectively resolved to "0" when the PMOS has a certain level after breakdown.

As shown in fig. 2, the gate high voltage VHV is connected to the input terminal of the breakdown inverter through a first high voltage inverter, and whether the input terminal is connected or not is determined by a control signal prog_en, if the control signal prog_en is "1", the input terminal of the breakdown inverter is grounded, otherwise, the input terminal of the breakdown inverter is connected to the input high voltage. As shown in fig. 2, the first high voltage inverter in this embodiment is composed of a first NMOS transistor and a first PMOS transistor connected in series between the gate high voltage VHV and the ground GND through source and drain terminals, the gates of the first NMOS transistor and the first PMOS transistor are connected as input terminals of the first high voltage inverter to the control signal prog_en, and the drain terminals of the first NMOS transistor and the first PMOS transistor are connected as output terminals of the first high voltage inverter to output a final PUF key (PUFOUT).

As shown in fig. 2, in this embodiment, the power supply terminal of the breakdown inverter is also connected to the normal power supply VDD or the ground GND through a second high voltage inverter, and whether it is connected to the normal power supply VDD or the ground GND is also determined by a control signal prog_en1, if the control signal prog_en1 is "1", the power supply terminal of the breakdown inverter is grounded, otherwise, the power supply terminal of the breakdown inverter is connected to the normal power supply VDD. As shown in fig. 2, the second high voltage inverter in this embodiment is composed of a second NMOS transistor and a second PMOS transistor connected in series between the power supply VDD and the ground GND through source and drain terminals, gates of the second NMOS transistor and the second PMOS transistor are connected to the control signal prog_en1 as input terminals of the second high voltage inverter, and drain terminals of the second NMOS transistor and the second PMOS transistor are connected to output terminals of the second high voltage inverter. The input control signals PROG_EN and PROG_EN1 of the two high-voltage inverters are 0 after the PUF key is read, so that the input end and the power end of the breakdown inverter are grounded, and electric leakage between the power end and the input end is prevented when the PMOS is broken down.

In addition, the embodiment also provides a PUF circuit, which comprises N PUF circuits based on random breakdown of the reverser and used for generating an N-bit PUF key in a combined mode. The embodiment also provides a chip, which comprises a chip body and a PUF circuit arranged in the chip body, wherein the PUF circuit is the PUF circuit.

In addition, the embodiment also provides an application method of the PUF circuit based on the random breakdown of the inverter, which comprises the following steps:

s101, in a PUF key generation stage, setting a control signal PROG_EN to be 0, connecting an input end of a breakdown inverter to a grid high voltage VHV through a first high voltage inverter, setting a control signal PROG_EN1 to be 1, enabling a power end of the breakdown inverter to be connected to a ground GND through a second high voltage inverter, enabling a grid-substrate random breakdown to occur on both an NMOS transistor and a PMOS transistor to generate PUF keys with random 0 and 1;

s102, in the PUF key extraction stage, setting a control signal PROG_EN to be '1', connecting the input end of the breakdown inverter to the ground GND, setting a control signal PROG_EN1 to be '0', enabling the power supply end of the breakdown inverter to be connected to the power supply VDD through a second high-voltage inverter, and obtaining different PUF keys according to different types of broken MOS tubes in the breakdown inverter:

(1) If only the grid electrode-substrate of the NMOS transistor is broken down, enabling the PUF key of the breakdown inverter to be 1, reversing and shaping the PUF key through the third high-voltage inverter, and outputting a final PUF key PUFOUT to be 0; if the NMOS breaks down in the PUF key generation stage, the equivalent circuit diagram of the NMOS is shown in fig. 3 in the PUF key extraction stage, at the moment, the input grid electrode of the breakdown inverter is connected to GND by the high-voltage inverter 1, because the NMOS grid-substrate breaks down and is also connected with the P-sub substrate of the NMOS, the P-sub substrate is grounded, therefore, the NMOS has no influence on a circuit when broken down, the output is pulled up to the power supply VDD by the PMOS tube with the grounded grid electrode, the output of the breakdown inverter is 1, and the final PUF output is 0 after passing through the third high-voltage inverter;

(2) If only the grid electrode-substrate of the PMOS transistor is broken down, enabling the PUF key of the breakdown inverter to be 0, reversing and shaping the PUF key through the third high-voltage inverter, and outputting a final PUF key PUFOUT to be 1; if the PMOS is broken down in the PUF key generation stage, the equivalent circuit diagram of the breakdown inverter is shown in fig. 4, at this time, the input gate of the PUF key extraction stage is still connected to GND, since the PMOS gate-substrate is broken down, the input gate GND is also connected to the N-sub substrate of the PMOS, and since the N-sub is connected to the normal power supply VDD, there is a leakage current between the input gate GND and the normal power supply VDD, but since the substrate potential clamping point of the PMOS is far away from the channel, the N-sub substrate within the transistor range is still determined by the gate GND of the breakdown point, at this time, two PN junctions exist between the output point invut of the breakdown inverter and ground, wherein the positive end of the PN junction formed by the PMOS N-type substrate and the P-type drain terminal is connected to invut, and the negative end of the other PN junction formed by the NMOS P-type substrate and the N-type drain terminal is connected to invut, so that the output point is pulled down to GND through the PN junction formed by the PMOS N-type substrate and the P-type drain terminal. Because the voltage of the PMOS N-sub substrate is the partial voltage of the power supply VDD and the grid GND at this moment, although the clamping point of the power supply VDD is far, the equivalent resistance is larger, so that the N-sub substrate potential of the PMOS is closer to the GND, but in order to avoid logic errors, the aspect ratio of the NMOS in the third high-voltage inverter is designed to be smaller than that of the PMOS, so that the final PUF output is '1', and the output end INVOUT can still be effectively resolved to be '0' when having a certain level;

(3) If the grid electrode-substrate of the NMOS transistor and the grid electrode-substrate of the PMOS transistor are broken down, the PUF key of the breakdown inverter is 0, and the final PUF key PUFOUT is 1 after the third high-voltage inverter inverts and shapes; if both NMOS and PMOS are broken down in the PUF key generation stage, the equivalent circuit diagram is shown in FIG. 5, and the broken down NMOS has no influence on the voltage of the output end, so that the situation is consistent with the situation that the single PMOS gate-substrate is broken down, and the equivalent circuits of the NMOS and the PMOS are similar, at the moment, two PN junctions still exist between the output point of the breakdown inverter and the ground, the output point is pulled down to GND by the PN junctions, and the final PUF output is obtained through the third high-voltage inverter, wherein the final PUF output is 1;

s103, after the key extraction is finished, the control signal PROG_EN and the control signal PROG_EN1 are both set to 0, so that the input end and the power end of the breakdown inverter are grounded to prevent electric leakage between the power end and the input end when the PMOS transistor in the breakdown inverter is broken down.

In summary, the breakdown inverter of the PUF circuit based on random breakdown of the inverter in this embodiment is composed of two NMOS and PMOS transistors with the same size, the gates of which are connected together to input high voltage or GND, the drains are also connected together to serve as the output of the inverter, the source of the NMOS is grounded, and the source of the PMOS is connected to normal supply voltage or GND. When the gate inputs high voltage, the process bias will cause the NMOS or PMOS to break down, or both break down, and the output of the inverter will be pulled up to power from PMOS or pulled down to ground from parasitic PN junction, respectively, to obtain different output keys. In this embodiment, the whole circuit of the PUF circuit based on random breakdown of the inverter is only composed of high-voltage and low-voltage MOS transistors, no special antifuse transistors, reference voltage generation circuits and comparator circuits are needed, the circuit is permanently fixed after one high-voltage breakdown, no matter whether NMOS or PMOS or both are broken down, stable keys are obtained in output, and the application range of the PUF circuit is greatly improved. The PUF circuit based on random breakdown of the inverter does not need an antifuse transistor of a special process, is compatible with a standard CMOS process, outputs a certain '0' or '1', does not have an intermediate state, does not need a reference voltage generating circuit and an analog comparator, is simple in circuit and low in implementation cost.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.

Claims (10)

1. The utility model provides a PUF circuit based on random breakdown of inverter, its characterized in that includes the breakdown inverter that constitutes by the NMOS transistor and the PMOS transistor of size, gate thickness are the same, the grid of NMOS transistor and PMOS transistor is together as the input of breakdown inverter, the drain terminal of PMOS transistor and NMOS transistor is as the output of breakdown inverter, the source terminal of PMOS transistor is as the power of breakdown inverter, the source terminal of NMOS transistor ground connection, the input of breakdown inverter is connected with the first high-voltage inverter that is used for selecting between grid high voltage VHV and ground GND, the power of breakdown inverter is connected with the second high-voltage inverter that is used for selecting between power VDD and ground GND, and when input high-voltage VHV is input to the input, both NMOS transistor and PMOS transistor take place grid-substrate random breakdown in order to produce the PUF key of random "0" and "1".

2. The PUF circuit of claim 1, wherein the PUF key of the punch-through inverter is "1" if only the gate-substrate of the NMOS transistor is broken down, the PUF key of the punch-through inverter is "0" if only the gate-substrate of the PMOS transistor is broken down, and the PUF key of the punch-through inverter is "0" if both the NMOS transistor and the gate-substrate of the PMOS transistor are broken down when the input terminal inputs the gate high voltage VHV.

3. The PUF circuit of claim 1, wherein a substrate potential clamp point of the PMOS transistor is spaced from the PMOS channel by a distance greater than a set value to prevent leakage current formed between a low gate potential of the PMOS transistor and a power supply VDD to which the PMOS substrate is connected when the gate-substrate of the PMOS transistor is broken down from being less than the set value.

4. The PUF circuit based on random breakdown of inverters of claim 1 wherein the output of the breakdown inverter is connected with a third high voltage inverter for inverting the shaping output of the PUF key.

5. The PUF circuit of claim 4, wherein the third high voltage inverter is comprised of a third NMOS transistor and a third PMOS transistor connected in series between the power supply VDD and ground GND through source and drain terminals, gates of the third NMOS transistor and the third PMOS transistor serve as input terminals of the third high voltage inverter, drain terminals of the third NMOS transistor and the third PMOS transistor serve as output terminals of the third high voltage inverter, and a width-to-length ratio of the third NMOS transistor is smaller than that of the third PMOS transistor.

6. The PUF circuit of claim 5, wherein the first high voltage inverter is comprised of a first NMOS transistor and a first PMOS transistor connected in series between a gate high voltage VHV and ground GND through a source terminal and a drain terminal, the gates of the first NMOS transistor and the first PMOS transistor being connected as an input terminal of the first high voltage inverter to a control signal prog_en, the drain terminals of the first NMOS transistor and the first PMOS transistor being an output terminal of the first high voltage inverter to output a final PUF key PUFOUT.

7. The PUF circuit of claim 6, wherein the second high voltage inverter is composed of a second NMOS transistor and a second PMOS transistor connected in series between a power supply VDD and a ground GND through a source terminal and a drain terminal, gates of the second NMOS transistor and the second PMOS transistor are connected as an input terminal of the second high voltage inverter to the control signal prog_en1, and drain terminals of the second NMOS transistor and the second PMOS transistor are connected as an output terminal of the second high voltage inverter.

8. A PUF circuit comprising N PUF circuits according to any one of claims 1 to 7 based on random breakdown of inverters for collectively combining to generate an N-bit PUF key.

9. A chip comprising a chip body and PUF circuitry provided in the chip body, wherein the PUF circuitry is the PUF circuitry of any one of claims 1 to 8.

10. A method of applying the inverter random breakdown based PUF circuit of claim 7, comprising:

s101, in a PUF key generation stage, setting a control signal PROG_EN to be 0, connecting an input end of a breakdown inverter to a grid high voltage VHV through a first high voltage inverter, setting a control signal PROG_EN1 to be 1, enabling a power end of the breakdown inverter to be connected to a ground GND through a second high voltage inverter, enabling a grid-substrate random breakdown to occur on both an NMOS transistor and a PMOS transistor to generate PUF keys with random 0 and 1;

s102, in the PUF key extraction stage, setting a control signal PROG_EN to be '1', connecting the input end of the breakdown inverter to the ground GND, setting a control signal PROG_EN1 to be '0', enabling the power supply end of the breakdown inverter to be connected to the power supply VDD through a second high-voltage inverter, and obtaining different PUF keys according to different types of broken MOS tubes in the breakdown inverter: (1) If only the grid electrode-substrate of the NMOS transistor is broken down, enabling the PUF key of the breakdown inverter to be 1, reversing and shaping the PUF key through the third high-voltage inverter, and outputting a final PUF key PUFOUT to be 0; (2) If only the grid electrode-substrate of the PMOS transistor is broken down, enabling the PUF key of the breakdown inverter to be 0, reversing and shaping the PUF key through the third high-voltage inverter, and outputting a final PUF key PUFOUT to be 1; (3) If the grid electrode-substrate of the NMOS transistor and the grid electrode-substrate of the PMOS transistor are broken down, the PUF key of the breakdown inverter is 0, and the final PUF key PUFOUT is 1 after the third high-voltage inverter inverts and shapes;

s103, after the key extraction is finished, the control signal PROG_EN and the control signal PROG_EN1 are both set to 0, so that the input end and the power end of the breakdown inverter are grounded to prevent electric leakage between the power end and the input end when the PMOS transistor in the breakdown inverter is broken down.