CN117059029A

CN117059029A - Display panel and display device

Info

Publication number: CN117059029A
Application number: CN202311089465.4A
Authority: CN
Inventors: 罗雅琴
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2023-08-25
Filing date: 2023-08-25
Publication date: 2023-11-14

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first reference signal line electrically connected with the initialization transistor, the first reference signal line comprises a first signal line connected with the red sub-pixel, a second signal line connected with the green sub-pixel and a third signal line connected with the blue sub-pixel, and at least two of a first reference voltage on the first signal line, a second reference voltage on the second signal line and a third reference voltage on the third signal line are different. According to the display panel and the display device provided by the embodiment of the invention, the sub-pixels with different colors are supplied with the reference signals through the different first reference signal lines, and the voltage amplitude values of the reference voltages received by the red sub-pixel, the green sub-pixel and the blue sub-pixel can be independently set according to the difference of the luminous characteristics of the red sub-pixel, the green sub-pixel and the blue sub-pixel, so that the luminous brightness of the red sub-pixel, the green sub-pixel and the blue sub-pixel is more uniform, and the display effect is improved.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

Organic Light-Emitting Diode (OLED) display panels have advantages of high visibility, high brightness, and lighter weight, and thus, OLED display panels are also being increasingly used.

However, in the conventional OLED display panel, there is a problem of uneven display brightness, which affects the display effect of the display panel.

Disclosure of Invention

The invention provides a display panel and a display device, which are used for improving the display brightness uniformity of the display panel.

According to an aspect of the present invention, there is provided a display panel including a plurality of sub-pixels and a plurality of reference signal lines;

the sub-pixel comprises a pixel circuit and a light emitting element, the pixel circuit comprises a driving transistor and an initializing transistor, and a first pole of the driving transistor, a first pole of the initializing transistor and an anode of the light emitting element are electrically connected;

the plurality of subpixels include a red subpixel, a green subpixel, and a blue subpixel;

the plurality of reference signal lines include a first reference signal line electrically connected to a second pole of the initialization transistor;

the first reference signal line comprises a first signal line, a second signal line and a third signal line, wherein the first signal line is electrically connected with the initializing transistor of the pixel circuit in the red sub-pixel, the second signal line is electrically connected with the initializing transistor of the pixel circuit in the green sub-pixel, and the third signal line is electrically connected with the initializing transistor of the pixel circuit in the blue sub-pixel;

The first signal line is used for transmitting a first reference voltage, the second signal line is used for transmitting a second reference voltage, and the third signal line is used for transmitting a third reference voltage;

at least two of the first reference voltage, the second reference voltage, and the third reference voltage are different.

According to another aspect of the present invention, there is provided a display device comprising the display panel of the first aspect.

The display panel and the display device provided by the embodiment of the invention are provided with the first reference signal line, the second signal line and the third signal line, wherein the first signal line is connected with the initializing transistor of the pixel circuit in the red sub-pixel, the second signal line is electrically connected with the initializing transistor of the pixel circuit in the green sub-pixel, the third signal line is electrically connected with the initializing transistor of the pixel circuit in the blue sub-pixel, and at least two of the first reference voltage transmitted by the first signal line, the second reference voltage transmitted by the second signal line and the third reference voltage transmitted by the third signal line are different. The sub-pixels with different luminous colors are supplied with reference signals through different first reference signal lines, so that at least two of a first reference voltage received by the red sub-pixel, a second reference voltage received by the green sub-pixel and a third reference voltage received by the blue sub-pixel are different, and accordingly, according to the difference of luminous characteristics of the red sub-pixel, the green sub-pixel and the blue sub-pixel, the voltage amplitudes of the first reference voltage received by the red sub-pixel, the second reference voltage received by the green sub-pixel and the third reference voltage received by the blue sub-pixel are independently set, and the luminous brightness of the red sub-pixel, the green sub-pixel and the blue sub-pixel is more uniform, and the display effect is improved. Meanwhile, the first signal line, the second signal line and the third signal line are respectively connected with the red sub-pixel and the green sub-pixel, and then each first reference signal line is only required to be connected with part of sub-pixels in the same row of sub-pixels, so that the number of the sub-pixels electrically connected with each first reference signal line is reduced, the load connected with each first reference signal line is reduced, the signal voltage drop transmitted on the first reference signal line is reduced, the signal potential transmitted on the first reference signal line is more uniform, and the display brightness uniformity of the display panel is further improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic cross-sectional view of FIG. 1 taken along the direction A-A';

fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a display panel according to the related art;

fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

Fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 11 is a schematic diagram of a partial cross-sectional structure of a pixel circuit according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 13 is a schematic diagram of the bottom reference signal line of FIG. 12;

FIG. 14 is a schematic diagram of a partial cross-sectional structure of another pixel circuit according to an embodiment of the invention;

FIG. 15 is a schematic diagram of a partial cross-sectional structure of a pixel circuit according to another embodiment of the present invention;

FIG. 16 is a schematic diagram of a partial cross-sectional structure of a pixel circuit according to another embodiment of the present invention;

FIG. 17 is a schematic diagram of a partial cross-sectional structure of a pixel circuit according to another embodiment of the present invention;

fig. 18 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 19 is a schematic diagram of the underlying reference signal lines and underlying metal layers of FIG. 18;

FIG. 20 is a schematic diagram of a partial cross-sectional structure of a pixel circuit according to another embodiment of the present invention;

Fig. 21 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural view of a display panel according to an embodiment of the present invention, fig. 2 is a schematic structural view of a cross section along A-A' direction of fig. 1, fig. 3 is a schematic structural view of a pixel circuit according to an embodiment of the present invention, fig. 4 is a schematic structural view of another pixel circuit according to an embodiment of the present invention, and as shown in fig. 1-4, the display panel according to an embodiment of the present invention includes a plurality of sub-pixels 10 and a plurality of reference signal lines Vref, the sub-pixels 10 include a pixel circuit 101 and a light emitting element 102, the pixel circuit 101 includes a driving transistor M3 and an initializing transistor M7, and a first electrode M31 of the driving transistor M3, a first electrode M71 of the initializing transistor M7 and an anode of the light emitting element 102 are electrically connected. The plurality of sub-pixels 10 include a red sub-pixel 10R, a green sub-pixel 10G, and a blue sub-pixel 10B, the plurality of reference signal lines 11 include a first reference signal line Vref1, the first reference signal line Vref1 is electrically connected to a second pole M72 of the initialization transistor M7, the first reference signal line Vref1 includes a first signal line Vref1R, a second signal line Vref1G, and a third signal line Vref1B, the first signal line Vref1R is electrically connected to the initialization transistor M7 of the pixel circuit 101 in the red sub-pixel 10R, the second signal line Vref1G is electrically connected to the initialization transistor M7 of the pixel circuit 101 in the green sub-pixel 10G, and the third signal line Vref1B is electrically connected to the initialization transistor M7 of the pixel circuit 101 in the blue sub-pixel 10B. The first signal line Vref1R is used to transmit a first reference voltage, the second signal line Vref1G is used to transmit a second reference voltage, and the third signal line Vref1B is used to transmit a third reference voltage, at least two of the first reference voltage, the second reference voltage, and the third reference voltage being different.

Specifically, as shown in fig. 1 to 4, the display panel provided in this embodiment may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel, on which a plurality of sub-pixels 10 arranged in an array are disposed, and the sub-pixels 10 may include at least two sub-pixels of different colors, for example, as shown in fig. 1, the sub-pixels 10 may include a red sub-pixel 10R, a green sub-pixel 10G, and a blue sub-pixel 10B, so as to implement color image display.

In fig. 1, only the plurality of sub-pixels 10 are illustrated in a standard RGB arrangement on the display panel, and in other embodiments, the plurality of sub-pixels 10 may be arranged in other arrangements. In addition, the shape of the light emitting region of the sub-pixel 10 includes, but is not limited to, the rectangle shown in fig. 1, and in other embodiments, the shape of the light emitting region of the sub-pixel 10 may be designed according to practical requirements, which is not particularly limited in the embodiments of the present invention.

Further, the sub-pixel 10 includes a pixel circuit 101 and a light emitting element 102, and as illustrated in fig. 2, the light emitting element 102 is exemplified as an organic light emitting diode, and the light emitting element 102 may include an anode 21, a light emitting layer 22 and a cathode 23 which are stacked, and when electrons and holes are respectively injected from the cathode 23 and the anode 21 into the light emitting layer 22, excitons are formed in the light emitting layer 22 and light emitting molecules are excited, so that the light emitting layer 22 emits visible light. In which different colors of visible light can be emitted by providing the light emitting layer 22 with different materials.

It should be noted that, as shown in fig. 2, the light emitting layers 22 of the light emitting elements 102 are separated by the pixel defining layer 24, where the pixel defining layer 24 includes a plurality of openings, at least a portion of the light emitting layers 22 are located in the openings, and the area where the openings of the pixel defining layer 24 are located is the light emitting area of the sub-pixel 10.

With continued reference to fig. 2 and 3, the pixel circuit 101 is electrically connected to the light emitting element 102, and the pixel circuit 101 is configured to transmit a driving current to the light emitting element 102 under the signal of a driving signal line (such as a scanning signal line, a data signal line, a power signal line, and a reference signal line) on the display panel, so as to provide the driving current to the light emitting element 102 to drive the light emitting element 102 to emit light.

Specifically, as shown in fig. 3, the pixel circuit 101 includes a driving transistor M3, the driving transistor M3 and the light emitting element 102 are connected in series between a first power signal line PVDD and a second power signal line PVEE, the first power signal line PVDD is used for transmitting a first power voltage, the second power signal line PVEE is used for transmitting a second power voltage, and the first power voltage is greater than the second power voltage.

The driving transistor M3 may be turned on according to the potential of its gate, and the driving current generated by the turn-on may be used to drive the light emitting element 102 to emit light. It can be understood that the gate potential of the driving transistor M3 is determined by the magnitude of the driving current formed by the on state of the driving transistor M3, so that the light-emitting brightness of the light-emitting element 102 can be adjusted by controlling the gate voltage of the driving transistor M3, thereby controlling the gray scale.

With continued reference to fig. 1-4, the pixel circuit 101 may further include an initialization transistor M7, wherein a gate of the initialization transistor M7 is electrically connected to the first scan signal line S1, a first electrode M71 of the initialization transistor M7 and an anode of the light emitting element 102 are electrically connected to the second node N2, and a second electrode M72 of the initialization transistor M7 is electrically connected to the first reference signal line Vref 1.

In the initialization stage, the first scan signal transmitted on the first scan signal line S1 turns on the initialization transistor M7, the initialization transistor M7 writes the reference voltage on the first reference signal line Vref1 into the anode of the light emitting element 102, resets the anode potential of the light emitting element 102, and can reduce the influence of the anode voltage of the light emitting element 102 of the previous frame on the anode voltage of the light emitting element 102 of the next frame, thereby contributing to improving the display uniformity.

Fig. 5 is a schematic structural diagram of a display panel in the related art, as shown in fig. 5, in which a plurality of sub-pixels 10 'of the display panel in the related art include a red sub-pixel 10R', a green sub-pixel 10G ', and a blue sub-pixel 10B', each of the first reference signal lines Vref1 is connected to a plurality of sub-pixels 10 'in a row, that is, the red sub-pixel 10R', the green sub-pixel 10G ', and the blue sub-pixel 10B' in each row of sub-pixels 10 'each provide a first reference signal by the same first reference signal line Vref1, and then the first reference signals received by the sub-pixels 10' in different light emission colors in the same row are the same.

The inventors have found that, when the light emission characteristics of the sub-pixels 10 'with different light emission colors are different, the same first reference signal is received to cause the light emission brightness of the sub-pixels 10' with different colors to be different, so that the display brightness of the display panel is uneven. In addition, one first reference signal line Vref1 is electrically connected to the sub-pixels 10' of the whole row, so that the load connected to each first reference signal line Vref1 is relatively large, and the voltage drop of the signal transmitted on the first reference signal line Vref1 is relatively large, which causes uneven signal potential transmitted on the first reference signal line Vref1, and further affects display uniformity.

Based on the above technical problems, as shown in fig. 1 to 4, in the embodiment of the present invention, the first reference signal line Vref1 is set to include a first signal line Vref1R, a second signal line Vref1G and a third signal line Vref1B, and the first signal line Vref1R is electrically connected to the pixel circuit 101 of the red subpixel 10R, so as to provide the first reference voltage for the pixel circuit 101 of the red subpixel 10R; the second signal line Vref1G is electrically connected to the pixel circuit 101 of the green sub-pixel 10G, thereby providing a second reference voltage to the pixel circuit 101 of the green sub-pixel 10G; the third signal line Vref1B is electrically connected to the pixel circuit 101 of the blue subpixel 10B, thereby supplying a third reference voltage to the pixel circuit 101 of the blue subpixel 10B.

As shown in fig. 1, in each row of the sub-pixels 10, the sub-pixels 10 having different light emission colors provide reference signals through different first reference signal lines Vref1, so that at least two of the first reference voltage received by the red sub-pixel 10R, the second reference voltage received by the green sub-pixel 10G, and the third reference voltage received by the blue sub-pixel 10B are different, and accordingly, the voltage magnitudes of the first reference voltage received by the red sub-pixel 10R, the second reference voltage received by the green sub-pixel 10G, and the third reference voltage received by the blue sub-pixel 10B can be independently set according to the light emission characteristics of the red sub-pixel 10R, the green sub-pixel 10G, and the blue sub-pixel 10B, so that the light emission brightness of the red sub-pixel 10R, the green sub-pixel 10G, and the blue sub-pixel 10B is more uniform, and the display effect is improved.

Meanwhile, in the same row of sub-pixels 10, the red sub-pixel 10R, the green sub-pixel 10G and the blue sub-pixel 10B are respectively connected with the first signal line Vref1R, the second signal line Vref1G and the third signal line Vref1B, so that each first reference signal line Vref1 only needs to be connected with part of the sub-pixels 10 in the same row of sub-pixels 10, thereby reducing the number of the sub-pixels 10 electrically connected with each first reference signal line Vref1, reducing the load connected with one first reference signal line Vref1, reducing the signal voltage drop transmitted on the first reference signal line Vref1, making the signal potential transmitted on the first reference signal line Vref1 more uniform, and being beneficial to improving the display brightness uniformity of the display panel.

It should be noted that the magnitude relation and the specific voltage magnitudes of the first reference voltage, the second reference voltage and the third reference voltage may be set according to the light emitting characteristics (e.g. the material system of the light emitting layer 22) of the actual red sub-pixel 10R, the green sub-pixel 10G and the blue sub-pixel 10B and the display requirement of the display panel, which are not limited in particular in the embodiments of the present invention.

Illustratively, the inventors have studied to find that the pixel capacitances of the light emitting elements 102 emitting light of different colors have different capacitance values due to the different materials of the light emitting layers 22 of the light emitting elements 102 in the sub-pixels 10 emitting light of different colors. In the light emitting stage, the anode 21 and the cathode 23 of the light emitting element 102 are turned on to charge the pixel capacitor of the light emitting element 102, at this time, the anode potential of the light emitting element 102 gradually increases, and when the pixel capacitor of the light emitting element 102 is full, the voltage across the light emitting element 102 reaches the turn-on voltage, and the light emitting element 102 starts to emit light continuously. The smaller the pixel capacitance of the light emitting element 102, the smaller the voltage difference between the anode and the cathode when the pixel capacitance is full, and the smaller the turn-on voltage; similarly, the larger the pixel capacitance of the light emitting element 102, the larger the voltage difference between the anode and the cathode when the pixel capacitance is full, and the larger the turn-on voltage. It can be understood that the on voltage is the voltage across the pixel capacitor when it is full, and the light emitting element 102 starts to emit light when the voltage across it reaches the on voltage.

Therefore, the light-emitting element 102 with smaller pixel capacitance only needs a shorter time to charge the pixel capacitance of the light-emitting element 102 in the light-emitting stage, so that the voltage across the light-emitting element 102 reaches the turn-on voltage to emit light; the light emitting element 102 with a larger pixel capacitance requires a longer time to charge the pixel capacitance of the light emitting element 102 in the light emitting stage, so that the voltage across the light emitting element reaches the on-voltage to emit light.

Since the pixel capacitor of the light emitting element 102 does not emit light before being fully charged, the shorter the charging time of the pixel capacitor of the light emitting element 102 is, the earlier the light emitting start time of the light emitting element 102 is, and the longer the light emitting element 102 emits light, so that the light emitting efficiency of the light emitting element 102 is higher; similarly, the longer the charge time of the pixel capacitance of the light emitting element 102, the later the light emission start time of the light emitting element 102, and the shorter the light emitting period of the light emitting element 102, so that the light emitting efficiency of the light emitting element 102 is low.

Therefore, the sub-pixels 10 (e.g., the red sub-pixel 10R, the green sub-pixel 10G, and the blue sub-pixel 10B) emitting different colors of light have a difference in the charge time (or the light emission time) of the pixel capacitance in the light emission stage due to the difference in the pixel capacitance of the light emitting element 102, and the light emission efficiency of the sub-pixels 10 emitting different colors of light is changed to have a large difference, which causes a color cast problem.

The inventors further studied and found that, due to the difference between the material of the light emitting layer 22 in the red sub-pixel 10R, the material of the light emitting layer 22 in the green sub-pixel 10G, and the material of the light emitting layer 22 in the blue sub-pixel 10B, the capacitance value of the pixel capacitance of the light emitting element 102 in the green sub-pixel 10G is smaller than the capacitance value of the light emitting layer 22 in the red sub-pixel 10R, and the capacitance value of the light emitting layer 22 in the red sub-pixel 10R is smaller than the capacitance value of the light emitting layer 22 in the blue sub-pixel 10B, so that the on-luminance voltage of the light emitting element 102 in the green sub-pixel 10G is smaller than the on-luminance voltage of the light emitting element 102 in the red sub-pixel 10R, and the on-luminance voltage of the light emitting element 102 in the red sub-pixel 10R is smaller than the on-luminance voltage of the light emitting element 102 in the blue sub-pixel 10B.

Therefore, in the light emitting stage, the pixel capacitor of the green sub-pixel 10G is fully charged first to start light emission, then the pixel capacitor of the red sub-pixel 10R is fully charged to start light emission, and finally the pixel capacitor of the blue sub-pixel 10B is fully charged to start light emission, that is, the charge time of the pixel capacitor in the green sub-pixel 10G is less than the charge time of the pixel capacitor in the red sub-pixel 10R is less than the charge time of the pixel capacitor in the blue sub-pixel 10B, and in the light emitting stage, the light emitting duration of the green sub-pixel 10G is greater than the light emitting duration of the red sub-pixel 10R is greater than the light emitting duration of the blue sub-pixel 10B, which finally results in the light emitting efficiency of the green sub-pixel 10G is greater than the light emitting efficiency of the red sub-pixel 10R is greater than the light emitting efficiency of the blue sub-pixel 10B, resulting in a greenish display screen of the display panel.

Based on the above technical problem, in an alternative embodiment, the third reference voltage > the first reference voltage > the second reference voltage is set, so that before the light-emitting stage, the third reference voltage at the anode of the light-emitting element 102 in the blue sub-pixel 10B is higher, so that the voltage across the light-emitting element 102 in the blue sub-pixel 10B is closer to the on-luminance voltage thereof, and in the light-emitting stage, the charging time of the pixel capacitor in the blue sub-pixel 10B can be shortened, the voltage across the light-emitting element 102 in the blue sub-pixel 10B can reach the on-luminance voltage thereof faster, the time when the blue sub-pixel 10B starts to emit light is advanced, the light-emitting duration of the blue sub-pixel 10B in the light-emitting stage can be prolonged, and the light-emitting efficiency of the blue sub-pixel 10B can be improved. Similarly, the second reference voltage at the anode of the light emitting element 102 in the green sub-pixel 10G is lower, so that the difference between the voltage across the light emitting element 102 in the green sub-pixel 10G and the on-state voltage thereof is larger, and thus, in the light emitting stage, the charging time of the pixel capacitor in the green sub-pixel 10G is prolonged, the voltage across the light emitting element 102 in the green sub-pixel 10G reaches the on-state voltage thereof at a slower speed, and the light emitting time of the green sub-pixel 10G is delayed, so that the light emitting time of the green sub-pixel 10G in the light emitting stage is shortened, and the light emitting efficiency of the green sub-pixel 10G is reduced. Finally, the light-emitting brightness of the blue sub-pixel 10B is improved, the light-emitting brightness of the green sub-pixel 10G is reduced, the problem that the display screen of the display panel is greenish is solved, and the display brightness uniformity of the display panel is improved.

In another possible embodiment, the driving current I generated by the driving transistor M3 may satisfy the following formula:

I＝1/2C _ox μW/L(Vgs-Vth) ²

wherein μ is carrier mobility of the driving transistor M3, W/L is width-to-length ratio of channel of the driving transistor M3, C _ox Vgs is a voltage difference between the gate and the source of the driving transistor M3, and Vth is a threshold voltage of the driving transistor M3, which is a gate oxide capacitance per unit area of the driving transistor M3.

As can be seen from the formula, the magnitude of the driving current I is related to the threshold voltage Vth of the driving transistor M3, and the magnitude of the driving current I determines the light emitting brightness of the light emitting element 102, so the magnitude of the threshold voltage Vth of the driving transistor M3 affects the light emitting brightness of the light emitting element 102.

The inventors have found that the threshold voltage Vth of the driving transistor M3 has a hysteresis effect, wherein the hysteresis effect means that the magnitude of the threshold voltage Vth of the driving transistor M3 varies with the variation of the gate voltage of the driving transistor M3.

However, when the sub-pixel 10 is switched from the black (L0 gray level) to the white (L255 gray level), the gate voltage of the driving transistor M3 is changed from the gate voltage corresponding to the black to the gate voltage corresponding to the white, but the threshold voltage Vth of the driving transistor M3 is changed with delay, so that the threshold voltage Vth of the driving transistor M3 still remains below the threshold voltage Vth corresponding to the gate voltage of the black when the first frame is switched from the black to the white, and the magnitude of the threshold voltage Vth of the driving transistor M3 affects the light-emitting brightness of the light-emitting element 102, so that the threshold voltage Vth of the driving transistor M3 is not changed into the threshold voltage Vth corresponding to the gate voltage of the white in time when the first frame is switched from the black to the white, resulting in that the sub-pixel 10 cannot reach the brightness of the L255 gray level when the first frame is switched from the black to the white, and the sub-pixel 10 has a problem that the brightness is biased compared with the sub-pixel 10 displaying the white in the periphery; in the next frame, the threshold voltage Vth of the driving transistor M3 is switched to the threshold voltage Vth corresponding to the gate voltage of the white screen, and at this time, the sub-pixel 10 can reach the L255 gray scale luminance, and the light emitting luminance is consistent with the sub-pixel 10 displaying the L255 gray scale at the periphery; as is clear from the above, when the sub-pixel 10 is switched from a black screen to a white screen, the luminance is dark for a short time (1 frame), and smear is generated.

Meanwhile, the inventor has further studied and found that, due to the different materials of the light emitting layers of the light emitting elements 102, the brightness attenuation of the sub-pixels 10 with different colors is different when the first frame is switched from the black frame to the white frame, so that the brightness of the sub-pixels 10 with different colors is inconsistent, and the problem of color shift in visual effect exists when the sub-pixels 10 are switched from the black frame to the first frame of the white frame, wherein in an optional usage scenario, the red sub-pixels 10R and the blue sub-pixels 10B are brighter when the first frame is switched from the black frame to the white frame, the green sub-pixels 10G are darker, so that the first frame is relatively purple when the first frame is switched from the black frame to the white frame, the user observes the purple-like smear, and the purple-like smear aggravates the visual effect of the human eyes, and affects the display effect of the display panel.

Based on the above technical problem, in an alternative embodiment, the second reference voltage > the first reference voltage > the third reference voltage is set, and as described above, before the light-emitting stage, the second reference voltage at the anode of the light-emitting element 102 in the green sub-pixel 10G may be made higher, so that the voltage across the light-emitting element 102 in the green sub-pixel 10G is closer to the on-luminance voltage thereof, and in the light-emitting stage, the charging time of the pixel capacitor in the green sub-pixel 10G may be shortened, the voltage across the light-emitting element 102 in the green sub-pixel 10G may reach the on-luminance voltage thereof faster, the time when the green sub-pixel 10G starts to emit light may be advanced, and the light-emitting duration of the green sub-pixel 10G in the light-emitting stage may be prolonged, thereby improving the light-emitting efficiency of the green sub-pixel 10G. Similarly, the first reference voltage at the anode of the light emitting element 102 in the red sub-pixel 10R and the third reference voltage at the anode of the light emitting element 102 in the blue sub-pixel 10B are lower, so that the difference between the voltage across the light emitting element 102 in the red sub-pixel 10R and the blue sub-pixel 10B and the on-luminance voltage thereof is larger, and in the light emitting stage, the charging time of the pixel capacitor in the red sub-pixel 10R and the blue sub-pixel 10B is prolonged, the voltage across the light emitting element 102 in the red sub-pixel 10R and the blue sub-pixel 10B reaches the on-luminance voltage thereof is slower, and the time when the red sub-pixel 10R and the blue sub-pixel 10B start to emit light is delayed, so that the light emitting time of the red sub-pixel 10R and the blue sub-pixel 10B in the light emitting stage is shortened, and the light emitting efficiency of the red sub-pixel 10R and the blue sub-pixel 10B is reduced. Finally, in the first frame of the white frame switched from the black frame to the white frame, the light-emitting brightness of the green sub-pixel 10G is improved, the light-emitting brightness of the red sub-pixel 10R and the blue sub-pixel 10B is reduced, so that the green light brightness is compensated in the first frame of the white frame, the phenomenon of the purplish image in the first frame of the white frame is improved, the problem of the purplish smear color can be improved, the smear color observed by a user is corrected, the severity of the smear is reduced in visual effect, and the display effect of the display panel is improved.

In yet another possible embodiment, the inventors have found that, due to the existence of the whole layers of the electron injection layer, the electron transport layer, the hole injection layer, and the hole transport layer in the light emitting element 102, that is, the electron injection layer, the electron transport layer, the hole injection layer, and the hole transport layer of the light emitting element 102 in the adjacent sub-pixels 10 are connected to each other, a lateral current exists between the different sub-pixels 10.

Since the on-voltage of the light emitting element 102 in the red sub-pixel 10R and the green sub-pixel 10G is small, when the red sub-pixel 10R and the green sub-pixel 10G are not driven to emit light, if the lateral current is transmitted to the red sub-pixel 10R and the green sub-pixel 10G, the cross voltage of the light emitting element 102 in the red sub-pixel 10R and the green sub-pixel 10G is easily up to the on-voltage to cause the lighting.

Based on the above technical problems, in an alternative embodiment, the third reference voltage > the first reference voltage > the second reference voltage, or the third reference voltage > the second reference voltage > the first reference voltage is set so that the reference voltage at the anode of the light emitting element 102 in the red sub-pixel 10R and the green sub-pixel 10G is lower, the difference between the voltage across the light emitting element 102 in the red sub-pixel 10R and the green sub-pixel 10G and the bright starting voltage thereof is increased, and thus when the red sub-pixel 10R and the green sub-pixel 10G are not driven to emit light, and the transverse current is transmitted to the red sub-pixel 10R and the green sub-pixel 10G, the difficulty that the voltage across the light emitting element 102 in the red sub-pixel 10R and the green sub-pixel 10G reaches the bright starting voltage is increased, so that the problem that the red sub-pixel 10R and the green sub-pixel 10G are easy to be peeped and bright is solved, and the display effect of the display panel is improved.

In summary, the display panel provided by the embodiment of the invention includes a red sub-pixel, a green sub-pixel, a blue sub-pixel and a first reference signal line, wherein the first reference signal line includes a first signal line, a second signal line and a third signal line, the first signal line is connected with an initialization transistor of a pixel circuit in the red sub-pixel, the second signal line is electrically connected with an initialization transistor of a pixel circuit in the green sub-pixel, the third signal line is electrically connected with an initialization transistor of a pixel circuit in the blue sub-pixel, and at least two of a first reference voltage transmitted by the first signal line, a second reference voltage transmitted by the second signal line and a third reference voltage transmitted by the third signal line are different. The sub-pixels with different luminous colors are supplied with reference signals through different first reference signal lines, so that at least two of a first reference voltage received by the red sub-pixel, a second reference voltage received by the green sub-pixel and a third reference voltage received by the blue sub-pixel are different, and accordingly, according to the difference of luminous characteristics of the red sub-pixel, the green sub-pixel and the blue sub-pixel, the voltage amplitudes of the first reference voltage received by the red sub-pixel, the second reference voltage received by the green sub-pixel and the third reference voltage received by the blue sub-pixel are independently set, and the luminous brightness of the red sub-pixel, the green sub-pixel and the blue sub-pixel is more uniform, and the display effect is improved. Meanwhile, the first signal line, the second signal line and the third signal line are respectively connected with the red sub-pixel and the green sub-pixel, and then each first reference signal line is only required to be connected with part of sub-pixels in the same row of sub-pixels, so that the number of the sub-pixels electrically connected with each first reference signal line is reduced, the load connected with each first reference signal line is reduced, the signal voltage drop transmitted on the first reference signal line is reduced, the signal potential transmitted on the first reference signal line is more uniform, and the display brightness uniformity of the display panel is further improved.

Fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention, where, as shown in fig. 6 and fig. 7, alternatively, the first signal line Vref1R and the third signal line Vref1B are the same signal line; alternatively, the first signal line Vref1R and the second signal line Vref1G are the same signal line.

As shown in fig. 6, when the first frame is switched from the black frame to the white frame, the red sub-pixel 10R and the blue sub-pixel 10B are brighter, and the green sub-pixel 10G is darker, so that the first frame is relatively purple, and when a user views the first frame, the user views the first frame, and the first frame is a purple smear, so that the user views the first frame, and the second frame, and the user views the first frame.

Therefore, in an alternative embodiment, the second reference voltage at the anode of the light emitting element 102 in the green sub-pixel 10G may be set higher, so that the voltage across the light emitting element 102 in the green sub-pixel 10G is closer to the turn-on voltage thereof, so that in the light emitting stage, the voltage across the light emitting element 102 in the green sub-pixel 10G can reach the turn-on voltage thereof faster, the charging time of the pixel capacitor in the green sub-pixel 10G is shortened, the light emitting duration of the green sub-pixel 10G in the light emitting stage is prolonged, and the light emitting efficiency of the green sub-pixel 10G is improved. Meanwhile, the first reference voltage at the anode of the light emitting element 102 in the red sub-pixel 10R and the third reference voltage at the anode of the light emitting element 102 in the blue sub-pixel 10B are set to be lower, so that the difference between the voltage across the light emitting element 102 in the red sub-pixel 10R and the blue sub-pixel 10B and the starting voltage thereof is larger, the speed of the voltage across the light emitting element 102 in the red sub-pixel 10R and the blue sub-pixel 10B reaching the starting voltage thereof can be slower in the light emitting stage, the charging time of the pixel capacitors in the red sub-pixel 10R and the blue sub-pixel 10B is prolonged, the light emitting time of the red sub-pixel 10R and the blue sub-pixel 10B in the light emitting stage is shortened, and the light emitting efficiency of the red sub-pixel 10R and the blue sub-pixel 10B is reduced. Finally, in the first frame of the white frame switched from the black frame to the white frame, the light-emitting brightness of the green sub-pixel 10G is improved, the light-emitting brightness of the red sub-pixel 10R and the blue sub-pixel 10B is reduced, so that the green light brightness is compensated in the first frame of the white frame, the phenomenon of the purplish image in the first frame of the white frame is improved, the problem of the purplish smear color can be improved, the smear color observed by a user is corrected, the severity of the smear is reduced in visual effect, and the display effect of the display panel is improved.

As shown in fig. 1, if 3 first reference signal lines Vref1 (for example, a first signal line Vref1R, a second signal line Vref1G, and a third signal line Vref1B in the drawing) are correspondingly disposed in each row of sub-pixels 10, the number of the first reference signal lines Vref1 is greater, and the light shielding area of the first reference signal lines Vref1 is larger, so that the light transmittance of the display panel is affected.

Based on the above technical problems, in the embodiment of the present invention, since the brightness compensation of the red sub-pixel 10R and the blue sub-pixel 10B is relatively close, the first reference voltage at the anode of the light emitting element 102 in the red sub-pixel 10R and the third reference voltage at the anode of the light emitting element 102 in the blue sub-pixel 10B can be the same in voltage amplitude, so that the first signal line Vref1R and the third signal line Vref1B can be set to be the same signal line, that is, the red sub-pixel 10R and the blue sub-pixel 10B share the same first reference signal line Vref1, so that the problem of individually compensating the green brightness in the first frame of the white frame is solved, the number of the first reference signal lines Vref1 can be reduced while the problem of light-blocking of the first reference signal line Vref1 is improved, the light transmittance of the display panel is improved, and the problem of influencing the performance of the under-screen optical devices such as the under-screen camera of the under-screen due to the light transmittance of the display panel is solved.

Further, as shown in fig. 6, the first signal line Vref1R and the third signal line Vref1B are the same signal line, so that the number of the sub-pixels 10 (red sub-pixel 10R and blue sub-pixel 10B) electrically connected to each first signal line Vref 1R/third signal line Vref1B is greater than the number of the sub-pixels 10 (green sub-pixel 10G) electrically connected to each second signal line Vref1G, so that the load connected to each first signal line Vref 1R/third signal line Vref1B is greater, and the voltage drop of the signals transmitted on the first signal line Vref 1R/third signal line Vref1B is greater, which results in uneven potential of the signals transmitted on the first signal line Vref 1R/third signal line Vref1B at different positions, and affects the uniformity of display brightness.

Based on the above technical problems, in the embodiment of the present invention, the resistivity of the first signal line Vref 1R/the third signal line Vref1B may be set smaller than the resistivity of the second signal line Vref1G, so as to reduce the resistance of the first signal line Vref 1R/the third signal line Vref1B, so that the voltage drop of the signal transmitted on the first signal line Vref 1R/the third signal line Vref1B is reduced, and the signal potential transmitted on the first signal line Vref 1R/the third signal line Vref1B is more uniform, which is beneficial to improving the uniformity of the display brightness of the display panel.

The first signal line Vref 1R/the third signal line Vref1B may have a larger line width than the second signal line Vref1G, so that the first signal line Vref 1R/the third signal line Vref1B has a smaller resistivity than the second signal line Vref 1G.

With continued reference to fig. 7, as described above, since the light emitting element 102 has the whole layers of the electron injection layer, the electron transport layer, the hole injection layer, the hole transport layer, and the like, that are the electron injection layer, the electron transport layer, the hole injection layer, and the hole transport layer of the light emitting element 102 in the adjacent sub-pixels 10 are connected to each other, a lateral current exists between the different sub-pixels 10.

Therefore, in an alternative embodiment, the first reference voltage and the second reference voltage may be set lower, so that the reference voltage at the anode of the light emitting element 102 in the red sub-pixel 10R and the green sub-pixel 10G is lower, the gap between the voltage across the light emitting element 102 in the red sub-pixel 10R and the green sub-pixel 10G and the turn-on voltage thereof is increased, and thus when the red sub-pixel 10R and the green sub-pixel 10G are not driven to emit light, the difficulty that the voltage across the light emitting element 102 in the red sub-pixel 10R and the green sub-pixel 10G reaches the turn-on voltage is increased, thereby solving the problem that the red sub-pixel 10R and the green sub-pixel 10G are easily peeped and lighted due to the influence of the lateral current, and improving the display effect of the display panel.

Similarly, as shown in fig. 1, if 3 first reference signal lines Vref1 (for example, a first signal line Vref1R, a second signal line Vref1G, and a third signal line Vref1B in the drawing) are correspondingly disposed in each row of sub-pixels 10, the number of the first reference signal lines Vref1 is large, and the light shielding area of the first reference signal lines Vref1 is large, so that the light transmittance of the display panel is affected.

Based on the above technical problems, in the embodiment of the present invention, since the reference voltages at the anode of the light emitting element 102 in the red sub-pixel 10R and the green sub-pixel 10G are low, the first reference voltage at the anode of the light emitting element 102 in the red sub-pixel 10R and the second reference voltage at the anode of the light emitting element 102 in the green sub-pixel 10G can be set to have the same voltage amplitude, and further the first signal line Vref1R and the second signal line Vref1G can be set to be the same signal line, that is, the red sub-pixel 10R and the green sub-pixel 10G share the same first reference signal line Vref1, so that the problem that the red sub-pixel 10R and the green sub-pixel 10G are easily stolen and bright due to the influence of lateral current can be solved, and the number of the first reference signal lines Vref1 can be reduced, thereby reducing the light shielding area of the first reference signal line Vref1, improving the light transmittance of the display panel, and solving the problem that the light transmittance of the display panel affects the performance of the under-screen camera.

Further, as shown in fig. 7, the first signal line Vref1R and the second signal line Vref1G are the same signal line, so that the number of the sub-pixels 10 (red sub-pixel 10R and green sub-pixel 10G) electrically connected to each first signal line Vref 1R/second signal line Vref1G is greater than the number of the sub-pixels 10 (blue sub-pixel 10B) electrically connected to each third signal line Vref1B, so that the load connected to each first signal line Vref 1R/second signal line Vref1G is greater, and the voltage drop of the signals transmitted on the first signal line Vref 1R/second signal line Vref1G is greater, which results in uneven potential of the signals transmitted on the first signal line Vref 1R/second signal line Vref1G at different positions, and affects the uniformity of display brightness.

Based on the above technical problems, in the embodiment of the present invention, the resistivity of the first signal line Vref 1R/the second signal line Vref1G may be set smaller than the resistivity of the third signal line Vref1B, so as to reduce the resistance of the first signal line Vref 1R/the second signal line Vref1G, so that the voltage drop of the signal transmitted on the first signal line Vref 1R/the second signal line Vref1G is reduced, and the signal potential transmitted on the first signal line Vref 1R/the second signal line Vref1G is more uniform, which is beneficial to improving the uniformity of the display brightness of the display panel.

The first signal line Vref 1R/the second signal line Vref1G may have a line width larger than that of the third signal line Vref1B, so that the resistivity of the first signal line Vref 1R/the second signal line Vref1G is smaller than that of the third signal line Vref 1B.

Fig. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention, as shown in fig. 3, 4 and 8, optionally, the pixel circuit 101 further includes a reset transistor M5, a first electrode M51 of the reset transistor M5 is electrically connected to a gate of the driving transistor M3, the plurality of reference signal lines Vref further includes a second reference signal line Vref2, the second reference signal line Vref2 is electrically connected to a second electrode M52 of the reset transistor M5, and a reference voltage transmitted by the second reference signal line Vref2 is different from a reference voltage transmitted by the first reference signal line Vref 1.

Specifically, as shown in fig. 3 and 4, the gate of the reset transistor M5 is electrically connected to the first scan signal line S1, the first electrode M51 of the reset transistor M5 is electrically connected to the gate of the driving transistor M3 at the first node N1, and the second electrode M52 of the reset transistor M5 is electrically connected to the second reference signal line Vref 2.

In the initialization stage, the first scan signal on the first scan signal line S1 turns on the reset transistor M5, and the reference voltage on the second reference signal line Vref2 is transmitted to the gate of the driving transistor M3 (i.e., the first node N1) through the reset transistor M5 to reset the gate of the driving transistor M3, at this time, the potential of the gate of the driving transistor M3 (i.e., the first node N1) is consistent with the reference voltage on the second reference signal line Vref2, so as to avoid the data signal of the previous frame carried on the gate of the driving transistor M3 from affecting the writing of the next frame of data signal.

As can be seen from the above description, the reference signal received by the first node N1 is used for resetting the gate of the driving transistor M3, and the reference signal received by the second node N2 is used for resetting the anode of the light emitting element 102, so that the first node N1 and the second node N2 need to receive different reference signals due to different structures that need to be reset. Therefore, in the embodiment of the present invention, the second reference signal line Vref2 is additionally provided, in the same pixel circuit 101, the first node N1 is electrically connected to the second reference signal line Vref2 through the reset transistor M5, the second node N2 is electrically connected to the first reference signal line Vref1 through the initialization transistor M7, and the reference voltage provided by the first reference signal line Vref1 and the reference voltage provided by the second reference signal line Vref2 may be different, so that independent reset of the gate of the driving transistor M3 and the anode of the light emitting element 102 is ensured, and a better reset effect of the gate of the driving transistor M3 and the anode of the light emitting element 102 is ensured.

The magnitudes of the reference voltages transmitted by the first reference signal line Vref1 and the second reference signal line Vref2 may be set according to different requirements of different nodes on the reference voltages, so as to improve the reset effect, for example, the voltage value of the reference voltage transmitted by the first reference signal line Vref1 is set to be negative, so that the driving transistor M3 is guaranteed to be turned on in the data writing stage, and the accurate writing of the data signal is ensured.

It should be noted that, in other embodiments, the first node N1 and the second node N2 of the same pixel circuit 101 may be electrically connected to the same reference signal line Vref, and at this time, the first node N1 and the second node N2 of the same pixel circuit 101 receive the same reset voltage, so that the number of the reference signal lines Vref may be reduced, thereby reducing the light shielding area of the reference signal line Vref, improving the light transmittance of the display panel, and being beneficial to meeting the requirements of the trend of the under-screen camera.

Fig. 9 is a schematic structural diagram of a display panel according to another embodiment of the present invention, as shown in fig. 3 and 9, optionally, the second reference signal line Vref2 includes a fourth signal line Vref2R, a fifth signal line Vref2G and a sixth signal line Vref2B, the fourth signal line Vref2R is electrically connected to the reset transistor M5 of the pixel circuit 101 in the red sub-pixel 10R, the fifth signal line Vref2G is electrically connected to the reset transistor M5 of the pixel circuit 101 in the green sub-pixel 10G, the sixth signal line Vref2B is electrically connected to the reset transistor M5 of the pixel circuit 101 in the blue sub-pixel 10B, the fourth signal line Vref2R is used for transmitting a fourth reference voltage, the fifth signal line Vref2G is used for transmitting a fifth reference voltage, and the sixth signal line Vref2B is used for transmitting a sixth reference voltage, at least two of the fourth reference voltage, the fifth reference voltage and the sixth reference voltage are different.

Specifically, as shown in fig. 3, the pixel circuit 101 further includes a data writing transistor M2 and an additional transistor M4, the gate of the data writing transistor M2 is electrically connected to the second scanning signal line S2, the first pole M21 of the data writing transistor M2 is electrically connected to the second pole M32 of the driving transistor M3, and the second pole M22 of the data writing transistor M2 is electrically connected to the data signal line Vdata. The gate of the additional transistor M4 is electrically connected to the second scan signal line S2, the first electrode M41 of the additional transistor M4 is electrically connected to the first electrode M31 of the driving transistor M3, and the second electrode M42 of the additional transistor M4 is electrically connected to the gate of the driving transistor M3.

In the data writing stage, the second scan signal on the second scan signal line S2 turns on the data writing transistor M2 and the additional transistor M4, and the gate potential of the driving transistor M3 is consistent with the reference voltage provided by the second reference signal line Vref2, the driving transistor M3 is also turned on, the data signal provided by the data signal line Vdata is applied to the gate of the driving transistor M3 via the data writing transistor M2, the driving transistor M3 and the additional transistor M4 (i.e. the first nodeN1), the potential of the first node N1 is gradually pulled up until the driving transistor M3 is turned off. When the driving transistor M3 is turned off, the gate potential of the driving transistor M3 is V _data -|V _th I, wherein V _data Voltage value of data signal on data signal line Vdata, |v _th I is the threshold voltage of the driving transistor M3.

Further, after the data writing stage is completed, the display panel may enter a light emitting stage, in which the first power signal on the first power signal line PVDD is transmitted to the second pole M32 of the driving transistor M3, and the voltage difference between the second pole M32 and the gate of the driving transistor M3 is V _PVDD -(V _data -|V _th I) such that the driving current generated by the driving transistor M3 is K (V) _data -V _PVDD ) ² K is a coefficient related to the size and material of the driving transistor M3, V _PVDD The voltage of the first power signal on the first power signal line PVDD is the same as the driving current generated by the driving transistor M3 and the threshold voltage |V _th The I is irrelevant.

In the data writing stage, the voltage V of the data signal written by the gate of the driving transistor M3 _data The magnitude of the driving current generated by the driving transistor M3 is controlled, and the magnitude of the driving current generated by the driving transistor M3 determines the gray scale finally presented by the display panel, so that the effect of writing the data signal into the gate of the driving transistor M3 during the data writing stage affects the display gray scale variation of the display panel, thereby affecting the display effect of the display panel.

The inventors have found that the reference voltage of the gate electrode (i.e. the first node N1) of the driving transistor M3 during the reset period affects the writing speed of the subsequent data signal before the data writing period, wherein the reference voltage of the gate electrode (i.e. the first node N1) of the driving transistor M3 during the reset period and the voltage value V of the data signal _data When the gap is large, the longer the data writing period is, the longer the time for the gate of the driving transistor M3 to complete writing the data signal, and the voltage of the data signal written by the gate of the driving transistor M3 in the sub-pixel 10 emitting different color light Value V _data Generally, if the reference voltages of the gate electrode of the driving transistor M3 in the sub-pixel 10 emitting different colors of light are the same during reset, the refresh rate of the display panel is high, which may result in the reference voltage of the gate electrode of the driving transistor M3 (i.e. the first node N1) in the sub-pixel 10 emitting partial colors of light and the voltage value V of the data signal during reset _data The gap is too large to cause insufficient charging, i.e. the writing of the data signal is not completed by the gate of the driving transistor M3 in the limited period of time in the data writing stage, so that the sub-pixel 10 cannot achieve accurate brightness in the light emitting stage, and the display effect of the display panel is affected.

Based on the above-mentioned technical problems, as shown in fig. 9, in the present embodiment, in each row of the sub-pixels 10, the sub-pixels 10 having different light emission colors provide the reference signals through the different second reference signal lines Vref2, so that at least two of the fourth reference voltage received by the red sub-pixel 10R, the fifth reference voltage received by the green sub-pixel 10G and the sixth reference voltage received by the blue sub-pixel 10B are different, and thus the light emission brightness of the red sub-pixel 10R, the green sub-pixel 10G and the blue sub-pixel 10B can be independently set according to the different data signal writing requirements of the red sub-pixel 10R, the green sub-pixel 10G and the blue sub-pixel 10B, the voltage amplitude of the fourth reference voltage received by the red sub-pixel 10R, the fifth reference voltage received by the green sub-pixel 10G and the sixth reference voltage received by the blue sub-pixel 10B can be ensured, and the accuracy of writing of the data signals can be further improved.

Meanwhile, in the same row of sub-pixels 10, the red sub-pixel 10R, the green sub-pixel 10G and the blue sub-pixel 10B are respectively connected with the fourth signal line Vref2R, the fifth signal line Vref2G and the sixth signal line Vref2B, so that each second reference signal line Vref2 only needs to be connected with part of the sub-pixels 10 in the same row of sub-pixels 10, thereby reducing the number of the sub-pixels 10 electrically connected with each second reference signal line Vref2, reducing the load connected with each second reference signal line Vref2, reducing the signal voltage drop transmitted on the second reference signal line Vref2, making the signal potential transmitted on the second reference signal line Vref2 more uniform, and being beneficial to improving the display brightness uniformity of the display panel.

Fig. 10 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention, as shown in fig. 3 and 10, optionally, the pixel circuit 101 further includes a data writing transistor M2, and a first pole M21 of the data writing transistor M2 is electrically connected to a second pole M32 of the driving transistor M3. The display panel further includes a second scan signal line S2 extending in the first direction X and a data signal line Vdata extending in the second direction Y, the second scan signal line S2 being electrically connected to the gate of the data writing transistor M2, the data signal line Vdata being electrically connected to the second pole M22 of the data writing transistor M2, wherein the first direction X and the second direction Y intersect. In the same pixel circuit 101, along the second direction Y, the reference signal line Vref is located at a side of the second scanning signal line S2 away from the driving transistor M3, and at least two reference signal lines Vref are located at different film layers.

The connection relationship and the technical effects of the data writing transistor M2 in the pixel circuit 101 can be referred to any of the above embodiments, and the explanation of the same or corresponding structure and terms as those of the above embodiments is not repeated here.

In the embodiment of the present invention, as shown in fig. 10, the extending direction of the second scanning signal line S2 (for example, the first direction X in the drawing) and the extending direction of the data signal line Vdata (for example, the second direction Y in the drawing) intersect. In the same pixel circuit 101, along the extending direction (for example, the second direction Y in the drawing) of the data signal line Vdata, the reference signal line Vref is disposed on the side of the second scanning signal line S2 away from the driving transistor M3, on the one hand, there is enough space for disposing the reference signal line Vref on the side of the second scanning signal line S2 away from the driving transistor M3, so that the layout design of the reference signal line Vref is easy to implement; on the other hand, the reference signal line Vref is closer to the reset transistor M5 and the initialization transistor M7, so that the reference signal line Vref is convenient to electrically connect with the reset transistor M5 and the initialization transistor M7; on the other hand, the distance between the reference signal line Vref and the driving transistor M3 is further, so that the influence of the signal transmitted on the reference signal line Vref on the driving transistor M3 can be reduced, the accuracy of the driving current generated by the driving transistor M3 is ensured, the light-emitting brightness of the sub-pixel 10 is more accurate, and the display effect of the display panel is improved.

Further, the inventor has found that, by setting the red sub-pixel 10R, the green sub-pixel 10G, and the blue sub-pixel 10B to be connected to the first signal line Vref1R, the second signal line Vref1G, and the third signal line Vref1B, respectively, the number of the reference signal lines Vref increases, and the plurality of sub-pixels 10 are densely arranged due to the high resolution requirement of the display panel, the planar space available for setting the reference signal lines Vref is limited, so that the wiring difficulty of a large number of reference signal lines Vref is high.

Based on the above technical problems, fig. 11 is a schematic diagram of a partial cross-sectional structure of a pixel circuit according to an embodiment of the present invention, as shown in fig. 10 and 11, in this embodiment, at least two reference signal lines Vref are disposed on different film layers, that is, at least two reference signal lines Vref are disposed on different layers, so that the reference signal lines Vref are changed from planar wiring on a single film layer to layered wiring, so that the number of reference signal lines Vref in each film layer can be reduced, and thus the wiring difficulty of the reference signal lines Vref in each film layer can be reduced.

In fig. 10 and fig. 11, only the first signal line Vref1R and the second reference signal line Vref2 are illustrated as being located in different layers, and in other embodiments, any two reference signal lines Vref may be located in different layers, which is not limited in the embodiments of the present invention.

It should be noted that, all the reference signal lines Vref may be layered in 2 or more layers, for example, the number of layers used for setting the reference signal lines Vref may be the same as the number of the reference signal lines Vref, that is, each reference signal line Vref is separately set in one layer, and any two reference signal lines Vref are in different layers, but not limited thereto.

It can be understood that the fewer the number of the film layers for setting the reference signal line Vref, the more advantageous the thickness of the display panel is reduced, which is helpful for realizing the light and thin design of the display panel; the larger the number of the film layers for setting the reference signal line Vref, the smaller the number of the reference signal line Vref in each film layer, which is more conducive to reducing the occupied space of the reference signal line Vref on the plane of the display area of the display panel, thereby further reducing the influence of the reference signal line Vref on the display effect of the display area.

In addition, the film layer position of the reference signal line Vref may also be set according to actual requirements, which is not specifically limited in the embodiment of the present invention. As illustrated in fig. 10 and 11, the pixel circuit 101 includes at least one thin film transistor T including an active layer 01, a gate layer 02, and a source-drain electrode layer 03 stacked on a substrate base 00, and the first signal line Vref1R and the second reference signal line Vref2 may be located at opposite sides of the active layer 01, respectively, in a thickness direction of the display panel, but is not limited thereto.

With continued reference to fig. 3, 10 and 11, the pixel circuit 101 optionally further includes a reset transistor M5, the first electrode M51 of the reset transistor M5 is electrically connected to the gate of the driving transistor M3, and the display panel further includes a first scan signal line S1 extending along the first direction X, the first scan signal line S1 being electrically connected to the gate of the reset transistor M5. In the same pixel circuit 101, the first scanning signal line S1 is located on a side of the second scanning signal line S2 away from the driving transistor in the second direction Y. In the same pixel circuit 101, at least two reference signal lines Vref located at different film layers are located at a side of the first scan signal line S1 away from the second scan signal line S2 along the second direction Y, and at least partially overlap between the reference signal lines Vref located at different film layers along the thickness direction of the display panel.

The connection relationship and the technical effects of the reset transistor M5 in the pixel circuit 101 can refer to any of the above embodiments, and the explanation of the same or corresponding structure and terms as those of the above embodiments is not repeated herein.

In the embodiment of the present invention, as shown in fig. 10, the extending direction (for example, the first direction X in the drawing) of the first scanning signal line S1 is the same as the extending direction (for example, the first direction X in the drawing) of the second scanning signal line S2. In the same pixel circuit 101, along the extending direction (for example, the second direction Y in the drawing) of the data signal line Vdata, the first scanning signal line S1 is located at one side of the second scanning signal line S2 away from the driving transistor, so that the distance between the reset transistor M5 and the initialization transistor M7, which are connected to the first scanning signal line S1, and the driving transistor M3 is further longer, and the distance between the reference signal line Vref, which is electrically connected to the reset transistor M5 and the initialization transistor M7, and the driving transistor M3 is further, so that the influence of the signal transmitted on the reference signal line Vref on the driving transistor M3 is reduced while sufficient space arrangement of the reference signal line Vref is ensured, the accuracy of the driving current generated by the driving transistor M3 is ensured, the light emitting brightness of the sub-pixel 10 is further accurate, and the display effect of the display panel is improved.

Further, as shown in fig. 10 and 11, the pixel circuit 101 includes at least one thin film transistor T including an active layer 01, a gate layer 02, and a source-drain electrode layer 03 stacked over a substrate base 00.

In the embodiment of the present invention, the transistors (e.g., the data writing transistor M2, the driving transistor M3, the additional transistor M4, the reset transistor M5, the initialization transistor M7, etc.) in the pixel circuit 101 are all the thin film transistors T.

It is understood that at least two metal film layers (e.g., the gate electrode layer 02 and the source-drain electrode layer 03) are provided in the thin film transistor T, and the wiring space of the reference signal line Vref is limited without adding a metal film layer.

In contrast, as shown in fig. 10, in the same pixel circuit 101, in the extending direction (for example, the second direction Y in the drawing) of the data signal line Vdata, the number of thin film transistors on the side of the first scanning signal line S1 away from the second scanning signal line S2 is small, and thus, a large area of wiring space exists for each metal film layer, and in this embodiment, the reference signal lines Vref located in different film layers can be disposed on the side of the first scanning signal line S1 away from the second scanning signal line S2, so that the conflict between the disposition of the reference signal lines Vref and the disposition of the thin film transistors can be reduced.

Meanwhile, as shown in fig. 10 and 11, at one side of the first scanning signal line S1 far away from the second scanning signal line S2, and at least two reference signal lines Vref arranged in different layers overlap in the thickness direction of the display panel, the shielding area of the reference signal lines Vref in the thickness direction of the display panel can be reduced, so that the light transmittance of the display panel can be improved, and the imaging performance of the under-screen optical device can be improved when the display panel is correspondingly provided with the under-screen optical device such as an under-screen camera.

It should be noted that, in fig. 10 and fig. 11, only the case where in the same pixel circuit 101, along the second direction Y, the first signal line Vref1R and the second reference signal line Vref2 are located in different layers, and the first signal line Vref1R and the second reference signal line Vref2 are located at a side of the first scanning signal line S1 away from the second scanning signal line S2, and along the thickness direction of the display panel, at least a part of overlap between the first signal line Vref1R and the second reference signal line Vref2 is illustrated, in other embodiments, any two reference signal lines Vref may be set so as to achieve a corresponding technical effect, and embodiments of the present invention are not limited in this way.

Fig. 12 is a schematic structural view of a further pixel circuit according to an embodiment of the present invention, fig. 13 is a schematic structural view of a bottom reference signal line in fig. 12, fig. 14 is a schematic structural view of a partial cross section of another pixel circuit according to an embodiment of the present invention, and as shown in fig. 12 to 14, optionally, a display panel according to an embodiment of the present invention further includes a substrate 00, the pixel circuit 101 includes at least one thin film transistor T, the thin film transistor T includes an active layer 01 and a source/drain electrode layer 03 stacked on one side of the substrate 00, and the source/drain electrode layer 03 is electrically connected to the active layer 01. The at least one thin film transistor T includes a driving transistor M3. At least one reference signal line Vref is positioned on one side of the active layer 01 close to the substrate 00, and the reference signal line Vref positioned on one side of the active layer 01 close to the substrate 00 is a bottom reference signal line Vref3. In the thickness direction of the display panel, the underlying reference signal line Vref3 and the active layer 01 of the driving transistor M3 overlap at least partially.

The connection relationship of the thin film transistor T in the pixel circuit 101 and the technical effects thereof can be referred to any of the above embodiments, and the explanation of the same or corresponding structure and terms as those of the above embodiments will not be repeated herein.

Further, the thin film transistor T includes the driving transistor M3, and the connection relationship and the technical effects of the driving transistor M3 in the pixel circuit 101 can also refer to any of the above embodiments, and the same or corresponding structure and terms as those of the above embodiments are not repeated herein.

Specifically, as shown in fig. 12-14, at least two metal film layers (for example, the gate layer 02 and the source-drain electrode layer 03) are disposed in the thin film transistor T, so that under the condition that the plurality of sub-pixels 10 are densely arranged, the arrangement density of the thin film transistor T is relatively high, the planar space in which the gate layer 02 and the source-drain electrode layer 03 are disposed is limited, and the side of the active layer 01 close to the substrate 00 is relatively less provided with the metal layer structure in the thin film transistor T.

With continued reference to fig. 12 to 14, the reference signal line Vref disposed on the side of the active layer 01 near the substrate 00 is used as the bottom reference signal line Vref3, and by setting at least a partial overlap between the vertical projection of the bottom reference signal line Vref3 on the substrate 00 and the vertical projection of the active layer 01 of the driving transistor M3 on the substrate 00, a certain light shielding effect can be achieved on the light ray emitted to the active layer 01 on the substrate 00 side by using the bottom reference signal line Vref3, which is helpful for reducing the influence of the light ray on the threshold voltage of the driving transistor M3, improving the stability of the driving transistor M3, further ensuring the light emitting brightness of the sub-pixel 10 to be more accurate, and being beneficial for improving the display effect.

Further, as shown in fig. 12-14, along the thickness direction of the substrate 00, the bottom reference signal line Vref3 may cover the active layer 01 of the driving transistor M3, so that the bottom reference signal line Vref3 may block the light emitted to the active layer 01 from the side of the substrate 10 to the maximum extent, thereby reducing the influence of the light on the threshold voltage of the driving transistor M3 to the maximum extent and further improving the stability of the driving transistor M3.

With continued reference to fig. 12-14, optionally, a part of the reference signal lines Vref may be disposed on a side of the active layer 01 near the substrate 00, and another part of the reference signal lines Vref may be disposed on other metal film layers, so that the planar wiring of the reference signal lines Vref is changed into layered wiring from planar wiring in a single film layer, so that the number of the reference signal lines Vref in each film layer can be reduced, and the wiring difficulty of the reference signal lines Vref in each film layer can be reduced.

As shown in fig. 3 and 14, the pixel circuit 101 further includes a capacitor Cst, a first electrode plate C1 of the capacitor Cst is electrically connected to the gate electrode of the driving transistor M3, a second electrode plate C2 of the capacitor Cst is electrically connected to the first power signal line PVDD, wherein the first electrode plate C1 and the gate electrode layer 02 of the thin film transistor T are located in a same film layer, the second electrode plate C2 and the first electrode plate C1 are located in different film layers, and the second electrode plate C2 and the first electrode plate C1 at least partially overlap along the thickness direction of the display panel.

In the embodiment of the present invention, as shown in fig. 12 to 14, the third signal line Vref1B and the second signal line Vref1G are exemplarily disposed on the active layer 01 side close to the substrate 00, that is, the third signal line Vref1B and the second signal line Vref1G are the bottom reference signal line Vref3, and the third signal line Vref1B covers the active layer 01 of the driving transistor M3 along the thickness direction of the substrate 00, so that the third signal line Vref1B shields the light emitted to the active layer 01 on the substrate 10 side, thereby reducing the influence of the light on the threshold voltage of the driving transistor M3 and improving the stability of the driving transistor M3.

Meanwhile, the first signal line Vref1R, the second reference signal line Vref2 and the second electrode plate C2 are arranged on the same film layer, so that on one hand, the arrangement of a metal layer can be reduced, and the purposes of reducing the production cost and the thickness of the display panel are achieved; on the other hand, the first signal line Vref1R and the second reference signal line Vref2 may be made of the same material as the second plate C2, so that the first signal line Vref1R, the second reference signal line Vref2 and the second plate C2 may be prepared in the same process, thereby shortening the process time; on the other hand, as shown in fig. 14, the film layer of the second polar plate C2 is not provided with the metal structure in the thin film transistor T, so that the film layer of the second polar plate C2 has enough space to arrange the reference signal line Vref, thereby reducing the wiring difficulty of the reference signal line Vref.

With continued reference to fig. 12 to 14, further, along the thickness direction of the display panel, the bottom reference signal line Vref3 may at least partially overlap with other reference signal lines, so as to reduce the shielding area of the reference signal line in the thickness direction of the display panel, thereby helping to improve the light transmittance of the display panel, and when the display panel is correspondingly provided with an under-screen optical device such as an under-screen camera, the imaging performance of the under-screen optical device may be improved.

As shown in fig. 12 to 14, the second signal line Vref1G and the first signal line Vref1R overlap in the thickness direction of the display panel, so that the setting area of the second signal line Vref1G can be increased while the shielding area of the second signal line Vref1G and the first signal line Vref1R is not increased, and thus the resistivity of the second signal line Vref1G can be reduced, and the voltage drop of the second reference voltage transmitted on the second signal line Vref1G is reduced, so that the second reference voltage potential transmitted on the second signal line Vref1G is more uniform, which is beneficial to improving the uniformity of the display brightness of the display panel.

It is to be understood that the specific film layer settings and the relative position settings of the first signal line Vref1R, the second signal line Vref1G, the third signal line Vref1B and the second reference signal line Vref2 are not limited to the above embodiments, and those skilled in the art may design the specific film layer settings and the position settings of each reference signal line according to actual requirements, which is not particularly limited in the embodiments of the present invention.

Fig. 15 is a schematic view of a partial cross-sectional structure of a pixel circuit according to another embodiment of the present invention, and as shown in fig. 10, 12 and 15, optionally, the display panel according to the embodiment of the present invention further includes a first insulating layer 31, a second insulating layer 32 and a connection metal layer 33, where the first insulating layer 31 is located between the underlying reference signal line Vref3 and the active layer 01, the second insulating layer 32 is located between the active layer 01 and the source drain electrode layer 03, and the connection metal layer 33 and the source drain electrode layer 03 are located on the same layer. The display panel further includes at least one connection via, the at least one connection via including a first via 41 and a second via 42, the first via 41 penetrating the first insulating layer 31 and the second insulating layer 32, and the second via 42 penetrating the second insulating layer 32. In the thickness direction of the display panel, the connection metal layer 33 and the first via hole 41 at least partially overlap, the connection metal layer 33 and the second via hole 42 at least partially overlap, the underlying reference signal line Vref3 and the first via hole 41 at least partially overlap, and the active layer 01 and the second via hole 42 at least partially overlap. The underlying reference signal line Vref3 is electrically connected to the connection metal layer 33 through the first via 41, and the connection metal layer 33 is electrically connected to the active layer 01 through the second via 42.

The inventors have found that if the first insulating layer 31 between the bottom reference signal line Vref3 and the active layer 01 is directly perforated to connect the bottom reference signal line Vref3 and the active layer 01, a separate mask process is required when the first insulating layer 31 is perforated, thereby increasing the process time and cost.

Based on the above technical problems, in the embodiment of the present invention, as shown in fig. 10, 12 and 15, a connection metal layer 33 is disposed on the film layer where the source-drain electrode layer 03 is located, a first via hole 41 is prepared on the first insulating layer 31 and the second insulating layer 32, a second via hole 42 is prepared on the second insulating layer 32, and an overlapping area exists among the connection metal layer 33, the first via hole 41 and the bottom reference signal line Vref3 along the thickness direction of the display panel, so that the connection metal layer 33 can be electrically connected with the bottom reference signal line Vref3 through the first via hole 41; meanwhile, there is an overlapping region between the connection metal layer 33, the second via hole 42 and the active layer 01, so that the connection metal layer 33 can be electrically connected with the active layer 01 through the second via hole 42, thus realizing that the underlying reference signal line Vref3 and the active layer 01 are electrically connected through the connection metal layer 33. The first via 41 and the second via 42 may be prepared in the same process with the connection via between the source drain electrode layer 03 and the active layer 01, that is, the first via 41, the second via 42, and the connection via between the source drain electrode layer 03 and the active layer 01 may be prepared in the same process, so that a mask process may be reduced, the problem that an additional mask process is required to be added to the connection via between the bottom reference signal line Vref3 and the active layer 01 to perform punching is solved, and the process time and cost are reduced.

Fig. 16 is a schematic view of a partial cross-sectional structure of a pixel circuit according to another embodiment of the present invention, as shown in fig. 16, optionally, the display panel according to the embodiment of the present invention further includes a first insulating layer 31, the first insulating layer 31 is located between the underlying reference signal line Vref3 and the active layer 01, the display panel further includes at least one connection via, the at least one connection via includes a third via 43, and the third via 43 penetrates through the first insulating layer 31. The bottom reference signal line Vref3 and the third via hole 43 at least partially overlap in the thickness direction of the display panel, and the active layer 01 and the third via hole 43 at least partially overlap, and the bottom reference signal line Vref3 is electrically connected to the active layer 01 through the third via hole 43.

Specifically, as shown in fig. 16, the third via hole 43 is prepared on the first insulating layer 31, and along the thickness direction of the display panel, there is an overlapping area between the bottom reference signal line Vref3, the third via hole 43 and the active layer 01, so that the bottom reference signal line Vref3 can be electrically connected with the active layer 01 through the third via hole 43, so that the bottom reference signal line Vref3 and the active layer 01 can be electrically connected with each other only by providing one connection via hole (for example, the third via hole 43), thereby reducing the number of connection via holes, reducing the shielding area of the connection via holes in the thickness direction of the display panel, thereby being beneficial to improving the light transmittance of the display panel, and improving the imaging performance of the under-screen optical device when the display panel is correspondingly provided with the under-screen optical device such as the under-screen camera.

With continued reference to fig. 3, 10 and 12, the pixel circuit 101 optionally further includes a data writing transistor M2 and a reset transistor M5, the first pole M21 of the data writing transistor M2 is electrically connected to the second pole M32 of the driving transistor M3, and the first pole M51 of the reset transistor M5 is electrically connected to the gate of the driving transistor M3. The display panel further includes a first scan signal line S1 and a second scan signal line S2 extending in the first direction X, and a data signal line Vdata extending in the second direction Y, the first scan signal line S1 being electrically connected to the gate of the reset transistor M5, the second scan signal line S2 being electrically connected to the gate of the data writing transistor M2, the data signal line Vdata being electrically connected to the second pole M22 of the data writing transistor M2, wherein the first direction X and the second direction Y intersect. In the same pixel circuit 101, the connection via is located between the first scan signal line S1 and the second scan signal line S2 along the second direction Y.

The inventor finds that if the connecting via hole overlaps with other signal lines in the display panel along the thickness direction of the display panel, parasitic capacitance is formed between the connecting via hole and the signal line overlapped with the connecting via hole, and signals transmitted on the signal line are interfered by reference voltages on the connecting via hole, so that the display effect of the display panel is affected finally.

Based on the above-mentioned technical problems, as shown in fig. 3, 10 and 12, in the present embodiment, in the same pixel circuit 101, the number of signal lines between the first scan signal line S1 and the second scan signal line S2 is small, so that sufficient layout space can be provided for the connection via holes, and meanwhile, along the extending direction (e.g., the second direction Y in the drawing) of the data signal line Vdata, the connection via holes (e.g., the first via holes 41 and the second via holes 42) are disposed between the first scan signal line S1 and the second scan signal line S2, so that the overlapping area between the connection via holes (e.g., the first via holes 41 and the second via holes 42) and other signal lines in the thickness direction of the display panel is avoided, and parasitic capacitance between the connection via holes (e.g., the first via holes 41 and the second via holes 42) and other signal lines can be reduced, thereby reducing signal interference between the connection via holes (e.g., the first via holes 41 and the second via holes 42) and other signal lines, which is beneficial to improving the display effect of the display panel.

It should be noted that, the arrangement position of the connection via between the underlying reference signal line Vref3 and the active layer 01 is not limited to the above embodiment, and in other embodiments, the connection via may be arranged at other positions, as long as it is ensured that the connection via does not overlap with other signal line structures in the thickness direction of the display panel.

In addition, in the present embodiment, the connection relationship and the technical effects of the data writing transistor M2, the reset transistor M5, the first scanning signal line S1 and the second scanning signal line S2 in the pixel circuit 101 can be referred to any of the above embodiments, and the same or corresponding structure and terms as those of the above embodiments are not repeated herein.

With continued reference to fig. 1, 3, 12 and 13, optionally, the display panel provided by the embodiment of the present invention further includes a first power signal line PVDD, a second power signal line PVEE, a first scan signal line S1, a second scan signal line S2, a data signal line Vdata and a light emission control signal line Emit. The pixel circuit 101 further includes a reset transistor M5, a data writing transistor M2, an additional transistor M4, and a light emission control transistor M16. The first power signal line PVDD is used for transmitting a first power voltage, and the second power signal line PVEE is used for transmitting a second power voltage, and the first power voltage is greater than the second power voltage. The driving transistor M3, the light emission control transistor M16, and the light emitting element 102 are connected in series between the first power supply signal line PVDD and the second power supply signal line PVEE. The gate of the reset transistor M5 is electrically connected to the first scan signal line S1, the first pole M51 of the reset transistor M5 is electrically connected to the gate of the driving transistor M3, and the second pole M52 of the reset transistor M5 is electrically connected to the reference signal line Vref (e.g., the first reference signal line Vref 1). The gate of the initialization transistor M7 is electrically connected to the first scan signal line S1, and the second pole M72 of the initialization transistor M7 is electrically connected to the reference signal line Vref (e.g., the second reference signal line Vref 2). The gate of the data writing transistor M2 is electrically connected to the second scanning signal line S2, the first pole M21 of the data writing transistor M2 is electrically connected to the second pole M32 of the driving transistor M3, and the second pole M22 of the data writing transistor M2 is electrically connected to the data signal line Vdata. The gate of the additional transistor M4 is electrically connected to the second scan signal line S2, the first electrode M41 of the additional transistor M4 is electrically connected to the first electrode M31 of the driving transistor M3, and the second electrode M42 of the additional transistor M4 is electrically connected to the gate of the driving transistor M3. The gate of the emission control transistor M16 is electrically connected to the emission control signal line Emit. Along the thickness direction of the display panel, at least one reference signal line Vref at least partially overlaps at least one of the first power signal line PVDD, the second power signal line PVEE, the first scan signal line S1, the second scan signal line S2, the data signal line Vdata, and the emission control signal line Emit.

Further, the pixel circuit 101 further includes a capacitor Cst, a first electrode plate C1 of which is electrically connected to the gate electrode of the driving transistor M3, and a second electrode plate C2 of which is electrically connected to the first power signal line PVDD.

Specifically, as shown in fig. 3, the driving process of the pixel circuit 101 is, for example:

in the initialization stage, the first scan signal on the first scan signal line S1 turns on the reset transistor M5, and the reference voltage on the reference signal line Vref is applied to one end of the capacitor Cst through the reset transistor M5, that is, the potential of the first node N1 is the reference voltage, so as to reset the first node N1, and at this time, the potential of the gate of the driving transistor M3 is also the reference voltage.

Meanwhile, in the initialization stage, the first scan signal on the first scan signal line S1 makes the initialization transistor M7 also turned on, the initialization transistor M7 writes the reference voltage on the reference signal line Vref into the anode of the light emitting element 102, resets the anode potential of the light emitting element 102, and can reduce the influence of the anode voltage of the light emitting element 102 of the previous frame on the anode voltage of the light emitting element 102 of the next frame, thereby contributing to improving the display uniformity.

In the data signal voltage writing stage, the second scan signal on the second scan signal line S2 turns on the data writing transistor M2 and the additional transistor M4, and at this time, the gate potential of the driving transistor M3 is the reference voltage, the driving transistor M3 is also turned on, and the data signal voltage on the data signal line Vdata is applied to the first node N1 through the data writing transistor M2, the driving transistor M3 and the additional transistor M4, thereby writing the data signal voltage into the capacitor Cst.

In the light emitting stage, the light emitting control signal on the light emitting control signal line Emit turns on the light emitting control transistor M16, and a current path is formed between the first power signal line PVDD, the light emitting control transistor M16, the driving transistor M3, the light emitting element 102 and the second power signal line PVEE, so that the driving current generated by the driving transistor M3 is provided to the light emitting element 102, and the light emitting element 102 is driven to Emit light by the driving transistor M3, thereby realizing the light emitting and display functions of the display panel.

In this embodiment, along the thickness direction of the display panel, at least one reference signal line Vref is at least partially overlapped with at least one of the first power signal line PVDD, the second power signal line PVEE, the first scanning signal line S1, the second scanning signal line S2, the data signal line Vdata and the emission control signal line Emit, so that the shielding area of the reference signal line Vref and other signal lines in the thickness direction of the display panel is reduced, thereby facilitating to improve the light transmittance of the display panel, and when the display panel is correspondingly provided with an under-screen optical device such as an under-screen camera, the imaging performance of the under-screen optical device can be improved.

As illustrated in fig. 12 and 13, an overlapping region between the second signal line Vref1G and the second reference signal line Vref2, the first signal line Vref1R, and the first scanning signal line S1 may be provided along the thickness direction of the display panel, so as to reduce the shielding areas of the second signal line Vref1G, the second reference signal line Vref2, the first signal line Vref1R, and the first scanning signal line S1 in the thickness direction of the display panel, thereby contributing to improving the light transmittance of the display panel, and improving the imaging performance of the under-screen optical device when the display panel is correspondingly provided with the under-screen optical device such as an under-screen camera.

In another embodiment, with continued reference to fig. 12 and 13, along the thickness direction of the display panel, an overlapping region between the third signal line Vref1B and the light emission control signal line Emit, the second scanning signal line S2 and the data signal line Vdata may be further provided, so as to reduce the shielding area of the third signal line Vref1B, the light emission control signal line Emit, the second scanning signal line S2 and the data signal line Vdata in the thickness direction of the display panel, thereby helping to improve the light transmittance of the display panel, and when the display panel is correspondingly provided with an under-screen optical device such as an under-screen camera, the imaging performance of the under-screen optical device may be improved.

In other embodiments, any reference signal line Vref and any other signal line may be located in different film layers, and there is an overlapping area in the thickness direction of the display panel, for example, at least a portion of the reference signal line Vref and the first power signal line PVDD overlap each other along the thickness direction of the display panel, so as to achieve a corresponding technical effect.

With continued reference to fig. 12 and 13, optionally, at least one reference signal line Vref has a grid structure, and the grid structure includes a first sub-trace 51 and a second sub-trace 52 electrically connected to each other, and an extending direction of the first sub-trace 51 intersects an extending direction of the second sub-trace 52.

For example, as shown in fig. 13, taking the second signal line Vref1G as an example, the second signal line Vref1G is in a grid structure, where the grid structure includes a plurality of first sub-wires 51 and second sub-wires 52 that are cross-connected, and an extending direction (for example, a first direction X in the drawing) of the first sub-wires 51 and an extending direction (for example, a second direction Y in the drawing) of the second sub-wires 52 intersect, where by setting the second signal line Vref1G as a grid structure, a resistivity of the second signal line Vref1G can be reduced, and a voltage drop of a second reference voltage transmitted on the second signal line Vref1G is reduced, so that a second reference voltage potential transmitted on the second signal line Vref1G is more uniform, which is beneficial to improving uniformity of display brightness of the display panel.

It should be noted that, in the above embodiment, the second signal line Vref1G is only illustrated as a grid structure, and in other embodiments, any reference signal line Vref may be set to a grid structure, so as to reduce the resistivity of the reference signal line Vref and improve the uniformity of the display brightness of the display panel.

Fig. 17 is a schematic view of a partial cross-sectional structure of still another pixel circuit according to an embodiment of the present invention, and as shown in fig. 17, at least one reference signal line Vref includes a third sub-trace 53 and a fourth sub-trace 54 electrically connected to each other, where the third sub-trace 53 and the fourth sub-trace 54 are located in different layers, and the third sub-trace 53 and the fourth sub-trace 54 at least partially overlap along a thickness direction of the display panel.

Specifically, as shown in fig. 17, the reference signal line Vref includes a third sub-wiring 53 and a fourth sub-wiring 54 connected in parallel, and the third sub-wiring 53 and the fourth sub-wiring 54 are located in different film layers, where at least a portion of the reference signal line Vref adopts a dual-layer wiring manner connected in parallel, so that the resistivity of the reference signal line Vref can be reduced, and then the voltage drop of the reference voltage transmitted on the reference signal line Vref is reduced, so that the reference voltage potential transmitted on the reference signal line Vref is more uniform, which is beneficial to improving the uniformity of the display brightness of the display panel.

Further, the third sub-wiring 53 and the fourth sub-wiring 54 at least partially overlap, so that the third sub-wiring 53 and the fourth sub-wiring 54 are connected through punching, and meanwhile, the shading area of the third sub-wiring 53 and the fourth sub-wiring 54 can be reduced, the light transmittance of the display panel is improved, and when the display panel is correspondingly provided with an under-screen optical device such as an under-screen camera, the imaging performance of the under-screen optical device can be improved.

It should be noted that the above embodiment is described only by taking the example that the third sub-trace 53 and the fourth sub-trace 54 are located at opposite sides of the active layer 01 in the thickness direction of the display panel, but the present invention is not limited thereto. In other embodiments, the specific film layer arrangement and position arrangement of the third sub-trace 53 and the fourth sub-trace 54 may be set according to actual space requirements, which is not limited in the embodiment of the present invention.

Meanwhile, any reference signal line Vref can be configured as a double-layer wiring structure to reduce the resistivity, which is not particularly limited in the embodiment of the present invention.

Fig. 18 is a schematic structural view of a further pixel circuit according to an embodiment of the present invention, fig. 19 is a schematic structural view of a bottom reference signal line and a bottom metal layer in fig. 18, and fig. 20 is a schematic structural view of a partial cross section of a further pixel circuit according to an embodiment of the present invention, as shown in fig. 18 to fig. 20, optionally, a display panel according to an embodiment of the present invention further includes a substrate 00 and a bottom metal layer 60, the pixel circuit 101 includes at least one thin film transistor T, the thin film transistor T includes an active layer 01 and a source/drain electrode layer 03 stacked on one side of the substrate 00, and the source/drain electrode layer 03 is electrically connected to the active layer 01. The at least one thin film transistor T includes a driving transistor M3. The underlying metal layer 60 is located at a side of the active layer 01 close to the substrate 00, and the underlying metal layer 60 and the active layer 01 of the driving transistor M3 are at least partially overlapped in a thickness direction of the display panel. At least one reference signal line Vref and the underlying metal layer 60 are located in the same film.

Specifically, as shown in fig. 18 to 20, a bottom metal layer 60 is disposed on a side of the active layer 01 close to the substrate 00, and vertical projection of the bottom metal layer 60 on the substrate 00 and vertical projection of the active layer 01 of the driving transistor M3 on the substrate 00 are at least partially overlapped, so that a certain shading effect can be achieved on light rays emitted to the active layer 01 on the substrate 00 side through the bottom metal layer 60, which is helpful for reducing influence of the light rays on threshold voltage of the driving transistor M3, improving stability of the driving transistor M3, further ensuring more accurate light emitting brightness of the sub-pixel 10, and being beneficial for improving display effect.

Further, as shown in fig. 18 to 20, by arranging at least one reference signal line Vref and the underlying metal layer 60 on the same film layer, the arrangement of one metal layer can be reduced, thereby achieving the purposes of reducing the production cost and reducing the thickness of the display panel; meanwhile, the reference signal line Vref may be made of the same material as the underlying metal layer 60, so that the reference signal line Vref and the underlying metal layer 60 may be prepared in the same process, thereby shortening the process time.

The reference signal line Vref is insulated from the underlying metal layer 60, so as to avoid the performance of the driving transistor M3 from being affected by the reference voltage on the reference signal line Vref on the underlying metal layer 60.

It should be noted that, in fig. 18 and fig. 19, only the second signal line Vref1G and the third signal line Vref1B are illustrated as being located on the same film layer as the underlying metal layer 60, but the present invention is not limited thereto, and in other embodiments, any reference signal line Vref and the underlying metal layer 60 may be located on the same film layer to achieve the corresponding beneficial effects, and the embodiments of the present invention are not limited thereto.

In addition, in other embodiments, the reference signal line Vref may be located in the same layer as other signal lines, so as to reduce the metal layer, thereby reducing the production cost and the thickness of the display panel, and meanwhile, the process time may be shortened.

Based on the same inventive concept, the embodiment of the present invention further provides a display device, and fig. 21 is a schematic structural diagram of the display device provided in the embodiment of the present invention, as shown in fig. 21, the display device 70 includes a display panel 71 according to any embodiment of the present invention, so that the display device 70 provided in the embodiment of the present invention has the technical effects of the technical solution in any embodiment, and the same or corresponding structure and explanation of terms as those of the embodiment are not repeated herein.

The display device 70 provided in the embodiment of the present invention may be a mobile phone as shown in fig. 21, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the invention.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A display panel, comprising a plurality of sub-pixels and a plurality of reference signal lines;

2. The display panel of claim 1, wherein the display panel comprises,

the first signal line and the third signal line are the same signal line;

Or,

the first signal line and the second signal line are the same signal line.

3. The display panel of claim 1, wherein the display panel comprises,

the pixel circuit further includes a reset transistor having a first electrode electrically connected to the gate of the drive transistor;

the plurality of reference signal lines further comprise a second reference signal line electrically connected to a second pole of the reset transistor;

the reference voltage transmitted by the second reference signal line is different from the reference voltage transmitted by the first reference signal line.

4. The display panel according to claim 3, wherein,

the second reference signal line includes a fourth signal line, a fifth signal line, and a sixth signal line;

the fourth signal line is electrically connected to the reset transistor of the pixel circuit in the red sub-pixel, the fifth signal line is electrically connected to the reset transistor of the pixel circuit in the green sub-pixel, and the sixth signal line is electrically connected to the reset transistor of the pixel circuit in the blue sub-pixel;

the fourth signal line is used for transmitting a fourth reference voltage, the fifth signal line is used for transmitting a fifth reference voltage, and the sixth signal line is used for transmitting a sixth reference voltage;

At least two of the fourth reference voltage, the fifth reference voltage, and the sixth reference voltage are different.

5. The display panel of claim 1, wherein the display panel comprises,

the pixel circuit further includes a data writing transistor, a first electrode of the data writing transistor being electrically connected to a second electrode of the driving transistor;

the display panel further comprises a second scanning signal line extending along a first direction and a data signal line extending along a second direction, wherein the second scanning signal line is electrically connected with a gate electrode of the data writing transistor, and the data signal line is electrically connected with a second electrode of the data writing transistor, and the first direction and the second direction intersect; in the same pixel circuit, along the second direction, the reference signal line is located at a side of the second scanning signal line away from the driving transistor, and at least two reference signal lines are located at different film layers.

6. The display panel of claim 5, wherein the display panel comprises,

The display panel further includes a first scan signal line extending in the first direction, the first scan signal line being electrically connected to a gate of the reset transistor;

in the same pixel circuit, along the second direction, the first scanning signal line is located at a side of the second scanning signal line away from the driving transistor;

in the same pixel circuit, at least two reference signal lines located in different film layers are located at one side of the first scanning signal line away from the second scanning signal line along the second direction, and at least partially overlap between the reference signal lines located in different film layers along the thickness direction of the display panel.

7. The display panel of claim 1, wherein the display panel comprises,

the display panel further comprises a substrate, the pixel circuit comprises at least one thin film transistor, the thin film transistor comprises an active layer and a source-drain electrode layer which are stacked on one side of the substrate, and the source-drain electrode layer is electrically connected with the active layer;

at least one of the thin film transistors includes the driving transistor;

at least one reference signal line is positioned on one side of the active layer close to the substrate base plate, and the reference signal line positioned on one side of the active layer close to the substrate base plate is a bottom layer reference signal line;

The underlying reference signal line and the active layer of the driving transistor at least partially overlap in a thickness direction of the display panel.

8. The display panel of claim 7, wherein the display panel comprises,

the display panel further comprises a first insulating layer, a second insulating layer and a connecting metal layer, wherein the first insulating layer is positioned between the bottom reference signal line and the active layer, the second insulating layer is positioned between the active layer and the source drain electrode layer, and the connecting metal layer and the source drain electrode layer are positioned on the same film layer;

the display panel further comprises at least one connecting via hole, wherein at least one connecting via hole comprises a first via hole and a second via hole, the first via hole penetrates through the first insulating layer and the second insulating layer, and the second via hole penetrates through the second insulating layer;

the connection metal layer and the first via hole at least partially overlap, the connection metal layer and the second via hole at least partially overlap, the underlying reference signal line and the first via hole at least partially overlap, and the active layer and the second via hole at least partially overlap along a thickness direction of the display panel;

The bottom layer reference signal line is electrically connected with the connection metal layer through the first via hole, and the connection metal layer is electrically connected with the active layer through the second via hole.

9. The display panel of claim 7, wherein the display panel comprises,

the display panel further comprises a first insulating layer, wherein the first insulating layer is positioned between the bottom layer reference signal line and the active layer;

the display panel further comprises at least one connecting via hole, wherein at least one connecting via hole comprises a third via hole, and the third via hole penetrates through the first insulating layer;

the bottom layer reference signal line and the third via hole at least partially overlap in a thickness direction of the display panel, and the active layer and the third via hole at least partially overlap;

the bottom layer reference signal line is electrically connected with the active layer through the third via hole.

10. The display panel according to claim 8 or 9, wherein,

the pixel circuit further comprises a data writing transistor and a reset transistor, wherein a first pole of the data writing transistor is electrically connected with a second pole of the driving transistor, and a first pole of the reset transistor is electrically connected with a grid electrode of the driving transistor;

The display panel further includes first and second scan signal lines extending in a first direction, and a data signal line extending in a second direction; the first scanning signal line is electrically connected with the grid electrode of the reset transistor; the second scanning signal line is electrically connected with the grid electrode of the data writing transistor; the data signal line is electrically connected with a second pole of the data writing transistor, wherein the first direction and the second direction intersect;

in the same pixel circuit, the connection via is located between the first scanning signal line and the second scanning signal line along the second direction.

11. The display panel of claim 1, wherein the display panel comprises,

the display panel further comprises a first power signal line, a second power signal line, a first scanning signal line, a second scanning signal line, a data signal line and a light-emitting control signal line;

the pixel circuit further includes a reset transistor, a data writing transistor, an additional transistor, and a light emission control transistor;

the first power supply signal line is used for transmitting a first power supply voltage, the second power supply signal line is used for transmitting a second power supply voltage, and the first power supply voltage is larger than the second power supply voltage;

The driving transistor, the light emission control transistor, and the light emitting element are connected in series between the first power supply signal line and the second power supply signal line;

the grid electrode of the reset transistor is electrically connected with the first scanning signal line, the first electrode of the reset transistor is electrically connected with the grid electrode of the driving transistor, and the second electrode of the reset transistor is electrically connected with the reference signal line;

the grid electrode of the initializing transistor is electrically connected with the first scanning signal line, and the second electrode of the initializing transistor is electrically connected with the reference signal line;

the grid electrode of the data writing transistor is electrically connected with the second scanning signal line, the first electrode of the data writing transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the data writing transistor is electrically connected with the data signal line;

the grid electrode of the additional transistor is electrically connected with the second scanning signal line, the first electrode of the additional transistor is electrically connected with the first electrode of the driving transistor, and the second electrode of the additional transistor is electrically connected with the grid electrode of the driving transistor;

the grid electrode of the light-emitting control transistor is electrically connected with the light-emitting control signal line;

At least one of the reference signal lines at least partially overlaps at least one of the first power signal line, the second power signal line, the first scan signal line, the second scan signal line, the data signal line, and the light emission control signal line in a thickness direction of the display panel.

12. The display panel of claim 1, wherein the display panel comprises,

at least one reference signal line is in a grid structure, and the grid structure comprises a first sub-wiring and a second sub-wiring which are mutually and electrically connected;

the extending direction of the first sub-wiring is intersected with the extending direction of the second sub-wiring.

13. The display panel of claim 1, wherein the display panel comprises,

at least one reference signal line comprises a third sub-wiring and a fourth sub-wiring which are electrically connected with each other;

the third sub-wiring and the fourth sub-wiring are located in different film layers, and at least partially overlap with each other along the thickness direction of the display panel.

14. The display panel of claim 1, wherein the display panel comprises,

the display panel also comprises a substrate base plate and a bottom metal layer, the pixel circuit comprises at least one thin film transistor, the thin film transistor comprises an active layer and a source-drain electrode layer, the active layer and the source-drain electrode layer are arranged on one side of the substrate base plate in a stacked mode, and the source-drain electrode layer and the active layer are electrically connected;

At least one of the thin film transistors includes the driving transistor;

the bottom metal layer is positioned on one side of the active layer, which is close to the substrate base plate, and at least partially overlapped with the active layer of the driving transistor along the thickness direction of the display panel;

at least one of the reference signal lines and the underlying metal layer are located in the same film layer.

15. A display device comprising the display panel of any one of claims 1-14.