CN117055817A - Data packet memory device and storage method based on single-port RAM - Google Patents
Data packet memory device and storage method based on single-port RAM Download PDFInfo
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- CN117055817A CN117055817A CN202311071559.9A CN202311071559A CN117055817A CN 117055817 A CN117055817 A CN 117055817A CN 202311071559 A CN202311071559 A CN 202311071559A CN 117055817 A CN117055817 A CN 117055817A
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- 238000000034 method Methods 0.000 title claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention belongs to the technical field of data packet storage, and particularly relates to a data packet storage device based on a single-port RAM, which comprises an address allocation module: for assigning a RAM address to each incoming data packet; an information storage module: the related information is used for recording the data packet; UP module: for increasing the data width of the incoming data packet interface; RAM write operation module: the system is respectively connected with the information storage module, the distribution module and the UP module and is used for converting the existing information into writing operation on the RAM; RAM read operation module: the information storage module is connected with the RAM and used for converting the existing information into read operation of the RAM; an arbiter: the system comprises a RAM write operation module, a RAM read operation module and a RAM read operation module, wherein the RAM write operation module and the RAM read operation module are respectively connected with the RAM write operation module and the RAM read operation module and are used for determining the priority of the operation when the read and/or write operation occurs; single port RAM module: for storing the data packets. The defects of the prior art are overcome, PID addressing of the data packet is adopted, and meanwhile, the high data rate single-port RAM is used for meeting the requirements.
Description
Technical Field
The invention belongs to the technical field of data packet storage, and particularly relates to a data packet storage device and a data packet storage method based on a single-port RAM.
Background
As information technology has entered the data age, the dramatic increase in data volume has prompted storage systems to continually increase the number of devices and capacity, and large distributed storage systems have grown and have evolved rapidly. The distributed storage system adopts an expandable system structure, utilizes a plurality of storage servers to share the storage load, utilizes the position servers to position the storage information, has the characteristics of higher storage reliability, availability, expandability and the like, and becomes the most main mode for storing the data information at present.
The current data storage and reading generally adopts the form of FIFO, and the method can buffer the data very conveniently. But this technique generally requires implementation using dual port RAM and takes up a large amount of area for the storage of a large number of data packets. Meanwhile, for a packet-based data transmission channel, buffering of data is an aspect, and some protocols also need to support retransmission of data packets, where the FIFO cannot support this feature.
Disclosure of Invention
The invention aims to provide a data packet memory device based on a single-port RAM, which overcomes the defects of the prior art, adopts PID addressing of data packets, and simultaneously uses the single-port RAM with high data rate to meet the demands.
In order to solve the problems, the technical scheme adopted by the invention is as follows:
a packet memory device based on single port RAM comprises
An address allocation module: for assigning a RAM address to each incoming data packet;
an information storage module: the related information is used for recording the data packet;
UP module: for increasing the data width of the incoming data packet interface;
RAM write operation module: the system is respectively connected with the information storage module, the distribution module and the UP module and is used for converting the existing information into writing operation on the RAM;
RAM read operation module: the information storage module is connected with the RAM and used for converting the existing information into read operation of the RAM;
an arbiter: the system comprises a RAM write operation module, a RAM read operation module and a RAM read operation module, wherein the RAM write operation module and the RAM read operation module are respectively connected with the RAM write operation module and the RAM read operation module and are used for determining the priority of the operation when the read and/or write operation occurs;
single port RAM module: for storing the data packets.
Further, the information stored by the information storage module includes: the RAM address of the data packet, the validity of the data packet, and the location of the start Byte of the data packet in the RAM Item.
Further, when the read and write operations occur simultaneously, the preset priority in the arbiter is that the priority of the read operation is higher than that of the write operation.
Further, a temporary storage module is arranged between the RAM writing operation module and the arbiter, and is used for temporarily storing the writing operation when the reading operation and the writing operation occur simultaneously, and outputting the writing operation after the reading operation is completed.
The invention also discloses a storage method of the data packet memory based on the single-port RAM, which comprises the following steps:
step 1, judging whether the data packet is a retransmitted data packet according to the PID of the data packet after the data packet is transmitted, if yes, acquiring the RAM address of the data packet from an information storage module, then entering step 3, and if not, entering step 2;
step 2, distributing RAM addresses through an address distribution module, and recording the related information of the data packet into an information storage module;
step 3, the data packet transmission UP module doubles or becomes 4 times the data rate of the data packet;
step 4, the RAM write operation module generates write operation to the RAM;
step 5, reading PID of the data packet, obtaining the initial address and the validity of the data packet from the information storage module, judging whether the data packet is valid, if the data packet is valid, entering step 6, and if the data packet is invalid, reading the data packet, and selecting to wait or skip the data packet;
step 6, the RAM read operation module generates read operation on the RAM;
step 7, the write operation generated in the step 4 and the read operation generated in the step 6 are transmitted to an arbiter, and the operation is performed according to the priority through the arbiter;
step 8, in the single-port RAM module, if the single-port RAM module is in a writing operation, writing data into the RAM; if the data is read, the data with doubled width is taken out;
step 9, the data with doubled width is converted back to the low data bit width after being taken out, and the correct data packet starting position is selected according to the position of the data packet starting Byte recorded in the information storage module in one RAM data.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention adopts PID addressing of the data packet to store and read the data packet in a convenient form, thereby improving the efficiency of data storage and reading.
2. The invention distinguishes the newly uploaded data packet from the re-uploaded data packet by identifying the data packet, and the re-uploaded data packet is not allocated with addresses, and still uses the original packet address space, thereby improving the efficiency of storage and reading.
3. The invention adopts the single-port RAM module to store data, and compared with the double-port RAM module, the single-port RAM module reduces the area by 2-3 times.
Drawings
Fig. 1 is a schematic diagram of a packet memory device based on a single port RAM.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the packet memory device based on a single port RAM of the present invention includes an address allocation module: for assigning a RAM address to each incoming data packet;
an information storage module: the related information is used for recording the data packet;
UP module: for increasing the data width of the incoming data packet interface;
RAM write operation module: the system is respectively connected with the information storage module, the distribution module and the UP module and is used for converting the existing information into writing operation on the RAM;
RAM read operation module: the information storage module is connected with the RAM and used for converting the existing information into read operation of the RAM;
an arbiter: the system comprises a RAM write operation module, a RAM read operation module and a RAM read operation module, wherein the RAM write operation module and the RAM read operation module are respectively connected with the RAM write operation module and the RAM read operation module and are used for determining the priority of the operation when the read and/or write operation occurs;
single port RAM module: for storing the data packets.
The information stored by the information storage module comprises: the RAM address of the data packet, the validity of the data packet, and the location of the start Byte of the data packet in the RAM Item.
When the read and write operations occur simultaneously, the preset priority in the arbiter is that the priority of the read operation is higher than the priority of the write operation.
The temporary storage module is arranged between the RAM writing operation module and the arbiter and is used for temporarily storing the writing operation when the reading operation and the writing operation occur simultaneously and outputting the writing operation after the reading operation is completed.
In summary, the method for storing the data packet memory device based on the single port RAM of the present invention includes the following steps:
step 1, judging whether the data packet is a retransmitted data packet according to the PID of the data packet after the data packet is transmitted, if yes, acquiring the RAM address of the data packet from an information storage module, then entering step 3, and if not, entering step 2;
step 2, distributing RAM addresses through an address distribution module, and recording the related information of the data packet into an information storage module;
step 3, the data packet transmission UP module doubles or becomes 4 times the data rate of the data packet;
step 4, the RAM write operation module generates write operation to the RAM;
step 5, reading PID of the data packet, obtaining the initial address and the validity of the data packet from the information storage module, judging whether the data packet is valid, if the data packet is valid, entering step 6, and if the data packet is invalid, reading the data packet, and selecting to wait or skip the data packet;
step 6, the RAM read operation module generates read operation on the RAM;
step 7, the write operation generated in the step 4 and the read operation generated in the step 6 are transmitted to an arbiter, and the operation is performed according to the priority through the arbiter; when the read-write operations occur simultaneously, firstly, the arbiter executes the read operation according to the principle of priority of the read operation, temporarily stores the write operation in the temporary storage module at the moment, and then executes the write operation in the temporary storage module after the read operation is completed;
step 8, in the single-port RAM module, if the single-port RAM module is in a writing operation, writing data into the RAM; if the data is read, the data with doubled width is taken out;
step 9, the data with doubled width is converted back to the low data bit width after being taken out, and the correct data packet starting position is selected according to the position of the data packet starting Byte recorded in the information storage module in one RAM data.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (5)
1. A single port RAM based packet memory device, characterized by: comprising
An address allocation module: for assigning a RAM address to each incoming data packet;
an information storage module: the related information is used for recording the data packet;
UP module: for increasing the data width of the incoming data packet interface;
RAM write operation module: the system is respectively connected with the information storage module, the distribution module and the UP module and is used for converting the existing information into writing operation on the RAM;
RAM read operation module: the information storage module is connected with the RAM and used for converting the existing information into read operation of the RAM;
an arbiter: the system comprises a RAM write operation module, a RAM read operation module and a RAM read operation module, wherein the RAM write operation module and the RAM read operation module are respectively connected with the RAM write operation module and the RAM read operation module and are used for determining the priority of the operation when the read and/or write operation occurs;
single port RAM module: for storing the data packets.
2. A single port RAM based packet memory device as claimed in claim 1 wherein: the information stored by the information storage module comprises: the RAM address of the data packet, the validity of the data packet, and the location of the start Byte of the data packet in the RAM Item.
3. A single port RAM based packet memory device as claimed in claim 1 wherein: when the read-write operations occur simultaneously, the preset priority in the arbiter is that the priority of the read operation is higher than that of the write operation.
4. A single port RAM based packet memory device as claimed in claim 3 wherein: the RAM writing operation module is used for temporarily storing writing operation when the reading operation and the writing operation occur simultaneously, and outputting writing operation after the reading operation is completed.
5. A method for storing a single port RAM based packet memory according to any one of claims 1 to 4, characterized by: the method comprises the following steps:
step 1, judging whether the data packet is a retransmitted data packet according to the PID of the data packet after the data packet is transmitted, if yes, acquiring the RAM address of the data packet from an information storage module, then entering step 3, and if not, entering step 2;
step 2, distributing RAM addresses through an address distribution module, and recording the related information of the data packet into an information storage module;
step 3, the data packet transmission UP module doubles or becomes 4 times the data rate of the data packet;
step 4, the RAM write operation module generates write operation to the RAM;
step 5, reading PID of the data packet, obtaining the initial address and the validity of the data packet from the information storage module, judging whether the data packet is valid, if the data packet is valid, entering step 6, and if the data packet is invalid, reading the data packet, and selecting to wait or skip the data packet;
step 6, the RAM read operation module generates read operation on the RAM;
step 7, the write operation generated in the step 4 and the read operation generated in the step 6 are transmitted to an arbiter, and the operation is performed according to the priority through the arbiter;
step 8, in the single-port RAM module, if the single-port RAM module is in a writing operation, writing data into the RAM; if the data is read, the data with doubled width is taken out;
step 9, the data with doubled width is converted back to the low data bit width after being taken out, and the correct data packet starting position is selected according to the position of the data packet starting Byte recorded in the information storage module in one RAM data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311071559.9A CN117055817A (en) | 2023-08-24 | 2023-08-24 | Data packet memory device and storage method based on single-port RAM |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311071559.9A CN117055817A (en) | 2023-08-24 | 2023-08-24 | Data packet memory device and storage method based on single-port RAM |
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| CN117055817A true CN117055817A (en) | 2023-11-14 |
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| CN202311071559.9A Pending CN117055817A (en) | 2023-08-24 | 2023-08-24 | Data packet memory device and storage method based on single-port RAM |
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- 2023-08-24 CN CN202311071559.9A patent/CN117055817A/en active Pending
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