CN117042465A

CN117042465A - Semiconductor structure and forming method thereof

Info

Publication number: CN117042465A
Application number: CN202310988096.6A
Authority: CN
Inventors: 谈亚丽
Original assignee: Changxin Technology Group Co ltd
Current assignee: Changxin Technology Group Co ltd
Priority date: 2023-08-04
Filing date: 2023-08-04
Publication date: 2023-11-10

Abstract

The present disclosure provides a semiconductor structure and a method of forming the same, the method of forming the semiconductor structure comprising: providing a substrate, wherein the substrate comprises a substrate, a first sacrificial layer and an insulating layer which are stacked and arranged along a first direction, and a groove penetrating through the insulating layer along the first direction and exposing the first sacrificial layer; the first direction is the thickness direction of the substrate; forming at least one second sacrificial layer, a plurality of dielectric layers and a plurality of third sacrificial layers which are arranged along a second direction in the groove; the dielectric layers and the third sacrificial layers are alternately arranged along the second direction; the second sacrificial layer is in direct contact with the insulating layer and the dielectric layer; the second direction is perpendicular to the first direction; removing the first sacrificial layer and the plurality of third sacrificial layers to form a first gap, and filling semiconductor materials in the first gap; and removing part of the dielectric layer along the first direction to form a plurality of second gaps, and filling the semiconductor material in the plurality of second gaps.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same.

Background

The magnetic random access memory (Magnetic Random Access Memory, MRAM) is a new type of nonvolatile random access memory (Non-Volatile Random Access Memory, NVRAM), and has excellent characteristics such as Non-volatile, high speed, high density, and low consumption, compared with other memory technologies, and is considered to be an ideal memory in electronic devices. MRAM uses magnetic tunnel junctions (Magnetic Tunnel Junction, MTJ) to store data, and how to increase the drive current applied to the magnetic tunnel junctions to improve the reliability of data writing is a current challenge.

Disclosure of Invention

Accordingly, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same to solve at least one of the problems in the prior art.

In order to achieve the above object, the technical solution of the embodiments of the present disclosure is implemented as follows:

in a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, including:

providing a substrate, wherein the substrate comprises a substrate, a first sacrificial layer and an insulating layer which are stacked and arranged along a first direction, and a groove penetrating the insulating layer along the first direction and exposing the first sacrificial layer; the first direction is the thickness direction of the substrate;

forming at least one second sacrificial layer, a plurality of dielectric layers and a plurality of third sacrificial layers which are arranged along a second direction in the groove; the dielectric layers and the third sacrificial layers are alternately arranged along the second direction; the second sacrificial layer is in direct contact with the insulating layer and the dielectric layer; the second direction is perpendicular to the first direction;

removing the first sacrificial layer and the plurality of third sacrificial layers to form a first gap, and filling semiconductor materials in the first gap;

and removing part of the dielectric layer along the first direction to form a plurality of second gaps, and filling the semiconductor material in the second gaps.

In an alternative embodiment, the forming at least one second sacrificial layer, a plurality of dielectric layers, and a plurality of third sacrificial layers arranged along the second direction in the trench includes:

forming a second sacrificial layer in the trench; the second sacrificial layer covers the side wall of the groove;

alternately forming the dielectric layer and the third sacrificial layer; the second sacrificial layer surrounds the dielectric layer closest to the insulating layer; the dielectric layer surrounds the third sacrificial layer on one side of the dielectric layer away from the second sacrificial layer; the third sacrificial layer surrounds the dielectric layer on a side of the third sacrificial layer away from the second sacrificial layer.

forming two second sacrificial layers on two opposite side walls of the groove along the second direction respectively;

the dielectric layers and the third sacrificial layers are alternately formed to form the dielectric layers and the third sacrificial layers which are located between the two second sacrificial layers and are alternately arranged along the second direction.

In an alternative embodiment, the removing the first sacrificial layer and the plurality of third sacrificial layers to form a first void and filling the first void with a semiconductor material includes:

removing the third sacrificial layers to form a plurality of first sub-voids;

removing the first sacrificial layer to form a second sub-void in communication with the plurality of first sub-voids;

filling the semiconductor material in the second sub-gaps to form first electrode structures in the second sub-gaps, and filling the semiconductor material in the plurality of first sub-gaps;

after the semiconductor material is filled in the second gaps, the rest dielectric layers form a plurality of gate dielectric layers, the semiconductor material between the gate dielectric layers forms a plurality of channel layers, and the semiconductor material on the gate dielectric layers and the channel layers forms a second electrode structure.

In an alternative embodiment, the method for forming a semiconductor structure further includes:

removing the second sacrificial layer to form a third gap, and forming a conductive layer in the third gap;

removing a part of the conductive layer along the first direction to form a fourth gap, forming a blocking structure in the fourth gap, and forming a gate electrode by the rest of the conductive layer; the bottom surface of the blocking structure is flush with the top surface of the gate dielectric layer; the top surface of the blocking structure is flush with the top surface of the second electrode structure.

forming an electrode contact structure on the second electrode structure;

forming a magnetic tunnel junction overlying the electrode contact structure; the magnetic tunnel junction includes a fixed layer, a tunnel layer, and a free layer stacked in the first direction.

In a second aspect, embodiments of the present disclosure provide a semiconductor structure comprising:

a substrate, a first electrode structure, and an insulating layer stacked and arranged along a first direction; the first direction is the thickness direction of the substrate;

at least one gate electrode, a plurality of gate dielectric layers and a plurality of channel layers, which are arranged along a second direction and are positioned in the insulating layer, and are positioned on the first electrode structure; the gate dielectric layers and the channel layers are alternately arranged along the second direction; the grid electrode is in direct contact with the insulating layer and the grid electrode dielectric layer; the second direction is perpendicular to the first direction;

and a second electrode structure located on the plurality of gate dielectric layers and the plurality of channel layers.

In an alternative embodiment, the semiconductor structure includes a gate; the gate encloses the gate dielectric layer closest to the insulating layer; the grid dielectric layer surrounds the channel layer on one side of the grid dielectric layer away from the grid; the channel layer surrounds the gate dielectric layer on a side of the channel layer remote from the gate.

In an alternative embodiment, the semiconductor structure includes two gates opposing in the second direction; the gate dielectric layers and the channel layers are located between the two gates and are alternately arranged along the second direction.

In an alternative embodiment, the semiconductor structure further includes:

a blocking structure located on the gate; the bottom surface of the blocking structure is flush with the top surface of the gate dielectric layer; the top surface of the blocking structure is flush with the top surface of the second electrode structure;

an electrode contact structure located on the second electrode structure;

a magnetic tunnel junction overlying the electrode contact structure; the magnetic tunnel junction includes a fixed layer, a tunnel layer, and a free layer stacked in the first direction.

In the technical scheme provided by the disclosure, the vertical transistor is used as a driving device of the magnetic tunnel junction, and the contact area between the gate dielectric layer and the channel layer is increased by forming the plurality of gate dielectric layers and the channel layer which are alternately arranged in the direction perpendicular to the thickness direction of the substrate, so that the concentration of carriers is increased under the condition that the channel layer is kept to have smaller thickness, thereby improving the control capability of the gate and the driving capability of the vertical transistor at the same time and improving the reliability of data writing.

Drawings

Fig. 1 is a flow chart illustrating a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 2 to 22 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present disclosure;

fig. 23 and 24 are schematic structural diagrams of a semiconductor structure according to another embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, like numbers refer to like elements throughout.

It will be appreciated that spatially relative terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

MRAM uses a magnetic tunnel junction to effect storage of data, the magnetic tunnel junction comprising a fixed layer, a tunnel layer, and a free layer stacked in sequence, the data being written in such a way that a magnetic field is generated by a current to cause a magnetic moment of the free layer to flip. Specifically, when current flows from the fixed layer to the free layer, electrons with spin directions consistent with the magnetization direction of the fixed layer more easily pass through the fixed layer and generate polarized electrons consistent with the magnetization direction of the fixed layer, when the polarized electrons reach the free layer through the fixed layer, a moment is generated on the magnetic moment of the free layer, the moment makes the magnetization direction of the free layer turn to a direction parallel to the fixed layer, and electrons opposite to the magnetization direction of the free layer are reflected back to the fixed layer to generate a moment for rotating the magnetization direction of the fixed layer, but the moment cannot rotate the magnetization direction of the fixed layer, finally, the magnetization direction of the free layer is parallel to the magnetization direction of the fixed layer, and the magnetic tunnel junction is in a low-resistance state to complete the writing of '0'; when current flows from the free layer to the fixed layer, electrons with the spin direction consistent with the magnetization direction of the free layer more easily pass through the free layer and generate polarized electrons consistent with the magnetization direction of the free layer, when the polarized electrons pass through the free layer to reach the fixed layer, a moment is generated on the magnetic moment of the fixed layer, the moment cannot rotate the magnetization direction of the fixed layer, electrons with the spin direction opposite to the magnetization direction of the fixed layer are reflected back to the free layer, a moment for rotating the magnetization direction of the free layer is generated, finally, the magnetization direction of the free layer and the magnetization direction of the fixed layer are antiparallel, the magnetic tunnel junction is in a high resistance state, and writing of '1' is completed.

In the process of writing data, a larger driving current is needed to generate a magnetic field so that the magnetic moment of the free layer of the magnetic tunnel junction is inverted, the driving current is usually provided by a driving device connected with the magnetic tunnel junction, the driving device can be a logic device or a transistor, the logic device can provide a driving current above 400uA/um, but the occupied area is larger, the improvement of the integration level of the MRAM is not facilitated, and therefore, in order to realize the high-density application of the MRAM, the reliability of writing data needs to be improved by improving the driving capability of the transistor. In this regard, the present disclosure proposes the following embodiments.

The disclosure provides a method for forming a semiconductor structure, and fig. 1 is a schematic flow chart of the method for forming a semiconductor structure provided by the disclosure, as shown in fig. 1, the method for forming a semiconductor structure includes the following steps:

step S10: providing a substrate, wherein the substrate comprises a substrate, a first sacrificial layer and an insulating layer which are stacked and arranged along a first direction, and a groove penetrating the insulating layer along the first direction and exposing the first sacrificial layer; the first direction is the thickness direction of the substrate;

step S20: forming at least one second sacrificial layer, a plurality of dielectric layers and a plurality of third sacrificial layers which are arranged along a second direction in the groove; the dielectric layers and the third sacrificial layers are alternately arranged along the second direction; the second sacrificial layer is in direct contact with the insulating layer and the dielectric layer; the second direction is perpendicular to the first direction;

step S30: removing the first sacrificial layer and the plurality of third sacrificial layers to form a first gap, and filling semiconductor materials in the first gap;

step S40: and removing part of the dielectric layer along the first direction to form a plurality of second gaps, and filling the semiconductor material in the second gaps.

Fig. 2 to 22 are schematic structural views of a semiconductor structure forming process according to an embodiment of the present disclosure, and a method for forming a semiconductor structure according to the present disclosure will be described in detail with reference to fig. 1 and 2 to 22.

Referring to fig. 2 and 3 in combination, step S10 is performed to provide a base including a substrate 101, a first sacrificial layer 102, and an insulating layer 103 stacked in a first direction, and a trench 104 penetrating the insulating layer 103 in the first direction and exposing the first sacrificial layer 102.

In some specific examples, the substrate 101 may be a simple substance semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (e.g., a silicon germanium substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.; the material of the first sacrificial layer 102 includes, but is not limited to, silicon germanium; the material of the insulating layer 103 includes, but is not limited to, monocrystalline silicon.

In some specific examples, after the substrate 101 forms the first sacrificial layer 102 and the insulating layer 103, the insulating layer 103 is etched in a first direction to form a trench 104 exposing the first sacrificial layer 102.

Referring to fig. 3 and 4 in combination, step S20 is performed to form at least one second sacrificial layer 201, a plurality of dielectric layers 202, and a plurality of third sacrificial layers 203 arranged in a second direction in the trench 104; the dielectric layers 202 and the third sacrificial layers 203 are alternately arranged along the second direction; the second sacrificial layer 201 is in direct contact with the insulating layer 103 and the dielectric layer 202.

In the embodiment of the present disclosure, the first direction is a thickness direction of the substrate 101, the second direction is perpendicular to the first direction, the first direction may be a Z direction, and the second direction may be an X direction.

In some specific examples, the material of the second sacrificial layer 201 includes, but is not limited to, silicon oxynitride; the material of the third sacrificial layer 203 includes, but is not limited to, silicon nitride; the material of the dielectric layer 202 may include a high dielectric constant material or silicon oxide, wherein the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In some embodiments, the specific process of performing step S20 may include: forming a second sacrificial layer 201 in the trench 104 by a deposition process, and the second sacrificial layer 201 covers the entire sidewall of the trench 104; alternating the formation of the dielectric layer 202 and the third sacrificial layer 203 by a deposition process, and the second sacrificial layer 201 surrounding the dielectric layer 202 closest to the insulating layer 103, the dielectric layer 202 surrounding the third sacrificial layer 203 on the side of the dielectric layer 202 remote from the second sacrificial layer 201; the third sacrificial layer 203 encloses the dielectric layer 202 on the side of the third sacrificial layer 203 remote from the second sacrificial layer 201.

In embodiments of the present disclosure, deposition processes include, but are not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), physical vapor deposition (Physical Vapor Deposition, PVD), and atomic layer deposition (Atomic Layer Deposition, ALD).

In a specific example, fig. 5 is a cross-sectional view along line AA' of fig. 4, and referring to fig. 3, 4 and 5 in combination, the cross-section of the trench 104 is circular, one second sacrificial layer 201, two dielectric layers 202 and two third sacrificial layers 203 are formed in the trench 104, and the dielectric layers 202 and the third sacrificial layers 203 are alternately arranged.

In another specific example, fig. 6 is a cross-sectional view along line AA' of fig. 4, and referring to fig. 3, 4, and 6 in combination, the cross-section of the trench 104 is rectangular, one second sacrificial layer 201, two dielectric layers 202, and two third sacrificial layers 203 are formed in the trench 104, and the dielectric layers 202 and the third sacrificial layers 203 are alternately arranged.

In other embodiments, the specific process of performing step S20 may include: forming two second sacrificial layers 201 on two opposite sidewalls of the trench 104 in the second direction, respectively, by a deposition process; the dielectric layers 202 and the third sacrificial layers 203 are alternately formed by a deposition process to form the dielectric layers 202 and the third sacrificial layers 203 which are located between the two second sacrificial layers 201 and are alternately arranged in the second direction.

In a specific example, fig. 7 is a cross-sectional view taken along line AA' of fig. 4, and referring to fig. 3, 4 and 7 in combination, the cross-section of the trench 104 is rectangular, two second sacrificial layers 201 are formed on two opposite sidewalls of the trench 104 in the second direction, respectively, and four dielectric layers 202 and three third sacrificial layers 203 are formed, and the dielectric layers 202 and the third sacrificial layers 203 are located between the two second sacrificial layers 201 and are alternately arranged in the second direction.

It should be noted that, in the above example, the shape of the cross section of the trench 104 and the specific number of the second sacrificial layer 201, the dielectric layer 202, and the third sacrificial layer 203 are merely examples, and the present disclosure is not limited to the shape of the cross section of the trench 104 and the specific number of the second sacrificial layer 201, the dielectric layer 202, and the third sacrificial layer 203 in the case where it is satisfied that the dielectric layer 202 and the third sacrificial layer 203 are alternately arranged in the second direction and the second sacrificial layer 201 is in direct contact with the insulating layer 103 and the dielectric layer 202.

Referring to fig. 4, 8 to 10 in combination, step S30 is performed to remove the first sacrificial layer 102 and the plurality of third sacrificial layers 203 to form a first void 301, and fill the first void 301 with a semiconductor material.

In some embodiments, performing the specific process of step S30 may include: referring to fig. 4 and 8 in combination, the plurality of third sacrificial layers 203 are removed to form a plurality of first sub-voids 3011 extending in the first direction; referring to fig. 8 and 9; removing the first sacrificial layer 102 to form a second sub-void 3012 communicating with the plurality of first sub-voids 3011, the first sub-void 3011 and the plurality of second sub-voids 3012 constituting the first void 301; referring to fig. 9 and 10 in combination, a semiconductor material is filled in the second sub-void 3012 to form a first electrode structure 302 in the second sub-void 3012, and the semiconductor material is filled in the first sub-void 3011.

In some specific examples, the third sacrificial layer 203 may be removed by a wet etching process, and a material of the third sacrificial layer 203 has a large etching selectivity ratio to a material of other structures. After the third sacrificial layer 203 is removed, the ratio of the etching solution can be changed, and the first sacrificial layer 102 is removed by a wet etching process, so that the material of the first sacrificial layer 102 and the material of other structures also have a larger etching selection ratio.

In other specific examples, the third sacrificial layer 203 may be removed by a dry etching process, and then the first sacrificial layer 102 may be removed by a wet etching process. Here, the dry Etching process may be one of Plasma Etching (PE), sputter Etching (Sputtering Etching, SE), ion Beam Etching (IBE), and reactive Ion Etching (Reactive Ion Etching, RIE).

In some specific examples, the semiconductor material may be silicon or germanium.

In other specific examples, the semiconductor material may be a low leakage material, such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), in order to further reduce the size of the device.

In some embodiments, after performing step S30, the method for forming a semiconductor structure further includes: referring to fig. 10 and 11 in combination, the second sacrificial layer 201 is removed to form a third void 303; referring to fig. 11 and 12 in combination, a conductive layer 304 is formed in the third void 303.

In some specific examples, the material of the conductive layer 304 may be one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

Referring to fig. 12 to 14 in combination, step S40 is performed to remove a portion of the dielectric layer 202 along the first direction to form a plurality of second voids 305, and fill the semiconductor material in the plurality of second voids 305. Here, the semiconductor material filled in the second void 305 is the same as the semiconductor material filled in the first void 301 in step S30.

As shown in fig. 14, after the semiconductor material is filled in the plurality of second gaps 305, the remaining dielectric layers constitute a plurality of gate dielectric layers 306, the semiconductor material located between the plurality of gate dielectric layers 306 constitutes a plurality of channel layers 307, and the gate dielectric layers 306 and the channel layers 307 are alternately arranged along the second direction; the semiconductor material located on the plurality of gate dielectric layers 306 and the plurality of channel layers 307 forms a second electrode structure 308.

In some specific examples, the thickness of each channel layer 307, i.e., the dimension of each channel layer 307 in the second direction, is less than 10 nanometers.

In some embodiments, referring back to fig. 10, after filling the second sub-void 3012 with the semiconductor material, the semiconductor material filled in the second sub-void 3012 may be doped from a side of the substrate 101 remote from the insulating layer 103 to form the first electrode structure 302. Referring to fig. 14, after filling the semiconductor material in the plurality of second voids 305, the semiconductor material located between the gate dielectric layers 306 may be doped from a side of the insulating layer 103 remote from the substrate 101 to form a plurality of channel layers 307, and the semiconductor material located on the gate dielectric layers 306 and the channel layers 307 may be doped to form a second electrode structure 308, and the doping type of the first electrode structure 302 and the second electrode structure 308 may be the same.

In some specific examples, the semiconductor material may be doped by an Ion implantation process (IMP). In a specific example, the first electrode structure 302 and the second electrode structure 308 are P-type doped, and the channel layer 307 is N-type doped. In another specific example, the first electrode structure 302 and the second electrode structure 308 are N-type doped and the channel layer 307 is P-type doped.

In other embodiments, after performing step S40, the semiconductor material filled in the second sub-void 3012, the semiconductor material located between the gate dielectric layers 306, and the semiconductor material located on the gate dielectric layers 306 may be doped to form the first electrode structure 302, the channel layer 307, and the second electrode structure 308, respectively.

In some embodiments, the method of forming a semiconductor structure further comprises: referring to fig. 14 and 15 in combination, a portion of the conductive layer 304 is removed in a first direction to form a fourth void 309, and the remaining conductive layer constitutes a gate 310; referring to fig. 15 and 16 in combination, a barrier structure 311 is formed in the fourth void 309, the bottom surface of the barrier structure 311 being flush with the top surface of the gate dielectric layer 306, the top surface of the barrier structure 311 being flush with the top surface of the second electrode structure 308.

In some specific examples, the material of the barrier structure 311 includes, but is not limited to, silicon nitride.

In the embodiment of the present disclosure, the gate 310, the gate dielectric layer 306, the first electrode structure 302, the channel layer 307, and the second electrode structure 308 obtained by the method for forming a semiconductor structure described above together form a vertical transistor, and the vertical transistor includes a plurality of gate dielectric layers 306 and channel layers 307 alternately arranged along the second direction.

It should be noted that the above-mentioned sequence of steps for forming the semiconductor structure including the vertical transistor is merely an example, and the above-mentioned sequence of steps may be appropriately adjusted without changing the structure of the vertical transistor to be finally formed, for example, the above-mentioned embodiment takes the example of forming the second electrode structure 308 first and then forming the barrier structure 311, and in other embodiments, the barrier structure 311 may be formed first and then forming the second electrode structure 308, which is not limited in this disclosure.

In some embodiments, referring to fig. 17 and 18, the method of forming a semiconductor structure further includes: forming an electrode contact structure 401 on the second electrode structure 308; a magnetic tunnel junction 402 is formed covering the electrode contact structure 401, the magnetic tunnel junction 402 including a fixed layer 4021, a tunnel layer 4022, and a free layer 4023 arranged in a stack in a first direction. The blocking structure 311 may prevent the electrode contact structure 401 or the magnetic tunnel junction 402 from contacting the gate 310 during the formation of the electrode contact structure 401 and the magnetic tunnel junction 402, resulting in device failure.

In the embodiment of the present disclosure, the electrode contact structure 401 is formed on the second electrode structure 308 for achieving electrical connection between the second electrode structure 308 and the fixing layer 4021, and the contact interface of the electrode contact structure 401 and the fixing layer 4021 includes an arc-shaped portion, whereby a larger contact area can be formed between the electrode contact structure 401 and the fixing layer 4021.

In some specific examples, the initial fixed layer, the initial tunnel layer, and the initial free layer covering the electrode contact structure 401 and the insulating layer 103 may be sequentially formed by a deposition process, and then the initial fixed layer, the initial tunnel layer, and the initial free layer on the insulating layer 103 may be removed by an etching process to form the magnetic tunnel junction 402 including the fixed layer 4021, the tunnel layer 4022, and the free layer 4023 stacked in the first direction.

In some specific examples, the material of the electrode contact structure 401 may be one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

In some specific examples, the materials of the fixed layer 4021 and the free layer 4023 may be the same or different, and the material of the fixed layer 4021 and/or the free layer 4023 may be one of metal materials such as iron, cobalt, nickel, or an alloy material including one or more metals of iron, cobalt, and nickel. Materials for tunnel layer 4022 include, but are not limited to, magnesium oxide.

In some embodiments, as shown in fig. 19, the method of forming a semiconductor structure further includes forming a barrier layer 403 overlying the magnetic tunnel junction 402, and subsequently forming a bit line contact structure in the barrier layer 403 in connection with the free layer 4023, and forming a bit line on the bit line contact structure.

In the semiconductor structure obtained by the method for forming a semiconductor structure in the embodiment of the present disclosure, the gate 310, the gate dielectric layer 306, the first electrode structure 302, the channel layer 307 and the second electrode structure 308 form a vertical transistor, and the vertical transistor and the magnetic tunnel junction 402 are connected through the electrode contact structure 401 to form a memory cell together, where the vertical transistor is a driving device in the memory cell, and may provide a driving current for the magnetic tunnel junction 402, so that the magnetic moment of the free layer 4023 is turned over, thereby implementing writing of data. Compared with a memory cell using a planar transistor as a driving device, the memory cell formed in the embodiment of the disclosure has smaller projection area on an XY plane, and fewer contact structures are required to be formed, which is more beneficial to improving the integration level of the memory.

In order to further improve the reliability of data writing on the basis of improving the memory integration, it is necessary to improve the driving capability of the vertical transistor, that is, to increase the driving current that the vertical transistor can supply. In some examples, the concentration of carriers is increased by increasing the thickness of the channel layer, however, increasing the thickness of the channel layer results in a subthreshold swing (Subthreshold Swing, SS) and an off-state current (I) _off ) The increase causes a decrease in the control capability of the gate and a decrease in the overall performance of the transistor.

In the embodiment of the present disclosure, as shown in fig. 19, the semiconductor structure obtained by the method of forming the semiconductor structure in the above embodiment includes a plurality of gate dielectric layers 306 and channel layers 307 alternately arranged in the second direction.

In some specific examples, fig. 20 or 21 is a cross-sectional view taken along line BB' of fig. 19, the semiconductor structure obtained by the method of forming the semiconductor structure in the above-described embodiments includes one gate 310; gate 310 encloses gate dielectric layer 306 nearest insulating layer 103; the gate dielectric layer 306 surrounds the channel layer 307 on a side of the gate dielectric layer 306 remote from the gate 310; the channel layer 307 surrounds the gate dielectric layer 306 on a side of the channel layer 307 remote from the gate 310. The semiconductor structure formed in this example includes two gate dielectric layers 306 and two channel layers 307 alternately arranged with a larger contact area between the gate dielectric layers 306 and the channel layers 307, relative to a transistor including only one gate dielectric layer surrounded by a gate and one channel layer surrounded by a gate dielectric layer.

In other specific examples, fig. 22 is a cross-sectional view taken along line BB' of fig. 19, the semiconductor structure obtained by the method of forming a semiconductor structure in the above-described embodiment includes two gates 310 opposing in the second direction; the gate dielectric layers 306 and the channel layers 307 are located between the two gates 310 and alternately arranged in the second direction. The semiconductor structure formed in this example includes four gate dielectric layers 306 and three channel layers 307 alternately arranged with a larger contact area between the gate dielectric layers 306 and the channel layers 307, as compared to a transistor including only two gate dielectric layers respectively in contact with two gates and one channel layer between the two gate layers.

In the embodiment of the present disclosure, the contact area between the gate dielectric layer 306 and the channel layer 307 is increased by forming the plurality of gate dielectric layers 306 and the channel layer 307 alternately arranged in the second direction to increase the concentration of carriers while maintaining the channel layer 307 to have a smaller thickness, so that the control capability of the gate 310 and the driving capability of the vertical transistor can be simultaneously improved, and the reliability of data writing can be improved.

In some embodiments, a semiconductor structure including a plurality of memory cells may also be obtained by the method of forming a semiconductor structure in the above embodiments.

In a specific example, referring to fig. 23, a semiconductor structure includes: a plurality of memory cells 501 arranged in an array along a second direction and a third direction, a plurality of source lines 502 extending along the second direction and arranged along the third direction, a plurality of word lines 503 extending along the third direction and arranged along the second direction, and a plurality of bit lines 504 extending along the second direction and arranged along the third direction. Here, the second direction is the X direction, and the third direction is the Y direction.

Fig. 24 is a cross-sectional view of the plurality of memory cells 501 arranged along the second direction in fig. 23 taken along line CC', and referring to fig. 23 and 24 in combination, one memory cell 501 includes a vertical transistor and magnetic tunnel junction 402 comprised of a gate 310, a gate dielectric layer 306, a first electrode structure 302, a channel layer 307, and a second electrode structure 308; the first electrode structures 302 of the plurality of memory cells 501 arranged in the second direction are located in the same source line 502; the gates 310 of the plurality of memory cells 501 arranged in the third direction are located in the same word line 503; the bit line 504 is located on the magnetic tunnel junction 402, and the free layers 4023 of the plurality of memory cells 501 arranged in the X direction are connected to the same bit line 504.

In the embodiment of the present disclosure, a plurality of memory cells 501 arranged in an array may be formed simultaneously to form a memory array, that is, a single memory cell may be formed, or a memory array including a plurality of memory cells may be formed by the method for forming a semiconductor structure provided in the embodiment of the present disclosure.

Based on the same concept as the method for forming the semiconductor structure described above, the embodiments of the present disclosure also provide a semiconductor structure that can be obtained by the method for forming a semiconductor structure in any of the embodiments described above. Fig. 19 is a schematic structural view of a semiconductor structure according to an embodiment of the disclosure, and fig. 20 to 22 are cross-sectional views along line BB' of fig. 19 in some specific examples.

As shown in fig. 19, the semiconductor structure includes: the substrate 101, the first electrode structure 302, and the insulating layer 103 arranged in a stack in the first direction; the first direction is the thickness direction of the substrate 101; at least one gate electrode 310, a plurality of gate dielectric layers 306, and a plurality of channel layers 307 arranged in a second direction on the first electrode structure 302 and located in the insulating layer 103; the gate dielectric layers 306 and the channel layers 307 are alternately arranged along the second direction; gate 310 is in direct contact with insulating layer 103 and gate dielectric layer 306; the second direction is perpendicular to the first direction; a second electrode structure 308 located over the plurality of gate dielectric layers 306 and the plurality of channel layers 307.

In some specific examples, fig. 20 or 21 is a cross-sectional view of fig. 19 taken along line BB', the semiconductor structure including a gate 310; gate 310 encloses gate dielectric layer 306 nearest insulating layer 103; the gate dielectric layer 306 surrounds the channel layer 307 on a side of the gate dielectric layer 306 remote from the gate 310; the channel layer 307 surrounds the gate dielectric layer 306 on a side of the channel layer 307 remote from the gate 310.

In some specific examples, fig. 22 is a cross-sectional view of fig. 19 along line BB', the semiconductor structure including two gates 310 opposing in a second direction; the gate dielectric layers 306 and the channel layers 307 are located between the two gates 310 and alternately arranged in the second direction.

In some embodiments, the semiconductor structure further comprises: a blocking structure 311 located on the gate 310; the bottom surface of the blocking structure 311 is flush with the top surface of the gate dielectric layer 306; the top surface of the blocking structure 311 is flush with the top surface of the second electrode structure 308.

In some embodiments, the semiconductor structure further comprises: an electrode contact structure 401 located on the second electrode structure 308; a magnetic tunnel junction 402 overlying the electrode contact structure 401; the magnetic tunnel junction 402 includes a fixed layer 4021, a tunnel layer 4022, and a free layer 4023 arranged in a stack in a first direction.

In the embodiment of the disclosure, the gate 310, the gate dielectric layer 306, the first electrode structure 302, the channel layer 307 and the second electrode structure 308 form a vertical transistor, and the vertical transistor and the magnetic tunnel junction 402 are connected through the electrode contact structure 401 to form a memory cell together, where the vertical transistor is a driving device in the memory cell, and may provide a driving current for the magnetic tunnel junction 402, so that the magnetic moment of the free layer 4023 is inverted, thereby implementing writing of data. Compared with a memory cell using a planar transistor as a driving device, the memory cell formed in the embodiment of the disclosure has smaller projection area on an XY plane, and fewer contact structures are required to be formed, which is more beneficial to improving the integration level of the memory.

In the embodiment of the disclosure, the vertical transistor includes a plurality of gate dielectric layers 306 and channel layers 307 which are alternately arranged, and a larger contact area is provided between the gate dielectric layers 306 and the channel layers 307, so that the concentration of carriers can be increased while the channel layers 307 are kept to have a smaller thickness, thereby improving the control capability of the gate 310 and the driving capability of the vertical transistor, and improving the reliability of data writing.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several device embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain a new device embodiment.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Claims

1. A method of forming a semiconductor structure, comprising:

2. The method of claim 1, wherein forming at least one second sacrificial layer, a plurality of dielectric layers, and a plurality of third sacrificial layers arranged in a second direction in the trench comprises:

3. The method of claim 1, wherein forming at least one second sacrificial layer, a plurality of dielectric layers, and a plurality of third sacrificial layers arranged in a second direction in the trench comprises:

4. The method of claim 1, wherein removing the first sacrificial layer and the plurality of third sacrificial layers to form a first void and filling the first void with semiconductor material comprises:

removing the third sacrificial layers to form a plurality of first sub-voids;

5. The method of forming a semiconductor structure of claim 4, further comprising:

6. The method of forming a semiconductor structure of claim 4, further comprising:

forming an electrode contact structure on the second electrode structure;

7. A semiconductor structure, comprising:

8. The semiconductor structure of claim 7, wherein the semiconductor structure comprises a gate; the gate encloses the gate dielectric layer closest to the insulating layer; the grid dielectric layer surrounds the channel layer on one side of the grid dielectric layer away from the grid; the channel layer surrounds the gate dielectric layer on a side of the channel layer remote from the gate.

9. The semiconductor structure of claim 7, wherein the semiconductor structure comprises two gates opposing in the second direction; the gate dielectric layers and the channel layers are located between the two gates and are alternately arranged along the second direction.

10. The semiconductor structure of claim 7, wherein the semiconductor structure further comprises:

an electrode contact structure located on the second electrode structure;