CN117041752A - High-speed large dynamic range pixel architecture compatible with three working modes - Google Patents
High-speed large dynamic range pixel architecture compatible with three working modes Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/42—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
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Abstract
The invention discloses a high-speed large dynamic range pixel architecture compatible with three working modes, which comprises a row gating circuit, a pixel array and a column-level comparator, wherein the pixel array is formed by M multiplied by N pixel structures, and the column-level comparator is formed by N comparators; each pixel structure comprises a photodiode, a transmission gate transistor, an FD capacitor, a reset transistor, a DCG capacitor, a gain control transistor, a first reset control transistor, a second reset control transistor, a source following transistor and a row selection transistor. The invention is compatible with three working modes of 4T, large dynamic range and high-speed pulse reading, can realize the dynamic range expansion of the DCG technology, can be compatible with a high-speed reading mode, and can effectively improve the chip frame rate.
Description
Technical Field
The invention relates to the field of image sensor pixels, in particular to a high-speed large dynamic range pixel architecture compatible with three working modes.
Background
A complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensor is an electronic device that converts an optical signal into an electrical signal, the basic structure of which consists of a set of individual photosensitive pixels, also called photo-spots or photodiodes. Each photodiode is responsible for converting incident light into an amount of charge proportional to the intensity of the light illuminating it, and then converting these charges into digital values representing the pixel color and brightness. CMOS image sensors are popular because of their low power consumption, fast read-out speed and high circuit integration capability. Such image sensors have become the dominant technology for many consumer electronics devices, and are applied to image sensors of digital cameras, smart phones and various other electronic devices, helping people capture image information, and promoting the development of the consumer electronics field.
With the development of consumer electronics, there is a growing demand for CMOS image sensors. The Dynamic Range (DR) of a CMOS image sensor refers to its ability to capture and represent a luminance Range in an image. It measures the span between darkest and brightest areas, i.e. the range of brightness that can be captured while retaining detail and avoiding overexposure or information loss. Dynamic range is typically expressed as the ratio between the maximum and minimum detectable light intensity levels. The dynamic range of a CMOS image sensor is affected by a number of factors, including the size and design of the pixels, the quality of the photodiodes and readout circuitry, and the noise characteristics of the sensor. The higher dynamic range enables it to better capture scenes with high contrast, such as scenes with bright highlights and dark shadows. To enhance dynamic range, CMOS image sensors employ various technologies. One common method to extend the dynamic range is to increase the conversion capability of the light intensity in the pixel, for example, the charge transfer node adopts a dual conversion gain pixel structure (Dual Conversion Gain, DCG), so as to convert the light intensity of the photosensitive node into high and low gains respectively, where the lower gain mode is used to capture a high brightness scene and the higher gain mode is used to capture a low brightness scene. This flexible gain adjustment allows the sensor to capture and retain detail over a wide range of brightness. The dynamic range of the image sensor can reach and even exceed 100dB by the dual conversion gain technique. Such dynamic range enables the sensor to capture high light portions of rich detail in extremely bright light conditions, while maintaining a low noise level in very low light conditions, and to capture dark detail. However, the DCG structure pixel needs to perform the readout of the high-gain signal and the low-gain signal in the readout stage, and the readout time limits the frame rate of the DCG image sensor, so that the DCG structure pixel cannot be used in a high-speed scene with a high frame rate requirement.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a high-speed large-dynamic-range pixel architecture compatible with three working modes. The feedback control of column-level signals on pixels is added on the basis of the traditional DCG structure, so that the pixel structure is compatible with a large dynamic range working mode and a high-speed pulse reading working mode besides a conventional 4T working mode, the dynamic range expansion of the DCG technology can be realized, the high-speed reading mode can be compatible, the reading time is only 200ns, and the chip frame rate can be effectively improved.
The aim of the invention is achieved by the following technical scheme.
The invention is compatible with the high-speed large dynamic range pixel architecture of three working modes, and comprises a row gating circuit, a pixel array and a column-level comparator, wherein the pixel array is composed of M multiplied by N identical pixel structures, the column-level comparator is composed of N comparators with identical structures, and each column of pixel structures corresponds to one comparator;
each pixel structure comprises a photodiode, a transmission gate transistor, an FD capacitor, a reset transistor, a DCG capacitor, a gain control transistor, a first reset control transistor, a second reset control transistor, a source follower transistor and a row selection transistor;
the grid electrode of the transmission grid transistor is applied with a transmission control signal provided by a row gating circuit, the drain electrode of the transmission grid transistor is connected to the upper polar plate of the FD capacitor, the lower polar plate of the FD capacitor is grounded, the source electrode of the transmission grid transistor is connected with the cathode of the photodiode, and the anode of the photodiode is grounded;
the grid electrode of the reset transistor is applied with a reset signal provided by a row gating circuit, the drain electrode of the reset transistor is connected with a power supply, the source electrode of the reset transistor is connected with the upper polar plate of the DCG capacitor, and the lower polar plate of the DCG capacitor is grounded;
the grid electrodes of the first reset control transistor and the second reset control transistor are simultaneously connected to the output end of the row gating circuit or the output end of the corresponding comparator, reset time sequence signals provided by the row gating circuit or column-level feedback signals provided by the corresponding comparator are simultaneously applied to the first reset control transistor and the second reset control transistor, and if the first reset control transistor and the second reset control transistor simultaneously receive the column-level feedback signals provided by the corresponding comparator, the level heights of the column-level feedback signals are opposite; the source electrode of the first reset control transistor is connected with a power supply, the source electrode of the second reset control transistor is grounded, and the drain electrodes of the first reset control transistor and the second reset control transistor are connected to the grid electrode of the gain control transistor; the drain electrode of the gain control transistor is connected to the upper polar plate of the DCG capacitor, and the source electrode of the gain control transistor is connected to the upper polar plate of the FD capacitor;
the grid electrode of the source following transistor is connected to the upper polar plate of the FD capacitor, the drain electrode is connected with a power supply, the source electrode is connected with the drain electrode of the row selection transistor, the source electrode of the row selection transistor is connected to the input end of the corresponding comparator through a column bus, and the grid electrode is used for applying a row selection control signal provided by a row gating circuit.
The invention is compatible with the high-speed large dynamic range pixel architecture of three working modes, and has a high-speed pulse reading working mode, a 4T working mode and a large dynamic range working mode;
in a high-speed pulse reading working mode, a column-level comparator is adopted to provide column-level feedback signals for a first reset control transistor and a second reset control transistor; the column-level comparator compares the pixel output signal of the previous frame with a column-level set threshold value, and takes the comparison result as a column-level feedback signal; if the pixel output signal of the previous frame is higher than the column-level set threshold, the column-level feedback signal controls the FD capacitance in the pixel structure of the current frame not to be reset, and the photo-generated charges transferred by the photodiode are continuously accumulated; if the pixel output signal of the previous frame is lower than the column-level set threshold, the column-level feedback signal controls the FD capacitor in the pixel structure of the current frame to reset, and photo-generated charges transferred by the photodiode are accumulated again;
in the 4T working mode, a row gating circuit is adopted to provide reset time sequence signals for a first reset control transistor 17 and a second reset control transistor 18; in the exposure process, photo-generated charges are accumulated by the photodiode 11, the photo-generated charges in the photodiode 11 are transferred to the FD capacitor 13 after the exposure is completed, and the pixel structure reads out the reset voltage and the integral voltage of the FD capacitor 13 from the corresponding comparator COMP after the transfer is completed;
the large dynamic range working mode comprises a high-gain sub-mode and a low-gain sub-mode, a first reset control transistor is used for controlling a gain control transistor switch, quantization of the high-gain sub-mode and the low-gain sub-mode is further controlled, and reset voltage and integral voltage during high-gain and low-gain are read out sequentially; the photo-generated charges accumulated in the photodiode are transferred twice, a first transfer signal is output to the FD capacitor after the transfer is completed, namely, the integrated voltage in the high-gain sub-mode, and a second transfer signal is output to two charge storage nodes of the FD capacitor and the DCG capacitor after the transfer is completed, namely, the integrated voltage in the low-gain sub-mode.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the invention provides a pixel architecture compatible with 4T, large dynamic range and high-speed pulse reading working modes. The pixel adds a structure to receive column level feedback signals on the basis of a conventional DCG. In the high-speed pulse reading working mode, the charge accumulation of the pixel photosensitive node is controlled by a column-level feedback signal, and a signal V is output pix Output signal V to pixels at column level pix Pulse quantization is carried out, and the quantized result is reset by controlling the pixel structure through column-level Feedback signals feed back_a and feed back_b. The mode can realize high-speed pixel reading, converts light intensity into a time domain pulse signal, and is favorable for high-speed scene application. The pixel has two charge storage nodes with high gain and low gain in a large dynamic range working mode, and the photo-generated charges accumulated by the photodiode are respectively quantized and read out under two gain conditions, so that the quantization precision and the dynamic range of the pixel are effectively improved, and meanwhile CDS can be carried out in a comparatorDouble sampling reduces noise and improves imaging quality.
Drawings
FIG. 1 is a schematic diagram of a high-speed large dynamic range pixel architecture compatible with three modes of operation according to the present invention.
Fig. 2 is a schematic diagram of a single pixel structure in the present invention.
FIG. 3 is a timing diagram of the operation of a pixel in a high-speed pulse readout mode of operation of the present invention; wherein,
(a) Feed back a high and feed back b low,
(b) Feed back_a low level, feed back_b high level.
Fig. 4 is a timing diagram of the operation of the pixel in the 4T operation mode of the present invention.
FIG. 5 is a timing diagram of the operation of a pixel in a large dynamic range mode of operation of the present invention.
Reference numerals: 11-photodiode, 12-pass gate transistor, 13-FD capacitor, 14-reset transistor, 15-DCG capacitor, 16-gain control transistor, 17-reset control transistor, 18-reset control transistor, 19-source follower transistor, 20-row select transistor; FD-floating diffusion node, VDD-power supply, GND-ground, mrst-reset signal, TX-transmission control signal, SEL-row selection control signal, COLUMN COLUMN bus, COMP-comparator, feedback_a, feedback_b are two paths of COLUMN-level feedback signals provided by the same comparator.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
With the requirements of the consumer electronics field for the imaging quality and sampling speed of CMOS image sensors, the conventional LOFIC or DCG technology is improved in terms of dynamic range, but cannot realize high frame rate reading due to the limitation of the number of readout signals. CMOS image sensors have high dynamic range requirements, and in general, the implementation is realized by capacitor overflow or adopting a dual gain structure, multiple signals need to be read out, and the readout time is long, so that the CMOS image sensor cannot be used in a high-speed scene. The pixel structure provided by the invention is compatible with a high-speed pulse reading working mode and a large dynamic range working mode besides a conventional 4T working mode. In a high-speed pulse reading working mode, a pixel light intensity signal is converted into a pulse signal in a time domain at a column level, and accumulation of photons in the pixel is controlled by a column-level feedback signal, so that the mode can be used for a high-speed scene. In the working mode with a large dynamic range, the photo-generated charges accumulated by the photosensitive nodes in the pixels are quantized with high gain and low gain respectively, and the pixels output reset and signal voltage under the high and low gain, so that the photo-generated charges can be used for scenes with a large dynamic range in the mode.
As shown in fig. 1, the high-speed large dynamic range pixel architecture compatible with three working modes mainly comprises a row gating circuit, a pixel array and a column-level comparator, wherein the pixel array is composed of m×n identical pixel structures, the column-level comparator is composed of N comparators COMP with identical structures, and each column of pixel structures corresponds to one comparator COMP. The pixel structures do not interact with each other, and the comparators COMP do not interact with each other.
As shown in fig. 2, each of the pixel structures includes a photodiode 11, a transfer gate transistor 12, an FD capacitance 13, a reset transistor 14, a DCG capacitance 15, a gain control transistor 16, a first reset control transistor 17, a second reset control transistor 18, a source follower transistor 19, a row select transistor 20, and the like.
The gate of the transmission gate transistor 12 is connected to the output end of the row gate circuit, a transmission control signal TX provided by the row gate circuit is applied, the drain is connected to the upper plate of the FD capacitor 13, the lower plate of the FD capacitor 13 is grounded GND, the source is connected to the cathode of the photodiode 11, and the anode of the photodiode 11 is grounded GND.
The gate of the reset transistor 14 is connected to the output end of the row strobe circuit, the reset signal Mrst provided by the row strobe circuit is applied, the drain is connected to the power supply VDD, the source is connected to the upper plate of the DCG capacitor 15, and the lower plate of the DCG capacitor 15 is grounded GND.
The second reset control transistor 18 is a pair of transistors of the first reset control transistor 17, the gates of the first reset control transistor 17 and the second reset control transistor 18 are simultaneously connected to the output end of the row strobe circuit or simultaneously connected to the output end of the corresponding comparator COMP, and the two transistors are simultaneously appliedThe reset time sequence signal provided by the row strobe circuit is added or the column-level feedback signal provided by the corresponding comparator COMP is simultaneously applied, and if the two signals simultaneously receive the column-level feedback signal provided by the corresponding comparator COMP, the level of the two signals is opposite, and the two signals are controlled to be turned on and off. For example, when the column Feedback signal feedback_a applied to the gate of the first reset control transistor 17 is at a high level, the column Feedback signal feedback_b applied to the gate of the second reset control transistor 18 is at a low level, and at this time, the reset control transistor 17 is turned on, and the second reset control transistor 18 is turned off, and vice versa. The comparator COMP has two input terminals, three output terminals, one for inputting pixel output signals, and one for inputting column level set threshold V th The two output terminals provide column-level Feedback signals feedback_a and feedback_b for the first reset control transistor 17 and the second reset control transistor 18, respectively, and one output terminal OUT provides an input signal for the subsequent stage circuit.
The source of the first reset control transistor 17 is connected to the power supply VDD, the source of the second reset control transistor 18 is grounded GND, and the drains of the first reset control transistor 17 and the second reset control transistor 18 are both connected to the gate of the gain control transistor 16. The drain electrode of the gain control transistor 16 is connected to the upper electrode plate of the DCG capacitor 15, and the source electrode is connected to the upper electrode plate of the FD capacitor 13.
The gate of the source follower transistor 19 is connected to the upper plate of the FD capacitor 13, the drain is connected to the power supply VDD, the source is connected to the drain of the row select transistor 20, the gate of the row select transistor 20 is connected to the output terminal of the row select circuit, the row select control signal SEL provided by the row select circuit is applied, the source of the row select transistor 20 is connected to the input terminal of the corresponding comparator via the COLUMN bus, and the output signal is transmitted to the corresponding comparator COMP via the COLUMN bus for comparison.
In the pixel architecture of the invention, which is compatible with three working modes, a structure for receiving column-level feedback signals is added on the basis of the traditional DCG, and the pixel architecture is changed into the pixel architecture which simultaneously has three working modes of high-speed pulse reading, 4T and large dynamic range. The FD capacitor 13 stores photo-generated charges transferred by the photodiode 11 in a high-speed pulse reading working mode, a column-level Feedback signal controls accumulation of photo-generated charges in a pixel structure, an integral signal is output, pulse quantization is carried out on a pixel output signal at a column level, and a quantized result is controlled to reset the pixel structure through column-level Feedback signals feed back_a and feed back_b. In the large dynamic range working mode, two charge storage nodes with high gain and low gain exist in the pixel structure, when a row selection signal arrives, the pixel structure carries out quantization readout on photo-generated charges accumulated by the photodiode 11 under two gain conditions respectively, and the quantization precision and the dynamic range of the pixel are effectively improved through processing the pixel signals outside the chip, meanwhile CDS double sampling can be carried out on a corresponding comparator COMP to reduce noise, and imaging quality is improved.
(1) The line time for pixel signal readout in the high-speed pulse readout operation mode is 200ns. The COLUMN-level comparator transmits the pixel output signal of the previous frame to the corresponding comparator COMP via the COLUMN bus to compare with the COLUMN-level set threshold, and uses the comparison result as COLUMN-level Feedback signals feedback_a and feedback_b. If the pixel output signal of the previous frame is higher than the column-level set threshold, the column-level feedback signal controls the FD capacitor 13 in the pixel structure of the current frame not to reset, and the photo-generated charges transferred by the photodiode 11 are continuously accumulated; if the pixel output signal of the previous frame is lower than the column-level set threshold, the column-level feedback signal controls the FD capacitor 13 in the pixel structure of the current frame to reset, and photo-generated charges transferred from the photodiode 11 are accumulated again. Only the FD capacitance 13 is used as a charge storage node in the high-speed pulse operation mode. The specific contents are as follows:
the high-speed pulse readout mode of operation the pixel operation timing is shown in fig. 3. In the high-speed pulse readout mode of operation, a column-level comparator is employed to provide column-level feedback signals for the first reset control transistor 17, the second reset control transistor 18. The current frame controls the reset transistor 14 to be in an on state in the high-speed pulse readout operation mode. Pixel output signal V of the previous frame pix Transmitted to the pair via COLUMN busThe comparison is performed in a corresponding comparator.
If the pixel outputs a signal V pix Exceeding the column level setting threshold V th The column level Feedback signal feedback_a is high, feedback_b is low, the first reset control transistor 17 is turned on, the second reset control transistor 18 is turned off, and the gain control transistor 16 is controlled to be turned on. The transfer gate transistor 12 is turned on during the turn-on period of the gain control transistor 16, the reset transistor 14 resets the photodiode 11 and the DCG capacitor 15 and FD capacitor 13, and after the reset is completed, an exposure stage is entered in which photo-generated charges are accumulated by the photodiode 11 during the exposure.
If the pixel outputs a signal V pix Set threshold V is not exceeded at the column level th The column-level Feedback signal feedback_a is at a low level, feedback_b is at a high level, the first reset control transistor 17 is turned off, the second reset control transistor 18 is turned on, the gain control transistor 16 cannot be turned on at this time, and the FD capacitor 13 cannot be reset, so that the FD capacitor 13 retains the photo-generated charge accumulated in the previous frame, and then enters an exposure stage, and the photo-generated charge is accumulated by the photodiode 11 during the exposure.
After the exposure phase is finished, the transfer gate transistor 12 is turned on, the photo-generated charge accumulated in the photodiode 11 flows to the FD capacitor 13, the FD capacitor 13 can be used as a floating diffusion node, after the transfer is finished, the transfer gate transistor 12 is turned off, the row selection transistor 20 is turned on, the signal reading phase is entered, the voltage signal of the FD capacitor 13 is output to the corresponding comparator COMP, and the output signal is continuously set with the threshold value V at the column level th The comparison result is fed back to the first reset control transistor 17 and the second reset control transistor 18 through the column-level Feedback signals feed back_a and feed back_b respectively, and the working process of the next frame is controlled in the same way.
(2) In the 4T working mode, a row gating circuit is adopted to provide reset time sequence signals for a first reset control transistor 17 and a second reset control transistor 18; photo-generated charges are accumulated by the photodiode 11 in the exposure process, the photo-generated charges in the photodiode 11 are transferred to the FD capacitor 13 after the exposure is completed, and the pixel structure reads out the reset voltage and the integral voltage of the FD capacitor 13 to the corresponding comparator COMP after the transfer is completed. The specific contents are as follows:
in the 4T mode, a row gating circuit is adopted to provide reset time sequence signals for the first reset control transistor 17 and the second reset control transistor 18, and photo-generated charges are not accumulated to the FD capacitor 13 frame by frame in the exposure process. The FD capacitance in the pixel structure serves as a storage node for the integrated charge, in which mode the reset transistor 14 is turned on and off in synchronization with the first reset control transistor 17, and the on and off of the first reset control transistor 17 controls the on and off of the gain control transistor. As shown in fig. 4, the pixel operation sequence is that, first, the reset transistor 14 and the first reset control transistor 17 are turned on synchronously, then the transfer gate transistor 12 is turned on, the reset of the photodiode 11 and the FD capacitor 13 is completed, the transfer gate transistor 12, the reset transistor 14, the first reset control transistor 17 are turned off, and then the exposure phase is entered. After the exposure, the signal readout stage is entered, the row selection transistor 20 is turned on, then the reset transistor 14 and the first reset control transistor 17 are turned on, the FD capacitor 13 is reset, after the reset is completed, the reset transistor 14 and the first reset control transistor 17 are turned off, the reset signal of the FD capacitor 13 is transmitted to the corresponding comparator COMP via the COLUMN bus, then the transmission transistor 12 is turned on, the charge transfer from the photodiode 11 to the FD capacitor 13 is performed, after the transfer is completed, the transmission transistor 12 is turned off, and the integral voltage of the FD capacitor 13 is transmitted to the corresponding comparator COMP. After the transfer is completed, the row select transistor 20 is turned off. And the working process of the next frame is carried out in the same way.
(3) The high dynamic range operation mode (abbreviated as "DCG mode") includes a high gain sub-mode (abbreviated as "HCG sub-mode") and a low gain sub-mode (abbreviated as "LCG sub-mode"). The first reset control transistor 17 controls the switch of the gain control transistor 16, so as to control the quantization of the two sub modes of high gain and low gain, and the reset and integral voltages of the high gain and the low gain are read out successively. The photo-generated charges accumulated in the photodiode 11 are transferred twice, the first transfer is performed to the FD capacitor 13, a first transfer signal, that is, an integrated voltage in a high gain sub-mode, is output after the transfer is completed, the second transfer is performed to two charge storage nodes of the FD capacitor 13 and the DCG capacitor 15 at the same time, and a second transfer signal, that is, an integrated voltage in a low gain sub-mode, is output after the transfer is completed. The specific contents are as follows:
in the large dynamic range working mode, a row gating circuit is adopted to provide reset time sequence signals for a first reset control transistor 17 and a second reset control transistor 18, the photodiode 11 does not accumulate the FD capacitance frame by frame in the exposure process, and the DCG capacitance 15 is required to be used as a double-gain charge storage node in the mode. The on and off of the first reset control transistor 17 controls the on and off of the gain control transistor. As shown in fig. 5, first, the reset transistor 14 and the first reset control transistor 17 are turned on, the transfer gate transistor 12 is turned on, the photodiode 11, the FD capacitor 13, and the DCG capacitor 15 are reset, the transfer gate transistor 12, the reset transistor 14, and the first reset control transistor 17 are turned off, and an exposure phase is entered, in which photo-generated charges are accumulated by the photodiode 11 during the exposure. After the exposure, the signal readout stage is entered, the row selection transistor 20 is turned on, then the reset transistor 14 and the first reset control transistor 17 are turned on, reset voltage (i.e., the current upper plate voltage of the FD capacitor 13 and the DCG capacitor 15) when LCG is transferred to the corresponding comparator COMP is then turned off, then the first reset control transistor 17 is turned off, reset voltage (i.e., the current upper plate voltage of the FD capacitor 13) when HCG is transferred to the corresponding comparator COMP is then turned off, the transfer gate transistor 12 is turned on after the transfer is completed, photo-generated charge accumulated in the photodiode 11 is transferred to the FD capacitor 13, then the transfer gate transistor 12 is turned off, integrated voltage (i.e., the current upper plate voltage of the FD capacitor 13) when HCG is transferred to the corresponding comparator COMP is then turned on again after the transfer is completed, the first reset control transistor 17 and the transfer gate transistor 12 are turned on, photo-generated charge is transferred to the two nodes of the FD capacitor 13 and the DCG capacitor 15, and the current upper plate voltage (i.e., the current upper plate voltage of the FD capacitor 13 and the DCG capacitor 15) when LCG is read out to the corresponding comparator COMP is completed. And the working process of the next frame is carried out in the same way.
Although the function and operation of the present invention has been described above with reference to the accompanying drawings, the present invention is not limited to the above-described specific functions and operations, but the above-described specific embodiments are merely illustrative, not restrictive, and many forms can be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the appended claims, which are included in the protection of the present invention.
Claims (2)
1. The high-speed large dynamic range pixel architecture compatible with three working modes is characterized by comprising a row gating circuit, a pixel array and a column-level comparator, wherein the pixel array is composed of M multiplied by N identical pixel structures, the column-level comparator is composed of N Comparators (COMP) with identical structures, and each column of pixel structures corresponds to one Comparator (COMP);
each pixel structure comprises a photodiode (11), a transmission gate transistor (12), an FD capacitor (13), a reset transistor (14), a DCG capacitor (15), a gain control transistor (16), a first reset control transistor (17), a second reset control transistor (18), a source follower transistor (19) and a row selection transistor (20);
the grid electrode of the transmission grid transistor (12) is applied with a transmission control signal (TX) provided by a row gating circuit, the drain electrode of the transmission grid transistor is connected to the upper polar plate of the FD capacitor (13), the lower polar plate of the FD capacitor (13) is Grounded (GND), the source electrode of the transmission grid transistor is connected with the cathode of the photodiode (11), and the anode of the photodiode (11) is Grounded (GND);
the grid electrode of the reset transistor (14) is applied with a reset signal (Mrst) provided by a row gating circuit, the drain electrode of the reset transistor is connected with a power supply (VDD), the source electrode of the reset transistor is connected with the upper polar plate of the DCG capacitor (15), and the lower polar plate of the DCG capacitor (15) is Grounded (GND);
the gates of the first reset control transistor (17) and the second reset control transistor (18) are simultaneously connected to the output end of the row gating circuit or simultaneously connected to the output end of the corresponding Comparator (COMP), and a reset time sequence signal provided by the row gating circuit or a column-level feedback signal provided by the corresponding Comparator (COMP) is simultaneously applied to the gates of the first reset control transistor and the second reset control transistor, if the gates of the first reset control transistor and the second reset control transistor simultaneously receive the column-level feedback signal provided by the corresponding Comparator (COMP), the levels of the column-level feedback signals are opposite; the source electrode of the first reset control transistor (17) is connected with a power supply (VDD), the source electrode of the second reset control transistor (18) is Grounded (GND), and the drain electrodes of the first reset control transistor (17) and the second reset control transistor (18) are both connected to the grid electrode of the gain control transistor (16); the drain electrode of the gain control transistor (16) is connected to the upper polar plate of the DCG capacitor (15), and the source electrode is connected to the upper polar plate of the FD capacitor (13);
the grid electrode of the source following transistor (19) is connected to the upper polar plate of the FD capacitor (13), the drain electrode is connected with the power supply (VDD), the source electrode is connected with the drain electrode of the row selecting transistor (20), the source electrode of the row selecting transistor (20) is connected to the input end of the corresponding Comparator (COMP) through the COLUMN bus (COLUMN), and the grid electrode is applied with the row selecting control Signal (SEL) provided by the row gating circuit.
2. The three-mode compatible high-speed large dynamic range pixel architecture of claim 1, having a combination of a high-speed pulse readout mode of operation, a 4T mode of operation, and a large dynamic range mode of operation;
in a high-speed pulse reading working mode, a column-level comparator is adopted to provide column-level feedback signals for a first reset control transistor (17) and a second reset control transistor (18); the column-level comparator compares the pixel output signal of the previous frame with a column-level set threshold value, and takes the comparison result as a column-level feedback signal; if the pixel output signal of the previous frame is higher than the column-level set threshold, the column-level feedback signal controls the FD capacitor (13) in the pixel structure of the current frame not to reset, and the photo-generated charge transferred by the photodiode (11) is continuously accumulated; if the pixel output signal of the previous frame is lower than the column-level set threshold, the column-level feedback signal controls the FD capacitor (13) in the pixel structure of the current frame to reset, and photo-generated charges transferred by the photodiode (11) are accumulated again;
in a 4T working mode, a row gating circuit is adopted to provide reset time sequence signals for a first reset control transistor (17) and a second reset control transistor (18); in the exposure process, photo-generated charges are accumulated by the photodiode (11), the photo-generated charges in the photodiode (11) are transferred to the FD capacitor (13) after the exposure is completed, and the pixel structure reads out the reset voltage and the integral voltage of the FD capacitor (13) to the corresponding Comparator (COMP) after the transfer is completed;
the large dynamic range working mode comprises a high-gain sub-mode and a low-gain sub-mode, a first reset control transistor (17) is used for controlling a gain control transistor (16) to be switched on and off, quantization of the high-gain sub-mode and the low-gain sub-mode is further controlled, and reset voltage and integral voltage during high-gain and low-gain are read out successively; the photo-generated charges accumulated in the photodiode (11) are transferred twice, the photo-generated charges are transferred to the FD capacitor (13) for the first time, signals of the first transfer, namely, integrated voltage in a high-gain sub-mode, are output after the transfer is completed, the photo-generated charges are transferred to two charge storage nodes of the FD capacitor (13) and the DCG capacitor (15) for the second time, and signals of the second transfer, namely, integrated voltage in a low-gain sub-mode, are output after the transfer is completed.
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