CN117040606B - Satellite communication multimode multi-frequency baseband radio frequency integrated SoC chip - Google Patents
Satellite communication multimode multi-frequency baseband radio frequency integrated SoC chip Download PDFInfo
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- CN117040606B CN117040606B CN202311298205.8A CN202311298205A CN117040606B CN 117040606 B CN117040606 B CN 117040606B CN 202311298205 A CN202311298205 A CN 202311298205A CN 117040606 B CN117040606 B CN 117040606B
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- 238000012545 processing Methods 0.000 claims abstract description 92
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- 230000005540 biological transmission Effects 0.000 claims abstract description 6
- 238000001914 filtration Methods 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 9
- 238000005070 sampling Methods 0.000 claims description 8
- 238000007493 shaping process Methods 0.000 claims description 8
- 230000008054 signal transmission Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 3
- 230000007613 environmental effect Effects 0.000 claims description 3
- 238000005562 fading Methods 0.000 claims description 3
- 238000005259 measurement Methods 0.000 claims description 3
- 230000010363 phase shift Effects 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/1851—Systems using a satellite or space-based relay
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/003—Arrangements to increase tolerance to errors in transmission or reception timing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/0035—Synchronisation arrangements detecting errors in frequency or phase
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W84/00—Network topologies
- H04W84/02—Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
- H04W84/04—Large scale networks; Deep hierarchical networks
- H04W84/06—Airborne or Satellite Networks
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention relates to the field of communication integrated circuit SoC chips, in particular to a satellite communication multimode multi-frequency baseband radio frequency integrated SoC chip which comprises an analog radio frequency processing module, a digital radio frequency front end module, a physical layer signal processing module, a controller and an application processor. In the invention, firstly, an analog radio frequency processing module and a digital radio frequency front-end module respectively improve the signal quality and process the conversion between digital signals and analog signals, a physical layer signal processing module receives the physical layer operation of the transmission process of the digital signals, a controller is responsible for processing the communication between a baseband and an application processor, and the application processor is responsible for advanced protocol functions and application processing.
Description
Technical Field
The invention relates to the field of communication integrated circuit (SoC) chips, in particular to a satellite communication multimode multi-frequency baseband radio frequency integrated SoC chip.
Background
Satellite communication uses communication satellites in space orbits as transmission relays of wireless signals, and covers areas which are difficult to be covered by ground communication networks, such as unmanned areas like deserts, forests and oceans, or aircrafts like airplanes and unmanned planes. The direction of future communication development is the integration of the world, and the integration of the world communication terminal all needs baseband and radio frequency SoC chip, and at present, almost all satellite communication terminals have independent radio frequency chip and baseband chip, however, the traditional chip application still has a plurality of drawbacks.
The satellite communication terminal cannot be embedded into a consumer mobile phone due to large volume, large power consumption and high cost, is often realized in a hardware mode in the aspect of signal conversion processing, increases the use area of a chip and is very inconvenient for users to carry, so that a satellite communication multimode multi-frequency baseband radio frequency integrated SoC chip is needed.
Disclosure of Invention
The invention aims to provide a satellite communication multimode multi-frequency baseband radio frequency integrated SoC chip so as to solve the problems in the background technology.
In order to achieve the above purpose, the present invention provides the following technical solutions: the utility model provides a satellite communication multimode multifrequency baseband radio frequency integration SoC chip, includes analog radio frequency processing module, digital radio frequency front end module, physical layer signal processing module, controller and application processor, wherein:
the analog radio frequency processing module is used for improving the quality of analog radio frequency signals;
the digital radio frequency front-end module is used for converting and processing between an analog radio frequency signal and a digital signal;
the physical layer signal processing module is used for processing physical layer operation in the digital signal transmission process;
the controller is used for processing communication between the baseband and the application processor;
the application processor is responsible for high-level protocol functions and application processing.
As a further improvement of the present technical solution, the analog radio frequency processing module includes an input signal processing unit, where the input signal processing unit is configured to process an external radio frequency signal, and specifically includes:
the radio frequency signal input interface sends radio frequency signals to the low noise amplifier to amplify the input radio frequency signals and reduce noise in the signal transmission process, the mixer is used for moving high frequency signals to low frequency, the variable gain amplifier and the filter are used for adjusting the gain level of the signals and removing unnecessary frequency components, and the processed signals are sent to the receiving end unit in the digital radio frequency front end module.
As a further improvement of the present technical solution, the analog radio frequency processing module includes an output signal processing unit, where the output signal processing unit is configured to process an internal radio frequency signal, and specifically includes:
the output signal processing unit receives the analog signal of the transmitting end unit in the digital radio frequency front end module, adjusts the gain level of the signal and removes unnecessary frequency components by utilizing the filtering and variable gain amplifier, shifts the low-frequency signal to high frequency by utilizing the mixer, and finally outputs the signal to an external amplifying circuit or an antenna after being amplified by the radio frequency power amplifier.
As a further improvement of the present technical solution, the digital radio frequency front end module includes a receiving end unit, where the receiving end unit is configured to process a signal sent by the input signal processing unit, and specifically includes:
the method comprises the steps of sampling an analog radio frequency signal 4 times by using a digital signal processing algorithm to obtain an I/Q two-channel baseband digital signal, eliminating a direct current component in the digital signal sampled by an analog-to-digital converter by using a direct current component elimination algorithm, compensating amplitude/phase unbalance between the I/Q two-channel signal by using an I/Q unbalance compensation algorithm, carrying out carrier frequency offset compensation on a received signal according to carrier frequency capturing and tracking estimated carrier frequency offset values, carrying out digital filtering on the signal by using a low pass and matched filter, inhibiting inter-symbol interference in the received signal, dynamically adjusting the gain of the digital signal by using an automatic gain control algorithm, and transmitting the processed signal to a signal flow unit in a physical layer signal processing module.
As a further improvement of the present technical solution, the digital radio frequency front end module includes a transmitting end unit, where the transmitting end unit receives a signal sent by the signal flow unit in the physical layer signal processing module, and specifically includes:
the method comprises the steps of up-sampling burst signals by 4 times through an interpolation algorithm, filtering out-of-band power of the transmitted signals through a low-pass and shaping filter, performing pulse shaping, performing carrier frequency offset compensation on the transmitted signals through a frequency offset estimation and compensation algorithm according to carrier frequency offset values issued by a random control channel, eliminating frequency offset caused by radio frequency devices and environmental influence factors, adjusting transmitted digital signal power through an automatic power control algorithm, converting the sampled signals into I/Q two-baseband analog signals through a digital signal processing algorithm, and transmitting the signals to an output signal processing unit.
As a further improvement of the technical scheme, the physical layer signal processing module comprises a signal flow unit, a hardware accelerator and a control flow unit, wherein the signal flow unit processes and decodes according to the signal sent by the receiving end unit, recovers the original data information or voice information, and sends the signal to the controller; the hardware accelerator is used for reducing the running power consumption and the running frequency of a chip, and a convolutional code coding and decoding algorithm and a channel separation algorithm are deployed on the accelerator; the control flow unit configures parameters according to the related protocol sent by the controller.
As a further improvement of the technical solution, the application processor comprises an upper layer protocol stack, the upper layer protocol stack is used for sending a protocol to the controller, and the controller is used for transferring communication between the control flow unit and the upper layer protocol stack.
As a further improvement of the present technical solution, the signal flow unit processes signals as follows:
synchronizing: the method comprises the steps of utilizing peak detection and a frequency locking loop algorithm to synchronously obtain the position of the optimal sample value point in the current 4 times of sample points at fixed time, and compensating residual frequency deviation existing in a current signal by carrier frequency synchronization;
equalization: obtaining channel coefficients through a channel estimation algorithm, and equalizing a received signal by using a linear equalization algorithm to compensate time-varying fading of a satellite channel;
channel separation: the signal is separated by a channel separation algorithm to obtain a signal of a target time slot, and the signal of the target time slot is demodulated and deinterleaved by a binary bit phase shift keying modulation mode and a time domain interleaving algorithm;
the deinterleaved signals are decoded by a convolutional code coding algorithm through a channel to obtain transmitted data information, the information is data information or coded voice information, the coded voice information is decoded by a self-adaptive error control code decoding algorithm through voice to obtain original voice information, and the original voice information is recovered by a voice reconstruction algorithm; and recovering the data of the format required by the data terminal from the information of the data information after the channel decoding through a data format conversion algorithm.
As a further improvement of the present technical solution, the parameters to be configured by the control flow unit specifically include:
the multimode multifrequency physical layer parameter configuration configures carrier frequency, bandwidth, signal waveform, frame structure, logical channel, physical channel parameter, cell search, beam selection, random access, mobile handover, timing/frequency acquisition, timing/frequency tracking, power control, measurement procedures according to the adopted communication standard.
Compared with the prior art, the invention has the beneficial effects that:
1. the satellite communication multimode multi-frequency baseband radio frequency integrated SoC chip realizes radio frequency signal processing and up-down conversion, carrier frequency offset compensation, digital low-pass filter, digital shaping/matching filter, synchronous receiving, channel coding decoding, modulation and demodulation and other baseband signal processing by using a software mode for conversion between digital signals and analog signals, can not only improve channel transmission gain, but also reconstruct radio frequency and baseband signal processing, and realizes the multimode multi-standard chip of satellite communication by using configurable software to replace a hardware mode, so that the chip can simultaneously support communication signals of various modulation modes, can simultaneously support high-orbit and low-orbit satellite communication protocol systems, and reduces the use area of the chip.
2. In order to reduce complexity and cost of the baseband radio frequency integrated SoC chip, the baseband and the protocol stack are communicated through the controller, the protocol stack is integrated on the application processor, the baseband and the controller are integrated on the SoC chip, the SoC chip is focused on signal processing tasks with high instantaneity, and the application processor is focused on advanced protocol functions and application processing, so that the overall system performance and efficiency are improved.
Drawings
FIG. 1 is a schematic diagram of the overall module of the present invention;
FIG. 2 is a schematic diagram of the individual modular units of the present invention;
FIG. 3 is a flow chart of the receiver-side unit process of the present invention;
FIG. 4 is a flow chart of the sender unit processing of the present invention;
FIG. 5 is a flow chart of a physical layer signal processing module according to the present invention;
in the figure: 100. a simulated radio frequency processing module; 101. an input signal processing unit; 102. an output signal processing unit; 200. a digital radio frequency front end module; 201. a receiving end unit; 202. a transmitting end unit; 300. a physical layer signal processing module; 301. a signal flow unit; 302. a hardware accelerator; 303. a control flow unit; 400. a controller; 500. an application processor; 501. an upper layer protocol stack.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-5, the present invention provides a technical solution: a satellite communication multimode multi-frequency baseband radio frequency integrated SoC chip comprises an analog radio frequency processing module 100, a digital radio frequency front end module 200, a physical layer signal processing module 300, a controller 400 and an application processor 500.
The input signal processing unit 101 in the analog rf processing module 100 receives an external rf signal according to the rf input interface, and in order to improve signal quality, the rf signal input interface firstly transmits the rf signal to the low noise amplifier to amplify the input rf signal and reduce noise in the signal transmission process, then uses the mixer to move the high frequency signal to a low frequency, then uses the variable gain amplifier and the filter to further adjust the gain level of the signal and remove unwanted frequency components, and finally transmits the processed signal to the receiving end unit 201 in the digital rf front end module 200.
The output signal processing unit 102 in the analog rf processing module 100 receives the analog signal sent by the transmitting end unit 202 in the digital rf front end module 200, first adjusts the gain level of the signal and removes unnecessary frequency components by using a filtering and variable gain amplifier, then shifts the low frequency signal to high frequency by using a mixer, and finally outputs the signal to an external amplifying circuit or antenna after being amplified by the rf power amplifier.
The receiving end unit 201 in the digital radio frequency front end module 200 receives the signal processed by the input signal processing unit 101, firstly performs 4 times sampling on the analog radio frequency signal by using a digital signal processing Algorithm (ADC) to obtain an I/Q two-baseband digital signal, then uses a dc component cancellation algorithm to cancel the dc component in the digital signal sampled by the analog-to-digital converter, then uses an I/Q imbalance compensation algorithm to compensate the amplitude/phase imbalance between the I/Q two-channel signal, captures and tracks the estimated carrier frequency offset value according to the carrier frequency, performs carrier frequency offset compensation on the received signal, performs digital filtering on the signal by using a low pass and matched filter and suppresses inter-symbol interference in the received signal, and finally uses an automatic gain control algorithm (digital AGC) to dynamically adjust the gain of the digital signal to compensate the influence of the digital filtering and matched filtering on the signal power, and sends the processed signal to the signal flow unit 301 in the physical layer signal processing module 300.
The transmitting end unit 202 in the digital radio frequency front end module 200 receives the burst signal sent by the signal flow unit 301, firstly, performs 4 times up sampling on the burst signal by utilizing an interpolation algorithm, then filters out the out-of-band power of the sending signal by utilizing a low-pass and shaping filter and performs pulse shaping, then performs carrier frequency offset compensation on the sending signal according to the carrier frequency offset value sent by the associated control channel by utilizing a frequency offset estimation and compensation algorithm, eliminates the frequency offset caused by radio frequency devices and environmental influence factors, adjusts the sent digital signal power by utilizing an automatic power control algorithm (digital APC) to realize accurate control of the signal power, and finally converts the sampling signal into an I/Q two-baseband analog signal by utilizing a digital signal processing algorithm (DAC) and sends the signal to the output signal processing unit 102.
The receiving end unit 201 and the transmitting end unit 202 in the digital radio frequency front end module 200 realize radio frequency signal processing and up-down conversion, carrier frequency offset compensation, digital low-pass filter, digital shaping/matching filter, synchronous receiving, channel coding and decoding, modulation and demodulation and other baseband signal processing in a software mode, so that channel transmission gain can be improved, radio frequency and baseband signal processing can be reconstructed, and a multimode multi-standard chip for satellite communication can be realized through configurable software, so that the chip can simultaneously support communication signals in various modulation modes, and can simultaneously support high-orbit (Tiantong one-number constellation) and low-orbit satellite communication protocol systems.
The signal flow unit 301 in the physical layer signal processing module 300 performs downlink signal processing according to the signal sent by the receiving end unit 201, where the processing procedure is as follows:
synchronizing: the method comprises the steps of utilizing peak detection and a frequency locking loop algorithm to synchronously obtain the position of the optimal sample value point in the current 4 times of sample points at fixed time, and compensating residual frequency deviation existing in a current signal by carrier frequency synchronization;
equalization: firstly, obtaining channel coefficients through a channel estimation algorithm, and then, carrying out equalization on received signals by utilizing a linear equalization algorithm to compensate time-varying fading of a satellite channel;
channel separation: the signal is separated by a channel separation algorithm to obtain a signal of a target time slot, and the signal of the target time slot is demodulated and deinterleaved by a binary bit phase shift keying modulation mode and a time domain interleaving algorithm;
the deinterleaved signals are decoded by a convolutional code coding and decoding algorithm through a channel to obtain transmitted data information, and the information corresponds to the data information for a data service; for voice service, the corresponding coded voice information is obtained by solving the coded voice information through voice decoding by utilizing a decoding algorithm of the self-adaptive error control code, so as to obtain original voice information, and the original voice information is recovered by utilizing a voice reconstruction algorithm; for data service, the information after channel decoding is used for recovering the data in the format required by the data terminal through a data format conversion algorithm;
and finally, the processed signals are sent to the controller 400, wherein the uplink signal processing is a reverse flow of the downlink signal processing.
The control flow unit 303 in the physical layer signal processing module 300 receives a control protocol instruction of the process controller 400, and specifically includes:
the multimode multifrequency physical layer parameter configuration configures carrier frequency, bandwidth, signal waveform, frame structure, logical channel, physical channel parameter, cell search, beam selection, random access, mobile handover, timing/frequency acquisition, timing/frequency tracking, power control, measurement procedures according to the adopted communication standard.
The hardware accelerator 302 in the physical layer signal processing module 300 deploys the algorithm with large operation amount and long processing time in the signal flow unit 301 on the hardware accelerator 302 to realize the real-time performance of satellite communication, and can reduce the running frequency of the digital signal processor and the whole running power consumption, and the hardware accelerator 302 deploys the convolution code coding and decoding algorithm with large operation amount and long processing time and the channel separation algorithm with high real-time performance requirement on the accelerator.
In order to reduce the complexity, cost and area of the baseband radio frequency integrated SoC chip, the communication between the signal flow unit 301 and the upper protocol stack 501 is completed by using the controller 400, the upper protocol stack 501 is integrated on the application processor 500, the signal flow unit 301 and the controller 400 are integrated on the SoC chip, the SoC chip focuses on the real-time high signal processing task through the intercommunication between the upper protocol stack 501 and the controller 400, and the application processor 500 focuses on the high-level protocol function and application processing, so that the overall system performance and efficiency are improved, that is, the baseband and the upper protocol stack 501 are intercommunicated by using the controller 400, so that the baseband signal processing with high real-time performance and the upper protocol stack 501 with near real-time performance can be separated, and the baseband processing and the protocol stack can be respectively configured with reasonably responsive chips, for example, in a smart phone, on the SoC processor AP, so that the complexity of the baseband radio frequency integrated chip can be reduced, and the cost and area can be reduced.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, and that the above-described embodiments and descriptions are only preferred embodiments of the present invention, and are not intended to limit the invention, and that various changes and modifications may be made therein without departing from the spirit and scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (3)
1. A satellite communication multimode multi-frequency baseband radio frequency integrated SoC chip is characterized in that: the system comprises an analog radio frequency processing module (100), a digital radio frequency front end module (200), a physical layer signal processing module (300), a controller (400) and an application processor (500), wherein:
the analog radio frequency processing module (100) is used for improving the quality of analog radio frequency signals;
the digital radio frequency front end module (200) is used for converting and processing between an analog radio frequency signal and a digital signal;
the physical layer signal processing module (300) is used for processing physical layer operation in the digital signal transmission process;
the controller (400) is configured to process communications between a baseband and an application processor (500);
the application processor (500) is configured to be responsible for high-level protocol functions and application processing;
the analog radio frequency processing module (100) comprises an input signal processing unit (101),
the input signal processing unit (101) is configured to process an external radio frequency signal, and specifically includes:
the radio frequency signal input interface sends radio frequency signals to the low noise amplifier to amplify the input radio frequency signals and reduce noise in the signal transmission process, the mixer is used for moving high frequency signals to low frequency, the variable gain amplifier and the filter are used for adjusting the gain level of the signals and removing unnecessary frequency components, and the processed signals are sent to a receiving end unit (201) in the digital radio frequency front end module (200);
the analog radio frequency processing module (100) comprises an output signal processing unit (102), and the output signal processing unit (102) is used for processing an internal radio frequency signal, and specifically comprises:
the output signal processing unit (102) receives an analog signal of a transmitting end unit (202) in the digital radio frequency front end module (200), adjusts the gain level of the signal and removes unnecessary frequency components by utilizing a filtering and variable gain amplifier, then moves a low-frequency signal to high frequency by utilizing a mixer, and finally outputs the signal to an external amplifying circuit or an antenna after being amplified by a radio frequency power amplifier;
the digital radio frequency front end module (200) comprises a receiving end unit (201), wherein the receiving end unit (201) is used for processing signals sent by an input signal processing unit (101), and specifically comprises:
the method comprises the steps of performing 4 times sampling on an analog radio frequency signal by using a digital signal processing algorithm to obtain an I/Q two-channel baseband digital signal, eliminating a direct current component in the digital signal sampled by an analog-to-digital converter by using a direct current component elimination algorithm, compensating amplitude/phase unbalance between the I/Q two-channel signal by using an I/Q unbalance compensation algorithm, performing carrier frequency offset compensation on a received signal according to carrier frequency acquisition and tracking estimated carrier frequency offset values, performing digital filtering on the signal by using a low pass and matched filter, suppressing inter-symbol interference in the received signal, dynamically adjusting gain of the digital signal by using an automatic gain control algorithm, and transmitting the processed signal to a signal flow unit (301) in a physical layer signal processing module (300);
the digital radio frequency front end module (200) comprises a transmitting end unit (202), and the transmitting end unit (202) receives signals sent by a signal flow unit (301) in a physical layer signal processing module (300), and specifically comprises:
4 times up-sampling is carried out on the burst signal by utilizing an interpolation algorithm, the out-of-band power of the transmission signal is filtered by utilizing a low-pass and shaping filter, pulse shaping is carried out, carrier frequency offset compensation is carried out on the transmission signal according to a carrier frequency offset value issued by a random control channel by utilizing a frequency offset estimation and compensation algorithm, frequency offset caused by a radio frequency device and environmental influence factors is eliminated, the power of the transmitted digital signal is regulated by utilizing an automatic power control algorithm, the sampling signal is converted into an I/Q two-baseband analog signal by utilizing a digital signal processing algorithm, and the signal is transmitted to an output signal processing unit (102);
the physical layer signal processing module (300) comprises a signal flow unit (301), a hardware accelerator (302) and a control flow unit (303), wherein the signal flow unit (301) processes and decodes according to a signal sent by the receiving end unit (201), restores original data information or voice information, and sends the signal to the controller (400); the hardware accelerator (302) is used for reducing the running power consumption and the running frequency of the chip, and a convolutional code coding and decoding algorithm and a channel separation algorithm are deployed on the accelerator; the control flow unit (303) configures parameters according to a related protocol sent by the controller (400);
the application processor (500) comprises an upper layer protocol stack (501), the upper layer protocol stack (501) being for sending a protocol to the controller (400), the controller (400) being for communicating a communication between the control flow unit (303) and the upper layer protocol stack (501);
communication between the signal flow unit (301) and the upper protocol stack (501) is completed by using the controller (400), the upper protocol stack (501) is integrated on the application processor (500), the signal flow unit (301) and the controller (400) are integrated on the SoC chip, and the SoC chip focuses on signal processing tasks with high real-time performance through intercommunication between the upper protocol stack (501) and the controller (400), and the application processor (500) focuses on advanced protocol functions and application processing.
2. The satellite communication multimode, multi-frequency baseband, radio frequency integrated SoC chip of claim 1, wherein: the signal flow unit (301) processes signals as follows:
synchronizing: the method comprises the steps of utilizing peak detection and a frequency locking loop algorithm to synchronously obtain the position of the optimal sample value point in the current 4 times of sample points at fixed time, and compensating residual frequency deviation existing in a current signal by carrier frequency synchronization;
equalization: obtaining channel coefficients through a channel estimation algorithm, and equalizing a received signal by using a linear equalization algorithm to compensate time-varying fading of a satellite channel;
channel separation: the signal is separated by a channel separation algorithm to obtain a signal of a target time slot, and the signal of the target time slot is demodulated and deinterleaved by a binary bit phase shift keying modulation mode and a time domain interleaving algorithm;
the deinterleaved signals are decoded by a convolutional code coding algorithm through a channel to obtain transmitted data information, the information is data information or coded voice information, the coded voice information is decoded by a self-adaptive error control code decoding algorithm through voice to obtain original voice information, and the original voice information is recovered by a voice reconstruction algorithm; and recovering the data of the format required by the data terminal from the information of the data information after the channel decoding through a data format conversion algorithm.
3. The satellite communication multimode, multi-frequency baseband, radio frequency integrated SoC chip of claim 1, wherein: the parameters configured by the control flow unit (303) specifically include:
multimode multifrequency physical layer parameter configuration, carrier frequency, bandwidth, signal waveform, frame structure, logical channel, physical channel parameters, cell search, beam selection, random access, mobile handoff, timing/frequency acquisition, timing/frequency tracking, power control and measurement procedures are configured according to the employed communication standard.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202189147U (en) * | 2011-04-19 | 2012-04-11 | 中国电子科技集团公司第五十四研究所 | Multimode navigation information terminal SoC (system on chip) chip integrating multiple IP cores |
| CN106209121A (en) * | 2016-07-15 | 2016-12-07 | 中国科学院微电子研究所 | A kind of communications baseband SoC chip of multimode multinuclear |
| CN108761503A (en) * | 2018-03-21 | 2018-11-06 | 青岛杰瑞自动化有限公司 | A kind of multi-mode satellite signal acquisition methods and SOC chip |
| CN109714065A (en) * | 2017-10-25 | 2019-05-03 | 南京理工大学 | A kind of spaceborne AIS and ADS-B integrated receiver based on micro-nano satellite |
| CN110311724A (en) * | 2019-06-27 | 2019-10-08 | 上海金卓网络科技有限公司 | A kind of digital front-end based on software definition, physical layer architecture and terminal |
| CN110311821A (en) * | 2019-07-09 | 2019-10-08 | 上海金卓网络科技有限公司 | Data transmission method and communication equipment based on software definition |
| CN113625306A (en) * | 2020-05-08 | 2021-11-09 | 上海栅源微电子有限公司 | High-precision multi-mode multi-frequency Beidou navigation SoC chip |
| CN113676201A (en) * | 2021-08-24 | 2021-11-19 | 中信科移动通信技术股份有限公司 | Multimode signal microdistribution system |
| CN215641851U (en) * | 2021-08-25 | 2022-01-25 | 武汉梦芯科技有限公司 | Multi-frequency-point GNSS positioning device |
| WO2022160306A1 (en) * | 2021-01-30 | 2022-08-04 | 华为技术有限公司 | Wireless communication apparatus and antenna switching method therefor |
| CN115664451A (en) * | 2022-10-24 | 2023-01-31 | 广东小天才科技有限公司 | Radio frequency front-end circuit, equipment terminal and chip |
| CN115865116A (en) * | 2022-10-12 | 2023-03-28 | 航天科工深圳（集团）有限公司 | Domestic unmanned equipment comprehensive communication integrated system and equipment |
-
2023
- 2023-10-09 CN CN202311298205.8A patent/CN117040606B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202189147U (en) * | 2011-04-19 | 2012-04-11 | 中国电子科技集团公司第五十四研究所 | Multimode navigation information terminal SoC (system on chip) chip integrating multiple IP cores |
| CN106209121A (en) * | 2016-07-15 | 2016-12-07 | 中国科学院微电子研究所 | A kind of communications baseband SoC chip of multimode multinuclear |
| CN109714065A (en) * | 2017-10-25 | 2019-05-03 | 南京理工大学 | A kind of spaceborne AIS and ADS-B integrated receiver based on micro-nano satellite |
| CN108761503A (en) * | 2018-03-21 | 2018-11-06 | 青岛杰瑞自动化有限公司 | A kind of multi-mode satellite signal acquisition methods and SOC chip |
| CN110311724A (en) * | 2019-06-27 | 2019-10-08 | 上海金卓网络科技有限公司 | A kind of digital front-end based on software definition, physical layer architecture and terminal |
| CN110311821A (en) * | 2019-07-09 | 2019-10-08 | 上海金卓网络科技有限公司 | Data transmission method and communication equipment based on software definition |
| CN113625306A (en) * | 2020-05-08 | 2021-11-09 | 上海栅源微电子有限公司 | High-precision multi-mode multi-frequency Beidou navigation SoC chip |
| WO2022160306A1 (en) * | 2021-01-30 | 2022-08-04 | 华为技术有限公司 | Wireless communication apparatus and antenna switching method therefor |
| CN113676201A (en) * | 2021-08-24 | 2021-11-19 | 中信科移动通信技术股份有限公司 | Multimode signal microdistribution system |
| CN215641851U (en) * | 2021-08-25 | 2022-01-25 | 武汉梦芯科技有限公司 | Multi-frequency-point GNSS positioning device |
| CN115865116A (en) * | 2022-10-12 | 2023-03-28 | 航天科工深圳（集团）有限公司 | Domestic unmanned equipment comprehensive communication integrated system and equipment |
| CN115664451A (en) * | 2022-10-24 | 2023-01-31 | 广东小天才科技有限公司 | Radio frequency front-end circuit, equipment terminal and chip |
Non-Patent Citations (1)
| Title |
|---|
| 卫星通信导航智能终端设计与实现;谌娜等;信息通信(第199期);第1-2节 * |
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