CN117040463B - Preparation method and structure of filter - Google Patents
Preparation method and structure of filter Download PDFInfo
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- CN117040463B CN117040463B CN202311296159.8A CN202311296159A CN117040463B CN 117040463 B CN117040463 B CN 117040463B CN 202311296159 A CN202311296159 A CN 202311296159A CN 117040463 B CN117040463 B CN 117040463B
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 239000013078 crystal Substances 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 238000002161 passivation Methods 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000005498 polishing Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- 238000003486 chemical etching Methods 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 239000013043 chemical agent Substances 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 claims description 3
- 229910002704 AlGaN Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 25
- 238000005260 corrosion Methods 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 8
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010897 surface acoustic wave method Methods 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 241000826860 Trapezium Species 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- -1 scandium aluminum Chemical compound 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
- H03H9/56—Monolithic crystal filters
- H03H9/564—Monolithic crystal filters implemented with thin-film techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
- H03H9/58—Multiple crystal filters
- H03H9/582—Multiple crystal filters implemented with thin-film techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
- H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type
Landscapes
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
The invention discloses a preparation method and a structure of a filter, wherein the preparation method comprises the following steps: forming the structure to be removed includes: the device comprises a substrate, a buffer layer, a dielectric layer, a sacrificial layer and an etching stop layer; forming a monocrystalline piezoelectric layer on the etch stop layer; forming a first electrode layer on one side of the monocrystalline piezoelectric layer away from the structure to be removed; the first electrode layer comprises a plurality of first electrodes; forming a first bonding layer on each first electrode; the first bonding layer is positioned at the edge area of the first electrode; arranging the high-resistance silicon layer on one side of the first bonding layer; the first surface of the high-resistance silicon layer is provided with a plurality of groove structures, and a second bonding layer is arranged in a partial area of the first surface, where the groove structures are not arranged; bonding the first bonding layer and the second bonding layer; forming a plurality of grooves between adjacent first electrodes, dividing the high-resistance silicon layer, and removing the structure to be removed; a second electrode is formed on a side of the single crystal piezoelectric layer remote from the first electrode layer. The invention can improve the performance and yield of the filter.
Description
Technical Field
The invention relates to the technical field of filters, in particular to a preparation method and a structure of a filter.
Background
With the advent of the 5G age, the filter market demand has grown dramatically, and at present, the 4G main filter market is on a Surface Acoustic Wave (SAW) filter, but the SAW filter cannot support the high frequency band of 5G, so that development of a high performance Bulk Acoustic Wave (BAW) filter product is required. The single crystal piezoelectric layer material has more excellent performance than the single crystal piezoelectric layer, however, due to the sandwich structure of the metal electrode-piezoelectric layer-metal electrode of the film bulk acoustic resonator (Fbar), the single crystal piezoelectric layer is difficult to deposit on the metal electrode, so the need of improving a new filter manufacturing process to produce a filter with high performance and high yield single crystal piezoelectric layer is increasingly urgent.
Disclosure of Invention
The invention provides a preparation method and a structure of a filter, which improve the performance and yield of the filter.
According to an aspect of the present invention, there is provided a method for manufacturing a filter, including:
forming a structure to be removed; wherein the structure to be removed comprises: the device comprises a substrate, a buffer layer, a dielectric layer, a sacrificial layer and an etching stop layer; the buffer layer is positioned on one side of the substrate; the medium layer is positioned on one side of the buffer layer, which is far away from the substrate, and comprises a plurality of first through holes; the sacrificial layer is positioned at one side of the dielectric layer far away from the buffer layer, covers the dielectric layer and fills the first through hole; the etching stop layer is positioned on one side of the sacrificial layer away from the substrate;
forming a monocrystalline piezoelectric layer on the etch stop layer;
forming a first electrode layer on one side of the monocrystalline piezoelectric layer away from the structure to be removed; the first electrode layer comprises a plurality of first electrodes, wherein the first electrodes are not contacted with each other or are electrically interconnected;
forming a first bonding layer on one side of each first electrode away from the single crystal piezoelectric layer; wherein the first bonding layer is positioned at the edge area of the first electrode;
disposing a high-resistance silicon layer on a side of the first bonding layer away from the monocrystalline silicon layer; the first surface of the high-resistance silicon layer is provided with a plurality of groove structures, and a second bonding layer is arranged in a partial area of the first surface, where the groove structures are not arranged; the second bonding layer is overlapped with the vertical projection of the first bonding layer on the high-resistance silicon layer;
bonding the first bonding layer and the second bonding layer;
forming a plurality of grooves between adjacent first electrodes, dividing the high-resistance silicon layer, and removing the structure to be removed;
a second electrode is formed on a side of the single crystal piezoelectric layer remote from the first electrode layer.
Optionally, forming a plurality of trenches between adjacent first electrodes, dividing the high-resistance silicon layer, and removing the structure to be removed, including:
etching is carried out between the adjacent first electrodes to form a plurality of grooves; the groove penetrates through the high-resistance silicon layer, the monocrystalline piezoelectric layer, the etching stop layer and the sacrificial layer to expose the dielectric layer;
and removing the dielectric layer, the buffer layer, the sacrificial layer and the etching stop layer through the grooves.
Optionally, the single crystal piezoelectric layer includes a central region and an edge region, the edge region surrounds the central region, the second electrode is located in the central region of the single crystal piezoelectric layer, and after the second electrode is formed on a side of the single crystal piezoelectric layer away from the first electrode layer, the method further includes:
forming a passivation layer on one side of the second electrode away from the single crystal piezoelectric layer; the passivation layer covers the edge area of the second electrode and the monocrystalline piezoelectric layer;
forming a plurality of third through holes on the surface of the passivation layer on the edge region, and forming a plurality of fourth through holes on the surface of the passivation layer on the central region; wherein the third via penetrates the passivation layer and the single crystal piezoelectric layer to expose the first electrode; the fourth through hole penetrates through the passivation layer to expose the second electrode;
forming a first metal layer in the third through hole and at one side of the passivation layer far away from the single crystal piezoelectric layer, and forming a second metal layer in the fourth through hole and at one side of the passivation layer far away from the second electrode; wherein the first metal layer covers part of the passivation layer, the second metal layer covers part of the passivation layer, and the first metal layer and the second metal layer are positioned on the same layer;
and forming an encapsulation layer on one side of the first metal layer and the second metal layer, which is far away from the passivation layer.
Optionally, forming the structure to be removed includes:
providing a substrate;
forming a buffer layer on one side of a substrate;
forming a dielectric layer on one side of the buffer layer away from the substrate; the dielectric layer comprises a plurality of first through holes;
forming a sacrificial layer in the first through hole of the dielectric layer and at one side of the dielectric layer far away from the buffer layer;
an etch stop layer is formed on a side of the sacrificial layer remote from the substrate.
Optionally, before forming the etching stop layer on the side of the sacrificial layer away from the substrate, the method further includes:
and carrying out chemical mechanical polishing on the sacrificial layer.
Optionally, removing the dielectric layer, the buffer layer, the sacrificial layer and the etch stop layer through the trench includes:
removing the dielectric layer by wet or dry chemical etching;
removing the buffer layer and the sacrificial layer by chemical agent corrosion;
the etch stop layer is removed by chemical mechanical polishing.
Alternatively, the cross-sectional shape of the groove structure parallel to the thickness direction includes one of a trapezoid, a semi-ellipse, and a regular quadrangle.
Optionally, the material of the buffer layer includes AlN;
the material of the sacrificial layer comprises any one of AlN, gaN and AlGaN;
the material of the monocrystalline piezoelectric layer comprises any one of monocrystalline AlN, monocrystalline GaN and monocrystalline Fe;
the material of the etching stop layer is Scan.
Alternatively, the thickness of the single crystal piezoelectric layer is 0.1-1.5 μm.
According to an aspect of the present invention, there is provided a filter structure, which is manufactured by using the method for manufacturing a filter according to any embodiment of the present invention.
The preparation method of the filter provided by the technical scheme of the embodiment of the invention comprises the steps of forming a structure to be removed; wherein the structure to be removed comprises: the device comprises a substrate, a buffer layer, a dielectric layer, a sacrificial layer and an etching stop layer; the buffer layer is positioned on one side of the substrate; the medium layer is positioned on one side of the buffer layer, which is far away from the substrate, and comprises a plurality of first through holes; the sacrificial layer is positioned at one side of the dielectric layer far away from the buffer layer, covers the dielectric layer and fills the first through hole; the etching stop layer is positioned on one side of the sacrificial layer away from the substrate; forming a monocrystalline piezoelectric layer on the etch stop layer; forming a first electrode layer on one side of the monocrystalline piezoelectric layer away from the structure to be removed; the first electrode layer comprises a plurality of first electrodes, wherein the first electrodes are not contacted with each other or are electrically interconnected; forming a first bonding layer on one side of each first electrode away from the single crystal piezoelectric layer; wherein the first bonding layer is positioned at the edge area of the first electrode; disposing a high-resistance silicon layer on a side of the first bonding layer away from the monocrystalline silicon layer; the first surface of the high-resistance silicon layer is provided with a plurality of groove structures, and a second bonding layer is arranged in a partial area of the first surface, where the groove structures are not arranged; the second bonding layer is overlapped with the vertical projection of the first bonding layer on the high-resistance silicon layer; bonding the first bonding layer and the second bonding layer; forming a plurality of grooves between adjacent first electrodes, dividing the high-resistance silicon layer, and removing the structure to be removed; a second electrode is formed on a side of the single crystal piezoelectric layer remote from the first electrode layer. The dielectric layer in the embodiment of the invention comprises a plurality of first through holes, so that the stress can be reduced when the dielectric layer is formed, the problem of overlarge warping of the filter structure in the process is avoided, and the yield of the filter is improved; the invention adopts the monocrystalline piezoelectric layer to replace the traditional polycrystalline piezoelectric layer, so that the performance of the filter can be improved, the first surface of the high-resistance silicon layer is provided with a plurality of groove structures, the groove structures are etched in advance, the steps of forming the groove structures by corrosion and release in the traditional process are simplified, the risks of fracture and collapse of the monocrystalline piezoelectric layer caused by the corrosion and release process can be effectively avoided, the monocrystalline piezoelectric layer is further protected from being damaged by the etching stop layer, and the yield of the filter is further improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for manufacturing a filter according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a structure to be removed according to an embodiment of the present invention.
Fig. 3 is a top view of a dielectric layer according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a single crystal piezoelectric layer formed on a structure to be removed according to an embodiment of the present invention.
Fig. 5 is a schematic view of a structure of forming a first electrode layer on a single crystal piezoelectric layer according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of forming a first bonding layer on a first electrode layer according to an embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a high-resistance silicon layer according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram of bonding a first bonding layer and a second bonding layer according to an embodiment of the present invention.
Fig. 9 is a schematic structural diagram of forming a trench according to an embodiment of the present invention.
Fig. 10 is a schematic structural diagram of removing a dielectric layer according to an embodiment of the present invention.
Fig. 11 is a schematic diagram of removing a structure to be removed according to an embodiment of the present invention.
Fig. 12 is a schematic view of another embodiment of the present invention for removing a structure to be removed.
Fig. 13 is a schematic view of a structure of forming a second electrode on a single crystal piezoelectric layer according to an embodiment of the present invention.
Fig. 14 is a flowchart of a preparation method of another filter according to an embodiment of the present invention.
Fig. 15 is a schematic structural view of a passivation layer formed on a second electrode according to an embodiment of the present invention.
Fig. 16 is a schematic structural view of forming a plurality of third through holes and a plurality of fourth through holes in a passivation layer according to an embodiment of the present invention.
Fig. 17 is a schematic structural diagram of forming a first metal layer and a second metal layer according to an embodiment of the present invention.
Fig. 18 is a schematic structural diagram of forming a package layer according to an embodiment of the present invention.
Fig. 19 is a refinement flowchart in step 110.
Fig. 20 is a schematic structural diagram of forming a buffer layer on a substrate according to an embodiment of the present invention.
Fig. 21 is a schematic structural diagram of forming a dielectric layer on a buffer layer according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a method for preparing a filter, and fig. 1 is a flowchart of the method for preparing a filter provided by the embodiment of the invention, and referring to fig. 1, the method for preparing the filter comprises the following steps:
s110, forming a structure to be removed; wherein the structure to be removed comprises: the device comprises a substrate, a buffer layer, a dielectric layer, a sacrificial layer and an etching stop layer; the buffer layer is positioned on one side of the substrate; the medium layer is positioned on one side of the buffer layer, which is far away from the substrate, and comprises a plurality of first through holes; the sacrificial layer is positioned at one side of the dielectric layer far away from the buffer layer, covers the dielectric layer and fills the first through hole; the etch stop layer is located on a side of the sacrificial layer remote from the substrate.
Fig. 2 is a schematic diagram of a structure to be removed according to an embodiment of the present invention, fig. 3 is a top view of a dielectric layer according to an embodiment of the present invention, and referring to fig. 2 and fig. 3, a buffer layer 20 is formed on one side of a substrate 10; forming a dielectric layer 30 on a side of the buffer layer 20 remote from the substrate 10; the dielectric layer 30 includes a plurality of first through holes 31; forming a sacrificial layer 40 in the first through hole 31 of the dielectric layer 30 and on a side of the dielectric layer 30 away from the buffer layer 20; an etch stop layer 50 is formed on the side of the sacrificial layer 40 remote from the substrate 10. The material of the substrate 10 includes alumina (Al 2 O 3 ) Any one of silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). The material of the buffer layer 20 may be aluminum nitride (AlN), and the thickness of the buffer layer 20 is between 1 and 100nm, preferably between 20 and 40nm. The material of dielectric layer 30 may be silicon dioxide (SiO 2 ) Or silicon (Si), and the first through hole 31 may be formed by patterning the dielectric layer 30, the material of the sacrificial layer 40 having a lattice constant similar to that of the material of the single crystal piezoelectric layer, and the material of the sacrificial layer 40 including any one of aluminum nitride (AlN), gallium nitride (GaN), and aluminum gallium nitride (AlGaN). The function of the etch stop layer 50 is to protect the single crystal piezoelectric layer from being damaged by etching when the sacrificial layer is etched, and the material of the etch stop layer 50 may be scandium aluminum nitride (scann).
And S120, forming a monocrystalline piezoelectric layer on the etching stop layer.
Fig. 4 is a schematic structural diagram of forming a single crystal piezoelectric layer on a structure to be removed according to an embodiment of the present invention, referring to fig. 4, a single crystal piezoelectric layer 60 is deposited on an etching stop layer 50, and may be deposited by using Metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), or other devices. The thickness of the single crystal piezoelectric layer 60 may be 0.2-2 μm, and the material of the single crystal piezoelectric layer 60 may be any one of single crystal AlN, single crystal GaN, and single crystal Fe: gaN, and the performance of the single crystal piezoelectric layer 60 is higher than that of the conventional polycrystalline piezoelectric layer, so that the performance of the filter may be improved.
S130, forming a first electrode layer on one side of the monocrystalline piezoelectric layer away from the structure to be removed; the first electrode layer comprises a plurality of first electrodes, and the first electrodes are not contacted with each other or are electrically interconnected.
Wherein fig. 5 is a schematic structural diagram of forming a first electrode layer on a single crystal piezoelectric layer according to an embodiment of the present invention, and referring to fig. 5, the first electrode layer is sputtered or deposited on the single crystal piezoelectric layer 60; the plurality of first electrodes 70 are formed through a patterning process, the plurality of first electrodes 70 are not in contact with each other or the plurality of first electrodes 70 are electrically interconnected, and a material of the first electrode layer includes molybdenum (Mo), tungsten (Wo), gold (Au), and titanium (Ti).
S140, forming a first bonding layer on one side of each first electrode far away from the single crystal piezoelectric layer; wherein the first bonding layer is located at an edge region of the first electrode.
Fig. 6 is a schematic structural diagram of forming a first bonding layer on a first electrode layer according to an embodiment of the present invention, and referring to fig. 6, a first bonding layer 80 may be formed on an edge region of a first electrode 70 by electroplating metal. Alternatively, the first bonding layer 80 may be the same layer as the first electrode 70 and formed simultaneously with the first electrode 70.
S150, arranging the high-resistance silicon layer on one side of the first bonding layer away from the monocrystalline silicon layer; the first surface of the high-resistance silicon layer is provided with a plurality of groove structures, and a second bonding layer is arranged in a partial area of the first surface, where the groove structures are not arranged, and the second bonding layer is overlapped with the vertical projection of the first bonding layer on the high-resistance silicon layer.
Fig. 7 is a schematic structural diagram of a high-resistance silicon layer according to an embodiment of the present invention, referring to fig. 7, a groove structure is etched in advance on the high-resistance silicon layer 90, and a second bonding layer 100 is disposed in a partial area of the first surface of the high-resistance silicon layer 90 where the groove structure is not disposed.
S160, bonding the first bonding layer and the second bonding layer
Fig. 8 is a schematic diagram of a bonding structure of a first bonding layer and a second bonding layer according to an embodiment of the present invention, and referring to fig. 8, the first bonding layer 80 and the second bonding layer 100 may be bonded together through a wafer bonding process.
S170, forming a plurality of grooves between the adjacent first electrodes, dividing the high-resistance silicon layer, and removing the structure to be removed.
Fig. 9 is a schematic structural view of forming a trench according to an embodiment of the present invention, fig. 10 is a schematic structural view of removing a dielectric layer according to an embodiment of the present invention, and fig. 11 is a schematic structural view of removing a structure to be removed according to an embodiment of the present invention, and referring to fig. 9 to fig. 11, etching may be performed between adjacent first electrodes 70 to form a plurality of trenches 32; trench 32 penetrates high-resistance silicon layer 90, single crystal piezoelectric layer 60, etch stop layer 50 and sacrificial layer 40, exposing dielectric layer 30; dielectric layer 30, buffer layer 20, sacrificial layer 40 and etch stop layer 50 are removed through trench 32. Dielectric layer 30 may be removed by wet or dry chemical etching; the buffer layer 20 and the sacrificial layer 40 may be removed by etching with a chemical agent, and the substrate 10 may be removed along with the removal of the buffer layer 20 when the buffer layer 20 is removed; the etching stop layer 50 can be removed by mechanical polishing, so that the substrate 10, the dielectric layer 30, the buffer layer 20, the sacrificial layer 40 and the etching stop layer 50 can be removed without damaging the single crystal piezoelectric layer, the substrate 10, the dielectric layer 30, the buffer layer 20, the sacrificial layer 40 and the etching stop layer 50 can be avoided from being physically polished, the time consumption of a physical polishing process is avoided from being long, the risks of uneven thickness and structural fracture after the structure is thinned are easily caused, and the process time can be saved. Fig. 12 is a schematic view of another embodiment of the present invention, in which the structures to be removed are removed, and after the structures to be removed are removed, a plurality of interconnected structures of fig. 12 may be formed, each structure including only one first electrode, which is a single resonator element of the filter.
And S180, forming a second electrode on one side of the single crystal piezoelectric layer away from the first electrode layer.
Wherein, fig. 13 is a schematic structural diagram of forming a second electrode on a single crystal piezoelectric layer according to an embodiment of the present invention; referring to fig. 13, the thickness of the second electrode 101 may be 0.1-0.3 μm, and the material of the second electrode 101 includes molybdenum (Mo), tungsten (Wo), gold (Au), and titanium (Ti), and the second electrode 101 may be formed by patterning, thereby forming a structure of a first electrode-single crystal piezoelectric layer-second electrode, constituting a complete resonator. The plurality of resonators are connected in series and parallel to form a filter.
The preparation method of the filter provided by the technical scheme of the embodiment of the invention comprises the steps of forming a structure to be removed; wherein the structure to be removed comprises: the device comprises a substrate, a buffer layer, a dielectric layer, a sacrificial layer and an etching stop layer; the buffer layer is positioned on one side of the substrate; the medium layer is positioned on one side of the buffer layer, which is far away from the substrate, and comprises a plurality of first through holes; the sacrificial layer is positioned at one side of the dielectric layer far away from the buffer layer, covers the dielectric layer and fills the first through hole; the etching stop layer is positioned on one side of the sacrificial layer away from the substrate; forming a monocrystalline piezoelectric layer on the etch stop layer; forming a first electrode layer on one side of the monocrystalline piezoelectric layer away from the structure to be removed; the first electrode layer comprises a plurality of first electrodes, wherein the first electrodes are not contacted with each other or are electrically interconnected; forming a first bonding layer on one side of each first electrode away from the single crystal piezoelectric layer; wherein the first bonding layer is positioned at the edge area of the first electrode; disposing a high-resistance silicon layer on a side of the first bonding layer away from the monocrystalline silicon layer; the first surface of the high-resistance silicon layer is provided with a plurality of groove structures, and a second bonding layer is arranged in a partial area of the first surface, where the groove structures are not arranged; the second bonding layer is overlapped with the vertical projection of the first bonding layer on the high-resistance silicon layer; bonding the first bonding layer and the second bonding layer; forming a plurality of grooves between adjacent first electrodes, dividing the high-resistance silicon layer, and removing the structure to be removed; a second electrode is formed on a side of the single crystal piezoelectric layer remote from the first electrode layer. The dielectric layer in the embodiment of the invention comprises a plurality of first through holes, so that the stress can be reduced when the dielectric layer is formed, the problem of overlarge warping of the filter structure in the process is avoided, and the yield of the filter is improved; the invention adopts the monocrystalline piezoelectric layer to replace the traditional polycrystalline piezoelectric layer, so that the performance of the filter can be improved, the first surface of the high-resistance silicon layer is provided with a plurality of groove structures, the groove structures are etched in advance, the steps of forming the groove structures by corrosion and release in the traditional process are simplified, the risks of fracture and collapse of the monocrystalline piezoelectric layer caused by the corrosion and release process can be effectively avoided, the monocrystalline piezoelectric layer is further protected from being damaged by the etching stop layer, and the yield of the filter is further improved.
Optionally, removing the structure to be removed includes: etching is carried out between the adjacent first electrodes to form a plurality of grooves; the groove penetrates through the high-resistance silicon layer, the monocrystalline piezoelectric layer, the etching stop layer and the sacrificial layer to expose the dielectric layer; and removing the dielectric layer, the buffer layer, the sacrificial layer and the etching stop layer through the grooves.
Referring to fig. 9 to 11, the dielectric layer 30 may be removed by wet or dry chemical etching, and the dielectric layer 30 may be etched to form a communicating cavity; introducing chemical reagent into the cavity to etch and remove the buffer layer 20 and the sacrificial layer 40, wherein the substrate 10 is removed along with the removal of the buffer layer 20 after the buffer layer 20 is removed, so that the single crystal piezoelectric layer 60 and the substrate 10 are peeled off; the etching stop layer 50 can be removed by mechanical polishing, the single crystal piezoelectric layer 60 can be exposed, and the upper surface of the single crystal piezoelectric layer can be continuously trimmed and flattened by using an etching trimming (trimming) process, so that the substrate 10, the dielectric layer 30, the buffer layer 20, the sacrificial layer 40 and the etching stop layer 50 can be removed without damaging the single crystal piezoelectric layer, the substrate 10, the dielectric layer 30, the buffer layer 20, the sacrificial layer 40 and the etching stop layer 50 can be avoided from being physically ground away, the time consumption of a physical grinding process is avoided, the risks of uneven thickness and structural fracture after the structure is thinned are easily caused, the process time can be saved, and the process steps are simple.
Optionally, the single crystal piezoelectric layer includes a central region and an edge region, the edge region surrounds the central region, the second electrode is located in the central region of the single crystal piezoelectric layer, fig. 14 is a flowchart of a preparation method of another filter according to an embodiment of the present invention, and referring to fig. 14, after forming the second electrode on a side of the single crystal piezoelectric layer away from the first electrode layer in step 180, the method further includes:
s210, forming a passivation layer on one side of the second electrode away from the monocrystalline piezoelectric layer; the passivation layer covers the second electrode and an edge region of the single crystal piezoelectric layer.
Fig. 15 is a schematic structural diagram of a passivation layer formed on a second electrode according to an embodiment of the present invention, referring to fig. 16, a passivation layer 102 is formed on a side of the second electrode 101 away from the single crystal piezoelectric layer 60, where the passivation layer 102 covers the second electrode 101 and an edge region of the single crystal piezoelectric layer 60, and may play a role in isolation protection when forming a first metal layer and a second metal layer in the following steps.
S220, forming a plurality of third through holes on the surface of the passivation layer on the edge area, and forming a plurality of fourth through holes on the surface of the passivation layer on the central area; wherein the third via penetrates the passivation layer and the single crystal piezoelectric layer to expose the first electrode; the fourth through hole penetrates through the passivation layer to expose the second electrode.
Fig. 16 is a schematic structural diagram of forming a plurality of third through holes and a plurality of fourth through holes in a passivation layer according to an embodiment of the present invention, and referring to fig. 16, a plurality of third through holes 33 and a plurality of fourth through holes 34 may be formed in a passivation layer 102 through a micro-nano hole processing process.
S230, forming a first metal layer in the third through hole and at one side of the passivation layer far away from the single crystal piezoelectric layer, and forming a second metal layer in the fourth through hole and at one side of the passivation layer far away from the second electrode; wherein the first metal layer covers part of the passivation layer, the second metal layer covers part of the passivation layer, and the first metal layer and the second metal layer are located on the same layer.
Fig. 17 is a schematic structural diagram of forming a first metal layer and a second metal layer according to an embodiment of the present invention, referring to fig. 17, a first metal layer 103 may be formed in a third via hole 33 and a side of a passivation layer 102 away from a second electrode 101 by re-wiring (RDL), and a second metal layer 104 may be formed in a fourth via hole 34 and a side of the passivation layer 102 away from the second electrode 101.
S240, forming an encapsulation layer on one side of the first metal layer and the second metal layer away from the passivation layer.
Fig. 18 is a schematic structural diagram of forming a package layer according to an embodiment of the present invention, and referring to fig. 18, a bump process is used for wafer level package, and a material of the package layer 105 includes any one of a high-resistance silicon wafer (wafer), a glass wafer, and a sapphire wafer.
Optionally, fig. 19 is a detailed flowchart in step 110, and referring to fig. 19, step 110, forming a structure to be removed includes:
s111, providing a substrate.
S112, forming a buffer layer on one side of the substrate.
Fig. 20 is a schematic structural diagram of forming a buffer layer on a substrate according to an embodiment of the present invention, and referring to fig. 20, a buffer layer 20 may be sputtered or deposited on a substrate 10.
S113, forming a dielectric layer on one side of the buffer layer away from the substrate; the dielectric layer includes a plurality of first vias.
Fig. 21 is a schematic structural diagram of forming a dielectric layer on a buffer layer according to an embodiment of the present invention, referring to fig. 21, a dielectric layer 30 is deposited on the buffer layer 20, and a patterning process may be performed on the dielectric layer 30 to form a first through hole 31.
S114, forming a sacrificial layer in the first through hole of the dielectric layer and on one side of the dielectric layer away from the buffer layer.
The sacrificial layer is formed in the first through hole of the dielectric layer and on one side of the dielectric layer away from the buffer layer through sputtering or deposition. The thickness of the deposited layer is higher than the height of the dielectric layer and completely covers the dielectric layer.
And S115, forming an etching stop layer on the side of the sacrificial layer away from the substrate.
Wherein the etch stop layer is formed by deposition on a side of the sacrificial layer remote from the substrate.
Optionally, before forming the etching stop layer on the side of the sacrificial layer away from the substrate, the method further includes: and carrying out chemical mechanical polishing on the sacrificial layer.
Wherein, carrying out chemical mechanical polishing to the sacrificial layer can improve the evenness of the surface of the sacrificial layer.
Optionally, removing the dielectric layer, the buffer layer, the sacrificial layer and the etch stop layer through the trench includes: removing the dielectric layer by wet or dry chemical etching; removing the buffer layer and the sacrificial layer by chemical agent corrosion; the etch stop layer is removed by chemical mechanical polishing.
The substrate can be removed along with the removal of the buffer layer after the buffer layer is removed, so that the substrate, the dielectric layer, the buffer layer, the sacrificial layer and the etching stop layer can be removed under the condition that the monocrystalline piezoelectric layer is not damaged, the substrate, the dielectric layer, the buffer layer, the sacrificial layer and the etching stop layer can be prevented from being ground in a physical mode, the time consumption of a physical grinding process is long, the risks of uneven thickness and structural fragmentation after the structure is thinned are avoided, and the process time can be saved.
Alternatively, the cross-sectional shape of the groove structure parallel to the thickness direction includes one of a trapezoid, a semi-ellipse, and a regular quadrangle.
The high-resistance silicon layer is etched into the groove structure in advance, and the groove structure is etched in advance, so that the cross section shape of the groove structure parallel to the thickness direction comprises one of trapezium, semi-ellipse and regular quadrangle, the step of forming the groove structure by corrosion and release in the traditional process is simplified, the risk of breakage and collapse of the monocrystalline piezoelectric layer caused by the corrosion and release process can be effectively avoided, the yield of the filter is improved, and the process steps in manufacturing the groove structure are simplified.
Optionally, the material of the buffer layer includes AlN; the material of the sacrificial layer comprises any one of AlN, gaN and AlGaN; the material of the monocrystalline piezoelectric layer comprises any one of monocrystalline AlN, monocrystalline GaN and monocrystalline Fe; the material of the etching stop layer is Scan.
The lattice constant of the material of the sacrificial layer is similar to that of the material of the monocrystalline piezoelectric layer, so that lattice mismatch can be reduced, and the monocrystalline piezoelectric layer with high quality can be formed. The material of the etching stop layer is ScAlN, so that the monocrystalline piezoelectric layer can be protected from being damaged.
Alternatively, the thickness of the single crystal piezoelectric layer is 0.1-1.5 μm.
The thickness of the single crystal piezoelectric layer is smaller than 0.1 mu m, the process is difficult to realize, and when the thickness of the single crystal piezoelectric layer is larger than 1.5 mu m, the structural size of the filter is enlarged, so that the integration is not facilitated; therefore, the thickness of the single crystal piezoelectric layer is 0.1-1.5 mu m, the process is simple, and the integration is facilitated.
The embodiment of the invention also provides a filter structure based on the embodiment, and the filter structure is prepared by adopting the preparation method of the filter according to any of the embodiments of the invention.
The filter structure part provided by the embodiment of the invention has the beneficial effects identical to those of the filter preparation method according to any of the embodiments of the invention.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of manufacturing a filter, comprising:
forming a structure to be removed; wherein the structure to be removed comprises: the device comprises a substrate, a buffer layer, a dielectric layer, a sacrificial layer and an etching stop layer; the buffer layer is positioned on one side of the substrate; the dielectric layer is positioned on one side of the buffer layer away from the substrate, and comprises a plurality of first through holes; the sacrificial layer is positioned on one side of the dielectric layer far away from the buffer layer, covers the dielectric layer and fills the first through hole; the etching stop layer is positioned on one side of the sacrificial layer away from the substrate;
forming a monocrystalline piezoelectric layer on the etching stop layer;
forming a first electrode layer on one side of the monocrystalline piezoelectric layer away from the structure to be removed; wherein the first electrode layer comprises a plurality of first electrodes, and the first electrodes are not contacted with each other or are electrically interconnected;
forming a first bonding layer on a side of each of the first electrodes remote from the single crystal piezoelectric layer; wherein the first bonding layer is positioned at the edge area of the first electrode;
disposing a high-resistance silicon layer on a side of the first bonding layer away from the monocrystalline silicon layer; the first surface of the high-resistance silicon layer is provided with a plurality of groove structures, and a second bonding layer is arranged in a partial area of the first surface, where the groove structures are not arranged; the second bonding layer is overlapped with the vertical projection of the first bonding layer on the high-resistance silicon layer;
bonding the first bonding layer and the second bonding layer;
forming a plurality of grooves between adjacent first electrodes, dividing the high-resistance silicon layer, and removing the structure to be removed;
a second electrode is formed on a side of the single crystal piezoelectric layer remote from the first electrode layer.
2. The method of manufacturing a filter according to claim 1, wherein forming a plurality of trenches between adjacent ones of the first electrodes, dividing the high-resistance silicon layer, and removing the structure to be removed, comprises:
etching between adjacent first electrodes to form a plurality of grooves; the groove penetrates through the high-resistance silicon layer, the monocrystalline piezoelectric layer, the etching stop layer and the sacrificial layer to expose the dielectric layer;
and removing the dielectric layer, the buffer layer, the sacrificial layer and the etching stop layer through the grooves.
3. The method of manufacturing a filter according to claim 1, wherein the single crystal piezoelectric layer includes a center region and an edge region, the edge region surrounding the center region, the second electrode being located in the center region of the single crystal piezoelectric layer, and further comprising, after forming the second electrode on a side of the single crystal piezoelectric layer remote from the first electrode layer:
forming a passivation layer on a side of the second electrode away from the single crystal piezoelectric layer; the passivation layer covers the edge area of the second electrode and the single crystal piezoelectric layer; forming a plurality of third through holes on the surface of the passivation layer on the edge region, and forming a plurality of fourth through holes on the surface of the passivation layer on the central region; wherein the third via penetrates the passivation layer and the single crystal piezoelectric layer exposing the first electrode; the fourth through hole penetrates through the passivation layer to expose the second electrode;
forming a first metal layer in the third through hole and at one side of the passivation layer away from the single crystal piezoelectric layer, and forming a second metal layer in the fourth through hole and at one side of the passivation layer away from the second electrode; wherein the first metal layer covers part of the passivation layer, the second metal layer covers part of the passivation layer, and the first metal layer and the second metal layer are positioned on the same layer;
and forming an encapsulation layer on one side of the first metal layer and the second metal layer away from the passivation layer.
4. The method of fabricating a filter of claim 1, wherein forming the structure to be removed comprises:
providing a substrate;
forming a buffer layer on one side of the substrate;
forming a dielectric layer on one side of the buffer layer away from the substrate; the dielectric layer comprises a plurality of first through holes;
forming a sacrificial layer in the first through hole of the dielectric layer and at one side of the dielectric layer away from the buffer layer;
an etch stop layer is formed on a side of the sacrificial layer remote from the substrate.
5. The method of manufacturing a filter according to claim 4, further comprising, before forming an etch stop layer on a side of the sacrificial layer remote from the substrate:
and carrying out chemical mechanical polishing on the sacrificial layer.
6. The method of manufacturing a filter according to claim 2, wherein removing the dielectric layer, the buffer layer, the sacrificial layer, and the etch stop layer through the trench comprises:
removing the dielectric layer through wet or dry chemical etching;
etching to remove the buffer layer and the sacrificial layer by chemical agents;
the etch stop layer is removed by chemical mechanical polishing.
7. The method of manufacturing a filter according to claim 1, wherein the cross-sectional shape of the groove structure parallel to the thickness direction includes one of a trapezoid, a semi-ellipse, and a regular quadrangle.
8. The method for manufacturing a filter according to claim 1, wherein,
the material of the buffer layer comprises AlN;
the material of the sacrificial layer comprises any one of AlN, gaN and AlGaN;
the material of the monocrystalline piezoelectric layer comprises any one of monocrystalline AlN, monocrystalline GaN and monocrystalline Fe: gaN;
the etching stop layer is made of ScAlN.
9. A method of manufacturing a filter according to claim 3, wherein the thickness of the single crystal piezoelectric layer is 0.1-1.5 μm.
10. A filter structure, characterized in that it is produced by the method for producing a filter according to any one of claims 1-9.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101962165A (en) * | 2010-09-10 | 2011-02-02 | 上海集成电路研发中心有限公司 | Microbridge structure of micro-electromechanical system and manufacturing method thereof |
| CN109341905A (en) * | 2018-11-29 | 2019-02-15 | 华景传感科技（无锡）有限公司 | A kind of capacitance pressure transducer, and preparation method thereof |
| CN110620563A (en) * | 2019-08-27 | 2019-12-27 | 河源市众拓光电科技有限公司 | Method for improving preparation yield of FBAR (film bulk acoustic resonator) filter and FBAR filter |
| CN114337585A (en) * | 2022-01-11 | 2022-04-12 | 武汉敏声新技术有限公司 | Single crystal film bulk acoustic resonator, preparation method thereof and filter |
| CN114465596A (en) * | 2022-01-27 | 2022-05-10 | 宁波华彰企业管理合伙企业(有限合伙) | Resonator with pre-embedded sacrificial layer structure and preparation method thereof |
| CN115001429A (en) * | 2022-08-03 | 2022-09-02 | 迈感微电子(上海)有限公司 | Preparation method of filter |
-
2023
- 2023-10-09 CN CN202311296159.8A patent/CN117040463B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101962165A (en) * | 2010-09-10 | 2011-02-02 | 上海集成电路研发中心有限公司 | Microbridge structure of micro-electromechanical system and manufacturing method thereof |
| CN109341905A (en) * | 2018-11-29 | 2019-02-15 | 华景传感科技（无锡）有限公司 | A kind of capacitance pressure transducer, and preparation method thereof |
| CN110620563A (en) * | 2019-08-27 | 2019-12-27 | 河源市众拓光电科技有限公司 | Method for improving preparation yield of FBAR (film bulk acoustic resonator) filter and FBAR filter |
| CN114337585A (en) * | 2022-01-11 | 2022-04-12 | 武汉敏声新技术有限公司 | Single crystal film bulk acoustic resonator, preparation method thereof and filter |
| CN114465596A (en) * | 2022-01-27 | 2022-05-10 | 宁波华彰企业管理合伙企业(有限合伙) | Resonator with pre-embedded sacrificial layer structure and preparation method thereof |
| CN115001429A (en) * | 2022-08-03 | 2022-09-02 | 迈感微电子(上海)有限公司 | Preparation method of filter |
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