CN117040451A - Balanced power amplifier and method for improving linearity - Google Patents
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- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
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Abstract
The application provides a balanced power amplifier and a method for improving linearity, comprising an input end, a power amplifying module and an output end, wherein the input end is used for equally dividing power through an input Lange coupler, and the output Lange coupler is used for carrying out power synthesis output after passing through a symmetrical power amplifying circuit. The application reduces IMD intermodulation components and improves the power amplification degree by utilizing the millimeter wave power amplification circuit matching technology. The gain compression characteristics of the front stage and the rear stage of the power amplifier are opposite by selecting proper static working points, so that the compression quantity of the phase is reduced, and the linearity is improved. Meanwhile, a harmonic matching technology is adopted, and a second harmonic series resonance matching technology is utilized, so that the inhibition degree and efficiency are improved.
Description
Technical Field
The application relates to the technical field of radio frequency integrated circuits, in particular to a balanced power amplifier and a method for improving linearity.
Background
High performance and high linearity monolithic microwave integrated circuit driver/power amplifiers for use in the Ka band are increasingly demanded in commercial wireless communications (e.g., point-to-point digital communications and radio) and advanced military millimeter wave systems. To meet the demands for high efficiency, high power, broadband operation and small size in active phase radar, future cellular, local multipoint distribution service and satellite communication applications, alGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors are distinguished by the advantages of high power density and high gain.
The power amplifier is used as a core component in the T/R assembly, primarily by using the obtained dc energy for amplifying the ac input energy. The linearity index is particularly important in order to ensure that the amplified signal does not undergo severe distortion, which would interfere with subsequent decoding. Meanwhile, the stability index directly influences the application of the power amplifier in different scenes, and parasitic capacitance in the transistor needs to be considered in the design process to form a positive feedback circuit so as to enable the circuit to self-oscillate. The stability of the circuit may be affected by changes in the ambient temperature and voltage supply. The millimeter wave transmitted in Ka band is short, so that the millimeter wave can only cover a smaller area range and is easy to be blocked under the conditions of free space propagation loss, penetration loss and diffraction loss. Therefore, in order to overcome the disadvantages of millimeter wave communication and meet the transmission requirements of the system, it is required to improve the output performance of the power amplifier. The application mainly provides a millimeter wave power amplifier for comprehensively improving linearity, efficiency and stability to solve the problems.
Disclosure of Invention
The application provides a balanced power amplifier, which comprises an input end, a power amplifying module and an output end, wherein the input end is used for dividing power equally through an input Lange coupler, and the power is synthesized and output through an output Lange coupler after passing through a symmetrical power amplifying circuit.
Preferably, the symmetrical power amplifying circuit comprises two power amplifying units, and each power amplifying unit consists of four stages of amplifying circuits and is in the working state of the class AB amplifier.
Preferably, the input signal of the power amplifier enters from the port A1 of the input Lange coupler, the port B1 and the port C1 are used as output ends, the amplitude of the output signals is equal, and the phase difference is 90 degrees.
Preferably, the output signals of the port B1 and the port C1 of the input Lange coupler are input through the port C2 and the port B2 of the output Lange coupler of the output end after passing through the two symmetrical power amplifiers, and the amplified power signal is output through the port A2 of the output Lange coupler after power synthesis.
Preferably, the input signal reaches the gate end of the transistor M1 through the blocking capacitor, the drain end output of the transistor M1 reaches the gate end of the transistor M2 through the blocking capacitor, the drain end of the transistor M2 is divided into two paths of signals to enter the gate end of the transistor M3 after passing through the blocking capacitor, the drain end of the transistor M3 is divided into two paths to enter the gate end of the transistor M4 after passing through the blocking capacitor, and the two paths of signals are combined into one path after being output through the blocking capacitor.
Preferably, the transistor M3 includes an upper transistor M31 and a lower transistor M32, and the transistor M4 includes a first upper transistor M41, a second upper transistor M42, a first lower transistor M43 and a second lower transistor M44.
Preferably, the lengths of the microstrip lines of the power distribution and the power synthesis corresponding to the transistor M3 and the transistor M4 are equal, and the layout is completely symmetrical.
Preferably, RC parallel circuits are added between the gate ends of the transistor M1 and the transistor M2 and the gate bias circuit so as to reduce low-frequency gain, thereby improving the overall stability of the circuit; the circuit adopts LC series resonance technology to match under the second harmonic, so that the impedance presented by the circuit to the fundamental wave is capacitive.
The method for improving the linearity of the circuit by using the balanced power amplifier is that the size of the transistor M1 is smaller than that of the transistors M2, M3 and M4, and the transistor M1 is used for improving the gain performance of the circuit and driving the transistor M2 to work; the size of the transistors M2 and M3 is larger to ensure that the transistor M4 is driven to work by outputting enough power, the size of the transistor M4 is determined by an output power index and power density, and the optimal output is realized through load traction; in order to ensure the high linearity requirement of the whole circuit, the four-stage pipes all work in a linear region, and when the size is selected, the corresponding qualification power of each stage is ensured to be larger than the output power of index splitting, so that the transistor does not work in a saturation region.
Preferably, the transistors M1, M2, M3, M4 are all independently powered, and a suitable static operating point is selected to enable the transistors to operate in different states, and the current densities of the corresponding transistors are unequal, so that the gain characteristics of each stage are independently controlled, the gain characteristics of the front stage and the back stage are opposite, and the phase compression amount is reduced; the gain of the final stage circuit is enabled to be in a high-end increasing state, and after the gain curves of the final stage circuit and the previous three stages of circuits are overlapped, the linearity of the circuit is effectively improved.
The above-described features may be combined in various suitable ways or replaced by equivalent features as long as the object of the present application can be achieved.
The power amplifier is one of the most important components in the transmit/receive module and the communication system. Power Added Efficiency (PAE) and output power level are considered key parameters for many applications. The power amplifier occupies more than 60% of the energy consumption of the whole communication system, and the next generation wireless communication system needs higher additional efficiency and stronger reliability. The power amplifier works in a nonlinear state, and the working efficiency of the power amplifier can reach about 1.5 times of the normal working efficiency. Therefore, in order to meet the requirement of high efficiency, the nonlinear radio frequency power needs to be properly regulated and utilized, but clutter can be generated on the basis of the original input signal, so that the transmission signal is distorted, and the error rate of the signal can be increased by the interference. The application of various linearization techniques is therefore required to improve channel quality. Power amplifiers typically operate in a large signal mode, wherein parasitic reactance from nonlinear effects of various components is prone to cause various oscillations, which can lead to power amplifier failure. The circuit stability of the power amplifier in different application scenes needs to be improved in order to ensure the safe operation of the equipment.
Compared with the prior art, the balanced power amplifier and the method for improving the circuit linearity have the following beneficial effects:
the application reduces IMD intermodulation components and improves the power amplification degree by utilizing the millimeter wave power amplification circuit matching technology. The gain compression characteristics of the front stage and the rear stage of the power amplifier are opposite by selecting proper static working points, so that the compression quantity of the phase is reduced, and the linearity is improved. Meanwhile, a harmonic matching technology is adopted, and a second harmonic series resonance matching technology is utilized, so that the inhibition degree and efficiency are improved. And the radio frequency circuit RC matching structure is adopted to reduce low frequency gain and improve stability, and an electric arm is introduced to increase resistive matching to improve high frequency stability. The millimeter wave packaging technology is adopted in the processing of the material object, and the thick copper and copper interconnection holes on the surface can improve the heat conductivity; the photoetching pattern of the ceramic substrate can ensure scattering while improving precision, and the highest chip temperature of the power amplifier is controlled in a normal range to maintain the stability of long-term application and ensure the high-frequency application and reliability of the circuit.
Drawings
The application will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
FIG. 1 shows a schematic diagram of a power amplifier of the present application;
FIG. 2 shows a circuit diagram of a power cell of the present application;
FIG. 3 shows a circuit diagram of an RC parallel stabilizing network of the present application;
FIG. 4 shows a final circuit gain plot of the present application;
FIG. 5 shows an actual measurement of the S parameter of the present application;
FIG. 6 shows a graph of the saturated power and efficiency measurements of the present application;
FIG. 7 shows an actual measurement of OIP3 of the present application;
description of the embodiments
The application will be further described with reference to the accompanying drawings.
As shown in fig. 1, the application provides a balanced power amplifier, which comprises an input end, a power amplifying module and an output end, wherein the input end is used for equally dividing power through an input Lange coupler, and the power is synthesized and output through an output Lange coupler after passing through a symmetrical power amplifying circuit.
In one embodiment, the symmetrical power amplifying circuit comprises two power amplifying units, and each power amplifying unit consists of four stages of amplifying circuits and is in the working state of the class AB amplifier.
In one embodiment, the input signal of the power amplifier enters from the port A1 of the input Lange coupler, the port B1 and the port C1 are used as output terminals, and the output signals have equal amplitude and are 90 degrees out of phase.
In one embodiment, the output signals of the port B1 and the port C1 of the input Lange coupler are input through the port C2 and the port B2 of the output Lange coupler of the output end after passing through two symmetrical power amplifiers, and the amplified power signal is output through the port A2 of the output Lange coupler after power synthesis.
In one embodiment, the input signal reaches the gate terminal of the transistor M1 through the blocking capacitor, the drain terminal output of the transistor M1 reaches the gate terminal of the transistor M2 through the blocking capacitor, the drain terminal of the transistor M2 is divided into two paths of signals to enter the gate terminal of the transistor M3 after passing through the blocking capacitor, the drain terminal of the transistor M3 is divided into two paths to enter the gate terminal of the transistor M4 after passing through the blocking capacitor, and the two paths of signals are combined into one path after being output through the blocking capacitor.
In one embodiment, the transistor M3 includes an up transistor M31 and a down transistor M32, and the transistor M4 includes a first up transistor M41, a second up transistor M42, a first down transistor M43, and a second down transistor M44.
In one embodiment, the microstrip lines of the power distribution and the power synthesis corresponding to the transistor M3 and the transistor M4 have equal lengths and are completely symmetrical in layout.
In one embodiment, RC parallel circuits are added between the gate ends of the transistor M1 and the transistor M2 and the gate bias circuit to reduce low-frequency gain, so that the overall stability of the circuit is improved; the circuit adopts LC series resonance technology to match under the second harmonic, so that the impedance presented by the circuit to the fundamental wave is capacitive.
The method for improving the linearity of the circuit by using the balanced power amplifier is that the size of the transistor M1 is smaller than that of the transistors M2, M3 and M4, and the transistor M1 is used for improving the gain performance of the circuit and driving the transistor M2 to work; the size of the transistors M2 and M3 is larger to ensure that the transistor M4 is driven to work by outputting enough power, the size of the transistor M4 is determined by an output power index and power density, and the optimal output is realized through load traction; in order to ensure the high linearity requirement of the whole circuit, the four-stage pipes all work in a linear region, and when the size is selected, the corresponding qualification power of each stage is ensured to be larger than the output power of index splitting, so that the transistor does not work in a saturation region.
In one embodiment, the transistors M1, M2, M3, and M4 are all independently powered, and a suitable static operating point is selected to enable the transistors to operate in different states, so that the current densities of the corresponding transistors are not equal, and thus the gain characteristics of each stage are independently controlled to enable the gain characteristics of the front stage and the back stage to be opposite, and the phase compression amount is reduced; the gain of the final stage circuit is enabled to be in a high-end increasing state, and after the gain curves of the final stage circuit and the previous three stages of circuits are overlapped, the linearity of the circuit is effectively improved.
The millimeter wave power amplifier can improve performance indexes of linearity, efficiency and stability to a certain extent. As shown in FIG. 1, the MMIC radio frequency power amplifier is a balanced amplifier and consists of an input Lange coupler, an amplifier chip unit and an output Lange coupler. The amplifier chip unit further comprises an input impedance matching network, a grid direct current bias network, a power amplifying transistor, a drain direct current bias network and an output impedance matching network. The input impedance matching network mainly comprises a microstrip line, a blocking capacitor, a grounding capacitor and a resistor-capacitor parallel circuit structure; the grid direct current bias network is mainly used for providing grid bias voltage of the transistor by a microstrip line, a resistor and a filter capacitor structure; the drain DC bias network mainly comprises a microstrip line and a filter capacitor structure for providing drain bias voltage of the transistor; the output impedance matching network mainly comprises a microstrip line, a blocking capacitor and a grounded capacitance structure.
In one embodiment, the amplifier chip unit of the application adopts a balanced amplifier structure, the input end is subjected to power halving through a Lange coupler, and the power synthesis output is performed through the Lange coupler after passing through two symmetrical power amplifying circuits. Each power unit consists of a four-stage amplifying circuit and is in the working state of the AB class amplifier.
In one embodiment, the front-end transistor amplification circuit of the amplifier chip unit is referred to as a driver stage amplification circuit, the high end of the gain curve of which exhibits a tendency to decay. The gain curve of the final-stage amplifying circuit can be expanded through designing the output impedance matching network, as shown in fig. 4, the gain is relatively flat after the final driving stage and the final stage are overlapped, and the phase compression amount is reduced, so that the linearity of the millimeter wave power amplifier is improved.
In one embodiment, the output impedance matching network adopts a second harmonic series resonance matching technology to participate in output matching under the condition that the fundamental wave is in a capacitive state, so that the output power efficiency and the second harmonic suppression degree are improved.
In one embodiment, in order to meet the stability of the circuit in different application scenarios, an RC parallel structure is connected in series between the input ends of the first two-stage transistors M1 and M2 and the gate dc bias network, as shown in fig. 3, so that the stability of the circuit is improved without affecting the radio frequency performance.
In one embodiment, the material object processing adopts millimeter wave packaging technology, and the thick copper and copper interconnection holes on the surface can improve the heat conductivity; the photoetching pattern of the ceramic substrate can ensure scattering while improving precision, and the highest chip temperature of the power amplifier is controlled in a normal range to keep the stability of long-term application.
In one embodiment, a balanced amplifier structure is adopted, and a Lange coupler with small phase error, tight coupling, high directivity, low standing wave ratio, low insertion loss and small volume is selected for design. The input signal of the power amplifier enters from the port A1 of the input Lange coupler, the port B1 and the port C1 are used as output ends, the amplitude of the output signals is equal, and the phase difference is 90 degrees. Normally, port D1 is an isolated port with no power output. Output signals of a port B1 and a port C1 of the input Lange coupler are input through a port C2 and a port B2 of the output Lange coupler after passing through two symmetrical power amplifying units, amplified power signals are output through a port A2 of the output Lange coupler after power synthesis, and full-band loss is less than 0.45dB through reasonable design.
In one embodiment, each stage of transistor constructs a complete power amplification circuit through an input impedance matching circuit, a grid direct current bias circuit, a drain direct current bias circuit and an output impedance matching circuit. The amplifier chip unit mainly comprises two symmetrical power amplifying units, wherein the structure of each unit is shown in fig. 2, an input signal reaches the gate end of a transistor M1 through a blocking capacitor, the output of the drain end of the transistor M1 reaches the gate end of a transistor M2 through the blocking capacitor, the drain end of the transistor M2 is divided into two paths of signals after passing through the blocking capacitor and enters the gate end of a transistor M3, the drain end of the transistor M3 is divided into two paths of signals after passing through the blocking capacitor and enters the gate end of a transistor M4, and the transistors M4 are combined into one path after being combined in pairs and output through the blocking capacitor. In order to ensure the consistency of signals, the lengths of the microstrip lines of the power distribution and the power synthesis corresponding to the transistor M3 and the transistor M4 are equal, and the layout is completely symmetrical. RC parallel circuits shown in FIG. 3 are added between the gate ends of the transistor M1 and the transistor M2 and the gate bias circuit, so that the low-frequency gain is reduced, and the overall stability of the circuit is improved. The circuit adopts an LC series resonance technology to match under the second harmonic, so that the impedance presented by the circuit to the fundamental wave is capacitive, and the second harmonic is restrained, thereby improving the additional efficiency of the circuit. Wherein the final power loss of a single power cell is only 0.2dB.
In one embodiment, the input stage, transistor M1, is primarily used to improve the gain performance of the circuit and drive transistor M2 into operation, with a smaller size to achieve higher gain, and a size selected to achieve a target output power and efficiency by a source pull optimization tradeoff. The size of transistors M2 and M3 should be chosen to be large to ensure that the output power is large enough to drive transistor M4, but excessive size should be avoided from wasting power and reducing efficiency. The size of transistor M4 is determined primarily by the output power index and power density, and optimal output can be achieved by load pulling. In order to ensure the high linearity requirement of the whole circuit, the four-stage pipes all work in a linear region, and when the size is selected, the corresponding power of each stage is ensured to be larger than the output power of index splitting, so that the pipes do not work in a saturation region.
In one embodiment, as the gain of the frequency boosting circuit decreases, in order to increase the output power and linearity, the transistors M1, M2, M3, M4 are independently powered to select appropriate static operating points to operate in different states, and the corresponding tube current densities are not equal, so that the gain characteristics of each stage are independently controlled, and the gain characteristics of the front stage and the back stage are opposite, so that the phase compression is reduced. The gain of the final stage circuit is in a high-end increased state through design, which is shown in fig. 4, and the linearity of the circuit can be effectively improved after the gain is overlapped with the gain curve of the previous three stages of circuits.
In one embodiment, the leadless ceramic package is pasted by a 7mm x 7mm surface, so that watertight grade packaging can be realized, and the surface of a pin bonding pad is treated by a nickel-plating gold process, so that the leadless ceramic package is suitable for a reflow soldering installation process. The surface of the ceramic substrate is provided with thick copper and copper interconnecting holes so as to improve the thermal conductivity and the photoetching pattern improving precision of the ceramic substrate, ensure heat dissipation, and control the highest chip temperature of the power amplifier to be in a normal range so as to ensure the high-frequency application and reliability of the circuit.
In one embodiment, as shown in fig. 5, the result of the millimeter wave power amplifier S parameter test proposed by the present application is shown. Under the continuous wave and +6V working voltage, the millimeter wave power amplifier tests the input reflection coefficient and the output reflection coefficient of the millimeter wave power amplifier in a frequency range of 37GHz-40GHz, and the small signal gain is about 25dB. The output power and efficiency are shown in fig. 6, the saturated output power is 34dBm, and the corresponding power added efficiency is 25% -28%. It can be seen from fig. 7 that the third-order intermodulation cut-off point of the output of the embodiment is about 40 dBm. In short, the test performance of the real device is better, and the linearity, efficiency and stability of the power amplifier can be comprehensively improved.
Although the application herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present application. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present application as defined by the appended claims. It should be understood that the different dependent claims and the features described herein may be combined in ways other than as described in the original claims. It is also to be understood that features described in connection with separate embodiments may be used in other described embodiments.
Claims (10)
1. The balanced power amplifier is characterized by comprising an input end, a power amplification module and an output end, wherein the input end is used for equally dividing power through an input Lange coupler, and the symmetrical power amplification circuit is used for outputting power through an output Lange coupler.
2. The balanced power amplifier according to claim 1, wherein the symmetrical power amplifying circuit comprises two power amplifying units, each power amplifying unit being composed of four stages of amplifying circuits and being in an operating state of the class AB amplifier.
3. The balanced power amplifier according to claim 2, wherein the input signal of the power amplifier enters from the A1 port of the input Lange coupler, the ports B1 and C1 are output terminals, and the output signals have equal amplitude and are 90 degrees out of phase.
4. The balanced type power amplifier according to claim 3, wherein the output signals inputted to the port B1 and the port C1 of the Lange coupler are inputted from the port C2 and the port B2 of the Lange coupler at the output end after passing through the two symmetrical power amplifying units, and the amplified power signal is outputted from the port A2 of the Lange coupler after power synthesis.
5. The balanced power amplifier according to claim 4, wherein the input signal reaches the gate terminal of the transistor M1 through the blocking capacitor, the drain terminal output of the transistor M1 reaches the gate terminal of the transistor M2 through the blocking capacitor, the drain terminal of the transistor M2 is divided into two paths of signals after passing through the blocking capacitor, the drain terminal of the transistor M3 is divided into two paths of signals after passing through the blocking capacitor, and the two paths of signals enter the gate terminal of the transistor M4, and the two paths of signals are combined into one path after being output through the blocking capacitor.
6. The balanced power amplifier according to claim 5, wherein the transistor M3 comprises an upper transistor M31 and a lower transistor M32, and the transistor M4 comprises a first upper transistor M41, a second upper transistor M42, a first lower transistor M43 and a second lower transistor M44.
7. The balanced power amplifier according to claim 6, wherein the microstrip lines of the power distribution and power synthesis of the transistor M3 and the transistor M4 are equal in length and are completely symmetrical in layout.
8. The balanced power amplifier according to claim 5, wherein RC parallel circuits are added between the gate terminals of the transistor M1 and the transistor M2 and the gate bias circuit to reduce low frequency gain, thereby improving the overall stability of the circuit; the circuit adopts LC series resonance technology to match under the second harmonic, so that the impedance presented by the circuit to the fundamental wave is capacitive.
9. A method for improving linearity using a balanced power amplifier according to any of claims 1-8, characterized in that the transistor M1 is smaller in size than the transistors M2, M3 and M4, the transistor M1 being used to improve gain performance of the circuit and to drive the transistor M2 into operation; the size of the transistors M2 and M3 is larger to ensure that the transistor M4 is driven to work by outputting enough power, the size of the transistor M4 is determined by an output power index and power density, and the optimal output is realized through load traction; in order to ensure the high linearity requirement of the whole circuit, the four-stage pipes all work in a linear region, and when the size is selected, the corresponding qualification power of each stage is ensured to be larger than the output power of index splitting, so that the transistor does not work in a saturation region.
10. The method for improving linearity of balanced power amplifier according to claim 9, wherein transistors M1, M2, M3, M4 are all independently powered, and a suitable static operating point is selected to make the transistors operate in different states, and the corresponding transistor current densities are not equal, so that gain characteristics of each stage are controlled separately, gain characteristics of the front stage and the back stage are opposite, and thus phase compression is reduced; the gain of the final stage circuit is enabled to be in a high-end increasing state, and after the gain curves of the final stage circuit and the previous three stages of circuits are overlapped, the linearity of the circuit is effectively improved.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117278111A (en) * | 2023-11-21 | 2023-12-22 | 南京纳特通信电子有限公司 | L-S wave band power amplifier assembly |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117278111A (en) * | 2023-11-21 | 2023-12-22 | 南京纳特通信电子有限公司 | L-S wave band power amplifier assembly |
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