CN117038450A - Manufacturing method of device with carrier storage interlayer, semiconductor device and insulated gate bipolar transistor - Google Patents
Manufacturing method of device with carrier storage interlayer, semiconductor device and insulated gate bipolar transistor Download PDFInfo
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- CN117038450A CN117038450A CN202311129596.0A CN202311129596A CN117038450A CN 117038450 A CN117038450 A CN 117038450A CN 202311129596 A CN202311129596 A CN 202311129596A CN 117038450 A CN117038450 A CN 117038450A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
The invention discloses a manufacturing method of a device with a carrier storage interlayer, a semiconductor device and an insulated gate bipolar transistor, wherein the method comprises the steps of cleaning a monocrystalline silicon wafer as a device substrate; growing an epitaxial layer on top of the substrate; selectively implanting ions on the epitaxial layer to form a super junction region with alternating P columns and N columns; growing to form a P-base region; growing to form an N-type carrier storage interlayer; ion implantation is carried out on the surface of the carrier storage interlayer to form an N-type emission region and a P+ region, and metal deposition is carried out on the N-type emission region and the P+ region to form emitter conductive metal of the device; photoetching to form a deep groove region; depositing polysilicon in the deep groove to form a groove gate, and performing metal deposition on the groove gate to form a gate conductive metal of the device; metal deposition is performed to form the collector conductive metal of the device. The introduced N-type carrier storage interlayer enables the device to have low forward voltage characteristics, and the super junction region enhances the conductivity modulation effect of the base region.
Description
Technical Field
The present invention relates to the field of power semiconductors, and more particularly, to a method for manufacturing a device having a carrier storage interlayer, a semiconductor device, and an insulated gate bipolar transistor.
Background
In recent years, with the rapid spread of power electronics in the fields of computers, industries, and the like, the demand for high-voltage IGBT (Insulated Gate Bipolar Transistor, insulated bipolar transistor) devices in power semiconductor devices has increased. To meet this demand, superjunction IGBTs have been developed. Compared with the traditional IGBT, the super-junction IGBT overcomes the limitation of silicon materials by realizing high voltage capability and low loss in a shorter drift region length, and can extract carriers more quickly, thereby improving the switching speed of the device and ensuring safe operation. However, minority carriers in the emitter region of the superjunction IGBT in the prior art are still limited, resulting in a significant on-resistance of the base region. The contradiction between low on-resistance requirements and high breakdown voltage requirements of the device is still evident.
Disclosure of Invention
In view of the problems existing in the prior art, the present invention provides a method for manufacturing a device having a carrier storage interlayer, comprising:
s100, cleaning a monocrystalline silicon wafer as a device substrate;
s200, growing an epitaxial layer on the top of the device substrate;
s300, selectively implanting ions on the epitaxial layer to form a super junction region with alternating P columns and N columns;
s400, growing epitaxy on the surface of the super junction region to form a P-base region;
s500, implanting ions into the surface of the P-base or epitaxially growing to form an N-type carrier storage interlayer;
s600, performing ion implantation on the surface of the carrier storage interlayer to form an N-type emission region and a P+ region, and performing metal deposition on the N-type emission region and the P+ region to form emitter conductive metal of the device;
s700, forming a deep groove region in the photoetching target region; depositing polysilicon in the deep groove to form a groove gate, and performing metal deposition on the groove gate to form a gate conductive metal of the device;
and S800, performing metal deposition on the back surface of the substrate to form collector conductive metal of the device.
Further, the doping concentration of the epitaxial layer is 400-500 Ω -cm.
Further, selective ion implantation on the epitaxial layer to form a super junction region of alternating P-pillars and N-pillars, comprising: the implantation junction depth of the selected P-type ions or N-type ions is 8-12 um.
Further, selectively implanting ions on the epitaxial layer to form a super junction region with alternating P-pillars and N-pillars, further comprising:
the thickness of the P column or the N column is 80-120 um.
Further, the selective ion implantation on the epitaxial layer to form a super junction region with alternating P pillars and N pillars, further comprises the following steps:
s301: p type or N type ion implantation is selected in the epitaxial layer;
s302: rapid thermal annealing to activate the doping impurities;
s303: steps S301, S302 are repeated five or more times to form the superjunction region with alternating P pillars and N pillars.
Further, the thickness of the N-type carrier storage interlayer is 10-20 um.
Further, the p+ region is connected to the P-base and the carrier storage interlayer.
Further, the target region is a region located at the left side of the P-base and the carrier storage interlayer, the bottom of the deep groove region penetrates through the N-type emission region, the carrier storage interlayer and the P-base, and the deep groove region is connected with the N column.
Further, the depositing polysilicon in the deep groove and performing metal deposition to form the grid electrode of the device comprises the following steps:
and photoetching the side wall of the deep groove, growing a gate oxide layer at the bottom of the deep groove, and depositing polysilicon on the surface of the gate oxide layer to form a trench gate.
Further, growing a gate oxide layer at the bottom of the deep groove comprises:
growing a silicon dioxide layer on the surface of the deep groove by using a dry oxidation method;
the wet oxidation process is continued to grow the gate oxide layer.
Further, before the metal deposition is performed on the back surface of the substrate to form the collector conductive metal of the device, the method further comprises the following steps:
step S801, implanting ions on the back surface of the substrate to form an electric field blocking layer, wherein the electric field blocking layer is adjacent to the bottoms of the P column and the N column;
step S802, injecting P-type ions into the electric field blocking layer to form a collector region;
and step 803, performing metal deposition on the surface of the collector region to form collector conductive metal of the device.
The invention also provides a semiconductor device which is manufactured by adopting any one of the manufacturing methods of the device with the carrier storage interlayer.
The invention also provides an insulated gate bipolar transistor which is manufactured by any one of the manufacturing methods of the device with the carrier storage interlayer.
The invention provides a manufacturing method of a device with a carrier storage interlayer, which comprises the steps of cleaning a monocrystalline silicon wafer as a device substrate; growing an epitaxial layer on the top of the device substrate; selectively implanting ions on the epitaxial layer to form a super junction region with alternating P columns and N columns; performing epitaxial growth on the surface of the super junction region to form a P-base region; ion implantation or epitaxial growth is carried out on the surface of the P-base to form an N-type carrier storage interlayer; ion implantation is carried out on the surface of the carrier storage interlayer to form an N-type emission region and a P+ region, and metal deposition is carried out on the N-type emission region and the P+ region to form emitter conductive metal of the device; forming a deep groove region in the photoetching target region; depositing polysilicon in the deep groove to form a groove gate, and performing metal deposition on the groove gate to form a gate conductive metal of the device; and carrying out metal deposition on the back surface of the substrate to form collector conductive metal of the device. According to the invention, the carrier storage interlayer is introduced into the surface of the P-base region to form a hole barrier for preventing holes from flowing into the P-base region, and the carrier storage interlayer can enhance electron injection of the super junction region, so that the penetration modulation effect is enhanced, and therefore, the device has lower forward voltage characteristics by introducing the N-type carrier storage interlayer at one side of the emitter; the super junction areas of the P columns and the N columns are alternately arranged, so that the breakdown voltage of the device is not influenced by charge balance, and the conductance modulation effect of the base region is enhanced under the condition that the breakdown voltage is not influenced, thereby obviously reducing the on voltage.
Drawings
Embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements, and wherein:
FIG. 1 is a flow chart of a manufacturing method in one embodiment of the invention;
FIG. 2 is a schematic diagram of a monocrystalline silicon wafer in an embodiment of the present invention after formation of a superjunction structure;
FIG. 3 is a schematic diagram of a single crystal silicon wafer after forming a carrier storage interlayer according to an embodiment of the present invention;
FIG. 4 is a schematic illustration of a monocrystalline silicon piece after forming an N+ region in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of a device after forming a gate oxide and a trench gate in one embodiment of the invention;
FIG. 6 is a schematic diagram of a device after forming an electric field blocking layer and a collector region in accordance with one embodiment of the present invention;
FIG. 7 is a schematic diagram of a device with a carrier storage interlayer after the device is formed with a conductive metal in accordance with an embodiment of the present invention;
FIG. 8 shows electron concentration of a device in an on mode according to an embodiment of the present invention;
fig. 9 is a graph showing electron concentration in the on-mode of the lower device of the prior art;
FIG. 10 is a graph showing the comparison of the conduction voltage of a super-junction IGBT and a conventional super-junction IGBT according to an embodiment of the invention;
fig. 11 is a graph comparing breakdown voltages of a superjunction IGBT according to an embodiment of the present invention and a conventional superjunction IGBT.
Description of the reference numerals:
10. a substrate; 20. p-base; 30. a superjunction region; 40. carrier storage interlayers; 50. an N-type emission region; 60. a P+ region; 70. a gate oxide layer; 71. a trench gate; 80. an electric field blocking layer; 81. collector region
Detailed Description
It should be noted that, without conflict, embodiments of the present invention and features in the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution of an embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiment of the present invention, and it is apparent that the described embodiment is only a part of the embodiment of the present invention, not all the embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, shall fall within the scope of the invention.
The on-voltage drop of the super-structure IGBT mainly results from the voltage drop (vp+n) of the N-substrate 10, i.e., the PN junction formed between the N drift region and the p+ collector region 81, the resistance voltage drop (VNB) of the N-substrate 10N drift region and the buffer layer due to the conductance modulation effect, and the voltage drop (VMOSFET) of the positive MOSFET portion. Therefore, by reducing the resistance of the MOSFET portion, the on-voltage of the device can be effectively reduced without changing the breakdown voltage.
According to the invention, the super junction region 30 is alternately formed by selectively implanting ions into the epitaxial layer to form the P columns and the N columns, so that the Breakdown Voltage (BV) of the super structure of the device is influenced by charge balance between the alternately arranged P columns and N columns, and the device enhances the conductivity modulation effect of the base region under the condition that the breakdown voltage is not influenced, thereby remarkably reducing the on voltage.
The current IGBT emitter has limited carrier quantity, so that on-resistance is higher, power consumption is lower, and the carrier quantity of the emitter is improved to meet the increasing demands of IGBT devices in the current high-power semiconductor industry. In order to further reduce the forward on-resistance of the super-junction IGBT and not reduce the reverse breakdown voltage of the super-junction IGBT, the invention additionally introduces a carrier storage interlayer 40 in a neutral body region to increase the injection of few electrons on the basis of the original super-junction IGBT power semiconductor device structure, thereby effectively solving the problem of overlarge on-resistance in the semiconductor device, reducing the on-resistance and simultaneously not influencing the breakdown voltage of the device and the short-circuit safe operating area range SC-SOA (Short Circuit Safe Operating Area, short-circuit safe operating area).
According to the invention, the carrier storage interlayer 40 is introduced into the surface of the P-base20 region to form a hole barrier for preventing holes from flowing into the P-base20 region, and the carrier storage interlayer 40 can enhance electron injection of the super junction region 30, so that the penetration modulation effect is enhanced, and therefore, the device has lower forward voltage characteristics by introducing the N-type carrier storage interlayer 40 at one side of an emitter. N-type carrier storage interlayer 40 replaces a portion of the prior art P-base20 region to prevent holes from immediately transporting to the emitter, and improves electron current density, so that the plasma density of the N-drift region is enhanced, thereby realizing stronger conductivity modulation. Usually when the device is in the blocking state, the carriers of the column region are depleted, the voltage drop is mainly borne by the N and P columns, and the current density jce=150a/cm between the collector and the emitter 2 The gate voltage vg=15v, which gives the device a lower on-voltage, but the breakdown voltage is reduced. By increasing the concentration of the N-type carrier-storage interlayer 40, the conduction voltage drop can be reduced without reducing the breakdown voltage by using the manufacturing method of the present invention. The device exhibits an almost zero thermal coefficient in the on state and can be operated in parallel when the operating current density is slightly increased.
In one embodiment of the present invention, a method of manufacturing a device having a carrier storage interlayer 40 is provided. Fig. 1 is a flow chart of a method of manufacturing a device having a carrier-storage interlayer 40 in accordance with an embodiment of the present invention. As shown in fig. 1, the method includes:
s100, a silicon single crystal wafer is cleaned as the device substrate 10.
And S200, growing an epitaxial layer on the top of the device substrate 10.
S300, selectively implanting ions on the epitaxial layer to form the super junction region 30 with alternating P pillars and N pillars.
And S400, performing epitaxial growth on the surface of the superjunction region 30 to form a P-base region P-base20.
S500, ion implantation or epitaxial growth is carried out on the surface of the P-base20 to form the N-type carrier storage interlayer 40.
S600, ion implantation is performed on the surface of the carrier storage interlayer 40 to form an N-type emitter region 50 (source) and a p+ region 60, and metal deposition is performed on the N-type emitter region 50 and the p+ region 60 to form an emitter conductive metal of the device.
S700, forming a deep groove region in the photoetching target region; polysilicon is deposited in the deep grooves to form trench gates 71, and metal deposition is performed on the trench gates 71 to form the gate conductive metal of the device.
And S800, performing metal deposition on the back surface of the substrate 10 to form collector conductive metal of the device.
In some embodiments of the present invention, as shown in FIGS. 1 and 2, the single crystal silicon wafer in step S100 is a lightly doped N-type 8 inch single crystal silicon wafer having a resistivity of 800 to 1000 Ω & cm, and is cleaned using the RCA standard cleaning process. The N-type monocrystalline silicon wafer is used as a mechanical support of a device, a collector region and ohmic contact thereof.
Step S200, growing an epitaxial layer on the top of the device substrate 10, specifically, forming a monocrystalline silicon epitaxial layer with low doping concentration on the surface of the device substrate 10 by adopting a solid phase epitaxy method, namely, growing the monocrystalline silicon epitaxial layer on the device substrate 10 silicon wafer in a silane atmosphere at 800-1000 ℃ for 10-60 minutes by adopting a Chemical vapor deposition method (Chemical VaporDeposition, CVD), wherein the thickness of the grown monocrystalline silicon epitaxial layer is 10-30 um; the in-situ doping method is adopted to enable the resistivity corresponding to the doping concentration of the epitaxial layer to be about 200-1000 ohm cm. The high-resistance monocrystalline silicon layer is grown by adopting CVD, so that the reaction temperature can be reduced, and the reaction rate can be enhanced. The reaction gas is SiH4, the reaction temperature is 600-700 ℃, the pressure of the reaction cavity is 11-14 Pa, the reaction time is 10-20min, and the silane flow is 13.1-17.5 sccm.
In one embodiment of the present invention, the doping concentration of the epitaxial layer is 400 to 500 Ω·cm.
In an embodiment of the present invention, step S300, selectively implanting ions on the epitaxial layer to form the super junction region 30 with alternating P pillars and N pillars, further comprises:
step S301: p type or N type ion implantation is selected in the epitaxial layer;
step S302: rapid thermal annealing to activate the doping impurities;
step S303: steps S301, S302 are repeated five or more times to form a superjunction region 30 of alternating P-pillars and N-pillars.
In one embodiment of the present invention, in step S300, the implantation junction depth of the selected P-type ion or N-type ion is 8-12 um.
In an embodiment of the present invention, in step S300, the thickness of the P pillar or the N pillar is 80-120 um.
In one embodiment of the present invention, further, selective ion implantation and annealing are performed on the epitaxial layer, wherein the junction depth of the selective ion implantation is 10um, and then rapid thermal annealing activation is performed to dope the impurities. Repeating S301 and S302 five times to form super junction region 30 with P columns and N columns alternating, wherein the preferable thickness of the P columns and the N columns is 100um. The columnar superjunction region 30 can withstand most of the reverse withstand voltage of the device. The doping concentration, thickness (or height) of the P column and the N column can be adjusted according to the voltage withstanding level required by the device.
In step S400, the P-base20 is formed by performing epitaxial growth on the surface of the superjunction region 30, and further, the doping concentration of the target P-base20 is adjusted by performing rapid thermal annealing to activate the doping impurities after performing P-type ion implantation on the superjunction region 30 and changing the flow of the doping gas. The P-base20 region is formed by P-type ion implantation, and P-base20 is the contact region between the emitter region and the base region. Only the epitaxial growth is needed to form the P-base20, and only the ion implantation and annealing processes are needed, so that the epitaxial growth process is saved, and the process cost is reduced.
As shown in fig. 3, in step S500, ions are implanted into the surface of P-base20 or epitaxially grown to form N-type carrier storage interlayer 40, and further, the thickness of carrier storage interlayer 40 may be adjusted by adjusting the ion implantation energy. The thickness of carrier storage interlayer 40 may be adjusted in the range of 10 to 20um. In the present invention, the thickness and depth of the carrier storage interlayer 40 are adjusted to meet the requirements of breakdown voltage and on-resistance performance, such as adjusting the ion implantation energy or dose to deepen the depth or doping concentration of the carrier storage interlayer, so as to further reduce the on-resistance and on-voltage drop of the device. In one embodiment of the present invention, the thickness of N-carrier storage interlayer 40 may vary from 10 to 20um, with the thickness of carrier storage interlayer 40 preferably being 10um. Carrier storage interlayer 40 is centered in P-base20. According to the invention, an N-type carrier storage interlayer 40 is introduced at one side of the emitter, the N-type carrier storage interlayer 40 replaces a part of the traditional P-base20 region, and the carrier storage interlayer 40 can prevent holes from being immediately transmitted to the emitter, so that the electron current density is improved. The carrier interlayer enhances the plasma density of the N-drift region and achieves a stronger conductance modulation.
In one embodiment of the present invention, interlayer P+ region 60 is connected to P-base20 and carrier storage interlayer 40. In step S600, as shown in fig. 4, N-type emitter 50, i.e., the n+ region in fig. 3-6, N-type emitter 50 is the source for forming the MOS structure, and p+ region 60 is connected to P-base20, which forms an ohmic contact with the emitter metal.
In one embodiment of the present invention, the target region is a region located on the left side of P-base20 and carrier storage interlayer 40, and the bottom of the deep recess region penetrates N-type emitter region 50, carrier storage interlayer 40 and P-base20, and the deep recess region is connected to the N pillar. Further, step S700 includes photolithography of the deep trench sidewall of the target region, growth of a gate oxide layer 70 at the bottom of the deep trench, and deposition of polysilicon on the surface of the gate oxide layer 70 to form a trench gate 71. Further, the lithographic target region may be defined as a lateral dimension in the range of 0.1-1.5 um to the right of the left edge of the device, and the depth of the deep recess may be in the range of 0.2-0.5 um. The deep trench etch may employ an ICP (Inductively Couple Plasma, inductively coupled plasma) etch process, or a deep silicon etch RIE process (Reaction Ion Etching, reactive ion etch).
In one embodiment of the present invention, as shown in fig. 5, growing a gate oxide layer 70 at the bottom of the deep trench comprises: growing a silicon dioxide layer on the surface of the deep groove by using a dry oxidation method; the wet oxidation process continues to grow gate oxide layer 70. Further, the first step uses a dry oxidation method to grow a dense silicon dioxide layer of 5-20 nm, and the second step uses a wet oxidation method to grow an oxide layer of 20-30 nm in thickness, so that the total gate oxide layer 70 is 25-50 nm in thickness. And (3) performing polysilicon deposition on the surface of the gate oxide layer 70 to form a polysilicon gate, performing cmp treatment to planarize the surface of the polysilicon gate, and then performing deposition of a silicon nitride passivation layer with the thickness of 300-1500 nm so as to perform passivation protection on the front surface of the silicon wafer. The deposited polysilicon may be silicon oxide or silicon nitride. When the passivation layer formed by the polysilicon is processed on the back surface of the device, the front surface of the device is protected by the passivation layer, so that the device is prevented from being polluted or damaged.
In one embodiment of the invention, after passivation of the front side of the device, the back side of the wafer is polished by a CMP chemical machine using a CMP process to thin the back side of the wafer to a desired thickness. Preferably, after the CMP process performs the thinning treatment, the thickness of the whole silicon wafer (including the passivation layer) is thinned to 200-500 um.
In an embodiment of the present invention, as shown in fig. 6 and 7, before the metal deposition is performed on the back surface of the substrate 10 to form the collector conductive metal of the device, the method further comprises the following steps:
in step S801, ions are implanted into the back surface of the substrate 10 to form an electric field stop layer 80, the electric field stop layer 80 being adjacent to the bottoms of the P and N pillars.
In step S802, P-type ions are implanted into the electric field stop layer 80 to form the collector region 81.
In step S803, a metal deposition is performed on the surface of the collector region 81 to form a collector conductive metal of the device.
In step S801, the electric field stop layer 80 abuts the bottoms of the N and P columns. The ions injected by the N-type electric field blocking layer 80 are P-type ions to increase the doping concentration of the N-type substrate 10, so that the N-type electric field blocking effect is realized, the voltage resistance of the device is borne by the superjunction region 30, and the voltage resistance of the device is improved. The P-type ions injected in step S802 reverse the bottom of the N-type substrate 10 from the highly doped N-type to the highly doped P-type, and the P-type collector 81 is adjacent to the N-type electric field stop layer 80 to form a p+/n+ highly doped PN junction. After P-type ion implantation is used in step S802, laser annealing is performed to activate the impurity-doped collector region 81 forming the superjunction IGBT. Metal deposition and annealing is performed on the surface of collector region 81, i.e., the back side of substrate 10, to form a collector metal, preferably aluminum.
The invention provides a manufacturing method of a device with a carrier storage interlayer, which selects a lightly doped monocrystalline silicon wafer and cleans the monocrystalline silicon wafer as a device substrate 10; growing an epitaxial layer on top of the device substrate 10; selective ion implantation on the epitaxial layer to form P-pillar and N-pillar alternating superjunction regions 30; performing epitaxial growth on the surface of the super junction region 30 to form a P-base region P-base20; ion implantation or epitaxial growth is carried out on the surface of the P-base20 to form an N-type carrier storage interlayer 40; ion implantation is carried out on the surface of the carrier storage interlayer 40 to form an N-type emission region 50 and a P+ region 60, and metal deposition is carried out on the N-type emission region 50 and the P+ region 60 to form emitter conductive metal of the device; forming a deep groove region in the photoetching target region; depositing polysilicon in the deep groove to form a groove gate 71, and performing metal deposition on the groove gate 71 to form a gate conductive metal of the device; metal deposition is performed on the backside of the substrate 10 to form the collector conductive metal of the device. According to the invention, the carrier storage interlayer 40 is introduced into the surface of the P-base20 region to form a hole barrier for preventing holes from flowing into the P-base20 region, and the carrier storage interlayer 40 can enhance the electron injection of the super junction region 30, so that the penetration modulation effect is enhanced, and therefore, the device has lower forward voltage characteristics by introducing the N-type carrier storage interlayer 40 at one side of the emitter; the superjunction regions 30 of the alternating P and N pillars make the breakdown voltage of the device unaffected by the charge balance, and enhance the conductance modulation effect of the base region without the breakdown voltage being affected, thereby significantly reducing the on-voltage.
Fig. 8 shows electron concentration of a device in an on mode according to an embodiment of the invention. Fig. 9 shows electron concentration in the on-mode of the lower device of the prior art. As can be seen by comparing fig. 8 and 9, the electron concentration in the device having the N-type carrier storage interlayer increases significantly. Fig. 10 is a graph comparing the conduction voltage value of a super-junction IGBT according to an embodiment of the invention with that of a conventional super-junction IGBT, and it can be seen that the conduction voltage drops by 1.09V at the peak of the conduction current compared with the conventional super-junction IGBT manufactured by the method according to an embodiment of the invention. Fig. 11 is a graph comparing breakdown voltages of a superjunction IGBT according to an embodiment of the present invention and an existing superjunction IGBT, and it can be seen that the breakdown voltage of the superjunction IGBT manufactured by the method of the present invention is not significantly reduced while the turn-on voltage drop is reduced compared to the existing superjunction IGBT.
The invention also provides a semiconductor device manufactured by adopting any one of the methods. The semiconductor device of the present invention has carrier storage interlayer 40 and may be a novel recessed type insulated gate bipolar transistor. The semiconductor device comprises an N-substrate 10, a super junction region 30 with alternating P columns and N columns arranged on the substrate 10, a P-type base region P-base20, a carrier storage interlayer 40, an N-type emission region 50 and a P+ region 60 which are sequentially arranged on the super junction region 30, a gate oxide layer 70 penetrating the N-type emission region 50, the carrier storage interlayer 40 and the N-type emission region 50 and a trench gate 71, wherein the gate oxide layer 70 is connected with the N columns, an electric field blocking layer 80 is arranged on the bottom surface of the N-substrate 10, and a collector region 81 is connected with the electric field blocking layer 80. Metal deposition forms the metal contacts of the gate, emitter and collector of the device on the surface of trench gate 71, the surface of the junction of N-type emitter region 50 and P + region 60, and the surface of collector region 81. According to the invention, the carrier storage interlayer 40 is introduced to prevent holes from being immediately transmitted to the emitter, so that the electron density of the P-base20 region is improved, the plasma density of the N-drift region is enhanced, and stronger conductivity modulation of the base region is realized; by introducing the superjunction regions 30 with alternating P and N pillars, the charge balance between the P and N pillars is achieved, thereby enhancing the conductance modulation effect of the base region while the device is unaffected by the breakdown voltage, and thereby reducing the on-voltage drop of the device.
The invention also provides an insulated gate bipolar transistor which is manufactured by adopting any one of the methods, and comprises an N-substrate 10, a super junction region 30 with alternating P columns and N columns arranged on the substrate 10, a P-type base region P-base20, a carrier storage interlayer 40, an N-type emitter region 50 and a P+ region 60 which are sequentially arranged on the super junction region 30, a gate oxide layer 70 and a trench gate 71 penetrating through the N-type emitter region 50, the carrier storage interlayer 40 and the N-type emitter region 50, wherein the gate oxide layer 70 is connected with the N columns, an electric field blocking layer 80 is arranged on the bottom surface of the N-substrate 10, and a collector region 81 is connected with the electric field blocking layer 80. Metal deposition forms the metal contacts of the gate, emitter and collector of the device on the surface of trench gate 71, the surface of the junction of N-type emitter region 50 and P + region 60, and the surface of collector region 81. According to the invention, the carrier storage interlayer 40 is introduced to prevent holes from being immediately transmitted to the emitter, so that the electron density of the P-base20 region is improved, the plasma density of the N-drift region is enhanced, and stronger conductivity modulation of the base region is realized; by introducing the superjunction regions 30 with alternating P and N pillars, the charge balance between the P and N pillars is achieved, thereby enhancing the conductance modulation effect of the base region while the device is unaffected by the breakdown voltage, and thereby reducing the on-voltage drop of the device.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (13)
1. A method of manufacturing a device having a carrier storage interlayer, comprising:
s100, cleaning a monocrystalline silicon wafer as a device substrate;
s200, growing an epitaxial layer on the top of the device substrate;
s300, selectively implanting ions on the epitaxial layer to form a super junction region with alternating P columns and N columns; s400, growing epitaxy on the surface of the super junction region to form a P-base region;
s500, implanting ions into the surface of the P-base or epitaxially growing to form an N-type carrier storage interlayer;
s600, performing ion implantation on the surface of the carrier storage interlayer to form an N-type emission region and a P+ region, and performing metal deposition on the N-type emission region and the P+ region to form emitter conductive metal of the device;
s700, photoetching to form a deep groove region; depositing polysilicon in the deep groove to form a groove gate, and performing metal deposition on the groove gate to form a gate conductive metal of the device;
and S800, performing metal deposition on the back surface of the substrate to form collector conductive metal of the device.
2. The method according to claim 1, characterized in that: the doping concentration of the epitaxial layer is 400-500 omega cm.
3. The method of claim 1, wherein selectively implanting ions on the epitaxial layer to form P-pillar and N-pillar alternating superjunction regions comprises:
the implantation junction depth of the selected P-type ions or N-type ions is 8-12 um.
4. The method of claim 3, wherein selectively implanting ions on the epitaxial layer to form P-pillar and N-pillar alternating superjunction regions further comprises:
the thickness of the P column or the N column is 80-120 um.
5. The method of claim 3, wherein selective ion implantation on the epitaxial layer to form alternating P-pillar and N-pillar superjunction regions further comprises the steps of:
s301: p type or N type ion implantation is selected in the epitaxial layer;
s302: rapid thermal annealing to activate the doping impurities;
s303: steps S301, S302 are repeated five or more times to form the superjunction region with alternating P pillars and N pillars.
6. The method according to claim 1, characterized in that: the thickness of the N-type carrier storage interlayer is 10-20 um.
7. The method according to claim 1, characterized in that: the P+ region is connected with the P-base and the carrier storage interlayer.
8. The method according to claim 1, characterized in that: the target area is an area positioned at the left side of the P-base and the carrier storage interlayer, the bottom of the deep groove area penetrates through the N-type emission area, the carrier storage interlayer and the P-base, and the deep groove area is connected with the N column.
9. The method of claim 8, wherein depositing polysilicon in the deep recess and depositing metal to form the gate of the device comprises:
and photoetching the side wall of the deep groove, growing a gate oxide layer at the bottom of the deep groove, and depositing polysilicon on the surface of the gate oxide layer to form a trench gate.
10. The method of claim 9, wherein growing a gate oxide layer at the bottom of the deep recess comprises:
growing a silicon dioxide layer on the surface of the deep groove by using a dry oxidation method;
the wet oxidation process is continued to grow the gate oxide layer.
11. The method of claim 1, further comprising the step of, prior to metal deposition on the back side of the substrate to form a collector conductive metal of the device:
step S801, implanting ions on the back surface of the substrate to form an electric field blocking layer, wherein the electric field blocking layer is adjacent to the bottoms of the P column and the N column;
step S802, injecting P-type ions into the electric field blocking layer to form a collector region;
and step 803, performing metal deposition on the surface of the collector region to form collector conductive metal of the device.
12. A semiconductor device manufactured by the method according to any one of claims 1 to 11.
13. An insulated gate bipolar transistor, characterized in that the insulated gate bipolar transistor is manufactured by the method of any one of claims 1 to 11 or is the semiconductor of claim 12.
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