CN117037819A

CN117037819A - USB audio coding/decoding SoC chip and power consumption management mode switching method thereof

Info

Publication number: CN117037819A
Application number: CN202310816765.1A
Authority: CN
Inventors: 廖红伟
Original assignee: Shenzhen Zhihua Technology Co ltd
Current assignee: Shenzhen Zhihua Technology Co ltd
Priority date: 2023-07-05
Filing date: 2023-07-05
Publication date: 2023-11-10

Abstract

The invention provides a USB audio coding/decoding SoC chip and a power consumption management mode switching method thereof, wherein the chip comprises: the clock module comprises a phase-locked loop corresponding to the audio equipment and the external equipment in the peripheral module; the peripheral module is used for monitoring the working state information of the external equipment; and the processor module is used for resetting the target phase-locked loop in the clock module after switching the power consumption management mode of the USB audio encoding/decoding SoC chip to a mode matched with the working state information according to the working state information. According to the USB audio encoding/decoding SoC chip and the power consumption management mode switching method thereof, the peripheral clock which does not participate in peripheral activities can be dynamically closed according to different working states, so that the power consumption can be effectively reduced on the premise of ensuring the voice quality.

Description

USB audio coding/decoding SoC chip and power consumption management mode switching method thereof

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a USB audio encoding and decoding SoC chip and a power consumption management mode switching method thereof.

Background

With the development of voice recognition and dialogue technology, intelligent multifunctional voice technology gradually enters into our line of sight, and the traditional single voice function cannot meet the demands of people. The multifunctional intelligent voice technology in different modes is a trend of development, so that high requirements are put on the output of the audio coding and decoding chip for guaranteeing the voice quality while the power consumption is low. Under the condition of low power consumption, only the power supply voltage is subjected to step-down treatment, so that the operating frequency of the chip is reduced, and the voice quality is reduced.

Disclosure of Invention

The invention provides a USB audio encoding and decoding SoC chip and a power consumption management mode switching method thereof, which are used for solving the defect that the voice quality is reduced due to the step-down processing of power supply voltage under the condition of low power consumption in the prior art.

The invention provides a USB audio coding/decoding SoC chip, comprising: the system comprises a processor module, a clock module, a peripheral module and a power module, wherein the clock module is connected with an interface of the processor module;

the clock module comprises a phase-locked loop corresponding to the audio equipment and the external equipment in the peripheral module;

the peripheral module is used for monitoring the working state information of the external equipment;

the processor module is used for resetting the target phase-locked loop in the clock module after switching the power consumption management mode of the USB audio coding/decoding SoC chip to a mode matched with the working state information according to the working state information;

the target phase-locked loop is a phase-locked loop corresponding to the audio device and/or the external device; the power consumption management mode comprises a normal mode, a normal sleep mode and a deep sleep mode; the phase-locked loops of the audio equipment and all the external equipment in the normal mode are in a high-level state; the phase-locked loops of the audio equipment in the common sleep mode are in a high level state, and the phase-locked loops of all the external equipment are in a low level state; the phase-locked loops of the audio device and all external devices in the deep sleep mode are in a low level state.

According to the USB audio coding/decoding SoC chip provided by the invention, the peripheral module comprises a USB controller, and the processor module and the peripheral module are in communication connection through a USB bus;

the USB bus is used for controlling the USB PHY chip to change the interface link state when detecting that the peripheral is in a suspension state or an awake state;

the USB controller is used for generating interrupt enabling after determining that the USB PHY chip changes the interface link state.

The invention provides a USB audio codec SoC chip, which also comprises a direct memory access (Direct Memory Access, DMA) controller;

the DMA controller provides up to 16 configurable channels for data transfer between memory to memory, memory to peripheral, peripheral to peripheral, and peripheral to memory.

The invention provides a USB audio coding/decoding SoC chip, which also comprises an interface module used for providing a data transmission and receiving channel between the processor module and the peripheral module;

the interface module includes: a first advanced high performance bus (Advanced High Performance Bus, AHB), a second AHB, and 1 peripheral bus (Advanced Peripheral Bus, APB);

The interface module also comprises an IIS audio interface;

the IIS audio interface supports digital-to-analog converter (Digital Analog Converter, DAC) data output, DMA first-in-first-out (First Input First Output, FIFO) memory output, DMA FIFO memory input, and DAC data input;

the processor module performs data operation on the first AHB, and the DMA controller performs data operation on the second AHB.

According to the USB audio coding/decoding SoC chip provided by the invention, the peripheral module comprises a successive approximation type analog-to-digital converter and a universal asynchronous transceiver;

the successive approximation type analog-to-digital converter converts analog data obtained by sampling an external sensor and a voltage signal into digital data through an APB, updates a state register and an interrupt signal, and exchanges data with a processor module;

the successive approximation type analog-to-digital converter is further used for driving the processor module to set the recovery bit of the power register to be 1 after receiving a starting signal of the remote peripheral and resetting to be 0 after lasting for a period of time;

the processor module transmits data with the universal asynchronous receiver-transmitter through an APB Bridge logic connector, and the DMA converts data with the universal asynchronous receiver-transmitter through an AHB;

Wherein the power register is in the power module.

According to the USB audio coding/decoding SoC chip provided by the invention, the peripheral module comprises a universal asynchronous receiver-transmitter;

the processor module transfers data with the universal asynchronous receiver/transmitter through an APB Bridge logical connector, and the DMA transfers data with the universal asynchronous receiver/transmitter through an AHB.

The invention also provides a power consumption management mode switching method of the USB audio coding/decoding SoC chip, which comprises the following steps:

the peripheral module monitors the working state information of the external equipment;

the processor module switches the power consumption management mode of the USB audio coding/decoding SoC chip to a mode matched with the working state information according to the working state information, and resets a target phase-locked loop in the clock module;

the target phase-locked loop is a phase-locked loop corresponding to the audio device and/or the external device; the power consumption management mode comprises a normal mode, a normal sleep mode and a deep sleep mode; the normal mode is that the phase-locked loops of the audio equipment and all external equipment are in a high-level state; the common sleep mode is that phase-locked loops of the audio equipment are in a high level state, and phase-locked loops of all external equipment are in a low level state; the phase locked loops of the deep sleep mode audio device and all external devices are in a low state.

According to the power consumption management mode switching method provided by the invention, after the power consumption management mode of the USB audio coding/decoding SoC chip is switched to a mode matched with the working state information according to the working state information, the processor module resets a target phase-locked loop in the clock module, and the method comprises the following steps:

the processor module receives working state information carrying a suspension interrupt instruction sent by the peripheral module;

the processor module responds to the suspension interrupt instruction, sets SLEEPDEEP bit of a system control register to 0, and switches the power consumption management mode from a normal mode to a common sleep mode;

the processor module sends a clock gating signal set to a low level state to the clock module, so that the clock module responds to the clock gating signal in the low level state, and the phase-locked loops of all external devices are set to the low level state while maintaining the current clock source, and the frequency of the phase-locked loops of the audio device is unchanged;

the suspension interrupt instruction is an instruction which is generated by controlling the USB controller when the USB bus does not generate data transmission with any external device within a preset time period; the current clock source is a clock source corresponding to the processor module before the power consumption management mode is switched to the common sleep mode; the clock source comprises a first USB PHY clock source, a second USB PHY clock source, an external input clock source, a USB clock source and an RC oscillator clock source; the power of the first USB PHY clock source is less than the power of the second USB PHY clock source.

the processor module sets SLEEPDEEP bits of a system control register to 1 and switches the power consumption management mode from a normal sleep mode to a deep sleep mode under the condition that the duration of the normal sleep mode in which the processor module is positioned is determined to be longer than or equal to a preset threshold value;

the processor module sends a clock gating signal set to a low level state to the clock module, so that the clock module responds to the clock gating signal in the low level state, after the phase-locked loops of all external devices are set to the low level state, the phase-locked loops of the audio device are controlled to be powered off through a register, and a clock source is switched to an RC oscillator clock source;

the RC oscillator clock source is the clock source with the minimum power.

The processor module receives working state information which is sent by the peripheral module and carries a wake-up interrupt instruction;

the processor module responds to the wake-up interrupt instruction and switches the power consumption management mode from a normal sleep mode or a deep sleep mode to a normal mode;

the processor module sends a clock gating signal set to a high level state to the clock module, so that the clock module responds to the clock gating signal in the high level state, sets phase-locked loops of the audio equipment and all external equipment to the high level state, and switches a clock source to a first USB PHY clock source;

the wake-up interrupt instruction is an instruction that controls the USB controller to generate when the USB bus re-generates data transmission with any external device.

According to the power consumption management mode switching method provided by the invention, the processor module switches the power consumption management mode through waiting time (Wait for Event, WFE), instruction waiting interrupt (Wait for Interrupt, WFI) instruction, wake-up interrupt controller (Wake-up Interrupt Controller, WIC) or system control register instruction.

According to the USB audio encoding/decoding SoC chip and the power consumption management mode switching method thereof, the peripheral module is used for monitoring the activity state of the peripheral, and the processor module is used for switching the power consumption management mode into a mode matched with the monitored working state information. Particularly for the operation scene of the low-power consumption mode, the peripheral clock which does not participate in the peripheral activity can be dynamically closed under the response of the corresponding mode, so that the power consumption can be effectively reduced on the premise of ensuring the voice quality.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a USB audio codec SoC chip provided by the present invention;

fig. 2 is a schematic diagram of a component structure of a SoC chip of a USB audio codec according to the present invention;

FIG. 3 is a second schematic diagram of the component structure of the SoC chip of the USB audio codec according to the present invention;

FIG. 4 is a second schematic diagram of a USB audio codec SoC chip according to the present invention;

FIG. 5 is a schematic flow chart of a power consumption management mode switching method according to the present invention;

FIG. 6 is a schematic diagram of mode switching of a power consumption management mode according to the present invention;

FIG. 7 is a schematic flow chart of mode switching according to the present invention;

FIG. 8 is a second schematic flow chart of the mode switching according to the present invention;

FIG. 9 is a third schematic flow chart of the mode switching according to the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," and the like in the description of the present application, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more.

It is to be understood that the terminology used in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

The terms "comprises" and "comprising" indicate the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1 is a schematic diagram of a structure of a USB audio codec SoC chip according to the present invention. As shown in fig. 1, a USB audio codec SoC chip provided in an embodiment of the present invention includes: a processor module 110, a clock module 120 connected to an interface of the processor module 110, a peripheral module 130, and a power module 140 for providing power.

The clock module 120 includes a phase-locked loop corresponding to the audio device and the external device in the peripheral module 130.

The peripheral module 130 is configured to monitor working state information of an external device.

The processor module 110 is configured to reset the target phase-locked loop in the clock module 120 after switching the power consumption management mode of the USB audio codec SoC chip to a mode matching the working state information according to the working state information.

The target phase-locked loop is a phase-locked loop corresponding to the audio device and/or the external device. The power consumption management mode includes a normal mode, a normal sleep mode, and a deep sleep mode. The phase-locked loops of the audio device and all external devices in the normal mode are in a high level state. The phase-locked loops of the audio equipment in the common sleep mode are in a high level state, and the phase-locked loops of all the external equipment are in a low level state. The phase-locked loops of the audio device and all external devices in the deep sleep mode are in a low level state.

Specifically, the USB audio codec SoC chip is provided with a processor module 110, a clock module 120, and a peripheral module 130 on the basis of a crystal oscillator circuit, and also correspondingly and correspondingly provided with a data storage module and an interface module, and provides electric energy for each module on the circuit by using a power module 140. Wherein:

the Processor module 110 may generate control signals to control the respective components and perform the respective operations, and the manifestations of the Processor module 110 include, but are not limited to, a central processing unit (Central Processing Unit, CPU), digital signal processing (Digital Signal Processing/Processor, DSP), a microcontroller unit (Micro Control Unit, MCU) and a microprocessor unit (Micro Processor Unit, MPU).

The clock module 120 includes an audio device and a peripheral phase locked loop (Phase Locked Loop, PLL) that can generate an audio clock from a USB oscillator at 12MHZ or a 12MHZ crystal of an external device and provide a clock source for the processor module 110 according to the phase locked loop sampling rate of the audio device.

The data storage module integrates a 16KB boot Read-Only Memory (ROM) and a 16KB Static Random-Access Memory (SRAM), the boot ROM is used for receiving program codes in a Universal Asynchronous Receiver Transmitter (UART) bus, and the program codes are stored in an internal media transfer protocol (Media Transfer Protocol, MTP). Whereas embedded high-speed SRAM static memory is designed for program code and register RAM to store data as a data memory.

The IIC bus interface controller in the interface module is a peripheral bus device that allows the host processor to act as a master or slave in the IIC bus. Data is transferred to and received from the IIC bus through the buffer interface. Standard and fast modes are supported by programming clock divide registers, 7-bit, 10-bit and general call addressing modes are supported. It has a glitch suppression capability by means of a debounce circuit. The slave address is programmable and supports master transmit, master receive, slave transmit and slave receive modes, as well as multi-master modes.

The power module 140 includes three parts: 3.3V power supply of chip analog circuit, 3.3V power supply of I/O and 1.8V power supply pad of internal low dropout linear regulator (Low Dropout Regulator, LDO). The 3.3V power supply of the analog circuit has 3 pairs of power/ground pins, a pair for USB PHY (Port Physical Layer ), a pair for PLL that requires a stable power supply to improve jitter and accuracy performance, and a pair for other analog module chips such as LDO, acceleration processor (Accelerated Processing Unit, APU), SARADC, LVR (medium order traversal algorithm) controller analog circuits. The 3.3V power supply for I/O includes 1 pair. The chip is provided with an LDO (low dropout regulator) which converts a 3.3V power supply into a 1.8V power supply, the output of the LDO supplies power for digital logic and USB PHY digital logic, and the output of the LDO is connected with a capacitor decoupling through a 1.8V pin.

The peripheral module 130 monitors and forwards the CPU resources and speed occupied by the peripheral when the peripheral generates output transmission to the processor module 110 for corresponding logic processing, including:

(1) When the peripheral module 130 monitors that the peripheral is in a high-saturation working state and occupies more CPU resources, the processor module 110 sets the power consumption management mode of the USB audio codec SoC chip to a corresponding normal mode, and correspondingly adjusts the clock module, so that the phase-locked loops of the audio equipment and all external equipment are in a high-level state, and the power-on working is performed by the default power consumption of the chip.

(2) When the peripheral module 130 monitors that the peripheral is in a low-saturation working state and occupies less CPU resources, the processor module 110 sets the power consumption management mode of the USB audio coding/decoding SoC chip to a corresponding ordinary sleep mode, and correspondingly adjusts the clock module, so that the audio equipment keeps working on a high level state for standby, phase-locked loops of other external equipment are powered on for sleep in a low level state, and the chip can operate in a standby mode with lower power consumption.

(3) When the peripheral module 130 monitors that the peripheral is in the low saturation standby state continuously and hardly occupies CPU resources, the processor module 110 sets the power consumption management mode of the USB audio codec SoC chip to a corresponding normal sleep mode, and correspondingly adjusts the clock module, so that the phase-locked loops of the audio device and all external devices are powered on and sleep in the low level state, and the chip is in standby operation with the lowest power consumption.

According to the embodiment of the invention, the peripheral module is used for monitoring the activity state of the peripheral, and the processor module is used for switching the power consumption management mode to a mode matched with the monitored working state information. Particularly for the operation scene of the low-power consumption mode, the peripheral clock which does not participate in the peripheral activity can be dynamically closed under the response of the corresponding mode, so that the power consumption can be effectively reduced on the premise of ensuring the voice quality.

On the basis of any of the above embodiments, the peripheral module 130 includes a USB controller, and the processor module and the peripheral module are communicatively connected through a USB bus.

The USB bus is used for controlling the USB PHY chip to change the interface link state when detecting that the peripheral is in a suspension state or an awake state.

Specifically, the peripheral module 130 mainly includes a USB controller. The embodiment of the invention does not limit the constitution of the USB controller in detail.

Fig. 2 is a schematic diagram of a component structure of a USB audio codec SoC chip according to the present invention. As shown in fig. 2, the USB controller may consist of UTM synchronization (UTM refers to a type of network security device, essentially a multifunctional security gateway), packet encoding/decoding, RAM controller endpoint control, and a CPU interface, and supports USB OTG, which may be used as a host to access an external USB device, or may be used as a USB device to access an external USB host. The USB controller conforms to USB Specification 2.0, conforms to real-time supplementation of USB Specification 2.0 1.0, supports UTMI+2 class transceivers, conforms to enhanced host controller interface Specification 1.0 (Enhanced Host Controller Interface, EHCI), supports session request protocol (OTG Session Request Protocol, OTG SRP) and host negotiation protocol (OTG Host Negotiation Protocol, HNP). Supporting point-to-point communication with a High Speed, full Speed, low Speed device, the end point of the module may be configured as an HS/FS device. Both the host and the device support isochronous, interrupt, control, and bulk transfers. It supports DMA access to internal FIFOs and supports suspend mode, remote wakeup and resume.

The processor module 110 and the peripheral module 130 are mainly in communication connection through a USB bus, and the actions of the chip entering the power consumption management mode are determined by the external USB end state, which may be specifically implemented as follows:

(1) When the suspend state is detected on the USB bus, i.e. the DP/DM line, the USB PHY chip changes the state of the Linestate and informs the USB controller, and if the suspend interrupt is enabled to be turned on, a suspend interrupt is generated, and the processor module 110 may execute the WFE or WFI instruction by using the resume instruction set and enter the normal sleep mode according to the SLEEPDEEP bit of the system control register SCB- > SCR being 0.

(2) After the normal sleep mode is maintained for a certain time, the WFE or WFI instruction is executed through the thumb instruction set, and the deep sleep mode is entered according to the SLEEPDEEP bit of the system control register SCB- > SCR as 1. However, in the normal sleep mode, the peripheral is not operated, and cannot exit the sleep state regularly, or the external interrupt can cause the CPU to exit the sleep depth sleep mode.

(3) In the normal sleep mode or the deep sleep mode, the USB controller is also in a suspended state, after the wake-up state is detected on the USB bus, the Linestate state is changed, the USB controller receives the wake-up signal to generate wake-up interrupt, the CPU exits from any sleep mode, the clock source and the power source are reconfigured, and the CPU returns to the normal state.

According to the USB controller, the USB PHY chip generates interruption to the activity monitored by the peripheral equipment aiming at the USB bus, and the processor module is controlled to switch the power consumption management mode to a mode matched with the power consumption management mode according to the response condition to the interruption. Different clock and power strategies in different power saving modes can be achieved through clock gating for a single IP.

The USB audio codec SoC chip further comprising a direct memory access (Direct Memory Access, DMA) controller based on any of the above embodiments.

Specifically, the USB audio codec SoC chip is further configured with a direct memory access (Direct Memory Access, DMA) controller, so that the direct memory access can improve system performance and reduce the occurrence of processor interrupts. The embodiment of the present invention does not particularly limit the configuration of the direct memory access DMA controller.

Fig. 3 is a schematic diagram illustrating a second component structure of the SoC chip for USB audio encoding and decoding according to the present invention. As shown in fig. 3, the DMA controller is composed of several modules, an AHB MASTER interface (AHB MASTER), an AHB SLAVE interface (AHB SLAVE), a FIFO buffer, and a DMA CORE (DMA CORE). The AHB master interface transfers data between the system and the DMA FIFO, the system may configure the DMA controller via the AHB slave interface, the FIFO buffer provides a buffer between the source and destination, the DMA core may be configured as a 16 channel DMA engine, both source and destination on the AHB bus, each channel may be assigned a group priority, servicing the same group priority in a round robin fashion.

The USB audio encoding and decoding SoC chip of the embodiment of the invention supports various common modes in each module, and also comprises a 16KB boot ROM, a 16KB SRAM static memory and 16 DMA of configurable channels so as to enlarge the operability and expandability of the chip.

An interface module for providing a data transmission and reception channel between the processor module 110 and the peripheral module 130 is further included on the basis of any of the above embodiments.

The interface module includes: a first advanced high performance bus (Advanced High Performance Bus, AHB), a second AHB, and 1 peripheral bus (Advanced Peripheral Bus, APB).

The processor module 110 performs a data operation on the first AHB, and the DMA controller performs a data operation on the second AHB.

Specifically, since the SoC chip for encoding and decoding USB audio needs to perform read-write operations on the SRAM and the USB PHY at the same time, the interface module is integrated with 2 advanced high-performance buses (Advanced High Performance Bus, AHB buses) besides mainly carrying the USB bus, that is, includes the first AHB and the second AHB. In addition, 1 peripheral bus (Advanced Peripheral Bus, APB) is integrated (compatible with the advanced microcontroller bus architecture (Advanced Microcontroller Bus Architecture, AMBA) protocol).

The processor module 110 operates as an AHB master in one of the AHB buses and the DMA controller operates as an AHB master on the other AHB bus.

The interface module includes an IIS audio interface.

The IIS audio interface supports digital-to-analog converter (Digital Analog Converter, DAC) data output, DMA first-in-first-out (First Input First Output, FIFO) memory output, DMA FIFO memory input, and DAC data input.

Specifically, the interface module is also provided with an IIS audio interface that supports digital-to-analog converter (Digital Analog Converter, DAC) data output, DMA first-in-first-out (First Input First Output, FIFO) memory output, DMA FIFO memory input, and DAC data input.

The data formats supported by the IIS audio interface in the above form include, but are not limited to, IIS, left_aligned, DSP (Digital Signal Processor ), right_aligned, and support 16-bit, 20-bit, 24-bit, and 32-bit word lengths.

According to the USB audio encoding and decoding SoC chip provided by the embodiment of the invention, the processor module and the DMA controller are enabled to perform data operation on two AHBs which are independent respectively, so that the SRAM and the USB PHY can be simultaneously subjected to read-write operation, and the instantaneity of data transmission is improved. Meanwhile, the IIS audio interface supports various input and output formats, and the flexibility and the expandability of the chip are greatly improved.

Based on any of the above embodiments, the peripheral module 130 includes a successive approximation analog-to-digital converter and a universal asynchronous receiver-transmitter.

The successive approximation type analog-to-digital converter converts analog data obtained by sampling an external sensor and a voltage signal into digital data through an APB, updates a state register and an interrupt signal, and exchanges data with a processor module.

The successive approximation type analog-to-digital converter is further used for driving the processor module to set the recovery bit of the power register to be 1 after receiving a starting signal of the remote peripheral and resetting to be 0 after a period of time.

Wherein the power register is in the power module.

Specifically, the successive approximation analog-to-digital converter (Successive Approximation Analog-to-Digital Converter, SARADC) provided in the peripheral module 130 is accessible via the APB bus by the processor module for sampling other analog voltage signals (e.g., the signals including not only the high-precision audio signals coming from the MIC port, but also the control signals modulated by the earphone cord) coming from the general purpose input-output (General Purpose Input Output, GPIO) interface, converting the data types, updating the status register and the interrupt signals.

In addition, if the SARADC receives a signal from a remote peripheral (e.g., a headset button), the chip should write to the power register, setting the resume bit to "1". The software should set this bit to about 10ms and then reset to 0. By that time, the hub should have taken over the controller signal on the USB. The USB controller will then exit the sleep mode. The registers may be reconfigured to turn on the system PLL, audio PLL, codec circuitry, and change the system clock to 48MHz.

The SARADC unit is a 3.3V power supply simulation module and is cooperated with the decimation filter to realize analog-to-digital transmission. The ADC control includes module timing generation, register control, interrupt generation, and APB bus wrapping.

Specifically, the peripheral module 130 also incorporates a universal asynchronous receiver/Transmitter (UART), accessible via an AHB bus or APB bus.

UARTs are a serial communication element that implements the most common infrared communication protocol. It also supports the IRDA1.3 SIR protocol (Infrared Data Association, infrared data communication; serial Infrared protocol) for household appliances Infrared transmitters and receivers (38 KHz).

The UART controller supports two modes of operation: UART mode, SIR mode. UART mode is enabled by default after power up or system reset. This mode uses a wired interface for serial communication with a remote device or modem. It can operate in full duplex mode and data transmission and reception can be performed simultaneously. It serves as a conventional serial asynchronous communication controller that converts parallel data received from a CPU or DMA controller into serial data. It also converts serial data received at the serial input into parallel data.

The APB, which is a part of AMBA bus protocol, is generally used for accessing or configuring registers of low-speed peripherals by the CPU, and has the characteristics of low cost, low power consumption and low bandwidth. APB Bridge can suspend multiple slaves to access the CPU.

Fig. 4 is a second schematic structural diagram of a USB audio codec SoC chip according to the present invention. As shown in fig. 4, an embodiment of the present invention provides an entity structure of a SoC chip capable of implementing USB audio encoding and decoding:

the USB audio codec SoC chip integrates a 32-bit RISC-CPU (Reduced Instruction Set Computer) and 16KB Static Memory (SRAM), universal serial bus (Universal Serial Bus, USB) 402, universal asynchronous receiver/transmitter (Universal Asynchronous Receiver/Transmitte, UART) 403, integrated circuit bus (Inter-Integrated Circuit, IIC) 404, audio codec, universal input/output (General Purpose Input Output, GPIO) 405, basic Timer (TIM) 406, watchdog Timer (Watch Dog Timer, WDT) 407, pulse width modulation (Pulse Width Modulation, PWM) 408, serial peripheral interface (Serial Peripheral Interface, SPI), internet information service (Internet Information Services, IIS), digital audio output (Sony/Philips Digital Interface, SPDIF), pulse density modulation (Pulse Density Modulation, PDM), successive approximation analog-to-digital converter (Successive-Approximation Analog to Digital Converter, SARADC) 409, phase-locked loop (Phase Locked Loop, PLL), low dropout regulator (Low Dropout Regulator, LDO), and the like.

The SPIB module 410 is one of the implementations of an API (Application Programming Interface, application program interface, module for providing third party interfaces) interface. IOP GPIO 405 is a hard core in IOP and is a hardware circuit already implemented in the chip. Boot rom is a Boot applet embedded in the chip CPU 401, which determines the execution of the code and verifies its correctness and validity. APB, which is part of AMBA bus protocol, is typically used for the CPU 401 to access or configure registers of low-speed peripherals, and has the characteristics of low cost, low power consumption, and low bandwidth, and APB Bridge can suspend multiple slave devices to access the CPU. The chip works by starting from the internal Read-Only Memory (ROM), and after powering up, the program is executed from the internal media transfer protocol (Media Transfer Protocol, MTP). The device can run to 48MHz, has very tight design, energy-saving mode, and simultaneously maintains flexibility and excellent performance under the condition of low power consumption. It includes clock gating for a single IP, which can further operate in different power saving modes: normal, idle, standby, shutdown, different modes have different clock and power policies.

According to the embodiment of the invention, the SARADC with smaller size specification is integrated in the USB audio coding/decoding SoC chip, so that the SARADC can still have high resolution and high precision when running with low power consumption even in a normal chip mode. And the full duplex asynchronous communication of the chip is realized by using the universal asynchronous receiver-transmitter, so that the cost is ensured, and the method has the advantage of high reliability for long-distance transmission.

Fig. 5 is a schematic flow chart of a power consumption management mode switching method provided by the invention. As shown in fig. 5, based on the content of any of the above embodiments, the power consumption management mode switching method of the USB audio codec SoC chip includes: in step 501, the peripheral module monitors working state information of the external device.

Step 502, after the processor module switches the power consumption management mode of the USB audio codec SoC chip to a mode matching with the working state information according to the working state information, resetting the target phase-locked loop in the clock module.

The target phase-locked loop is a phase-locked loop corresponding to the audio device and/or the external device. The power consumption management mode includes a normal mode, a normal sleep mode, and a deep sleep mode. The normal mode is that the phase-locked loops of the audio device and all external devices are in a high level state. The common sleep mode is that the phase-locked loops of the audio equipment are in a high level state, and the phase-locked loops of all the external equipment are in a low level state. The phase locked loops of the deep sleep mode audio device and all external devices are in a low state.

Specifically, in step 501, the peripheral module monitors the CPU resources and speed occupied by the peripheral module when output transmission occurs in the peripheral module, and forwards corresponding operating state information to the processor module.

In step 502, the processor module performs corresponding logic processing according to the working state information, including:

(1) When the working state information sent by the peripheral module indicates that the peripheral is in a high-saturation working state and occupies more CPU resources, the processor module sets the power consumption management mode of the USB audio coding/decoding SoC chip to a corresponding normal mode, and correspondingly adjusts the clock module, so that the phase-locked loops of the audio equipment and all external equipment are in a high-level state, and the power-on working is executed by the default power consumption of the chip.

(2) When the working state information sent by the peripheral module indicates that the peripheral is in a low-saturation working state and occupies less CPU resources, the processor module sets the power consumption management mode of the USB audio coding/decoding SoC chip to a corresponding common sleep mode, and correspondingly adjusts the clock module, so that the audio equipment keeps power-on working for standby in a high-level state, phase-locked loops of other external equipment are powered-off for sleep in a low-level state, and the chip can operate in standby with lower power consumption.

(3) When the working state information sent by the peripheral module indicates that the peripheral is in a low-saturation standby state continuously and hardly occupies CPU resources, the processor module sets the power consumption management mode of the USB audio coding/decoding SoC chip to a corresponding common sleep mode, and correspondingly adjusts the clock module, so that the phase-locked loops of the audio equipment and all external equipment are powered on to sleep in a low-level state and operate in a standby mode with the lowest power consumption of the chip.

Based on any one of the above embodiments, after the processor module switches the power consumption management mode of the USB audio codec SoC chip to a mode matching the working state information according to the working state information, resetting a target phase-locked loop in the clock module, including: and the processor module receives the working state information carrying the suspension interrupt instruction and sent by the peripheral module.

The processor module sets SLEEPDEEP bits of a system control register to 0 in response to the suspend interrupt instruction, switching the power management mode from a normal mode to a normal sleep mode.

The processor module sends the clock gating signal set to the low level state to the clock module for the clock module to respond to the clock gating signal in the low level state, and the phase-locked loops of all external devices are set to the low level state while maintaining the current clock source, and the frequency of the phase-locked loops of the audio device is unchanged.

The suspension interrupt instruction is an instruction which is generated by controlling the USB controller when the USB bus does not generate data transmission with any external device within a preset time period. The current clock source is the clock source corresponding to the processor module before the power consumption management mode is switched to the common sleep mode. The clock sources include a first USB PHY clock source, a second USB PHY clock source, an external input clock source, a USB clock source, and an RC oscillator clock source. The power of the first USB PHY clock source is less than the power of the second USB PHY clock source.

It should be noted that, the clock structure of the USB audio codec SoC chip is related to power consumption, and may be set to be five in total, namely, 48MHz of the USB PHY (i.e., the first USB PHY clock source), 480MHz of the USB PHY (i.e., the second USB PHY clock source), 48MHz of the external input (e.g., the crystal) (i.e., the external input clock source), 30MHz of the USB (i.e., the USB clock source), and 10kHz of the internal RC oscillator (RC oscillator clock source).

The second USB PHY clock source switch is controllable and has the highest frequency. The system clock can be switched and divided between these five clock sources and the gating with respect to DCLK and SCLK is automatic, with the clock gating signal being the same hclk_en, i.e. the same switch, which is associated with the power management mode.

It should be noted that, before step 502, when the USB bus detects that no data transmission occurs with any external device within a preset period of time, that is, the peripheral device is in a suspend state (suspend), the USB PHY chip changes the state of the suspend and informs the USB controller, at this time, if the suspend interrupt is enabled to be turned on, a suspend interrupt instruction is generated, and the instruction is packaged to the working state information and sent to the processor module.

Specifically, in step 502, the processor module may execute a WFE or WFI instruction through the thumb instruction set using a suspend interrupt instruction and switch from the normal mode to the normal sleep mode according to the SLEEPDEEP bit of the internal system control register SCB- > SCR being 0.

Subsequently, the clock gating signal (hclk_en signal) is pulled low, at which time the clocks of almost all peripherals and functional modules are stopped. The clock source selection is unchanged, and only the phase lock loop of the audio device is kept working and the frequency is unchanged. Once the processor module wakes up, the clock gating signal goes high and the chip returns to normal mode.

When the peripheral activity is not active, the USB controller is decided to send a suspension interrupt instruction to the processor module, so that after the processor module enters the normal sleep mode, the clock gating signal is pulled down, clocks of other peripheral circuits are closed, only clock sources of audio equipment are reserved, the system clock is maintained at the lowest system running power, and the high performance is achieved with the minimum power consumption while the flexibility is ensured.

Based on any one of the above embodiments, after the processor module switches the power consumption management mode of the USB audio codec SoC chip to a mode matching the working state information according to the working state information, resetting a target phase-locked loop in the clock module, including: and under the condition that the duration of the current normal sleep mode is greater than or equal to a preset threshold value, the processor module sets SLEEPDEEP bits of a system control register to 1, and switches the power consumption management mode from the normal sleep mode to the deep sleep mode.

The processor module sends the clock gating signal set to the low level state to the clock module, so that the clock module responds to the clock gating signal in the low level state, after the phase-locked loops of all external devices are set to the low level state, the phase-locked loops of the audio device are controlled to be powered off through the register, and the clock source is switched to the RC oscillator clock source.

The RC oscillator clock source is the clock source with the minimum power.

Specifically, in step 502, after determining that the current normal SLEEP mode is maintained for a certain period of time, the processor module executes a WFE or WFI instruction through a thumb instruction set, and switches from the normal SLEEP mode to a deep SLEEP mode (denoted as SLEEP) according to SLEEPDEEP bits of the internal system control register SCB- > SCR being 1.

The clock gating signal is then pulled low, at which point the clocks of almost all peripherals and functional modules are stopped. The Audio pll is powered off by the register configuration pdf signal and the system clock source is switched to 10kHz of the internal RC oscillator.

If the processor module is awakened, the clock source is configured as the PLL and the pdf switch of the PLL is opened, and the processor module returns to the normal working state after the PLL clock is locked again.

After the processor module detects the common sleep mode for a certain time, the embodiment of the invention makes a decision to enable the processor module to enter the deep sleep mode, pulls down the clock gating signal, closes clocks of all circuits, only the oscillator clock source with the lowest power, enables the system clock to be maintained on the lowest system running power, ensures the flexibility and achieves high performance with the lowest power consumption.

Based on any one of the above embodiments, after the processor module switches the power consumption management mode of the USB audio codec SoC chip to a mode matching the working state information according to the working state information, resetting a target phase-locked loop in the clock module, including: and the processor module receives the working state information carrying the wake-up interrupt instruction and sent by the peripheral module.

The processor module responds to the wake-up interrupt instruction to switch the power consumption management mode from a normal sleep mode or a deep sleep mode to a normal mode.

The processor module sends a clock gating signal set to a high level state to the clock module for the clock module to set phase locked loops of the audio device and all external devices to the high level state and switch the clock source to the first USB PHY clock source in response to the clock gating signal in the high level state.

It should be noted that, before step 502, when the USB bus detects that any external device resumes data transmission, that is, the peripheral device is in a wake-up state (resume), the USB PHY chip changes the state of linestate and informs the USB controller, at this time, if resume interrupt enable is turned on, a wake-up interrupt instruction is generated, and the instruction is packaged into working state information and sent to the processor module.

Specifically, in step 502, the processor module may exit any sleep mode using a wake-up interrupt instruction, reconfigure the clock source, power supply, and return to the normal mode.

The clock gating signal is then pulled high and all modules are operating, clocked normally, system 48Mhz, uac section 24.5792Mhz or 22.576Mhz.

When the peripheral activity is determined to be recovered to be active, the USB controller is decided to send a wake-up interrupt instruction to the processor module, so that after the processor module enters a normal mode, clock gating signals are pulled high, clocks of other peripheral circuits are recovered, the system clock is maintained at the lowest system running power, and the high performance is achieved with the minimum power consumption while the flexibility is ensured.

On the basis of any of the above embodiments, the processor module performs switching of the power consumption management mode by waiting for an interrupt (Wait for Interrupt, WFI) instruction, a Wake-up interrupt controller (Wake-up Interrupt Controller, WIC) or a system control register instruction by a Wait for Event (WFE) instruction.

Specifically, the USB audio codec SoC chip switches between a normal mode, a normal sleep mode, and a deep sleep mode.

FIG. 6 is a schematic diagram of mode switching of a power consumption management mode according to the present invention. As shown in fig. 6, the embodiment of the present invention provides a mode switching manner:

(1) NORMAL to IDLE

Due to application scenario requirements, the actions of entering sleep or sleep mode, or waking up are determined by the usb end state. When the suspend state is detected on the usb bus, namely the DP/DM line, the usb_phy changes the state of the linestate and informs the usb controller, and at the moment, if the suspend interrupt is enabled to be opened, the suspend interrupt is generated, and the CM0P can execute the WFE or WFI instruction through the thumb instruction set by using the interrupt and enter the normal sleep state according to the SLEEPDEEP bit of the internal system control register SCB- > SCR as 0.

(2) IDLE to SLEEP

After the IDLE state is kept for a certain time, the WFE or WFI instruction is executed through the thumb instruction set, and the deep sleep state is entered according to SLEEPDEEP bits of an internal system control register SCB- > SCR as 1. However, since none of the peripherals is active in the IDLE state, how the time is calculated, and the interrupt causes CM0P to exit the sleep state.

(3) Exit SLEEP state (IDLE/SLEEP)

In the IDLE or SLEEP state, the USB controller is also in a suspend state, after the resume is detected on the USB bus, the linestate is changed, the controller receives the resume signal, generates resume interrupt, the CM0P exits the SLEEP mode, the clock source and the power source are reconfigured, and the state returns to the NORMAL state.

Wherein entering any sleep mode may be performed by:

(1) Fig. 7 is a schematic flow chart of mode switching according to the present invention. As shown in FIG. 7, sleep may be entered by a WFE instruction (wait for event wakeup), i.e., the event latch state is checked while the corresponding WFE instruction is executed. If the event latch state is 1, the event latch is cleared and the next instruction is continued. If the event latch state is 0, the sleep mode is entered, and the corresponding normal sleep mode or deep sleep mode is entered through the binary value of SLEEPDEEP. When an event or interrupt occurs, the sleep mode is exited.

(2) FIG. 8 is a second schematic flow chart of the mode switching according to the present invention. As shown in fig. 8, the system may enter sleep through a WFI instruction (waiting for interrupt wakeup), that is, directly checking SLEEPDEEP the binary value of the corresponding WFI instruction to enter a corresponding normal sleep mode or deep sleep mode respectively when executing the corresponding WFI instruction. When an interrupt or debug suspension occurs, the sleep mode is exited.

(3) FIG. 9 is a third schematic flow chart of the mode switching according to the present invention. As shown in fig. 9, a deep sleep mode of a WIC (wakeup interrupt controller) may be utilized.

(4) Mode switching may also be performed using a system control register (SCB > SCR), the register bit number table being shown below.

TABLE 1 one of the peripheral configuration information schematic forms

Therefore, in a 32-bit instruction, different values may be set in bits 4, 2 and 1 to perform the corresponding switching actions.

The embodiment of the invention executes mode switching among a normal mode, a normal sleep mode and a deep sleep mode through a WFE instruction, a WFI instruction, a WIC instruction or a system control register instruction. The peripheral clock which does not participate in peripheral activities can be dynamically closed under the response of the corresponding mode, so that the power consumption can be effectively reduced on the premise of ensuring the voice quality.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A USB audio codec SoC chip comprising: the system comprises a processor module, a clock module, a peripheral module and a power module, wherein the clock module is connected with an interface of the processor module;

2. The USB audio codec SoC chip of claim 1, wherein the peripheral module includes a USB controller, the processor module and the peripheral module being communicatively coupled via a USB bus;

3. The USB audio codec SoC chip of claim 1 or 2, further comprising a direct memory access (Direct Memory Access, DMA) controller;

4. The USB audio codec SoC chip of claim 3, further comprising an interface module for providing a data transmission and reception channel between the processor module and the peripheral module;

The interface module also comprises an IIS audio interface;

5. The USB audio codec SoC chip of claim 3, wherein the peripheral module comprises a successive approximation analog-to-digital converter and a universal asynchronous receiver/transmitter;

Wherein the power register is in the power module.

6. The power consumption management mode switching method based on the USB audio codec SoC chip as claimed in any one of claims 1 to 5, comprising:

7. The power consumption management mode switching method according to claim 6, wherein the processor module resets the target phase-locked loop in the clock module after switching the power consumption management mode of the USB audio codec SoC chip to a mode matching the operating state information according to the operating state information, comprising:

the suspension interrupt instruction is an instruction which is generated by controlling the USB controller when the USB bus does not generate data transmission with any external device within a preset time period; the current clock source is a clock source corresponding to the processor module before the power consumption management mode is switched to the common sleep mode; the clock source comprises a first USB PHY clock source, a second USB PHY clock source, an external input clock source, a USB clock source and an RC oscillator clock source; the power of the first USB PHY clock source is smaller than the power of the second USB BPHY clock source.

8. The power consumption management mode switching method according to claim 6, wherein the processor module resets the target phase-locked loop in the clock module after switching the power consumption management mode of the USB audio codec SoC chip to a mode matching the operating state information according to the operating state information, comprising:

the RC oscillator clock source is the clock source with the minimum power.

9. The power consumption management mode switching method according to claim 6, wherein the processor module resets the target phase-locked loop in the clock module after switching the power consumption management mode of the USB audio codec SoC chip to a mode matching the operating state information according to the operating state information, comprising:

10. The power consumption management mode switching method according to any one of claims 6-9, wherein the processor module switches power consumption management modes by a Wait time (Wait for Event, WFE), an instruction Wait for interrupt (Wait for Interrupt, WFI) instruction, a Wake-up interrupt controller (Wake-upInterrupt Controller, WIC), or a system control register instruction.