CN117014919A - Wireless communication debugging circuit and system - Google Patents
Wireless communication debugging circuit and system Download PDFInfo
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- CN117014919A CN117014919A CN202311280678.5A CN202311280678A CN117014919A CN 117014919 A CN117014919 A CN 117014919A CN 202311280678 A CN202311280678 A CN 202311280678A CN 117014919 A CN117014919 A CN 117014919A
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/06—Testing, supervising or monitoring using simulated traffic
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/02—Arrangements for optimising operational condition
Abstract
The application relates to a wireless communication debugging circuit and a system, wherein the circuit comprises: a master circuit and a slave circuit. The host circuit includes: the host switching circuit, the host controller and the host wireless communication module; the slave circuit includes: the system comprises a slave wireless communication module, a slave controller, a DUT debugging interface, various communication circuits and various functional debugging circuits. The host controller is connected with a host in wireless communication debugging through a host switching circuit so as to acquire communication data sent by the host, and the communication data is sent to the slave wireless communication module through the host wireless communication module; the communication data at least comprises: address data, communication mode data, and control data; the slave machine controller is connected with the slave machine in wireless communication debugging, is also connected with the slave machine wireless communication module, and is also connected with the DUT debugging interface through the communication circuit and the function debugging circuit. The slave circuit adopts various communication circuits, and can realize various communication modes through one slave circuit, thereby meeting the multi-mode communication requirement.
Description
Technical Field
The present application relates to the field of communications debug circuitry, and in particular, to a wireless communications debug circuitry and system.
Background
Most electronic control products need to perform function debugging verification on a finished circuit board through a communication debugging circuit so as to judge whether the finished circuit board can meet design requirements and expose possible problems in the finished circuit board. Most products adopt reserved debugging communication ports when designing external communication interfaces, are debugged in a wired connection mode, and in the practical use process, the remote debugging cannot be carried out due to the limitation of practical debugging wires, and crosstalk is easily introduced when the wires are lengthened, so that communication faults are caused.
In order to solve the problem, a wireless communication debugging circuit is adopted to replace a wired communication debugging circuit in the prior art, a host machine and a slave machine in the prior wireless communication debugging circuit perform one-to-one wireless communication debugging, and the slave machine can only perform single-mode communication. However, some products may require more communication modes to perform redundancy design and adapt to different working conditions, and the slave circuit with a single communication mode cannot meet the multi-mode communication requirement.
Disclosure of Invention
In order to at least overcome the problem that a slave circuit with a single communication mode cannot meet the multi-mode communication requirement in the related art to a certain extent, the application provides a wireless communication debugging circuit and a system.
The scheme of the application is as follows:
according to a first aspect of an embodiment of the present application, there is provided a wireless communication debugging circuit, including:
a master circuit and a slave circuit;
the host circuit includes: the host switching circuit, the host controller and the host wireless communication module;
the slave circuit includes: the device comprises a slave wireless communication module, a slave controller, a DUT (device under test, a tested device) debugging interface, a plurality of communication circuits and a plurality of function debugging circuits;
the host controller is connected with a host in wireless communication debugging through the host switching circuit so as to acquire communication data sent by the host, and the communication data is sent to the slave wireless communication module through the host wireless communication module; the communication data at least comprises: address data, communication mode data, and control data;
the slave machine controller is connected with a slave machine in wireless communication debugging, is also connected with the slave machine wireless communication module, and is also connected with the DUT debugging interface through the communication circuit and the function debugging circuit;
the slave controller acquires the communication data through the slave wireless communication module, determines an execution communication circuit in various communication circuits according to communication mode data in the communication data, determines an execution function debugging circuit in various function debugging circuits according to control data in the communication data, and sends the control data to the DUT debugging interface through the execution communication circuit;
the executive function debugging circuit acquires the control data from the DUT debugging interface, carries out debugging according to the control data and sends a debugging result to the slave controller;
and the slave controller sends the debugging result to the host wireless communication module through the slave wireless communication module according to the address data.
Preferably, the host circuit further comprises:
a host debug circuitry;
the host controller is connected with the host through the host debugging circuit so as to receive programming debugging performed by the host; the programming debugging includes at least: and (3) debugging a data transmission mode and debugging a data analysis mode.
Preferably, the slave circuit further includes:
a slave debugging circuit;
the slave controller is connected with the slave through the slave debugging circuit so as to receive programming debugging performed by the slave; the programming debugging includes at least: and (3) debugging a data transmission mode and debugging a data analysis mode.
Preferably, the host switching circuit includes:
a USB (Universal Serial Bus ) interface and a USB to serial IC (integrated circuit ) circuit;
the USB interface is connected with the host;
the USB-to-serial port IC circuit is connected with the USB interface and the host controller.
Preferably, the host circuit further comprises:
a host power supply circuit;
the host power supply circuit is connected with the host switching circuit, the host controller and the host wireless communication module;
the host power supply circuit is connected with power supply from the host through the host switching circuit and provides the power supply to the host controller and the host wireless communication module.
Preferably, the slave circuit further includes:
a slave power supply circuit;
the slave power supply circuit is connected with the slave wireless communication module, the slave controller, the DUT debugging interface and the communication circuit;
the slave power supply circuit is provided with a voltage reducing module;
the slave power supply circuit is connected to a power supply from the DUT debugging interface and provides the power supply to the slave wireless communication module, the slave controller and the communication circuit.
Preferably, the communication circuit includes at least:
422-to-serial communication circuit, IIC (Inter-Integrated Circuit, integrated circuit bus) communication circuit, CAN (Controller Area Network, controller area network bus) communication circuit, SPI (Serial Peripheral Interface ) communication circuit, and serial communication circuit;
wherein, 422 drive IC chips are configured in the 422-to-serial port communication circuit; and the CAN communication circuit is provided with a CAN drive IC chip.
Preferably, the function debugging circuit comprises at least:
GPIO (General Purpose I/O Ports, general purpose input/output port) port debugging circuit, two paths of analog voltage signal output comparison circuits, an analog signal voltage value measuring circuit, a digital-to-analog conversion output testing circuit, a temperature sensor function verification circuit and a PWM input debugging circuit.
Preferably, the communication data includes at least: a master frame header bit, a master address bit, a slave address bit, a bit number bit, a sub-frame header bit, a data bit, a sub-CRC (cyclic redundancy check ) check bit, a sub-frame tail bit, a control function bit, a control content bit, a master CRC check bit, and a master frame tail bit;
wherein, the sub-frame head bit, the data bit, the sub-CRC check bit and the sub-frame tail bit form the communication mode data;
the control function bit and the control content bit form the control data;
the master address bits and the slave address bits form the address data.
According to a second aspect of an embodiment of the present application, there is provided a wireless communication debugging system including:
a set of host systems and a plurality of sets of slave systems;
wherein the host system comprises: a host, and a host circuit as claimed in any one of the preceding claims;
the slave system includes: a slave, and a slave as claimed in any preceding claim.
The technical scheme provided by the application can comprise the following beneficial effects: the wireless communication debugging circuit in the application comprises: a master circuit and a slave circuit. The host circuit includes: the host switching circuit, the host controller and the host wireless communication module; the slave circuit includes: the system comprises a slave wireless communication module, a slave controller, a DUT debugging interface, various communication circuits and various functional debugging circuits. The host controller is connected with a host in wireless communication debugging through a host switching circuit so as to acquire communication data sent by the host, and the communication data is sent to the slave wireless communication module through the host wireless communication module; the slave machine controller is connected with the slave machine in wireless communication debugging, is also connected with the slave machine wireless communication module, and is also connected with the DUT debugging interface through the communication circuit and the function debugging circuit. In implementation, the communication data at least comprises: address data, communication mode data, and control data; the slave controller acquires communication data through the slave wireless communication module, determines an execution communication circuit in various communication circuits according to communication mode data in the communication data, determines an execution function debugging circuit in various function debugging circuits according to control data in the communication data, and sends the control data to the DUT debugging interface through the execution communication circuit; the executive function debugging circuit acquires control data from the DUT debugging interface, carries out debugging according to the control data and sends a debugging result to the slave controller; and the slave controller transmits the debugging result to the host wireless communication module through the slave wireless communication module according to the address data. The slave circuit adopts various communication circuits, contains various communication mode hardware resources, and can realize various communication modes through one slave machine, so that the slave machine can meet the multi-mode communication requirement.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic diagram of a wireless communication debug circuit according to one embodiment of the present application;
FIG. 2 is a schematic diagram of a host circuit in a wireless communication debug circuit according to an embodiment of the present application;
fig. 3 is a schematic diagram of a slave circuit in a wireless communication debug circuit according to an embodiment of the present application.
Reference numerals: a host circuit-1; a host switching circuit-11; a USB interface-111; USB-to-serial IC circuit-112; a host controller-12; a host wireless communication module-13; host debug circuitry-14; a host power supply circuit-15; a slave circuit-2; a slave wireless communication module-21; a slave controller-22; DUT debug interface-23; a communication circuit-24; function debug circuitry-25; slave debug circuitry-26; a slave power supply circuit-27.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
Example 1
Fig. 1 is a schematic structural diagram of a wireless communication debug circuit according to an embodiment of the present application, and referring to fig. 1 to 3, a wireless communication debug circuit includes:
a master circuit 1 and a slave circuit 2;
the host circuit 1 includes: host switching circuit 11, host controller 12, host wireless communication module 13;
the slave circuit 2 includes: a slave wireless communication module 21, a slave controller 22, a DUT debug interface 23, a variety of communication circuits 24, and a variety of function debug circuits 25;
the host controller 12 is connected with a host in wireless communication debugging through the host switching circuit 11 to acquire communication data sent by the host, and sends the communication data to the slave wireless communication module 21 through the host wireless communication module 13; the communication data at least comprises: address data, communication mode data, and control data;
the slave controller 22 is connected with a slave in wireless communication debugging, is also connected with the slave wireless communication module 21, and is also connected with the DUT debugging interface 23 through the communication circuit 24 and the function debugging circuit 25;
the slave controller 22 acquires communication data through the slave wireless communication module 21, determines an execution communication circuit 24 among a plurality of communication circuits 24 according to communication mode data in the communication data, determines an execution function debugging circuit 25 among a plurality of function debugging circuits 25 according to control data in the communication data, and transmits the control data to the DUT debugging interface 23 through the execution communication circuit 24;
the executive function debugging circuit 25 acquires control data from the DUT debugging interface 23, performs debugging according to the control data, and transmits a debugging result to the slave controller 22;
the slave controller 22 transmits the debug result to the master wireless communication module 13 through the slave wireless communication module 21 according to the address data.
Note that, the host in this embodiment refers to a host in wireless communication debugging, that is, an upper computer used for transmitting communication data in wireless communication debugging, and the slave in this embodiment refers to a slave in wireless communication debugging, that is, a lower computer used for receiving communication data in wireless communication debugging and performing debugging according to the communication data.
Referring to fig. 2, the host switching circuit 11 includes:
a USB interface and a USB-to-serial IC circuit;
the USB interface is connected with the host;
the USB to serial IC circuit connects the USB interface to the host controller 12.
It should be noted that, since the host is generally a computer terminal, most of the computer terminals are configured with USB interfaces, the host circuit 1 in this embodiment is connected to the host through the USB interfaces and the USB-to-serial IC circuit, and provides a communication function by using the USB interfaces on the host.
The master controller 12 and the slave controller 22 may be programmable MCUs (Microcontroller Unit, micro control units), or may be programmable control chips such as CPLDs (complex programmable logic devices, complex Programmable Logic Device) or FPGAs (Field Programmable Gate Array, field programmable gate arrays).
The master wireless communication module 13 and the slave wireless communication module 21 may be, but not limited to, a LoRa wireless communication module.
The communication circuit 24 includes at least:
422-to-serial communication circuit 24, IIC communication circuit 24, CAN communication circuit 24, SPI communication circuit 24, and serial communication circuit 24;
wherein 422 drive IC chips are configured in the 422-to-serial communication circuit 24; the CAN communication circuit 24 is provided with a CAN driver IC chip.
Note that 422 communication, which has been RS-422 communication in the past, is now EIA-422, and is a series of data transmission protocols that are prescribed to use 4-wire, full duplex, differential transmission, and multipoint communication. The transmission line adopts balanced transmission and unidirectional/irreversible transmission line with or without an enabling end. Unlike RS-485, EIA-422 does not allow multiple senders to be present but only multiple acceptors. The hardware constitution of the EIA-422 (RS-422) is equivalent to two groups of EIA-485 (RS-485), namely, two half-duplex EIA-485 (RS-485) constitute one full-duplex EIA-422 (RS-422).
IIC, also known as I2C, is a simple, bi-directional, two-wire bus standard. The method is widely used for master-slave communication of the master and the slave in the occasions with small data volume and short transmission distance. The master starts the bus and generates a clock for transmitting data, in which case any device receiving data is considered a slave.
CAN is a serial communication protocol that is internationally standardized by iso. Initially CAN was designed to form an automotive electronic control network by exchanging information between automotive electronic control devices as a communication in the automotive environment. Due to their excellent performance, extremely high reliability and low cost, they are now widely used in numerous fields such as industrial field control, medical instruments, etc.
SPI is a synchronous peripheral interface that allows a single-chip microcomputer to communicate with various peripheral devices in a serial fashion to exchange information. The peripheral devices include Flash RAM, a network controller, an LCD display driver, an A/D converter, an MCU, etc.
A serial interface is a device that converts parallel data characters received from a computer into a continuous serial data stream for transmission, and converts the received serial data stream into parallel data characters for supply to the computer.
In the prior art, the slave circuit 2 with a single communication mode cannot meet the multi-mode communication requirement, and the slave circuit 2 in the embodiment adopts a plurality of communication circuits 24, contains a plurality of communication mode hardware resources, and can realize a plurality of communication modes through one machine, so that the slave machine can meet the multi-mode communication requirement.
The function debug circuitry 25 includes at least:
the device comprises a GPIO port debugging circuit, a two-path analog voltage signal output comparison circuit, an analog signal voltage value measuring circuit, a digital-to-analog conversion output testing circuit, a temperature sensor function verification circuit and a PWM input debugging circuit.
In the prior art, the slave circuit 2 does not have functions of GPIO port debugging, two-way analog voltage signal output comparison, analog signal voltage value measurement, digital-to-analog conversion output test, temperature sensor function verification, PWM input debugging and the like, and in the embodiment, a plurality of functional debugging circuits 25 are configured in the slave circuit 2, and the functions of GPIO port debugging, two-way analog voltage signal output comparison, analog signal voltage value measurement, digital-to-analog conversion output test, temperature sensor function verification, PWM input debugging and the like can be completed through the plurality of functional debugging circuits 25.
Note that, in the present embodiment, the communication circuit 24 and the function debugging circuit 25 are not limited to the communication circuit 24 and the function debugging circuit 25 in the above example, and other kinds of communication circuits 24 and function debugging circuits 25 may be added according to specific needs in specific practice.
In the specific implementation, the host transmits communication data to the host circuit 1 by dedicated software.
In a specific implementation, the communication data at least includes: a master frame header bit, a master address bit, a slave address bit, a bit number bit, a sub-frame header bit, a data bit, a sub-CRC check bit, a sub-frame tail bit, a control function bit, a control content bit, a master CRC check bit, and a master frame tail bit;
wherein, the sub-frame head bit, the data bit, the sub-CRC check bit and the sub-frame tail bit form communication mode data;
the control function bit and the control content bit are used for receiving control data;
the master address bits and the slave address bits constitute address data.
After receiving the communication data, the slave controller 22 needs to analyze the communication data, including address analysis, communication mode analysis, and control function analysis. The address resolution is used for judging whether the communication data is issued for the local machine according to the address bit of the slave machine, and storing the host machine address for use in data return. The communication mode analysis judges the sub-frame header, sub-frame tail, and sub-CRC check, analyzes the communication contents therein after confirming that there is no error, determines to execute the communication circuit 24 among the plurality of communication circuits 24, and transmits control data to the DUT debug interface 23 through the execution communication circuit 24. The control function analysis refers to analyzing control function bits and control content bits in the communication data to obtain control instructions and control content issued by the host, and controlling the function debugging circuit 25 according to the control instructions and the control content to achieve the effect of debugging the DUT function.
The executive function debugging circuit 25 acquires the control data from the DUT debugging interface 23, performs debugging according to the control data, and transmits the debugging result to the slave controller 22, and the slave controller 22 transmits the debugging result to the master wireless communication module 13 through the slave wireless communication module 21 according to the address data. In particular practice, the slave controller 22 distinguishes between communicating return data in the debug result and debug return data.
It should be noted that the debug result also includes address data, which is composed of a host address bit and a slave address bit.
After receiving the debugging result, the host circuit 1 sends the debugging result to the host, and the host displays the debugging result through special software, so that a tester can intuitively judge the debugging.
It can be appreciated that the wireless communication debug circuit in this embodiment includes: a master circuit 1 and a slave circuit 2. The host circuit 1 includes: host switching circuit 11, host controller 12, host wireless communication module 13; the slave circuit 2 includes: a slave wireless communication module 21, a slave controller 22, a DUT debug interface 23, various communication circuits 24, and various function debug circuits 25. The host controller 12 is connected with a host in wireless communication debugging through the host switching circuit 11 to acquire communication data sent by the host, and sends the communication data to the slave wireless communication module 21 through the host wireless communication module 13; the slave controller 22 is connected to a slave in wireless communication debugging, is also connected to the slave wireless communication module 21, and is also connected to the DUT debugging interface 23 through the communication circuit 24 and the function debugging circuit 25. In implementation, the communication data at least comprises: address data, communication mode data, and control data; the slave controller 22 acquires communication data through the slave wireless communication module 21, determines an execution communication circuit 24 among a plurality of communication circuits 24 according to communication mode data in the communication data, determines an execution function debugging circuit 25 among a plurality of function debugging circuits 25 according to control data in the communication data, and transmits the control data to the DUT debugging interface 23 through the execution communication circuit 24; the executive function debugging circuit 25 acquires control data from the DUT debugging interface 23, performs debugging according to the control data, and transmits a debugging result to the slave controller 22; the slave controller 22 transmits the debug result to the master wireless communication module 13 through the slave wireless communication module 21 according to the address data. The slave circuit 2 in this embodiment adopts a plurality of communication circuits 24, and includes a plurality of communication mode hardware resources, so that a plurality of communication modes can be realized by one slave machine, and the slave machine can meet the multi-mode communication requirements.
Example two
Referring to fig. 2, the host circuit 1 further includes:
host debug circuitry 14;
the host controller 12 is connected with a host through a host debugging circuit 14 to receive programming debugging performed by the host; programming debugging includes at least: and (3) debugging a data transmission mode and debugging a data analysis mode.
Referring to fig. 3, the slave circuit 2 further includes:
slave debug circuitry 26;
the slave controller 22 connects to the slave through the slave debug circuitry 26 to receive programming debug by the slave; programming debugging includes at least: and (3) debugging a data transmission mode and debugging a data analysis mode.
It should be noted that, since there may be various response delay situations in the host communication, the data transmission, the slave communication and the debug backhaul, in this embodiment, by utilizing the programmable advantages of the host controller 12 and the slave controller 22, the function debug circuit 25 is used to perform field programming and debugging, so as to implement the optimal data transmission/backhaul manner of the response according to the actual working requirements.
In particular practice, the master debug circuitry 14 and the slave debug circuitry 26 may be, but are not limited to, a debug download port for JLINK.
Referring to fig. 2, the host circuit 1 further includes:
a host power supply circuit 15;
the host power supply circuit 15 is connected with the host switching circuit 11, the host controller 12 and the host wireless communication module 13;
the host power circuit 15 is connected to power from the host through the host switching circuit 11, and supplies the power to the host controller 12 and the host wireless communication module 13.
It should be noted that, referring to fig. 2, the host power circuit 15 is connected to a Current of 5V and 0.5A from the host through a USB interface in the host switching circuit 11, and can obtain a supply Current of 3.3V and 680mA through a DC/DC (Direct Current) switching circuit (90% conversion efficiency), wherein a working Current of 100mA-50mA is required at a transmitting end of the host wireless communication module 13, a working Current of 8-2.4mA is required at a receiving end, a working Current of 350mA is required at the host controller 12 and the peripheral circuit, and a working Current of 50mA is required at the USB to serial IC circuit and the peripheral circuit.
Referring to fig. 3, the slave circuit 2 further includes:
a slave power supply circuit 27;
the slave power supply circuit 27 connects the slave wireless communication module 21, the slave controller 22, the DUT debug interface 23, and the communication circuit 24;
the slave power supply circuit 27 is provided with a step-down module;
the slave power supply circuit 27 is connected to the power supply from the DUT debug interface 23 and provides to the slave wireless communication module 21, the slave controller 22 and the communication circuit 24.
The slave power supply circuit 27 supplies power by using the power supply on the DUT debug interface 23, and if the DUT debug interface 23 is 3.3V power, the power supply is directly introduced, and if the DUT debug interface is higher than 3.5V, the power supply is performed after the voltage is reduced by using an LDO (low dropout regulator, low dropout linear regulator) voltage reducing module.
Example III
A wireless communication debugging system, comprising:
a set of host systems and a plurality of sets of slave systems;
wherein the host system includes: a host, and a host circuit 1 as in the above embodiments;
the slave system includes: a slave, and a slave 2 as in the above embodiment.
It should be noted that, the wireless communication debugging system in this embodiment adopts a master and slave design, the master is a single system, the slave can support multiple groups of systems, the slave 2 determines whether to respond by receiving address data in the communication data, if the address data corresponds to the slave, the slave responds, otherwise, the slave does not respond. And the host judges which slave machine sends the data according to the address data in the debugging result returned by the slave machine.
It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.
It should be noted that in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "plurality" means at least two.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (10)
1. A wireless communication debug circuit, comprising:
a master circuit and a slave circuit;
the host circuit includes: the host switching circuit, the host controller and the host wireless communication module;
the slave circuit includes: the system comprises a slave wireless communication module, a slave controller, a DUT debugging interface, various communication circuits and various function debugging circuits;
the host controller is connected with a host in wireless communication debugging through the host switching circuit so as to acquire communication data sent by the host, and the communication data is sent to the slave wireless communication module through the host wireless communication module; the communication data at least comprises: address data, communication mode data, and control data;
the slave machine controller is connected with a slave machine in wireless communication debugging, is also connected with the slave machine wireless communication module, and is also connected with the DUT debugging interface through the communication circuit and the function debugging circuit;
the slave controller acquires the communication data through the slave wireless communication module, determines an execution communication circuit in various communication circuits according to communication mode data in the communication data, determines an execution function debugging circuit in various function debugging circuits according to control data in the communication data, and sends the control data to the DUT debugging interface through the execution communication circuit;
the executive function debugging circuit acquires the control data from the DUT debugging interface, carries out debugging according to the control data and sends a debugging result to the slave controller;
and the slave controller sends the debugging result to the host wireless communication module through the slave wireless communication module according to the address data.
2. The wireless communication debug circuitry of claim 1, wherein the host circuitry further comprises:
a host debug circuitry;
the host controller is connected with the host through the host debugging circuit so as to receive programming debugging performed by the host; the programming debugging includes at least: and (3) debugging a data transmission mode and debugging a data analysis mode.
3. The wireless communication debug circuitry of claim 1, wherein the slave circuitry further comprises:
a slave debugging circuit;
the slave controller is connected with the slave through the slave debugging circuit so as to receive programming debugging performed by the slave; the programming debugging includes at least: and (3) debugging a data transmission mode and debugging a data analysis mode.
4. The wireless communication debug circuitry of claim 1, wherein the host transfer circuitry comprises:
a USB interface and a USB-to-serial IC circuit;
the USB interface is connected with the host;
the USB-to-serial port IC circuit is connected with the USB interface and the host controller.
5. The wireless communication debug circuitry of claim 1, wherein the host circuitry further comprises:
a host power supply circuit;
the host power supply circuit is connected with the host switching circuit, the host controller and the host wireless communication module;
the host power supply circuit is connected with power supply from the host through the host switching circuit and provides the power supply to the host controller and the host wireless communication module.
6. The wireless communication debug circuitry of claim 1, wherein the slave circuitry further comprises:
a slave power supply circuit;
the slave power supply circuit is connected with the slave wireless communication module, the slave controller, the DUT debugging interface and the communication circuit;
the slave power supply circuit is provided with a voltage reducing module;
the slave power supply circuit is connected to a power supply from the DUT debugging interface and provides the power supply to the slave wireless communication module, the slave controller and the communication circuit.
7. The wireless communication debug circuitry of claim 1, wherein the communication circuitry comprises at least:
422-to-serial communication circuit, IIC communication circuit, CAN communication circuit, SPI communication circuit and serial communication circuit;
wherein, 422 drive IC chips are configured in the 422-to-serial port communication circuit; and the CAN communication circuit is provided with a CAN drive IC chip.
8. The wireless communication debug circuitry of claim 1, wherein the functional debug circuitry comprises at least:
the device comprises a GPIO port debugging circuit, a two-path analog voltage signal output comparison circuit, an analog signal voltage value measuring circuit, a digital-to-analog conversion output testing circuit, a temperature sensor function verification circuit and a PWM input debugging circuit.
9. The wireless communication debug circuitry of claim 1, wherein the communication data comprises at least: a master frame header bit, a master address bit, a slave address bit, a bit number bit, a sub-frame header bit, a data bit, a sub-CRC check bit, a sub-frame tail bit, a control function bit, a control content bit, a master CRC check bit, and a master frame tail bit;
wherein, the sub-frame head bit, the data bit, the sub-CRC check bit and the sub-frame tail bit form the communication mode data;
the control function bit and the control content bit form the control data;
the master address bits and the slave address bits form the address data.
10. A wireless communication debugging system, comprising:
a set of host systems and a plurality of sets of slave systems;
wherein the host system comprises: a host, and a host circuit as claimed in any one of claims 1 to 9;
the slave system includes: a slave, and a slave as claimed in any one of claims 1 to 9.
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