CN117012837A - Semi-floating gate transistor and preparation method thereof - Google Patents
Semi-floating gate transistor and preparation method thereof Download PDFInfo
- Publication number
- CN117012837A CN117012837A CN202210441161.9A CN202210441161A CN117012837A CN 117012837 A CN117012837 A CN 117012837A CN 202210441161 A CN202210441161 A CN 202210441161A CN 117012837 A CN117012837 A CN 117012837A
- Authority
- CN
- China
- Prior art keywords
- semi
- region
- control gate
- floating
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007667 floating Methods 0.000 title claims abstract description 205
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 230000015654 memory Effects 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims description 80
- 239000000945 filler Substances 0.000 claims description 63
- 229910052751 metal Inorganic materials 0.000 claims description 57
- 239000002184 metal Substances 0.000 claims description 57
- 230000008569 process Effects 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 34
- 150000004767 nitrides Chemical class 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 20
- 229910052721 tungsten Inorganic materials 0.000 claims description 16
- 239000010937 tungsten Substances 0.000 claims description 16
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 12
- 229910052715 tantalum Inorganic materials 0.000 claims description 11
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 11
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 10
- 229910052707 ruthenium Inorganic materials 0.000 claims description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 229910017052 cobalt Inorganic materials 0.000 claims description 9
- 239000010941 cobalt Substances 0.000 claims description 9
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 9
- 229910052750 molybdenum Inorganic materials 0.000 claims description 9
- 239000011733 molybdenum Substances 0.000 claims description 9
- -1 tungsten nitride Chemical class 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 120
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 22
- 229920005591 polysilicon Polymers 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 230000005684 electric field Effects 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 10
- 239000011241 protective layer Substances 0.000 description 10
- 230000014759 maintenance of location Effects 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000004891 communication Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 230000003936 working memory Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
Abstract
The embodiment of the application provides a semi-floating gate transistor and a preparation method thereof, which can be applied to the field of semiconductors, and the semi-floating gate transistor comprises: the semiconductor device comprises a source electrode region, a channel region, a drain electrode region, a control gate, two semi-floating gates and a side wall protection layer. The channel region is stacked on the upper surface of the source region, the drain region is stacked on the upper surface of the channel region, grooves are formed in the source region, the channel region and the drain region, a control gate and two semi-floating gates are formed in the grooves, the two semi-floating gates are respectively located in the left lower region and the right lower region of the control gate, and side wall protection layers are located on two sides of the control gate and on the upper surface of the drain region. The semi-floating gate transistor provided by the embodiment of the application comprises a left memory cell and a right memory cell, so that the size of a single memory cell can be effectively reduced, and a larger capacity can be obtained under the same chip area.
Description
Technical Field
The application relates to the field of semiconductor devices, in particular to a semi-floating gate transistor and a preparation method thereof.
Background
A semi-floating gate transistor (SFGT) is a transistor interposed between a metal-oxide-semiconductor field-effect transistor (MOSFET) and a floating gate transistor, which connects the semi-floating gate and the drain through a tunneling field-effect transistor (TFET) and uses the TFET to control the charge and discharge of the semi-floating gate, thereby forming a dynamic memory.
The semi-floating gate transistor comprises a source region, a drain region, a channel region, a split gate, a control gate, a semi-floating gate and the like, wherein the semi-floating gate is embedded into a substrate where the channel region is located, and the source region and the drain region are respectively formed on the left side and the right side of the semi-floating gate. The control gate covers the semi-floating gate, and the split gate is positioned on one side of the control gate and the semi-floating gate. In operation, the source region and the drain region communicate through the channel region under the semi-floating gate.
The semi-floating gate transistor is of a horizontal structure, and a single device occupies a large chip area.
Disclosure of Invention
The embodiment of the application provides a semi-floating gate transistor and a preparation method thereof, which can reduce the size of a single device and have larger capacity under the same chip area.
In a first aspect, a semi-floating gate transistor is provided, the semi-floating gate transistor comprising: the drain electrode region is stacked on the upper surface of the channel region, grooves are formed in the source electrode region, the channel region and the drain electrode region, and the grooves penetrate through the drain electrode region and the channel region; the control gate and the two semi-floating gates are formed in the groove, the two semi-floating gates are respectively positioned in the left lower area and the right lower area of the control gate, and the upper surface of the control gate is higher than the upper surface of the drain electrode area; and the side wall protection layers are positioned on two sides of the control gate and are positioned on the upper surface of the drain electrode region.
In particular, the groove may be a U-shaped groove.
The trench penetrates through the drain region and the channel region, and the control gate and the two semi-floating gates are formed in the trench, which can be understood as a substrate where the two semi-floating gates and the control gate are buried in the source region.
The source region, the channel region and the drain region are sequentially stacked in the vertical direction, so that the whole device is of a vertical structure. The channel region is of a vertical structure, and it is understood that the source region and the drain region are communicated in a vertical direction when the semi-floating gate transistor is operated.
It will be appreciated that the source and drain regions are in communication in the vertical direction such that the left and right sides of the control gate form the source, channel and drain regions of two cells, respectively, whereby the vertical structure of the semi-floating gate transistor forms the left and right two memory cells.
Based on the scheme, the semi-floating gate transistor provided by the application comprises the left memory cell and the right memory cell, so that the size of a single memory cell can be effectively reduced, and a larger capacity can be obtained under the same chip area.
On the other hand, the semi-floating gate transistor does not comprise split gates, and is simpler in structure.
In addition, the control gate of the semi-floating gate transistor is shared by two memory cells, so that the size of a single memory cell can be reduced.
It should be appreciated that the semi-floating gate transistor is of a vertical structure, so that the electric field of the gate has less interference to the electric field of the drain region, and even if no split gate is included, the interference of the electric field of the drain region is not greatly affected, and therefore, the retention time of data is not affected without the split gate.
With reference to the first aspect, in certain implementations of the first aspect, the control gate is a metal gate.
When the semi-floating gate transistor is used as a memory cell, the control gate is a bus of a word line, and in the semi-floating gate transistor provided by the embodiment of the application, the control gate is a metal gate, and the resistivity is much smaller than that of the traditional polysilicon control gate, so that the capacity of a memory array can be greatly improved, and high-density and large-capacity integration is realized.
With reference to the first aspect, in certain implementations of the first aspect, the control gate includes a filler and a barrier layer, the filler material being a metal or a metal nitride.
In the semi-floating gate transistor provided by the embodiment of the application, the material of the control gate replaces polysilicon with metal or metal nitride, and the threshold voltage of the semi-floating gate transistor is larger and the electric leakage is smaller because the work function of the metal or metal nitride material is larger than that of polysilicon, so that the data retention time of the semi-floating gate transistor is longer.
With reference to the first aspect, in certain implementations of the first aspect, the metal is tungsten, tantalum, molybdenum, cobalt, ruthenium, or aluminum, and the metal nitride is titanium nitride, tungsten nitride, or tantalum nitride.
Tungsten (W), aluminum (Al), tantalum (Ta), molybdenum (Mo), cobalt (Co), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) and the like have better process miniaturization performance and larger work function, and the device threshold voltage can be improved, the leakage current is reduced, and the data retention capacity of the semi-floating gate transistor is improved while the resistance is reduced.
With reference to the first aspect, in certain implementations of the first aspect, an upper surface of the two semi-floating gates is flush with an upper surface of the drain region.
The upper surfaces of the two semi-floating gates are flush with the upper surface of the drain region, which is understood to mean that the upper surfaces of the two semi-floating gates are in the same horizontal plane with the upper surface of the drain region, or that the plane of the upper surfaces of the two semi-floating gates is substantially coincident with the plane of the upper surface of the drain region.
In the semi-floating gate transistor provided by the embodiment of the application, the upper surface of the semi-floating gate is flush with the upper surface of the drain electrode region, so that the processing technology of the semi-floating gate transistor is simpler.
With reference to the first aspect, in certain implementations of the first aspect, the upper surfaces of the two semi-floating gates are located between the upper surface of the drain region and the upper surface of the channel region.
The upper surfaces of the two semi-floating gates are located between the upper surface of the drain region and the upper surface of the channel region, which is understood to mean that the plane of the upper surfaces of the two semi-floating gates is between the plane of the upper surface of the drain region and the plane of the upper surface of the channel region.
In the semi-floating gate transistor provided by the embodiment of the application, the upper surface of the semi-floating gate is arranged between the upper surface of the drain electrode region and the upper surface of the channel region, so that the distance between the control gate and the drain electrode region is relatively short, and the semi-floating gate transistor has higher programming efficiency.
In a second aspect, a method for manufacturing a semi-floating gate transistor is provided, the method comprising: sequentially forming a source region, a channel region and a drain region on a substrate, wherein the channel region is stacked on the upper surface of the source region, the drain region is stacked on the upper surface of the channel region, grooves are formed in the source region, the channel region and the drain region, and the grooves penetrate through the drain region and the channel region; forming two semi-floating gates in the trench; forming a control gate between the two semi-floating gates, wherein the upper surface of the control gate is higher than the upper surface of the drain electrode region, and the two semi-floating gates are respectively positioned in the left lower region and the right lower region of the control gate; and forming side wall protection layers on two sides of the control gate, wherein the side wall protection layers are positioned on the upper surface of the drain electrode region.
In particular, the groove may be a U-shaped groove.
The trench penetrates through the drain region and the channel region, and the control gate and the two semi-floating gates are formed in the trench, which can be understood as a substrate where the two semi-floating gates and the control gate are buried in the source region.
The source region, the channel region and the drain region are sequentially stacked in a vertical method, so that the whole device is of a vertical structure. The channel region is of a vertical structure, and it is understood that the source region and the drain region are communicated in a vertical direction when the semi-floating gate transistor is operated.
It will be appreciated that the source and drain regions are in communication in the vertical direction such that the left and right sides of the control gate form the source, channel and drain regions. In addition, since the semi-floating gate transistor includes two semi-floating gates, left and right memory cells are formed in the semi-floating gate transistor.
Based on the scheme, the semi-floating gate transistor provided by the application comprises the left memory cell and the right memory cell, so that the size of a single memory cell can be effectively reduced, and a larger capacity can be obtained under the same chip area.
On the other hand, the semi-floating gate transistor does not comprise split gates, and is simpler in structure.
It should be appreciated that the semi-floating gate transistor is of a vertical structure, so that the electric field of the gate has less interference to the electric field of the drain region, and even if no split gate is included, the interference of the electric field of the drain region is not greatly affected, and therefore, the retention time of data is not affected without the split gate.
With reference to the second aspect, in certain implementations of the second aspect, the control gate is a metal gate.
With reference to the second aspect, in certain implementations of the second aspect, the control gate includes a filler and a blocking layer, the filler is made of metal or metal nitride, and the control gate is formed between the two semi-floating gates, including: depositing a barrier layer and a filler between the two semi-floating gates by utilizing an atomic layer deposition process and a vapor deposition technology; and etching the barrier layer and the filler by using an etching process to form the control gate.
With reference to the second aspect, in certain implementations of the second aspect, the metal is tungsten, tantalum, molybdenum, cobalt, ruthenium, or aluminum, and the metal nitride is titanium nitride, tungsten nitride, or tantalum nitride.
With reference to the second aspect, in some implementations of the second aspect, the upper surfaces of the two semi-floating gates are flush with the upper surface of the drain region.
With reference to the second aspect, in some implementations of the second aspect, the upper surfaces of the two semi-floating gates are located between the upper surface of the drain region and the upper surface of the channel region.
In a third aspect, a memory is provided, the memory comprising a memory array, a word line and a bit line, the memory array comprising the semi-floating gate transistor of the first aspect or any implementation of the first aspect, the memory array being connected to the word line and the bit line, respectively.
With reference to the third aspect, in some implementations of the third aspect, the memory further includes peripheral circuitry, the memory peripheral circuitry being coupled to the memory array.
In a fourth aspect, there is provided an electronic device comprising a printed circuit board (printed circuit board, PCB) and a memory in any one of the implementations of the foregoing third or third aspects.
Drawings
Fig. 1 is a schematic diagram of a semi-floating gate transistor 100.
Fig. 2 is a schematic structural diagram of a semi-floating gate transistor 200 according to an embodiment of the present application.
Fig. 3 is a flowchart of a method 300 for fabricating a semi-floating gate transistor according to the present application.
Fig. 4 is a schematic diagram of a structure formed in the preparation process of a semi-floating gate transistor according to the present application.
Fig. 5 is a schematic structural diagram of a semi-floating gate transistor 500 according to an embodiment of the present application.
Fig. 6 is a flowchart of a method 600 for fabricating a semi-floating gate transistor according to the present application.
Fig. 7 is a schematic diagram of a structure formed in the fabrication process of a semi-floating gate transistor according to the present application.
Detailed Description
The technical scheme of the application will be described below with reference to the accompanying drawings.
The semi-floating gate transistor (semi-floating gate transistor, SFGT) provided by the application can be used as a substitute of a traditional dynamic random access memory (dynamic random access memory, DRAM) to be used as a main memory in an electronic product, and provides a working memory for a processor of the electronic product. For example, it can be used in the fields of computer hosts, mobile terminal products (e.g., cell phones) or artificial intelligence (artificial intelligence, AI) computing, etc.
A semi-floating gate transistor is a transistor interposed between a metal-oxide-semiconductor field-effect transistor (MOSFET) transistor and a floating gate transistor, which connects a semi-floating gate (SFG) and a drain through a tunneling field-effect transistor (TFET), and controls charge and discharge of the semi-floating gate by the TFET, thereby forming a dynamic memory.
The main working principle of the semi-floating gate device is that the current magnitude is determined according to the threshold voltage of the transistor during reading, and the state of the semi-floating gate device can be determined according to the current intensity. In addition, the semi-floating gate device has the advantages of high speed, small area, low power consumption, compatibility with standard complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) processes, and no need of integrating new materials.
Fig. 1 is a schematic diagram of a semi-floating gate transistor. As shown in fig. 1, the semi-floating gate transistor 100 includes: the semiconductor device comprises a source region 102, a drain region 103, a channel region 101, a first gate dielectric layer 104, a semi-floating gate 105, a second gate dielectric layer 106, a control gate 107, a silicon nitride layer 108, a third gate dielectric layer 109, a split gate 110, an oxide layer 111 and a side wall 112. Wherein the semi-floating gate 105 is buried in the substrate, and the source region 102 and the drain region 103 are formed on both sides of the semi-floating gate 105, respectively. The control gate 107 covers the semi-floating gate 105 and the split gate 110 is located on one side of the control gate 107 and the semi-floating gate 105. In operation, the source region 102 and the drain region 103 communicate through the channel region 101 under the semi-floating gate.
The semi-floating gate transistor 100 shown in fig. 1 includes a semi-floating gate 105, a control gate 107 and a split gate 110, and has a relatively complex structure, and the whole device has a horizontal structure, so that the area occupied by a single device is relatively large.
In view of this, the present application proposes a semi-floating gate transistor capable of reducing the size of a single device and having a larger capacity under the same chip area.
Fig. 2 is a schematic structural diagram of a semi-floating gate transistor according to an embodiment of the present application, and as shown in fig. 2, the semi-floating gate transistor 200 includes a source (source) region 201, a channel (channel) region 202 stacked on the source region 201, and a drain (drain) region 203 stacked on the channel region 202. Therein, a trench (trench) is formed in the source region 201, the channel region 202 and the drain region 203, the trench penetrates the channel region 202 and the drain region 203, the top of the trench is located on the upper surface of the drain region 203, and the bottom of the trench is located in the source region 201.
It should be understood that the bottom of the trench may be located on the upper surface of the source region 201 or may be located in the source region 201, and the present application is not limited. As an example, fig. 2 shows the latter case.
In particular, the groove may be a U-shaped groove.
Two semi-floating gates 205 and a control gate 207 are formed in the trench. As shown in fig. 2, a portion of the control gate 207 is formed outside the trench, the upper surface of the control gate 207 is higher than the upper surface of the drain region 203, and the two half floating gates 205 are located in the left lower region and the right lower region of the control gate 207, respectively.
The semi-floating gate transistor 200 further includes a sidewall protection layer (spacer) 208, the sidewall protection layer 208 being located on both sides of the control gate 207 and on the upper surface of the drain region 203.
As shown in fig. 2, both the half floating gate 205 and the control gate 207 are buried in the substrate and the channel region 203 is of a vertical structure, so that the entire device is of a vertical structure. Where the channel region 203 is a vertical structure, it is understood that the source region 201 and the drain region 203 are in communication in a vertical direction when the semi-floating gate transistor is in operation.
It will be appreciated that the source region 201 and the drain region 203 are in communication in a vertical direction such that the left and right sides of the control gate 207 form the source, channel and drain regions of two cells, and thus the vertical structure of the semi-floating gate transistor 200 forms the left and right two memory cells.
Based on the above embodiment, the semi-floating gate transistor provided by the application comprises the left memory cell and the right memory cell, so that the size of a single memory cell can be effectively reduced, and a larger capacity can be obtained under the same chip area.
On the other hand, the semi-floating gate transistor does not comprise split gates, and is simpler in structure.
In addition, the control gate of the semi-floating gate transistor is shared by two memory cells, so that the size of a single memory cell can be reduced.
It should be appreciated that the semi-floating gate transistor is of a vertical structure, so that the electric field of the gate has less interference to the electric field of the drain region, and even if no split gate is included, the interference of the electric field of the drain region is not greatly affected, and therefore, the retention time of data is not affected without the split gate.
In one implementation, control gate 207 is a metal gate.
Specifically, as shown in fig. 2, the control gate 207 includes a barrier layer 2071 and a first filler 2072, and the control gate 207 is a metal gate, it being understood that the material of the first filler 2072 is a metal or a metal nitride. The first filler 2072 is the filler of the metal gate.
As an example, the metal may be tungsten (W), aluminum (Al), tantalum (Ta), molybdenum (Mo), cobalt (Co), ruthenium (Ru), etc., and the metal nitride may be titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.
Tungsten (W), aluminum (Al), tantalum (Ta), molybdenum (Mo), cobalt (Co), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) and the like have better process miniaturization performance and larger work function, and the device threshold voltage can be improved, the leakage current is reduced, and the data retention capacity of the semi-floating gate transistor is improved while the resistance is reduced.
The barrier layer 2071 is used to block diffusion of the first filler 2072 into a material outside the barrier layer 2071, and the barrier layer 2071 may be a metal barrier layer or a composite layer of conductive materials. For example, the material of the metal barrier layer may be titanium (Ti), tungsten (W), tantalum (Ta), ruthenium (Ru), titanium Tungsten (TiW), tantalum nitride (TaN), titanium nitride (TiN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), or the like, and the material of the conductive material composite layer may be a composite material of tantalum and tantalum nitride (Ta/TaN), a composite material of titanium and titanium nitride (Ti/TiN).
When the semi-floating gate transistor is used as a memory cell, the control gate is a bus of a word line, and in the semi-floating gate transistor provided by the embodiment of the application, the control gate is a metal gate, and the resistivity is much smaller than that of the traditional polysilicon control gate, so that the capacity of a memory array can be greatly improved, and high-density and large-capacity integration is realized.
On the other hand, the material of the control gate replaces polysilicon with metal or metal nitride, and the data retention time of the semi-floating gate transistor is longer because the work function of the metal or metal nitride material is larger than that of polysilicon and the electric leakage is smaller.
In one implementation, as shown in fig. 2, in the semi-floating gate transistor 200, the upper surfaces of the two semi-floating gates 205 are flush with the upper surface of the drain region 203.
The upper surfaces of the two semi-floating gates 205 are flush with the upper surface of the drain region 203, and it is understood that the upper surfaces of the two semi-floating gates 205 are in the same horizontal plane as the upper surface of the drain region 203, or that the plane of the upper surfaces of the two semi-floating gates 205 substantially coincides with the plane of the upper surface of the drain region 203.
In the semi-floating gate transistor provided by the embodiment of the application, the upper surface of the semi-floating gate is flush with the upper surface of the drain electrode region, so that the processing technology of the semi-floating gate transistor is simpler.
In one implementation, as depicted in fig. 2, the semi-floating gate transistor 200 further includes a first gate dielectric layer 204. The first gate dielectric layer 204 is formed in the trench, with one portion of the two half floating gates 205 covering the first gate dielectric layer 204 and the other portion of the two half floating gates 205 covering a portion of the surface of the trench.
Wherein the first gate dielectric layer 204 is an insulating layer, as an example, the material of the first gate dielectric layer 204 is silicon dioxide (SiO 2 )。
In one implementation, as shown in fig. 2, the semi-floating gate transistor 200 further includes a second gate dielectric layer 206. The second gate dielectric layer 206 is formed between the control gate 207 and the two half floating gates 205, the second gate dielectric layer 206 covering the upper surfaces and side surfaces of the two half floating gates 205 and extending to cover portions of the upper surfaces of the drain regions 203 of the surfaces of the trenches.
Wherein the second gate dielectric layer 206 is an insulating layer, as an example, a second gate dielectric layer206 is silicon dioxide (SiO 2 )。
It should be understood that the materials of the first gate dielectric layer 204 and the second gate dielectric layer 206 may be the same or different, which is not a limitation of the present application.
Wherein, as shown in fig. 2, a barrier layer 2071 covers the surface of the second gate dielectric layer 206.
Wherein the material of the two semi-floating gates 205 is polysilicon.
The material of the side protection layer 208 is an insulating material, and may be any of the following: silicon oxide (SiO), silicon nitride (Si 3 N 4 ) And a multilayer film formed of silicon oxide and silicon nitride.
The method of fabricating the semi-floating gate transistor 200 shown in fig. 2 is described in detail below in conjunction with fig. 3 and 4.
Fig. 3 is a flowchart of a method for manufacturing a semi-floating gate transistor according to the present application, and the method 300 includes the following steps.
S310, a source region 201, a channel region 202, and a drain region 203 are sequentially formed on the substrate, and trenches are formed in the source region 201, the drain region 202, and the channel region 203.
The channel region 202 is stacked on the upper surface of the source region 201, and the drain region 203 is stacked on the upper surface of the channel region 202.
Specifically, the forming process of S310 may include S301 and S302 described below.
S301, a source region 201, a channel region 202, and a drain region 203 are formed on a substrate, respectively.
Wherein the source region 201, the channel region 202 and the drain region 203 may all be formed by a doping process. The doping types of the source region 201 and the drain region 203 are the same, and the doping types of the source region 201 and the channel region 202 are opposite, for example, the doping types of the source region 201 and the drain region 203 are both N-type, and the doping type of the channel 202 is P-type.
Alternatively, the channel region 202 and the drain region 203 may also be formed by a silicon epitaxial technique.
As one example, the structure formed after S301 is as shown in fig. 4 (a).
S302, a trench is formed in the source region 201, the channel region 202, and the drain region 203 by etching treatment, the trench penetrating the channel region 202 and the drain region 203.
In particular, the groove may be a U-shaped groove.
The etching process used in S302 may be dry etching.
As an example, the trench is located in the source region 201, and the structure formed after S302 is shown in fig. 4 (b), for example.
Alternatively, in S302, a trench may be formed in the regions of the channel region 202 and the drain region 203 by an etching process, that is, the bottom of the trench formed in S302 may be located on the upper surface of the source region 201.
S320, two semi-floating gates 205 are formed in the trench.
Specifically, the formation process of the two half floating gates 205 may include S303 to S3010 described below.
S303, growing a first insulating layer 401 on the surface of the trench through a thermal oxidation process or a chemical vapor deposition (chemical vapor deposition, CVD) process.
Specifically, the first insulating layer 401 may be silicon dioxide.
As an example, the structure formed after S303 is as shown in fig. 4 (c).
S304, filling the second filler 402 in the trench after S303 by a chemical vapor deposition process, and polishing the upper surface of the second filler 402 so that the upper surface of the second filler 402 is substantially flush with the upper surface of the first insulating layer 401.
Specifically, the second filler 402 may be silicon nitride.
Specifically, the upper surface of the second filler 402 may be polished flat by a chemical mechanical polishing process.
As an example, the structure formed after S304 is as shown in fig. 4 (d).
S305, removing a part of the second filler 402 by etching, and the remaining second filler 402 is denoted as filler 403, and the upper surface of the filler 403 is higher than the upper surface of the channel region 202.
Wherein, the etching treatment in the step (2) may be dry etching.
In S305, the upper surface of the filler 403 is closer to the upper surface of the drain region 203 than the upper surface of the drain region 203 and the upper surface of the channel region 202.
As one example, the structure formed after S305 is as shown in fig. 4 (e).
S306, the first insulating layer 401 located on the upper side of the filler 403 is removed by etching treatment.
That is, the trench sidewall and the first insulating layer 401 exposed on the upper surface of the drain region 203 are removed.
The remaining first insulating layer 401 is the first gate dielectric layer 204.
The etching process used in S306 may be wet selective etching.
As one example, the structure formed after S306 is as shown in fig. 4 (f).
S307, the filler 403 is removed by etching.
The etching process used in S307 may be dry etching or wet etching.
As one example, the structure formed after S307 is as shown in fig. 4 (g).
S308, depositing polysilicon 404 in the trench by chemical vapor deposition, wherein the upper surface of polysilicon 404 is flush with the upper surface of drain region 203.
As one example, the structure formed after S308 is as shown in (h) of fig. 4.
S309, a Hard Mask (HM) material 405 is deposited, and then the intermediate portions of the hard mask material 405 and the polysilicon 404 are removed by a photolithography and etching process.
As an example, hard Mask (HM) material 405 may be Spin On Carbon (SOC) material.
Wherein 406 is Photoresist (PR).
The polysilicon 404 remaining inside the trench forms two semi-floating gates 205, one for each memory cell when the semi-floating gate transistor is used as a memory.
The etching process used in S309 may be dry etching or wet etching.
As one example, the structure formed after S309 is as shown in fig. 4 (i).
S3010, photoresist 406 and hard mask material 405 over the two semi-floating gates are removed.
As one example, the structure formed after S3010 is as shown in fig. 4 (j).
Through S303 to S3010, a first gate dielectric layer 204 and two semi-floating gates 205 are formed in the trench.
S330, control gate 207 is formed between two half floating gates 104.
Specifically, the formation process of the control gate 207 may include S3011 to S3013 described below.
S3011, growing a second insulating layer 407 on the surface of the trench after S3010 by a thermal oxidation process or a chemical vapor deposition process, the second insulating layer 407 extending to cover the upper surface of the drain region 203.
Specifically, the second insulating layer 407 may be silicon dioxide.
As one example, the structure formed after S3011 is shown in fig. 4 (k).
S3012, growing a first protective layer 408 on the surface of the second insulating layer 407 by an atomic layer deposition (atomiclayer deposition, ALD) process, filling the filler 409 by a vapor deposition technique, filling the trench with the filler 409, and covering the first protective layer 408 with the filler 409.
Wherein the filler 409 may be a metal nitride or a metal.
Specifically, the metal nitride may be titanium nitride, tantalum nitride, tungsten nitride, etc., and the metal may be tungsten, aluminum, tantalum, molybdenum, cobalt, ruthenium, etc.
Alternatively, the filler 409 may be polysilicon.
Among them, the vapor deposition technique used in S3012 may be chemical vapor deposition or physical vapor deposition (physical vapor deposition, PVD).
As one example, the structure formed after S3012 is as shown in fig. 4 (l).
S3013, a part of the filler 409, the first protective layer 408, and the left and right sides of the second insulating layer 407 on the upper side of the drain region 203 is etched by etching.
Wherein the remaining second insulating layer 407 covers the semi-floating gate 205 and extends over a portion of the upper surface of the drain region 203.
The remaining second insulating layer 407 is the second gate dielectric layer 206. The remaining filler 409 and the remaining first protective layer 408 form the control gate 207, the remaining filler 409 being the filler 2072 of the control gate 207 and the remaining first protective layer 408 being the barrier 2071 of the control gate 207.
The etching process used in S3013 may be dry etching or wet etching.
As one example, the structure formed after S3013 is as shown in (m) of fig. 4.
Through S3011 to S3013, a second gate dielectric layer 206 and a control gate 207 are formed in the trench.
S340, sidewall protection layers 208 are formed on the left and right sides of the second gate dielectric layer 206 and the control gate 207.
Wherein the sidewall protection layer 208 is located on the upper surface of the drain region 203.
Specifically, sidewall protection layers (spacers) are deposited on the left and right sides of the second gate dielectric layer 206 and the control gate 207, and the upper surfaces of the sidewall protection layers are polished flat so that the upper surfaces of the sidewall protection layers are substantially flush with the upper surfaces of the control gate 207. The sidewall protection layer 208 is further formed by removing the unnecessary portion of the sidewall protection layer by an etching process.
The sidewall protection layer 208 is formed of an insulating material, for example, silicon dioxide or silicon nitride.
The etching process used in S340 may be dry etching or wet etching.
Specifically, the upper surface of the sidewall protection layer may be polished flat by a chemical mechanical polishing process.
As one example, the structure formed after S340 is as shown in (n) of fig. 4.
It should be understood that the above process flows and methods are merely examples, and the present application is not limited to a specific process flow, as long as the semi-floating gate transistor 200 can be formed.
Based on the above embodiment, the semi-floating gate transistor provided by the application comprises the left memory cell and the right memory cell, so that the size of a single memory cell can be effectively reduced, and a larger capacity can be obtained under the same chip area.
On the other hand, the semi-floating gate transistor does not comprise split gates, and is simpler in structure.
Fig. 5 is another schematic structural diagram of a semi-floating gate transistor according to an embodiment of the present application, and as shown in fig. 5, the semi-floating gate transistor 500 includes a source region 501, a channel region 502 stacked on the source region 501, and a drain region 503 stacked on the channel region 502. Wherein a trench is formed in the source region 501, the channel region 502 and the drain region 503, the trench penetrates the channel region 502 and the drain region 503, a top of the trench is located on an upper surface of the drain region 503, and a bottom of the trench is located in the source region 501.
It should be understood that the bottom of the trench may be located on the upper surface of the source region 501 or may be located in the source region 501, which is not limited by the present application. As an example, fig. 5 shows the latter case.
In particular, the groove may be a U-shaped groove.
Two half floating gates 505 and a control gate 507 are formed in the trench. As shown in fig. 5, a portion of the control gate 507 is formed outside the trench, the upper surface of the control gate 507 is higher than the upper surface of the drain region 503, and the two half floating gates 505 are respectively located in the left lower region and the right lower region of the control gate 507.
The semi-floating gate transistor 500 further includes a sidewall protection layer 508, where the sidewall protection layer 508 is located on both sides of the control gate 507 and on the upper surface of the drain region 503.
As shown in fig. 5, both the half floating gate 505 and the control gate 507 are buried in the substrate and the channel region 503 is of a vertical structure, such that the entire device is of a vertical structure. Where the channel region 503 is a vertical structure, it is understood that the source region 501 and the drain region 503 are in communication in a vertical direction when the semi-floating gate transistor is in operation.
It will be appreciated that the source region 501 and the drain region 503 are in communication in the vertical direction such that the left and right sides of the control gate 507 form the source, channel and drain regions of two cells, and thus, the vertical structure of the semi-floating gate transistor 500 forms the left and right two memory cells.
Based on the above embodiment, the semi-floating gate transistor provided by the application comprises the left memory cell and the right memory cell, so that the size of a single memory cell can be effectively reduced, and a larger capacity can be obtained under the same chip area.
On the other hand, the semi-floating gate transistor does not comprise split gates, and is simpler in structure.
In addition, the control gate of the semi-floating gate transistor is shared by two memory cells, so that the size of a single memory cell can be reduced.
It should be appreciated that the semi-floating gate transistor is of a vertical structure, so that the electric field of the gate has less interference to the electric field of the drain region, and even if no split gate is included, the interference of the electric field of the drain region is not greatly affected, and therefore, the retention time of data is not affected without the split gate.
In one implementation, control gate 507 is a metal gate.
Specifically, as shown in fig. 5, the control gate 507 includes a barrier layer 5071 and a first filler 5072, and the control gate 207 is a metal gate, it being understood that the material of the first filler 5072 is a metal or a metal nitride. The first filler 5072 is a filler of the metal gate.
For specific description of the control gate 507, the barrier layer 5071, and the first filler 5072, reference may be made to the control gate 207, the barrier layer 2071, and the first filler 2072, which are not described herein.
When the semi-floating gate transistor is used as a memory cell, the control gate is a bus of a word line, and in the semi-floating gate transistor 400 provided by the embodiment of the application, the control gate is a metal gate, and the resistivity is much smaller than that of the traditional polysilicon control gate, so that the capacity of a memory array can be greatly improved, and high-density and large-capacity integration is realized.
On the other hand, the material of the control gate replaces polysilicon with metal or metal nitride, and the data retention time of the semi-floating gate transistor is longer because the work function of the metal or metal nitride material is larger than that of polysilicon and the electric leakage is smaller.
In one implementation, as shown in fig. 5, in the semi-floating gate transistor 500, the upper surfaces of the two semi-floating gates 505 are located between the upper surface of the drain region 503 and the upper surface of the channel region.
The upper surfaces of the two half floating gates 505 are located between the upper surface of the drain region 503 and the upper surface of the channel region, and it is understood that the plane of the upper surfaces of the two half floating gates 505 is between the plane of the upper surface of the drain region 503 and the plane of the upper surface of the channel region.
In the semi-floating gate transistor provided by the embodiment of the application, the upper surface of the semi-floating gate is arranged between the upper surface of the drain electrode region and the upper surface of the channel region, so that the distance between the control gate and the drain electrode region is relatively short, and the semi-floating gate transistor has higher programming efficiency.
In one implementation, as depicted in fig. 5, the semi-floating gate transistor 500 further includes a first gate dielectric layer 504. The first gate dielectric layer 504 is formed in the trench, with one portion of the two half floating gates 505 covering the first gate dielectric layer 504 and the other portion of the two half floating gates 505 covering a portion of the surface of the trench.
Wherein the first gate dielectric layer 504 is an insulating layer, as an example, the material of the first gate dielectric layer 504 is silicon dioxide (SiO 2 )。
In one implementation, as shown in fig. 5, the semi-floating gate transistor 500 further includes a second gate dielectric layer 506. The second gate dielectric layer 506 is formed between the control gate 507 and the two half floating gates 505, the second gate dielectric layer 506 covering the upper surfaces and side surfaces of the two half floating gates 505 and extending to cover portions of the surfaces of the trenches and portions of the upper surfaces of the drain regions 503.
Wherein the second gate dielectric layer 506 is an insulating layer, as an example, the material of the second gate dielectric layer 506 is silicon dioxide (SiO 2 )。
It should be understood that the materials of the first gate dielectric layer 504 and the second gate dielectric layer 506 may be the same or different, which is not limited by the present application.
Wherein, as shown in fig. 5, the barrier layer 5071 covers the surface of the second gate dielectric layer 506.
Wherein the material of the two half floating gates 505 is polysilicon.
The material of the side protection layer 508 is an insulating material, and may be any of the following: silicon oxide (SiO), silicon nitride (Si 3 N 4 ) And a multilayer film formed of silicon oxide and silicon nitride.
The method of fabricating the semi-floating gate transistor 400 shown in fig. 4 is described in detail below in conjunction with fig. 5 and 6.
Fig. 6 is a flowchart of a method for manufacturing a semi-floating gate transistor according to the present application, and the method 500 includes the following steps.
S610, a source region 501, a channel region 502, and a drain region 503 are sequentially formed on the substrate, and trenches are formed in the source region 501, the channel region 502, and the drain region 503.
Specifically, the forming process of S610 includes S601 and S602.
S601, a source region 501, a channel region 502, and a drain region 503 are formed on a substrate, respectively.
S601 refers to S301 above, and will not be described again here, the structure formed by S601 is shown in fig. 7 (a).
S602, a trench is formed in the source region 501, the channel region 502, and the drain region 503 by etching treatment, the trench penetrating the channel region 502 and the drain region 503.
S602 refers to S302 above, and will not be described again here, and the structure formed by S602 is shown in fig. 7 (b).
S620, two semi-floating gates 505 are formed in the trench.
Specifically, the formation process of the two half floating gates 505 may include S603 to S6010 described below.
S603, growing a first insulating layer 701 on the surface of the trench by a thermal oxidation process or a chemical vapor deposition process.
S603 refers to S303 above, and is not described here again. The structure formed in S603 is shown in fig. 7 (c).
S604, filling the second filler 702 in the trench after S603 by a chemical vapor deposition process, and polishing the upper surface of the second filler 702 so that the upper surface of the second filler 702 and the upper surface of the first insulating layer 701 are substantially flush.
S604 refers to S304 above, and will not be described again here, and the structure formed by S604 is shown in fig. 7 (d).
S605, a portion of the second filler 702 is removed by etching, and the remaining second filler 702 is denoted as filler 703, and the upper surface of the filler 703 is higher than the upper surface of the channel region 502.
S605 refers to S305 above, and will not be described again here, and the structure formed in S605 is shown in fig. 7 (e).
Among them, S605 differs from S305 in that the depth of etching in S605 is deeper, and in S605, the upper surface of the filler 703 is closer to the upper surface of the channel region 502 than the upper surface of the drain region 503 and the upper surface of the channel region 502.
S606, the first insulating layer 701 located on the upper side of the filler 703 is removed by etching treatment.
S606 refers to S306 above, and will not be described again here, the structure formed by S606 is shown in fig. 7 (f).
The remaining first insulating layer 701 is the first gate dielectric layer 504.
S607, the filler 703 is removed by etching processing.
S607 reference is made to S307 above, and details of the structure formed in S607 are shown in fig. 7 (g) and will not be repeated here.
S608, polysilicon is deposited by a chemical vapor deposition process, and a portion of the polysilicon is removed by an etching process, wherein the upper surface of the remaining polysilicon 704 is higher than the plane in which the uppermost end of the first gate dielectric layer 504 is located.
The etching process used in S608 may be dry etching or wet etching.
As one example, the structure formed after S608 is as shown in (h) of fig. 7.
S609, a hard mask material 705 is deposited to fill the trench, and then the intermediate portions of the hard mask material 705 and the polysilicon 704 are removed by photolithography and etching processes.
As an example, the hard mask material 705 may be a spin-on carbon material.
Wherein 706 is photoresist.
The polysilicon 704 remaining inside the trench forms two half floating gates 505, each corresponding to a memory cell when the half floating gate transistor is used as a memory.
The etching process used in S609 may be dry etching or wet etching.
As one example, the structure formed after S609 is as shown in fig. 7 (i).
S6010, photoresist 706 and hard mask material 705 over the two semi-floating gates are removed.
As one example, the structure formed after S6010 is as shown in (j) of fig. 7.
Through S603 to S6010, a first gate dielectric layer 504 and two half floating gates 505 are formed in the trench.
S630, a control gate 507 is formed between the two half floating gates 505.
Specifically, the formation process of the control gate 507 may include S6011 to S6014 described below.
S6011, a second insulating layer 707 is grown on the surface of the trench after S6010 by a thermal oxidation process or a chemical vapor deposition process, the second insulating layer 707 extending to cover the upper surface of the drain region 503.
Specifically, the second insulating layer 407 may be silicon dioxide.
As an example, the structure formed through S6011 is shown in (k) of fig. 7.
S6012, growing a first protective layer 708 on the surface of the second insulating layer 707 by an atomic layer deposition process, filling the filler 709 with a vapor deposition technique, filling the trench with the filler 709, and covering the first protective layer 708 with the filler 709.
Wherein the filler 709 may be a metal nitride or a metal.
Specifically, the metal nitride may be titanium nitride, tantalum nitride, tungsten nitride, etc., and the metal may be tungsten, aluminum, tantalum, molybdenum, cobalt, ruthenium, etc.
Optionally, the filler 709 may also be polysilicon.
Among them, the vapor deposition technique used in S6012 may be chemical vapor deposition or physical vapor deposition.
As an example, the structure formed through S6012 is shown in (l) of fig. 7.
S6013, etching a part of the filler 709, the first protective layer 708, and the left and right sides of the second insulating layer 707 on the upper side of the drain region 503 by etching.
Wherein the remaining second insulating layer 707 covers the semi-floating gate 505 and extends over a portion of the upper surface of the drain region 503.
The remaining second insulating layer 707 is the second gate dielectric layer 506. The remaining filler 709 and the remaining first protective layer 708 form the control gate 507, the remaining filler 709 is the filler 7072 of the control gate 707, and the remaining first protective layer 408 is the barrier layer 5071 of the control gate 507.
Among them, the etching process used in S6013 may be dry etching or wet etching.
As an example, the structure formed through S6013 is shown in (m) of fig. 7.
S640, sidewall protection layers 508 are formed on the left and right sides of the control gate 507 and the second gate dielectric layer 506.
Wherein, the sidewall protection layer 508 is located on the upper surface of the drain region 503.
Specifically, a sidewall protection layer is deposited on the left and right sides of the control gate 507 and the second gate dielectric layer 506 by using a chemical vapor deposition process, and the upper surface of the sidewall protection layer is polished flat, so that the upper surface of the sidewall protection layer is substantially flush with the upper surface of the control gate 507. The unnecessary portion of the sidewall protection layer is further removed by an etching process, so as to form sidewall protection layer 508.
The sidewall protection layer 508 is formed of an insulating material, for example, silicon dioxide or silicon nitride.
The etching process used in S640 may be dry etching or wet etching.
Specifically, the upper surface of the sidewall protection layer may be polished flat by a chemical mechanical polishing process.
As one example, the structure formed after S640 is as shown in fig. 7 (n).
It should be understood that the above process flows and methods are merely examples, and the present application is not limited to a specific process flow, as long as the semi-floating gate transistor 500 can be formed.
Based on the above embodiment, the semi-floating gate transistor provided by the application comprises the left memory cell and the right memory cell, so that the size of a single memory cell can be effectively reduced, and a larger capacity can be obtained under the same chip area.
On the other hand, the semi-floating gate transistor does not comprise split gates, and is simpler in structure.
The embodiment of the application also provides a memory, which comprises a memory array, a word line and a bit line, wherein the memory array comprises the semi-floating gate transistor 200 or 500, and the memory array is respectively connected with the word line and the bit line.
Optionally, the memory further comprises a memory peripheral circuit, the memory peripheral circuit being connected to the memory array.
The embodiment of the application also provides electronic equipment which comprises a printed circuit board (printed circuit board, PCB) and the memory.
It should be noted that, the azimuth or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. herein are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present application.
Furthermore, the details described herein, such as the structure, materials, dimensions, processing and techniques of the devices, are for ease of understanding the technical solution of the present application only and are not necessarily meant to be implemented in accordance with these details. For example, the materials of the various parts of the device may be realized by materials known to those skilled in the art, or may be realized by materials having similar functions developed in the future.
It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural. In addition, the character "/" herein generally indicates that the associated object is an "or" relationship, but may also indicate an "and/or" relationship, and may be understood by referring to the context.
In the present application, "at least one" means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
In the embodiment of the application, prefix words such as "first" and "second" are adopted, and only for distinguishing different description objects, no limitation is imposed on the position, sequence, priority, quantity or content of the described objects. For example, the object being described is an "insulating layer," and ordinal numbers preceding the "insulating layer" in the "insulating layer" and the "second insulating layer" do not limit the position or order or priority between the "insulating layers.
It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (15)
1. A semi-floating gate transistor, the semi-floating gate transistor comprising:
a source region, a channel region and a drain region, wherein the channel region is stacked on the upper surface of the source region, the drain region is stacked on the upper surface of the channel region, and grooves are formed in the source region, the channel region and the drain region and penetrate through the channel region and the drain region;
The control gate and the two semi-floating gates are formed in the groove, the two semi-floating gates are respectively positioned in the left lower area and the right lower area of the control gate, and the upper surface of the control gate is higher than the upper surface of the drain electrode area;
and the side wall protection layers are positioned on two sides of the control gate and on the upper surface of the drain electrode region.
2. The semi-floating gate transistor of claim 1, wherein said control gate is a metal gate.
3. The semi-floating gate transistor of claim 1 or 2, wherein the control gate comprises a filler and a barrier layer, the filler material being a metal or metal nitride.
4. The semi-floating gate transistor of claim 3, wherein said metal is tungsten, tantalum, molybdenum, cobalt, ruthenium, or aluminum and said metal nitride is titanium nitride, tungsten nitride, or tantalum nitride.
5. The semi-floating gate transistor of any one of claims 1 to 4, wherein an upper surface of the two semi-floating gates is flush with an upper surface of the drain region.
6. The semi-floating gate transistor of any one of claims 1 to 4, wherein the upper surfaces of the two semi-floating gates are located between the upper surface of the drain region and the upper surface of the channel region.
7. A method for manufacturing a semi-floating gate transistor, the method comprising:
sequentially forming a source region, a channel region and a drain region on a substrate, wherein the channel region is stacked on the upper surface of the source region, the drain region is stacked on the upper surface of the channel region, and grooves are formed in the source region, the channel region and the drain region and penetrate through the channel region and the drain region;
forming two semi-floating gates in the groove;
forming a control gate between the two semi-floating gates, wherein the upper surface of the control gate is higher than the upper surface of the drain electrode region, and the two semi-floating gates are respectively positioned in the left lower region and the right lower region of the control gate;
and forming side wall protection layers on two sides of the control gate, wherein the side wall protection layers are positioned on the upper surface of the drain electrode region.
8. The method of claim 7, wherein the control gate is a metal gate.
9. The method of claim 7 or 8, wherein the control gate comprises a filler and a barrier layer, the filler being a metal or metal nitride, the forming the control gate between the two semi-floating gates comprising:
Depositing the barrier layer and the filler between the two semi-floating gates using an atomic layer deposition process and a vapor deposition technique;
and etching the barrier layer and the filler by using etching treatment to form the control gate.
10. The method of claim 9, wherein the metal is tungsten, tantalum, molybdenum, cobalt, ruthenium, or aluminum and the metal nitride is titanium nitride, tungsten nitride, or tantalum nitride.
11. The method of any of claims 7 to 10, wherein the upper surfaces of the two semi-floating gates are flush with the upper surface of the drain region.
12. The method of any of claims 7 to 10, wherein the upper surfaces of the two semi-floating gates are located between the upper surface of the drain region and the upper surface of the channel region.
13. A memory, comprising: a memory array comprising the semi-floating gate transistor of any one of claims 1 to 6, a word line, and a bit line, the memory array being connected to the word line and the bit line, respectively.
14. The memory of claim 13, further comprising a memory peripheral circuit, the memory peripheral circuit being coupled to the memory array.
15. An electronic device, comprising: a printed circuit board and a memory as claimed in claim 13 or 14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210441161.9A CN117012837A (en) | 2022-04-25 | 2022-04-25 | Semi-floating gate transistor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210441161.9A CN117012837A (en) | 2022-04-25 | 2022-04-25 | Semi-floating gate transistor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117012837A true CN117012837A (en) | 2023-11-07 |
Family
ID=88574814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210441161.9A Pending CN117012837A (en) | 2022-04-25 | 2022-04-25 | Semi-floating gate transistor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117012837A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117596878A (en) * | 2024-01-15 | 2024-02-23 | 上海朔集半导体科技有限公司 | U-shaped floating gate type split gate embedded non-volatile memory and manufacturing method thereof |
-
2022
- 2022-04-25 CN CN202210441161.9A patent/CN117012837A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117596878A (en) * | 2024-01-15 | 2024-02-23 | 上海朔集半导体科技有限公司 | U-shaped floating gate type split gate embedded non-volatile memory and manufacturing method thereof |
| CN117596878B (en) * | 2024-01-15 | 2024-04-09 | 上海朔集半导体科技有限公司 | U-shaped floating gate type split gate embedded non-volatile memory and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109075175B (en) | Through storage level through hole structure between stepped areas in three-dimensional storage device and preparation method thereof | |
| US10559590B2 (en) | Three-dimensional semiconductor devices | |
| US9691778B2 (en) | Multiheight contact via structures for a multilevel interconnect structure | |
| CN110313061B (en) | Bonding opening structure of three-dimensional memory device and forming method thereof | |
| US7649779B2 (en) | Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems | |
| US9601502B2 (en) | Multiheight contact via structures for a multilevel interconnect structure | |
| US9236392B1 (en) | Multiheight electrically conductive via contacts for a multilevel interconnect structure | |
| US9142563B2 (en) | Three dimensional semiconductor memory devices and methods of fabricating the same | |
| US11107832B2 (en) | Apparatuses including memory cells and related methods | |
| KR101350584B1 (en) | Flash memory having multi-level architecture | |
| JP3564472B2 (en) | Method for manufacturing semiconductor device | |
| CN117012837A (en) | Semi-floating gate transistor and preparation method thereof | |
| US20200111794A1 (en) | Method for fabricating semiconductor device | |
| EP3971990B1 (en) | Semiconductor structure and method for manufacturing same | |
| CN111373533B (en) | Three-dimensional memory device including hydrogen diffusion barrier structure and method of fabricating the same | |
| KR20210148931A (en) | Semiconducting metal oxide transistors having a patterned gate and methods for forming the same | |
| US20070057317A1 (en) | Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory | |
| CN116367539B (en) | Semiconductor device, memory, manufacturing method of memory and electronic equipment | |
| US11877440B2 (en) | Bit line structure including ohmic contact and forming method thereof | |
| CN116406164B (en) | Semiconductor structure and preparation method thereof | |
| CN116723700B (en) | Semiconductor device, manufacturing method thereof and electronic equipment | |
| US20230369431A1 (en) | Semiconductor structure and method for manufacturing semiconductor structure | |
| CN115064498A (en) | Method for manufacturing semiconductor structure and semiconductor structure | |
| CN115274417A (en) | Semiconductor structure and preparation method thereof | |
| CN114551470A (en) | Three-dimensional memory and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication |