CN117008382A - Array substrate, display device and display mother board - Google Patents
Array substrate, display device and display mother board Download PDFInfo
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- CN117008382A CN117008382A CN202210475499.6A CN202210475499A CN117008382A CN 117008382 A CN117008382 A CN 117008382A CN 202210475499 A CN202210475499 A CN 202210475499A CN 117008382 A CN117008382 A CN 117008382A
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The embodiment of the application provides an array substrate, a display device and a display motherboard, wherein the array substrate comprises: the first substrate comprises a display area and a sub-peripheral area positioned at one side of the display area, and the first sub-peripheral area comprises a binding area; the signal terminals are positioned in the binding areas and connected with the data lines in the corresponding display areas; the first test electrode is positioned in the first sub-peripheral area and connected with the signal terminal; and one end of the second conductive wire is connected with the first test electrode, and the other end of the second conductive wire extends to the edge of the array substrate. According to the embodiment of the application, the second conductive wire is arranged so that the second conductive wire spans the split wire. Static electricity generated by friction between the cutting knife wheel and the metal wire in the breaking process is avoided, so that charges accumulated on the metal wire are reduced, and the probability of static electricity discharge generated by the metal wire is reduced. And further, the conduction of the signal path is ensured, and the accuracy and the reliability of the lighting test are improved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a display device and a display motherboard.
Background
The liquid crystal display device (Liquid Crystal Display, LCD) has many advantages such as thin body, power saving, no radiation, etc., and is widely used as follows: liquid crystal televisions, mobile phones, personal digital assistants (Personal Digital Assistant, PDAs), digital cameras, computer screens or notebook computer screens, and the like.
The structure of the liquid crystal panel is generally composed of a Color Filter substrate (CF), a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and a liquid crystal layer (Liquid Crystal Layer, LC) disposed between the two substrates, and the working principle is that the rotation of liquid crystal molecules of the liquid crystal layer is controlled by applying a driving voltage to the two glass substrates, so that the light of the backlight module is refracted to generate a picture.
In the production process of the CF substrate and the TFT array substrate, especially in the production process of the TFT array substrate, electrostatic discharge (ESD) is a very common phenomenon that is also difficult to avoid. The electrostatic discharge can result in reduced yield, increased cost and reduced throughput of the LCD panel. The signal lighting inspection process is an important process in the liquid crystal display industry, and aims to screen out bad panels in time before the panels are attached and the signal terminals are pressed, so that the waste of module materials is avoided. The signal lighting includes an Array signal lighting Test (AT) and a box signal lighting Test (Cell Test, CT), the AT mainly performs power-up inspection on the panel after the Array substrate manufacturing process is completed, and the CT mainly performs inspection after the panel is broken. The manufacturing process of the array substrate generally includes manufacturing a large-area motherboard, and then cutting the motherboard to obtain a plurality of array substrates. The method comprises the steps of carrying out AT test after the mother board is formed, cutting (cutting) and then carrying out CT test, wherein the CT test is easy to report errors, and the detection precision of good products is low.
In summary, the array substrate in the prior art has the technical problem of the dark line misjudgment phenomenon during the box signal lighting test.
Disclosure of Invention
The application provides an array substrate, a display device and a display motherboard aiming at the defects of the prior art, which are used for solving the technical problem that the array substrate in the prior art has a dark line misjudgment phenomenon during the box signal lighting test.
In a first aspect, an embodiment of the present application provides an array substrate, including:
the first substrate comprises a display area and a sub-peripheral area positioned at one side of the display area, and the first sub-peripheral area comprises a binding area;
the signal terminals are positioned in the binding areas and connected with the data lines in the corresponding display areas;
the first test electrode is positioned in the first sub-peripheral area and connected with the signal terminal; and
and one end of the second conductive wire is connected with the first test electrode, and the other end of the second conductive wire extends to the edge of the array substrate.
In some embodiments of the present application, the array substrate further includes a first signal line, a terminal lead, and a first conductive line, where the first signal line is connected to the first test electrode and the first conductive line, and the terminal lead is connected to the first conductive line and the signal terminal, respectively.
In some embodiments of the application, the material of at least one of the first conductive line and the second conductive line comprises a transparent conductive material.
In some embodiments of the present application, the array substrate includes a first metal layer and a second metal layer located on a side of the first metal layer away from the first substrate, at least a portion of the first metal layer forming a terminal lead, at least a portion of the second metal layer forming a first signal line.
In some embodiments of the present application, at least a portion of the first conductive line is located on a side of the second metal layer away from the first metal layer, a first insulating layer is disposed between the first metal layer and the second metal layer, a second insulating layer is disposed between a portion of the first conductive line and the second metal layer, first bridging holes are formed in the first insulating layer and the second insulating layer, and a portion of the first conductive line is filled in the first bridging holes.
In some embodiments of the present application, at least a portion of the first conductive line is located on a side of the first metal layer away from the second metal layer, a first insulating layer is disposed between the first metal layer and the second metal layer, a second insulating layer is disposed between a portion of the first conductive line and the first metal layer, first bridging holes are formed in the first insulating layer and the second insulating layer, and a portion of the first conductive line is filled in the first bridging holes.
In some embodiments of the present application, at least a portion of the first conductive line is located between the second metal layer and the first metal layer, a first insulating layer is disposed between the first metal layer and a portion of the first conductive line, a second insulating layer is disposed between a portion of the first conductive line and the second metal layer, first bridging holes are formed in the first insulating layer and the second insulating layer, and a portion of the first conductive line is filled in the first bridging holes.
In some embodiments of the application, the first metal layer comprises at least one of titanium, molybdenum, niobium, copper, and aluminum, and the second metal layer comprises at least one of titanium, molybdenum, niobium, copper, and aluminum.
In a second aspect, an embodiment of the present application provides a display apparatus, including: the color film substrate is arranged oppositely, and the array substrate is provided by any embodiment of the first aspect.
In some embodiments of the application, the signal terminals are tied to the chip terminals; or the signal terminals are bound with the flip-chip film terminals.
In a third aspect, an embodiment of the present application provides a display motherboard, including:
the second substrate comprises at least two display areas, wherein a dividing line is arranged in a peripheral area between the two display areas, a first sub-peripheral area is arranged between the dividing line and at least one of the two display areas, a second sub-peripheral area is arranged on the dividing line far away from the first sub-peripheral area, and a binding area is arranged on the first sub-peripheral area;
the signal terminals are positioned in the binding areas and connected with the data lines in the corresponding display areas;
the first test electrode is positioned in the first sub-peripheral area and connected with the signal terminal; and
the second testing electrode is positioned in the second sub-peripheral area and connected with the first testing electrode through a second conductive wire, one part of the second conductive wire is positioned in the first sub-peripheral area and connected with the first testing electrode, and the other part of the second conductive wire is positioned in the second sub-peripheral area and connected with the second testing electrode.
In some embodiments of the present application, the display motherboard further includes a second signal line connected to the second test electrode and the second conductive line, respectively.
In some embodiments of the present application, the display motherboard includes a first metal layer and a second metal layer located on a side of the first metal layer away from the second substrate, at least a portion of the first metal layer forming a terminal lead, at least a portion of the second metal layer forming a second signal line.
In some embodiments of the present application, at least a portion of the second conductive line is located on a side of the second metal layer away from the second substrate, a third insulating layer is disposed between a portion of the second conductive line and the second metal layer, a second bridge hole is formed in the third insulating layer, and a portion of the second conductive line is filled in the second bridge hole.
The technical scheme provided by the embodiment of the application has the beneficial technical effects that: a test path is formed by arranging a second conductive wire to communicate the first test electrode and the second test electrode, so that the second conductive wire replaces a metal wire to cross the split wire. Compared with the prior art, the static electricity generated by friction between the cutting knife wheel and the metal wire in the breaking process is avoided, so that the accumulated charges on the metal wire are reduced, and the probability of static electricity discharge generated by the metal wire is reduced. And further, the conduction of the signal path is ensured, the accuracy and the reliability of the lighting test are improved, the product yield of the display device is improved, and the production cost is reduced. Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of an array substrate according to an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of an array substrate along line C-C' in FIG. 1;
FIG. 3 is a schematic cross-sectional view of another array substrate along line C-C' in FIG. 1;
FIG. 4 is an enlarged schematic view of a left connection point of the array substrate Q in FIG. 1;
FIG. 5 is a schematic cross-sectional view of an array substrate along B-B' in FIG. 1;
fig. 6 is an enlarged schematic view of the array substrate P in fig. 5;
fig. 7 is a schematic diagram showing the structure of a motherboard according to an embodiment of the present application.
In the figure:
1-a first substrate; 11-breaking lines;
21-a first test electrode; 22-a first conductive line; 23-a first signal line; 24-a first insulating layer; 25-a second insulating layer;
31-a second test electrode; 32-a second conductive line; 33-a second signal line; 34-a third insulating layer; 35-a fourth insulating layer;
41-signal terminals; 42-terminal leads;
5-data lines; 6-a second substrate; 7-an array substrate; 8-color film substrate; 9-frame glue.
Detailed Description
The present application is described in detail below, examples of embodiments of the application are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. Further, if detailed description of the known technology is not necessary for the illustrated features of the present application, it will be omitted. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
It is found that in the panel breaking process, the cutting knife wheel can accumulate charges on the metal wire under high-speed rotation, the conductive layer is damaged by the ESD, even the conductive layer is broken, signals cannot be conducted to the data line, and the signals are displayed as dark lines in the display area.
In the prior art, static electricity is easy to generate in the panel breaking process, so that a conductive layer is damaged by explosion, and the technical problem of misjudgment of a dark line exists when a box signal is generated for lighting test is solved.
The application provides an array substrate, a display device and a display motherboard, and aims to solve the technical problems in the prior art. The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments.
In a first aspect, an embodiment of the present application provides an array substrate. As shown in fig. 1, fig. 1 is a schematic structural diagram of an array substrate 7 according to an embodiment of the application. An array substrate 7, comprising:
a first substrate 1, which comprises a display area and a sub-peripheral area positioned at one side of the display area, wherein the first sub-peripheral area comprises a binding area;
the signal terminal 41 is positioned in the binding area and is connected with the data line 5 in the corresponding display area;
a first test electrode 21 located in the first sub-peripheral area and connected to the signal terminal 41; and
and a second conductive wire 32 having one end connected to the first test electrode 21 and the other end extending to the edge of the array substrate 7, the second conductive wire 32 being used to connect to the second test electrode 31 on the array motherboard before the array substrate 7 is broken.
In a specific embodiment, the second conductive line 32 is located in a common conductive layer, a portion of the common conductive layer located in the display area forms a common electrode, and a portion of the common conductive layer located in the first sub-peripheral area forms the second conductive line 32.
A test path is formed by providing a second conductive line 32 to communicate the first test electrode 21 and the second test electrode 31 such that the second conductive line 32 crosses the breaking line 11 instead of a metal wire. Compared with the prior art, the static electricity generated by friction between the cutting knife wheel and the metal wire in the breaking process is avoided, so that the accumulated charges on the metal wire are reduced, and the probability of static electricity discharge generated by the metal wire is reduced.
In some embodiments of the application, at least part of the second conductive line 32 is located on the side of the first test electrode 21 remote from the first substrate 1.
As shown in fig. 2, fig. 2 is a schematic cross-sectional view of an array substrate along C-C' in fig. 1. The first test electrode 21 and the first signal wire 23 are arranged on the first substrate 1 in the same layer, the main body part of the second conductive wire 32 is positioned at one side of the first test electrode 21 far away from the first substrate 1, a third insulating layer 34 is arranged between the second conductive wire 32 and the first test electrode 21, a second bridging hole is formed in the third insulating layer 34, the bridging part of the second conductive wire 32 is filled in the second bridging hole, and the second conductive wire 32 is communicated with the first test electrode 21.
In the sectioning process, the second conductive wire 32 and the cutter wheel generate high-speed friction, the second conductive wire 32 may become a discharge body, and the circuit with weak antistatic performance is a sensitive body. One factor affecting the electrostatic discharge strength includes: the distance between the discharge body and the sensitive body. Static electricity is a high-frequency disturbance, and an electromagnetic field is generated when a discharge body discharges. When the distance between the discharge body and the sensitive body is smaller, larger parasitic capacitance and smaller coupling impedance are generated, and the sensitive body is more easily disturbed and damaged. In this embodiment, by disposing the second conductive wire 32 on the side of the first test electrode 21 away from the first substrate 1, and in at least one embodiment, the sensitive body is located on the side of the first test electrode 21 close to the first substrate 1, the distance between the second conductive wire 32 and the sensitive body is increased, the probability of electrostatic discharge on the second conductive wire 32 is reduced, the sensitive body is damaged by a scratch, and conduction of the signal path is ensured.
As shown in fig. 3, fig. 3 is a schematic cross-sectional view of another array substrate along C-C' in fig. 1. As shown in fig. 2, fig. 2 is a schematic cross-sectional view of an array substrate along C-C' in fig. 1. The first test electrode 21 and the first signal wire 23 are arranged on the first substrate 1 in the same layer, the main body part of the second conductive wire 32 is positioned on one side of the first test electrode 21 far away from the first substrate 1, a third insulating layer 34 and a fourth insulating layer 35 are arranged between the second conductive wire 32 and the first test electrode 21, sub-holes are respectively formed in the third insulating layer 34 and the fourth insulating layer 35, the two sub-holes are communicated up and down to form a second bridging hole, the bridging part of the second conductive wire 32 is filled in the second bridging hole, and the second conductive wire 32 is communicated with the first test electrode 21.
In other embodiments of the present application, the material in the first conductive line 22 comprises a transparent conductive material and the material in the second conductive line 32 comprises a transparent conductive material.
In one embodiment, the transparent conductive material is indium tin oxide; in another embodiment, the transparent conductive material is indium zinc oxide.
Another factor affecting the electrostatic discharge strength includes: the materials of the discharge bodies are different. The migration speed of charges is different between different materials. In at least one embodiment, the material of the second conductive line 32 includes indium tin oxide, the square resistance of the indium tin oxide is greater than that of the metal wire in the prior art, the migration speed of the charges in the indium tin oxide is smaller than that of the charges in the metal wire, and then the amount of charges exchanged between the indium tin oxide and the dicing wheel is smaller than that exchanged between the metal wire and the dicing wheel. Thereby reducing the probability of electrostatic discharge on the second conductive line 32, reducing damage to the sensitive body by the shock, and ensuring conduction of the signal path.
Based on the above embodiments, the present application also discloses some embodiments, as shown in fig. 4, and fig. 4 is an enlarged schematic diagram of a left connection point at the array substrate Q in fig. 1. The array substrate 7 further includes a first signal line 23, a terminal lead 42, and a first conductive line 22, wherein the first signal line 23 is connected to the first test electrode 21 and the first conductive line 22, respectively, and the terminal lead 42 is connected to the first conductive line 22 and the signal terminal 41, respectively.
After the breaking process, at least a signal path for the box signal lighting test is reserved in the array substrate 7. It comprises the following steps: the first test electrode 21 receives the cartridge test signal, and the cartridge test signal is transmitted from the output end of the first test electrode 21 to the signal terminal 41 through the first signal line 23, the first conductive line 22, and the terminal lead 42 in this order. The signal terminal 41 is transmitted to the data line 5 to light up, thereby checking the defective panel.
It will be appreciated that at least the signal paths of the array signal lighting test and the signal paths of the box signal lighting test are simultaneously reserved in the display motherboard prior to the breaking process. The signals of the box-forming signal lighting test are as in the above embodiments, and are not described herein. The signal path of the array signal lighting test includes: the second test electrode 31 receives the array test signal, and the output end of the second test electrode 31 sequentially passes through the second signal line 33, the second conductive line 32 and the input end of the first test electrode 21 to be transferred to the first test electrode 21, and then the output end of the first test electrode 21 sequentially passes through the first signal line 23, the first conductive line 22 and the terminal lead 42 to be transferred to the signal terminal 41. The signal terminal 41 is transmitted to the data line 5 to light up, thereby checking the defective panel.
In some embodiments of the present application, the array substrate 7 includes a first metal layer and a second metal layer located on a side of the first metal layer away from the first substrate 1, at least a portion of the first metal layer forming the terminal lead 42, and at least a portion of the second metal layer forming the first signal line 23.
In the present embodiment, the first signal line 23 and the terminal lead 42 are respectively located at different layers, so that the first signal line 23 and the terminal lead 42 are prevented from being staggered in the same layer or the length of the first signal line 23 or the terminal lead 42 is prolonged to avoid the staggering, which results in more occupied wiring space and more wasted manufacturing cost. In one embodiment, the terminal leads 42 are located in a first metal layer near the first substrate 1 and the first signal lines 23 are located in a second metal layer far from the first substrate 1. In another embodiment, the terminal leads 42 are located in the second metal layer away from the first substrate 1 and the first signal lines 23 are located in the first metal layer close to the first substrate 1.
In one embodiment of the present application, as shown in fig. 5 and 6, fig. 5 is a schematic cross-sectional view of an array substrate along B-B' in fig. 1, and fig. 6 is an enlarged schematic view of an array substrate P in fig. 5. At least part of the first conductive wires 22 are located at one side, far away from the first metal layer, of the second metal layer, a first insulating layer 24 is arranged between the first metal layer and the second metal layer, a second insulating layer 25 is arranged between part of the first conductive wires 22 and the second metal layer, first bridging holes are formed in the first insulating layer and the second insulating layer, and part of the first conductive wires 22 are filled in the first bridging holes. The panel edge is the position of the breaking line 11, the minimum distance between the breaking line 11 and the metal wire is D, and D is larger than 0, so that the metal wire closest to the panel edge still keeps a certain distance from the breaking line 11, and static electricity is prevented from being accumulated due to direct contact between the metal wire and the cutting knife wheel.
In the present embodiment, at least part of the first conductive line 22 is located on the side of the first metal layer and the second metal layer away from the first substrate 1, i.e. the main body portion of the first conductive line 22 is located at the outermost side of the array substrate 7 compared to the first metal layer and the second metal layer. In a specific embodiment, the main portion of the first conductive line 22, the first metal layer and the second metal layer are parallel. First bridging holes are formed between the main body of the first conductive wire 22 and the first metal layer, and between the main body of the first conductive wire 22 and the second metal layer, and the bridging portions of the first conductive wire 22 are respectively filled in the at least two first bridging holes, so that the first conductive wire 22 is electrically connected with the first metal layer and the second metal layer respectively. Thereby realizing the exchange and conduction between the first metal layer and the second metal layer at the same time, and forming a complete signal path. In the above embodiment, only the first conductive wire 22 is described as including one main body portion, if the first conductive wire 22 includes two or more main body portions, the two or more main body portions are located in different layers and parallel to each other, more first bridging holes are formed between the different main body portions, the bridging portions of the first conductive wire 22 are filled in the newly formed first bridging holes, and the plurality of main body portions cooperate to realize the electrical connection between the first conductive wire 22 and the first metal layer and the second metal layer, respectively.
It should be noted that the main portion of the first conductive line 22 and the main portion of the second conductive line 32 may be both located in a common conductive layer, or one of them may be located in the common conductive layer and disposed in the same layer as the common electrode located in the display area.
In another embodiment of the present application, at least a portion of the first conductive line 22 is located on a side of the first metal layer away from the second metal layer, a first insulating layer 24 is disposed between the first metal layer and the second metal layer, a second insulating layer 25 is disposed between a portion of the first conductive line 22 and the first metal layer, first bridging holes are formed in the first insulating layer 24 and the second insulating layer 25, and a portion of the first conductive line 22 is filled in the first bridging holes.
In this embodiment, at least part of the first conductive line 22 is located on the side of the first metal layer and the second metal layer close to the first substrate 1, i.e. the main body portion of the first conductive line 22 is located at the innermost side of the array substrate 7 compared to the first metal layer and the second metal layer. In a specific embodiment, the main portion of the first conductive line 22, the first metal layer and the second metal layer are parallel. First bridging holes are formed between the main body of the first conductive wire 22 and the first metal layer, and between the main body of the first conductive wire 22 and the second metal layer, and the bridging portions of the first conductive wire 22 are respectively filled in the at least two first bridging holes, so that the first conductive wire 22 is electrically connected with the first metal layer and the second metal layer respectively. Thereby realizing the exchange and conduction between the first metal layer and the second metal layer at the same time, and forming a complete signal path. In the above embodiment, only the first conductive wire 22 is described as including one main body portion, if the first conductive wire 22 includes two or more main body portions, the two or more main body portions are located in different layers and parallel to each other, more first bridging holes are formed between the different main body portions, the bridging portions of the first conductive wire 22 are filled in the newly formed first bridging holes, and the plurality of main body portions cooperate to realize the electrical connection between the first conductive wire 22 and the first metal layer and the second metal layer, respectively.
In yet another embodiment of the present application, at least a portion of the first conductive line 22 is located between the second metal layer and the first metal layer, a first insulating layer 24 is disposed between the first metal layer and a portion of the first conductive line 22, a second insulating layer 25 is disposed between a portion of the first conductive line 22 and the second metal layer, first bridging holes are formed in each of the first insulating layer 24 and the second insulating layer 25, and a portion of the first conductive line 22 is filled in the first bridging holes.
In the present embodiment, at least part of the first conductive line 22 is located between the first metal layer and the second metal layer, that is, the main body portion of the first conductive line 22 is located between the first metal layer and the second metal layer. In a specific embodiment, the main portion of the first conductive line 22, the first metal layer and the second metal layer are parallel. First bridging holes are formed between the main body of the first conductive wire 22 and the first metal layer, and between the main body of the first conductive wire 22 and the second metal layer, and the bridging portions of the first conductive wire 22 are respectively filled in the at least two first bridging holes, so that the first conductive wire 22 is electrically connected with the first metal layer and the second metal layer respectively. Thereby realizing the exchange and conduction between the first metal layer and the second metal layer at the same time, and forming a complete signal path. In the above embodiment, only the first conductive wire 22 is described as including one main body portion, if the first conductive wire 22 includes two or more main body portions, the two or more main body portions are located in different layers and parallel to each other, more first bridging holes are formed between the different main body portions, the bridging portions of the first conductive wire 22 are filled in the newly formed first bridging holes, and the plurality of main body portions cooperate to realize the electrical connection between the first conductive wire 22 and the first metal layer and the second metal layer, respectively.
In some embodiments of the application, the material in the first metal layer comprises titanium, molybdenum, niobium, copper, or aluminum and the material in the second metal layer comprises titanium, molybdenum, niobium, copper, or aluminum.
The material has excellent ductility and conductivity, and the first metal layer and the second metal layer are patterned to form various wires, so that the manufacturing process profile and the manufacturing cost are low, and the signal transmission speed of the various wires is high.
Based on the same inventive concept, in a second aspect, an embodiment of the present application further provides a display device, including: the color film substrate 8 and the array substrate 7 in the above embodiment are oppositely arranged, and the color film substrate 8 and the array substrate 7 are connected through the frame glue 9.
In some embodiments of the present application, the signal terminals 41 are bonded with Chip On Film (COF) terminals. The flip chip film is a die-to-die packaging technique for attaching an integrated circuit to a flexible circuit board, and the chip is bonded to a flexible substrate circuit using a flexible additional circuit board as a carrier for the packaged chip. The COF not only has the function of connecting the panel, but also can bear active and passive components, so that the product is lighter and thinner.
In other embodiments of the present application, signal terminals 41 are tied to chip terminals. The signal terminals are connected to circuitry within the chip prior to packaging.
Based on the same inventive concept, in a third aspect, the embodiment of the present application further provides a display motherboard, as shown in fig. 7, and fig. 7 is a schematic structural diagram of the display motherboard in an embodiment of the present application. A display motherboard, comprising:
a second substrate 6, including at least two display areas, wherein a peripheral area between the two display areas is provided with a breaking line 11, a first sub-peripheral area is provided between the breaking line 11 and at least one of the two display areas, the breaking line 11 is provided with a second sub-peripheral area away from the first sub-peripheral area, and the first sub-peripheral area is provided with a binding area;
the signal terminal 41 is positioned in the binding area of the second substrate 6 and is connected with the data line 5 in the corresponding display area;
a first test electrode 21 located in the first sub-peripheral region and connected to the signal terminal 41 via a terminal lead 42 and a first conductive line 22; and
the second test electrode 31 is located in the second sub-peripheral area and is connected to the first test electrode 21 through the second conductive line 32, a part of the second conductive line 32 is located in the first sub-peripheral area and is connected to the first test electrode 21, and another part of the second conductive line 32 is located in the second sub-peripheral area and is connected to the second test electrode 31. The second conductive line 32 spans the split line 11.
In this embodiment, the first test electrode 21 is located in the bonding region, the second test electrode 31 is located in the test region, and the at least one breaking line 11 is located between the bonding region and the test region. After the array signal lighting test is completed, the cutter wheel cuts the display mother board along the breaking line 11 to form a plurality of array substrates 7. Since the second test electrode 31 is not required for the subsequent box forming signal lighting test, the split line 11 is generally staggered with the signal path of the array signal lighting test, but does not interfere with the signal path of the box forming signal lighting test, that is, the second conductive line 32 in the signal path of the array signal lighting test is staggered with at least one split line 11.
Before the breaking process, at least the signal path of the array signal lighting test and the signal path of the box signal lighting test are reserved in the display mother board. The signal path of the array signal lighting test includes: the second test electrode 31 receives the array test signal, and the output end of the second test electrode 31 sequentially passes through the second signal line 33, the second conductive line 32 and the input end of the first test electrode 21 to be transferred to the first test electrode 21, and then the output end of the first test electrode 21 sequentially passes through the first signal line 23, the first conductive line 22 and the terminal lead 42 to be transferred to the signal terminal 41. The signal terminal 41 is transmitted to the data line 5 to light up, thereby checking the defective panel.
In some embodiments of the present application, the display mother board further includes a second signal line 33, and the second signal line 33 is connected to the second test electrode 31 and the second conductive line 32, respectively.
In some embodiments of the present application, the display motherboard includes a first metal layer and a second metal layer located on a side of the first metal layer remote from the second substrate 6, at least a portion of the first metal layer forming the terminal lead 42, at least a portion of the second metal layer forming the second signal line 33, the second signal line 33 being disposed in the same layer as the first signal line 23.
In the present embodiment, the second signal line 33 and the terminal lead 42 are respectively located at different layers, so that the second signal line 33 and the terminal lead 42 are prevented from being staggered in the same layer or the length of the second signal line 33 or the terminal lead 42 is prolonged to avoid the staggering, which results in more occupied wiring space and more wasted manufacturing cost.
In one embodiment, the terminal leads 42 are located in a first metal layer near the second substrate 6 and the second signal lines 33 are located in a second metal layer remote from the second substrate 6.
In another embodiment, the terminal leads 42 are located in a second metal layer remote from the second substrate 6 and the second signal lines 33 are located in a first metal layer close to the second substrate 6.
In yet another embodiment, the second signal line 33 is arranged in the same layer as the first signal line 23. In the process of preparing the metal layer, the first signal line 23 and the second signal line 33 can be simultaneously formed in one patterning process, thereby saving the process and time cost.
In still another embodiment, the second signal line 33 is provided in a different layer from the first signal line 23. The positions of the second signal line 33 and the first signal line 23 are free, so that the display device can be adapted to more different types of display devices, and the applicability is wider.
In some embodiments of the present application, at least a portion of the second conductive line 32 is located on a side of the second metal layer away from the second substrate 6, a third insulating layer 34 is disposed between a portion of the second conductive line 32 and the second metal layer, a second bridge hole is formed in the third insulating layer 34, and a portion of the second conductive line 32 is filled in the second bridge hole.
In the present embodiment, at least part of the second conductive line 32 is located on the side of the second test electrode 31 and the second metal layer away from the second substrate 6, i.e. the main body portion of the second conductive line 32 is located at the outermost side of the array substrate 7 compared to the second test electrode 31 and the second metal layer. In a specific embodiment, the main body of the first conductive line 22, the second test electrode 31 and the second metal layer are parallel to each other. First bridging holes are respectively formed between the main body of the first conductive wire 22 and the second test electrode 31 and between the main body of the first conductive wire 22 and the second metal layer, and the bridging parts of the first conductive wire 22 are respectively filled in the at least two first bridging holes, so that the first conductive wire 22 is respectively electrically connected with the second test electrode 31 and the second metal layer. Thereby simultaneously realizing the exchange and conduction between the second test electrode 31 and the second metal layer and forming a complete signal path. In the above embodiment, only the first conductive wire 22 is described as including one main body portion, if the first conductive wire 22 includes two or more main body portions, the two or more main body portions are located in different layers and parallel to each other, more first bridging holes are formed between the different main body portions, the bridging portions of the first conductive wire 22 are filled in the newly formed first bridging holes, and the plurality of main body portions cooperate to realize the electrical connection between the first conductive wire 22 and the second test electrode 31 and the second metal layer, respectively.
By applying the embodiment of the application, at least the following beneficial effects can be realized: a test path is formed by providing a second conductive line 32 to communicate the first test electrode 21 and the second test electrode 31 such that the second conductive line 32 crosses the breaking line 11 instead of a metal wire. Compared with the prior art, the static electricity generated by friction between the cutting knife wheel and the metal wire in the breaking process is avoided, so that the accumulated charges on the metal wire are reduced, and the probability of static electricity discharge generated by the metal wire is reduced. And further, the conduction of the signal path is ensured, the accuracy and the reliability of the lighting test are improved, the product yield of the display device is improved, and the production cost is reduced.
In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is only a partial embodiment of the present application, and it should be noted that it will be apparent to those skilled in the art that modifications and adaptations can be made without departing from the principles of the present application, and such modifications and adaptations are intended to be comprehended within the scope of the present application.
Claims (15)
1. An array substrate, characterized by comprising:
the display device comprises a first substrate, a second substrate and a first display unit, wherein the first substrate comprises a display area and a sub-peripheral area positioned at one side of the display area, and the first sub-peripheral area comprises a binding area;
the signal terminal is positioned in the binding area and is connected with the data line in the corresponding display area;
the first test electrode is positioned in the first sub-peripheral area and is connected with the signal terminal; and
and one end of the second conductive wire is connected with the first test electrode, and the other end of the second conductive wire extends to the edge of the array substrate.
2. The array substrate of claim 1, further comprising a first signal line, a terminal lead, and a first conductive line, wherein the first signal line is connected to the first test electrode and the first conductive line, respectively, and the terminal lead is connected to the first conductive line and the signal terminal, respectively.
3. The array substrate of claim 2, wherein the material in the first conductive line comprises a transparent conductive material and the material in the second conductive line comprises a transparent conductive material.
4. The array substrate of claim 2, wherein the array substrate comprises a first metal layer and a second metal layer located on a side of the first metal layer away from the first substrate, at least a portion of the first metal layer forming a terminal lead, at least a portion of the second metal layer forming a first signal line.
5. The array substrate of claim 4, wherein at least a portion of the first conductive line is located at a side, away from the first metal layer, of the second metal layer, a first insulating layer is disposed between the first metal layer and the second metal layer, a second insulating layer is disposed between a portion of the first conductive line and the second metal layer, first bridge holes are formed in the first insulating layer and the second insulating layer, and a portion of the first conductive line is filled in the first bridge holes.
6. The array substrate of claim 4, wherein at least a portion of the first conductive line is located at a side of the first metal layer away from the second metal layer, a first insulating layer is disposed between the first metal layer and the second metal layer, a second insulating layer is disposed between a portion of the first conductive line and the first metal layer, first bridge holes are formed in the first insulating layer and the second insulating layer, and a portion of the first conductive line is filled in the first bridge holes.
7. The array substrate of claim 4, wherein at least a portion of the first conductive line is located between the second metal layer and the first metal layer, a first insulating layer is disposed between the first metal layer and a portion of the first conductive line, a second insulating layer is disposed between a portion of the first conductive line and the second metal layer, first bridge holes are formed in the first insulating layer and the second insulating layer, and a portion of the first conductive line is filled in the first bridge holes.
8. The array substrate of claim 4, wherein the first metal layer comprises at least one of titanium, molybdenum, niobium, copper, and aluminum, and the second metal layer comprises at least one of titanium, molybdenum, niobium, copper, and aluminum.
9. The array substrate of claim 1, wherein at least a portion of the second conductive line is located on a side of the first test electrode remote from the first substrate.
10. A display device comprising oppositely disposed color film substrates and an array substrate according to any one of claims 1 to 9.
11. The display device of claim 10, wherein the signal terminals are tied to chip terminals; or the signal terminal is bound with the flip-chip film terminal.
12. A display mother panel, comprising:
a second substrate including at least two display areas, and a peripheral area between the two display areas having a dividing line: a first sub-peripheral area is arranged between the breaking line and at least one of the two display areas, the breaking line is far away from the first sub-peripheral area and is provided with a second sub-peripheral area, and the first sub-peripheral area is provided with a binding area;
the signal terminal is positioned in the binding area and is connected with the data line in the corresponding display area;
the first test electrode is positioned in the first sub-peripheral area and is connected with the signal terminal; and
the second testing electrode is positioned in the second sub-peripheral area and connected with the first testing electrode through a second conductive wire, one part of the second conductive wire is positioned in the first sub-peripheral area and connected with the first testing electrode, and the other part of the second conductive wire is positioned in the second sub-peripheral area and connected with the second testing electrode.
13. The display motherboard of claim 12, further comprising a second signal line connected to the second test electrode and the second conductive line, respectively.
14. The display motherboard of claim 13, comprising a first metal layer and a second metal layer on a side of the first metal layer remote from the second substrate, at least a portion of the first metal layer forming a terminal lead, at least a portion of the second metal layer forming a second signal line.
15. The display motherboard of claim 13, wherein at least a portion of the second conductive line is located on a side of the second metal layer away from the second substrate, a third insulating layer is disposed between a portion of the second conductive line and the second metal layer, a second bridge hole is formed in the third insulating layer, and a portion of the second conductive line is filled in the second bridge hole.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210475499.6A CN117008382A (en) | 2022-04-29 | 2022-04-29 | Array substrate, display device and display mother board |
| PCT/CN2023/090933 WO2023208061A1 (en) | 2022-04-29 | 2023-04-26 | Array substrate, display device, and display motherboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210475499.6A CN117008382A (en) | 2022-04-29 | 2022-04-29 | Array substrate, display device and display mother board |
Publications (1)
| Publication Number | Publication Date |
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| CN117008382A true CN117008382A (en) | 2023-11-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210475499.6A Pending CN117008382A (en) | 2022-04-29 | 2022-04-29 | Array substrate, display device and display mother board |
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| Country | Link |
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| CN (1) | CN117008382A (en) |
| WO (1) | WO2023208061A1 (en) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100831280B1 (en) * | 2001-12-26 | 2008-05-22 | 엘지디스플레이 주식회사 | Liquid Crystal Display Device |
| KR20050108886A (en) * | 2004-05-14 | 2005-11-17 | 삼성전자주식회사 | Mother board having array substrate for display panel |
| US9076362B2 (en) * | 2006-09-22 | 2015-07-07 | Samsung Display Co., Ltd. | Display substrate and method of manufacturing a motherboard for the same |
| KR20090126052A (en) * | 2008-06-03 | 2009-12-08 | 삼성전자주식회사 | Thin film transistor substrate and display device having the same |
| KR102381850B1 (en) * | 2015-07-30 | 2022-04-01 | 엘지디스플레이 주식회사 | Display device |
| CN107290907B (en) * | 2017-06-20 | 2020-07-31 | 武汉华星光电技术有限公司 | Panel box-forming structure |
| CN109801909A (en) * | 2018-06-12 | 2019-05-24 | 京东方科技集团股份有限公司 | Array substrate motherboard and its manufacturing method, array substrate, display device |
| KR20200043580A (en) * | 2018-10-17 | 2020-04-28 | 삼성디스플레이 주식회사 | Display device |
-
2022
- 2022-04-29 CN CN202210475499.6A patent/CN117008382A/en active Pending
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- 2023-04-26 WO PCT/CN2023/090933 patent/WO2023208061A1/en unknown
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| WO2023208061A1 (en) | 2023-11-02 |
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