CN117007620A - Chip internal structure detection method - Google Patents
Chip internal structure detection method Download PDFInfo
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- CN117007620A CN117007620A CN202311266359.9A CN202311266359A CN117007620A CN 117007620 A CN117007620 A CN 117007620A CN 202311266359 A CN202311266359 A CN 202311266359A CN 117007620 A CN117007620 A CN 117007620A
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/02—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material
- G01N23/04—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material and forming images of the material
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/20—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials
- G01N23/20008—Constructional details of analysers, e.g. characterised by X-ray source, detector or optical system; Accessories therefor; Preparing specimens therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/20—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials
- G01N23/20058—Measuring diffraction of electrons, e.g. low energy electron diffraction [LEED] method or reflection high energy electron diffraction [RHEED] method
Abstract
The application provides a chip internal structure detection method, which is characterized in that wafer blocks of a plurality of structures to be observed are cut in a number of times, a structure sub-region to be observed corresponding to one structure to be observed is reserved on an idle grid upright post in each cutting, and the structure sub-region to be observed is thinned to obtain a transmission electron microscope sample corresponding to the structure to be observed, so that a transmission electron microscope sample is correspondingly welded on each grid upright post, the grids are transferred into a transmission electron microscope after sample preparation is finished, the corresponding samples on the upright posts are observed in sequence, whether the internal structure of the chip is abnormal or not is determined through the observation result, the problem that one transmission electron microscope sample is taken out for observation every time when a plurality of adjacent structures are manufactured in the prior art is solved, the problem that only one sample is prepared when other structures are contained is solved, the frequency of multiple times of sample replacement between the sample and the transmission electron microscope is reduced, and the technical effect of improving the detection efficiency is achieved.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a method for detecting an internal structure of a chip.
Background
In the prior art, if a plurality of structures with relatively close intervals exist on a chip in a wafer, if a TEM (Transmission Electron Microscope ) sample of each structure in the chip is prepared, other structures of the chip around the chip structure are damaged due to a pit digging process in the preparation process, and each chip structure cannot be prepared into a TEM chip, so that the production condition of the whole wafer cannot be comprehensively monitored, or corresponding failure points cannot be comprehensively observed, and the production quality of the wafer is further affected, or corresponding complaints are generated.
Disclosure of Invention
Therefore, an object of the present application is to provide a method for detecting an internal structure of a chip, in which wafer blocks of a plurality of structures to be observed are cut in a number of times, each time the wafer blocks are cut, a sub-region of the structure to be observed corresponding to the structure to be observed is reserved on an idle grid column, and the sub-region of the structure to be observed is thinned, so as to obtain a transmission electron microscope sample corresponding to the structure to be observed, so that each transmission electron microscope sample is welded to a transmission electron microscope observation region correspondingly on each grid column, and then each transmission electron microscope sample can be moved together to the transmission electron microscope observation region, so that each transmission electron microscope sample can be observed respectively to determine whether the internal structure of the chip is abnormal, thereby not only solving the problem that in the prior art, each time one transmission electron microscope sample is manufactured, the observation is taken out, but also solving the problem that only one sample can be prepared due to the sacrifice of other structures when the structure is included, further reducing the frequency of multiple sample replacement between the sample and the transmission electron microscope, and achieving the technical effect of improving the detection efficiency of detecting the internal structure of the chip.
The application mainly comprises the following aspects:
in a first aspect, an embodiment of the present application provides a method for detecting an internal structure of a chip, where the method includes: digging a wafer block from a wafer sample, wherein the wafer block comprises a plurality of structures to be observed, which are arranged along a first preset direction, on the wafer sample, and the structures to be observed are correspondingly arranged in a chip; the following cutting process is performed for the workpiece to be cut: welding a target side surface of a piece to be cut on an idle grid upright post on a sample table, wherein the piece to be cut is a wafer block during primary cutting, the target side surface is a side surface, close to first side surfaces of a plurality of structures to be observed, in the piece to be cut, of the first side surfaces, the first side surfaces are composed of lengths and heights of the structures to be observed, the piece to be cut is cut, so that a divided wafer is cut from the grid upright post, a structure subarea to be observed is reserved on the grid upright post, the structure subarea to be observed comprises a corresponding target structure to be observed, the divided wafer comprises other structures to be observed except the target structure to be observed in the piece to be cut, thinning is performed on thinning side surfaces, close to the target structure subarea to be observed, of the structures to be observed in a second preset direction, the second preset direction is a direction perpendicular to the first preset direction, and the thinning side surfaces are composed of a second side surface, close to the second side surfaces, close to the target structure to be observed, of the structures to be observed, of the second side surfaces and the heights of the structures to be observed; taking the divided wafer as a piece to be cut, and repeatedly executing the cutting treatment until the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid upright; and detecting the internal structure of the chip of the transmission electron microscope sample on each grid upright post.
Optionally, cutting the piece to be cut comprises: taking a structure to be observed on any side of the piece to be cut as a target structure to be observed; cutting the target structure to be observed and the corresponding adjacent structure to be observed in a second preset direction according to marking lines in a spacing area between the target structure to be observed and the corresponding adjacent structure to be observed, wherein the marking lines are used for marking the positions of the structures to be observed; and cutting welding positions except for the projection of the first side surface of the target structure to be observed in the welding positions of the target side surface and the corresponding grid upright columns along a first preset direction.
Optionally, the marking line is already existing between two adjacent structures to be observed before the wafer block is excavated, and the marking line comprises a parallel marking line, wherein the parallel marking line is any line which is positioned in a spacing area between the adjacent structures to be observed and is parallel to the width of the structures to be observed; alternatively, the marker lines include distance marker lines for marking the separation distance between adjacent structures to be observed, the distance marker lines being parallel to the length of the structures to be observed.
Optionally, the marker lines comprise parallel marker lines, and the cutting is performed between the target structure to be observed and the corresponding adjacent structure to be observed in the following manner: cutting a first length along the parallel marking lines to divide the part between the sub-region of the structure to be observed and the divided wafer, wherein the ratio of the first length to the width of the piece to be cut is a preset ratio; and cutting a second length along the parallel mark lines so as to divide the region of the structure to be observed and the divided wafer completely.
Optionally, the marker line includes a distance marker line, and the cutting is performed between the target structure to be observed and the corresponding adjacent structure to be observed in the following manner: performing first cutting on the interval region between the target structure to be observed and the corresponding adjacent structure to be observed according to the distance mark line so as to divide the part between the sub-region of the structure to be observed obtained by cutting and the divided wafer; and cutting the interval area between the target structure to be observed and the corresponding adjacent structure to be observed for the second time according to the distance mark line so as to lead the sub-area of the structure to be observed and the division wafer to be completely divided.
Optionally, the wafer block is excavated from the wafer sample by: determining a target area of a wafer sample, wherein the target area comprises a plurality of structures to be observed which are arranged on a chip along a first preset direction, and projections of the structures to be observed along the first preset direction in a second preset direction are overlapped; determining mark lines of a spacing region between adjacent structures to be observed in the target region; after etching the marking line, depositing a protective layer on the surface of the target area, and exposing the etched marking line part outside the protective layer; and extracting the target area after the deposition of the protective layer from the wafer sample to obtain a wafer block.
Optionally, the marker line is determined by: and determining mark lines between the adjacent structures to be observed according to interval line segments between the adjacent structures to be observed, wherein the interval line segments are used for representing the distance between the adjacent structures to be observed in the direction of the length of the structures to be observed.
Optionally, the method further comprises: and when the number of other structures to be observed corresponding to the divided wafer is one, welding one side surface, close to the first side surface, of the corresponding structure to be observed in the divided wafer on one idle grid stand column of the sample stage, thinning one side surface, close to the second side surface, of the target structure to be observed in the divided wafer in a second preset direction to obtain a transmission electron microscope sample corresponding to the divided wafer, so that the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid stand column.
In a second aspect, embodiments of the present application further provide a transmission electron microscope sample, where the transmission electron microscope sample includes a plurality of transmission electron microscope samples, each of the transmission electron microscope samples is located on one of the grid posts, and each of the transmission electron microscope samples corresponds to a structure to be observed.
In a third aspect, an embodiment of the present application further provides a method for preparing a transmission electron microscope sample, where the method includes: digging a wafer block from a wafer sample, wherein the wafer block comprises a plurality of structures to be observed, which are arranged along a first preset direction, on the wafer sample, and the structures to be observed correspond to a chip; the following cutting process is performed for the workpiece to be cut: welding the target side surface of a piece to be cut on an idle grid upright post of a sample stage, wherein the piece to be cut is a wafer block during primary cutting, the target side surface is one side surface of the piece to be cut, which is close to the first side surfaces of a plurality of structures to be observed, the first side surface consists of the length and the height of the structures to be observed, cutting the piece to be cut so as to cut a split wafer from the grid upright post, reserving a structure subarea to be observed on the grid upright post, the structure subarea to be observed comprises a corresponding target structure to be observed, the split wafer comprises other structures to be observed except the target structure to be observed in the piece to be cut, thinning the thinned side surface of the sub-region of the structure to be observed in a second preset direction to obtain a transmission electron microscope sample corresponding to the target structure to be observed, wherein the second preset direction is a direction perpendicular to the first preset direction, the thinned side surface is a side surface, close to the second side surface of the target structure to be observed, of the sub-region of the structure to be observed, the second side surface consists of the height and the width of the structure to be observed, the divided wafer is used as a piece to be cut, the cutting processing is repeatedly performed until the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid upright, and the transmission electron microscope sample positioned on each grid upright is used as the transmission electron microscope sample.
The embodiment of the application provides a method for detecting the internal structure of a chip, which comprises the following steps: digging a wafer block from a wafer sample, wherein the wafer block comprises a plurality of structures to be observed, which are arranged along a first preset direction, on the wafer sample, and the structures to be observed correspond to a chip; the following cutting process is performed for the workpiece to be cut: welding a target side surface of a piece to be cut on an idle grid upright post of a sample stage, wherein the piece to be cut is a wafer block during primary cutting, the target side surface is a side surface, close to first side surfaces of a plurality of structures to be observed, of the piece to be cut, the first side surfaces are composed of lengths and heights of the structures to be observed, the piece to be cut is cut so as to cut a split wafer from the grid upright post, a structure subarea to be observed is reserved on the grid upright post, the structure subarea to be observed comprises a corresponding target structure to be observed, the split wafer comprises other structures to be observed except the target structure to be observed in the piece to be cut, thinning is performed on thinned side surfaces of the structure subarea to be observed in a second preset direction, the second preset direction is a direction perpendicular to the first preset direction, the thinned side surfaces are a side surface, close to the second side surfaces of the structure to be observed, of the target structure to be observed, of the second side surfaces to be observed, and the second side surfaces are composed of the structures to be observed and the heights of the structures to be observed; taking the divided wafer as a piece to be cut, and repeatedly executing the cutting treatment until the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid upright; and detecting the internal structure of the chip of the transmission electron microscope sample on each grid upright post. According to the application, the wafer blocks of the structures to be observed are cut for multiple times, one structural subarea to be observed corresponding to the structures to be observed is reserved on the idle grid upright posts each time, and the structural subarea to be observed is thinned to obtain the transmission electron microscope samples corresponding to the structures to be observed, so that each grid upright post is correspondingly welded with one transmission electron microscope sample, and then each transmission electron microscope sample can be moved into the observation area of the transmission electron microscope together, so that each transmission electron microscope sample is observed by the transmission electron microscope respectively to determine whether the internal structure of the chip is abnormal or not, the problem that only one sample can be prepared because of sacrificing other structures when the adjacent structures are produced in the prior art is solved, the frequency of multiple sample changing between the sample and the transmission electron microscope is reduced, and the technical effect of improving the detection efficiency of the internal structure of the detection chip is achieved.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a flowchart of a method for detecting an internal structure of a chip according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a wafer block according to an embodiment of the application.
Fig. 3 shows a schematic diagram of a structure to be observed according to an embodiment of the present application.
Fig. 4 shows a top view of a wafer block according to an embodiment of the application.
Fig. 5 shows a top view of a second wafer block according to an embodiment of the application.
Fig. 6 shows a schematic diagram of cutting a workpiece according to an embodiment of the present application.
Fig. 7 shows a top view of a workpiece to be cut according to an embodiment of the present application.
Fig. 8 shows a schematic diagram of a transmission electron microscope sample provided by an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for the purpose of illustration and description only and are not intended to limit the scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this disclosure, illustrates operations implemented according to some embodiments of the present application. It should be appreciated that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to or removed from the flow diagrams by those skilled in the art under the direction of the present disclosure.
In addition, the described embodiments are only some, but not all, embodiments of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art based on embodiments of the application without making any inventive effort, fall within the scope of the application.
In the prior art, when preparing the TEM samples corresponding to each structure to be observed, it is necessary to sequentially prepare the corresponding TEM samples for each structure to be observed, and after each preparation of the TEM samples, move the TEM samples to a transmission electron microscope to observe whether the structure of the sample has a bad area, and when the observed samples are more, frequent sample replacement is required in the transmission electron microscope, so that the efficiency of observing the TEM samples is affected.
Based on this, the embodiment of the application provides a method for detecting an internal structure of a chip, which can simultaneously reserve a plurality of similar target structures, and through carrying out a fractional cutting on a plurality of wafer blocks of the structures to be observed, and the cutting process can not damage or sacrifice other structures, each cutting reserves a structure sub-area to be observed corresponding to the structure to be observed on an idle grid upright, and thins the structure sub-area to be observed to obtain a transmission electron microscope sample corresponding to the structure to be observed, so that each transmission electron microscope sample is correspondingly welded on each grid upright, and then each transmission electron microscope sample can be moved together into an observation area of a transmission electron microscope, so that each transmission electron microscope sample is respectively observed to determine whether the internal structure of the chip is abnormal, thereby solving the technical problems that in the prior art, each transmission electron microscope sample is manufactured for observation, and then multiple movements between a sample stage and the transmission electron microscope are required, and achieving the technical effects of improving the detection efficiency of the internal structure of the chip are achieved, and are as follows:
Referring to fig. 1, fig. 1 is a flowchart of a method for detecting an internal structure of a chip according to an embodiment of the application. As shown in fig. 1, the method for detecting the internal structure of a chip provided by the embodiment of the application comprises the following steps:
s101: a wafer block is excavated from the wafer sample.
The wafer block comprises a plurality of structures to be observed, which are arranged along a first preset direction, on a wafer sample, wherein the structures to be observed are correspondingly arranged in a chip.
Referring to fig. 2, fig. 2 is a schematic diagram of a wafer block according to an embodiment of the application. As shown in fig. 2, the wafer block 10 is approximated as a cube, and each structure 101 to be observed is approximated as a cube belonging to the wafer block 10. That is, the wafer block 10 includes a plurality of structures 101 to be observed.
The multiple structures to be observed can be the same structure or different structures, and only the multiple structures to be observed are required to be arranged along the first preset direction x. Length a of wafer block 1 The straight line is taken as a first preset direction (x-axis direction in fig. 2) to ensure the width b of the wafer block 1 The direction of the straight line is taken as the y-axis direction, and the height c of the wafer block is determined 1 The direction of the straight line is taken as the z-axis direction.
Referring to fig. 3, fig. 3 is a schematic diagram of a structure to be observed according to an embodiment of the present application. As shown in fig. 3, the length a of the structure to be observed 2 The direction of the straight line is the same as the direction of the straight line of the length of the wafer block, and the width b of the structure to be observed 2 The direction of the straight line is the same as the direction of the straight line of the width of the wafer block, and the height c of the structure to be observed 2 The direction of the straight line is the same as the direction of the straight line of the height of the wafer block, and furthermore, the first preset direction is also the direction of the straight line of the length of the structure to be observed.
Referring to fig. 4 and fig. 5, fig. 4 is a top view of a first wafer block according to an embodiment of the present application, and fig. 5 is a top view of a second wafer block according to an embodiment of the present application. As shown in fig. 4, the projection surfaces of the to-be-observed mechanisms are obtained by projecting the plurality of structures to be observed onto the projection side surfaces of the wafer block in the first preset direction, the projection surfaces corresponding to the to-be-observed mechanisms are all overlapped, and the bold line in fig. 4 represents all overlapped parts of the projection surfaces corresponding to the to-be-observed mechanisms. As shown in fig. 5, a plurality of structures to be observed are projected onto the projection side surface of the wafer block in the first preset direction, the projection surfaces corresponding to the mechanisms to be observed are partially overlapped, and the bold line in fig. 5 indicates the partially overlapped portion of the projection surfaces corresponding to the mechanisms to be observed.
The projection side of the wafer block is defined by the width b of the wafer block 1 And height c 1 One side of the composition. Or, the projection side of the wafer block is a side perpendicular to the first preset direction.
The following cutting process is performed for the workpiece to be cut: the piece to be cut is a wafer block during primary cutting.
S102: the target side of the piece to be cut is welded to an empty grid column of the sample stage.
As shown in fig. 2, the target side is a side of the workpiece to be cut, which is close to a first side 1011 of the plurality of structures 101 to be observed, the first side being defined by a length a of the structures to be observed 2 And height c 2 Composition is prepared. During the primary dicing, the target side is defined by the length a of the wafer block 1 And height c 1 Composition is prepared.
That is, the first sides of the plurality of structures to be observed are projected vertically toward the target side of the workpiece to be cut, and the projection surface of the first side of each structure to be observed is included on the target side, and there is no overlap between the projection surfaces of the first sides of the respective structures to be observed on the target side.
Returning to fig. 1, S103: and cutting the piece to be cut to cut the split wafer from the grid upright so as to reserve a structural subarea to be observed on the grid upright.
Referring to fig. 6, fig. 6 is a schematic diagram of cutting a workpiece according to an embodiment of the application. After the workpiece to be cut is cut, the singulated wafer 20 is cut from the grid posts, and a structural sub-area 30 to be observed is left on the grid posts, as shown in fig. 6. The to-be-observed structure subarea comprises a corresponding target to-be-observed structure, and the divided wafer comprises other to-be-observed structures except the target to-be-observed structure in the to-be-cut piece.
The cutting of the piece to be cut comprises the following steps: taking a structure to be observed on any side of the piece to be cut as a target structure to be observed; cutting the target structure to be observed and the corresponding adjacent structure to be observed in a second preset direction according to marking lines in a spacing area between the target structure to be observed and the corresponding adjacent structure to be observed, wherein the marking lines are used for marking the positions of the structures to be observed; and cutting welding positions except for the projection of the first side surface of the target structure to be observed in the welding positions of the target side surface and the corresponding grid upright columns along a first preset direction.
Generally, the target structure to be observed is a structure to be observed on the workpiece to be cut at any end in the first preset direction. That is, the target structure to be observed has only one adjacent mechanism to be observed on the piece to be cut.
The marking line is arranged between two adjacent structures to be observed before the wafer block is excavated, and comprises parallel marking lines which are any line which is positioned in a spacing area between the adjacent structures to be observed and is parallel to the width of the structures to be observed; alternatively, the marker lines include distance marker lines for marking the separation distance between adjacent structures to be observed, the distance marker lines being parallel to the length of the structures to be observed.
As shown in fig. 6, the parallel mark lines L are located on the spacing regions between the adjacent structures to be observed in the wafer block, and the parallel mark lines L are parallel to the width of the structures to be observed, thereby separating the adjacent structures to be observed.
As shown in fig. 6, the distance mark line D is parallel to the length of the structure to be observed on the interval area between the adjacent structures to be observed in the wafer block, and is used for indicating the distance between the adjacent structures to be observed, and further, the distance mark line D may also separate the adjacent structures to be observed.
And then, cutting the welding positions except for the projection of the first side surface of the target structure to be observed in the welding positions of the target side surface and the corresponding grid upright posts along the first preset direction so as to separate the divided wafer from the grid upright posts, and welding the divided wafer obtained this time on other idle grid upright posts when the next cutting is carried out.
Specifically, the cutting may be performed along the straight line where the parallel marking line L is located in the second preset direction, and then the cutting may be performed on the welding position except the projection of the first side of the target structure to be observed in the welding position of the target side and the corresponding grid column, so as to obtain the sub-region of the structure to be observed that remains on the grid column, and the split wafer that is separated from the grid column. Or firstly cutting the welding positions except for the projection of the first side surface of the target structure to be observed in the welding positions of the target side surface and the corresponding grid upright posts, and then cutting along the straight line where the parallel marking line L is positioned in a second preset direction to obtain the structural subarea to be observed which remains on the grid upright posts and the split wafer which is separated from the grid upright posts.
That is, the welding position of the target side surface with respect to the welding position of the corresponding grid column other than the first side surface projection of the target structure to be observed can be understood as: and dividing the welding position between the wafer and the grid upright post.
The marking lines comprise parallel marking lines, and the target structure to be observed and the corresponding adjacent structure to be observed are cut in the following mode: cutting a first length along the parallel marking lines to divide the part between the sub-region of the structure to be observed and the divided wafer, wherein the ratio of the first length to the width of the piece to be cut is a preset ratio; and cutting a second length along the parallel mark lines so as to divide the region of the structure to be observed and the divided wafer completely.
Referring to fig. 7, fig. 7 is a top view illustrating a workpiece to be cut according to an embodiment of the application. As shown in fig. 7, the first length L is cut along the parallel marking lines L 1 The structure subarea to be observed and the dividing wafer are partially divided, and then, the structure subarea to be observed and the dividing wafer are partially connected together. The first length l 1 The width ratio of the workpiece to be cut is a preset ratio, and the preset ratio is [1/3,1/2 ]]Between them. Because the space during the segmentation is smaller, a process of redeposition after etching exists, the first length is cut firstly, so that a part of gaps exist between the structural subarea to be observed and the segmented wafer, deposition generated by the cutting is convenient to adsorb, and then the second length is cut along the parallel mark line, so that the structural subarea to be observed and the segmented wafer are completely segmented.
The second length may be l 21 I.e. the difference between the width and the first length of the piece to be cut; the second length may also be l 22 I.e. the width of the piece to be cut.
The marking lines comprise distance marking lines, and the target structure to be observed and the corresponding adjacent structure to be observed are cut in the following mode: performing first cutting on the interval region between the target structure to be observed and the corresponding adjacent structure to be observed according to the distance mark line so as to divide the part between the sub-region of the structure to be observed obtained by cutting and the divided wafer; and cutting the interval area between the target structure to be observed and the corresponding adjacent structure to be observed for the second time according to the distance mark line so as to lead the sub-area of the structure to be observed and the division wafer to be completely divided.
As shown in fig. 7, the first dicing is performed on the spacing region between the target structure to be observed and the corresponding adjacent structure to be observed according to the distance mark line D, so as to divide the portion between the sub-region of the structure to be observed and the divided wafer, and the dicing length l of the first dicing is performed 3 Parallel to the width of the piece to be cut, a cutting length l of the first cut 3 The width ratio of the workpiece to be cut is a preset ratio, and the preset ratio is [1/3,1/2 ]]Between them. Further, there is a portion of the connection between the sub-region of the structure to be observed and the singulated wafer after the first dicing. Because the space during the division is smaller, there is a process of redeposition after etching, so the first cutting is performed first, so that a part of gaps exist between the structural subarea to be observed and the divided wafer, the deposition generated by the cutting is convenient to be absorbed, and then according to the distance mark line D,and performing secondary cutting on the interval area between the target structure to be observed and the corresponding adjacent structure to be observed so as to enable all the sub-areas of the structure to be observed and the divided wafers to be divided, wherein the cutting length for performing secondary cutting is parallel to the width of the piece to be cut. The cutting length of the second cut may be l 31 I.e. width and l of the piece to be cut 3 Is a difference in (2); the second length may also be l 32 I.e. the width of the piece to be cut.
Preferably, the parallel marker lines may be arranged as midlines located in spaced areas between adjacent structures to be observed and parallel to the width of the structures to be observed.
As shown in fig. 7, the adjacent structures to be observed are divided into one structure to be observed and another structure to be observed, the target second side of the one structure to be observed and the target second side of the other structure to be observed are determined, and the target second side of the one structure to be observed and the target second side of the other structure to be observed are the adjacent surfaces between the one structure to be observed and the other structure to be observed, and when the mark line L is a center line which is located in a space region between the one structure to be observed and the other structure to be observed and is parallel to the width of the structure to be observed, a straight line distance d1 between the mark line and the target second side of the one structure to be observed is equal to a straight line distance d2 between the mark line and the target second side of the one structure to be observed.
A wafer block is excavated from a wafer sample by: determining a target area of a wafer sample, wherein the target area comprises a plurality of structures to be observed which are arranged on a chip along a first preset direction, and projections of the structures to be observed along the first preset direction in a second preset direction are overlapped; determining mark lines of a spacing region between adjacent structures to be observed in the target region; after etching the marking line, depositing a protective layer on the surface of the target area, and exposing the etched marking line part outside the protective layer; and extracting the target area after the deposition of the protective layer from the wafer sample to obtain a wafer block.
That is, each structure to be observed projects a projection plane of each structure to be observed, which is obtained by projecting each structure to a side surface of the wafer block perpendicular to the first preset direction, along the first preset direction, and the projection planes of each structure to be observed are overlapped.
The marker line is determined by: and determining mark lines between the adjacent structures to be observed according to interval line segments between the adjacent structures to be observed, wherein the interval line segments are used for representing the distance between the adjacent structures to be observed in the direction of the length of the structures to be observed.
The distance line segment is translated to the position where the length of the structure to be observed is located, the translated distance line segment is used as a distance mark line, and the distance of translation only needs to ensure that the distance mark line is not completely covered when the protective layer is deposited; or, in the interval region between the adjacent structures to be observed, any line which forms an included angle with the interval line segments and is parallel to the width of the structures to be observed is determined as a parallel mark line, the length of the parallel mark line is smaller than or equal to the width of the wafer block, and the parallel mark line is not completely covered after the protective layer is deposited.
Depositing a protective layer on the surface of the target area by: depositing a first protective layer on the surface of the target area through electron beams; and depositing a second protective layer on the surface of the first protective layer by an ion beam, wherein the height of the first protective layer is smaller than that of the second protective layer.
That is, a target area is determined in the wafer sample, and a plurality of structures to be observed, which are arranged along a first preset direction on one chip, are included in the target area; etching the mark line of the interval region between the adjacent structures to be observed in the target region; depositing a first protective layer on the surface of the target area by an electron beam after etching the mark line, and depositing a second protective layer on the surface of the first protective layer by an ion beam; the target area is extracted from the wafer sample to obtain a wafer block.
The wafer sample can be damaged by the ion beam when the protective layer is deposited, so that the efficiency of generating the protective layer by the electron beam is low, and then the first protective layer is deposited by the electron beam and then deposited by the ion beam, so that the height of the first protective layer in the z-axis direction of the electron beam deposition is smaller than the height of the second protective layer in the z-axis direction of the ion Shu Chenji for improving the efficiency. The first protective layer is typically about 100 nanometers in height and the second protective layer is typically about 1.9 microns in height. The material of the protective layer can be molybdenum (Pt), tungsten (W) or carbon (C) with shallow lining.
The target area is extracted from the wafer sample, the ion beam with larger beam current (generally between 9.0 nanoampere nA and 25 nanoampere) can be selected to etch and pit the target area, then the ion beam with smaller beam current (generally between 1.5 nanoampere and 2.5 nanoampere) is selected to refine the etching surface of the target area, and the conventional U-shaped cutting (U-CUT) mode is selected to CUT off, so that the wafer block is obtained. Wherein the depth of the pits exceeds 1.5-2 times the height of the required TEM sample. And finally, connecting the manipulator of the sample stage with the wafer block, and extracting the wafer block.
Selecting a sample table with a prefabricated tilting angle, inserting a manipulator, welding a piece to be cut on a grid upright post, cutting off and withdrawing the manipulator; the sample table is rotated, a certain included angle exists between the first preset direction of the piece to be cut on the grid upright post and the spraying direction of the ion beam, so that the piece to be cut is conveniently cut through the ion beam, the manipulator is welded on the piece to be cut, one corner, far away from the grid upright post, of the piece to be cut on the split wafer, the piece to be cut is cut through the ion beam, the manipulator is withdrawn after the split wafer and the structural subarea to be observed are obtained, and the split wafer is also taken away from the grid upright post by the manipulator. The ion beam current used for cutting can be set between 0.4 nanoampere and 0.8 nanoampere.
Returning to fig. 1, S104: and thinning the second side surface of the sub-region of the structure to be observed in a second preset direction to obtain a transmission electron microscope sample corresponding to the target structure to be observed.
Wherein the second preset direction is a direction perpendicular to the first preset direction, and the second side 1012 is composed of a height and a width of the structure to be observed.
The second preset direction may be a y-axis direction or a z-axis direction, and which direction to select the structure of the sample stage to thin the two opposite second sides of the sub-region of the structure to be observed, so as to obtain a transmission electron microscope sample corresponding to the target structure to be observed.
Referring to fig. 8, fig. 8 is a schematic diagram of a transmission electron microscope according to an embodiment of the application. As shown in fig. 8, the structural sub-region 30 to be observed is thinned in the second preset direction, so as to obtain a transmission electron microscope sample TEM2 corresponding to the structural sub-region 30 to be observed, and further, the transmission electron microscope sample corresponding to the structural sub-region to be observed obtained by the last cutting is TEM1 in the figure.
And the projection positions obtained by projecting the length of the structure to be observed on the length of each transmission electron microscope sample in the first preset direction can be different. That is, different positions of each structure to be observed in the first preset direction can be observed, so that the positions of defective areas of the chip can be more comprehensively known through adjacent TEM samples.
S105: and determining whether the number of other structures to be observed corresponding to the divided wafer is one.
That is, after the piece to be cut is cut each time to obtain the divided wafer and the sub-region of the structure to be observed, the number of other structures to be observed except the target structure to be observed included in the divided wafer that is cut is determined.
S106: and taking the divided wafer as a piece to be cut.
If the number of other structures to be observed corresponding to the divided wafer is not one, the divided wafer is used as a piece to be cut, and the step S102 is returned to be continuously executed, namely the cutting process is repeatedly executed until the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid stand column.
The grid columns on each grid correspond to one transmission electron microscope sample, generally, 3 to 5 grid columns are arranged on one grid, and a plurality of TEM samples are obtained finally. And when each grid column in one grid is correspondingly welded with one TEM sample and each structure to be observed in the wafer block is not correspondingly manufactured into the TEM sample, a new grid can be taken to continuously execute cutting processing.
S107: and welding one side surface, close to the first side surface of the corresponding structure to be observed, of the divided wafer on an idle grid stand column of the sample stage, and thinning one side surface, close to the second side surface of the target structure to be observed, of the divided wafer in a second preset direction to obtain a transmission electron microscope sample corresponding to the divided wafer, so that the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid stand column.
And if the number of other structures to be observed corresponding to the divided wafer is one, welding one side surface, close to the first side surface of the corresponding structure to be observed, of the divided wafer on one idle grid upright post of the sample stage, and thinning one side surface, close to the second side surface of the target structure to be observed, of the divided wafer in a second preset direction to obtain a transmission electron microscope sample corresponding to the divided wafer, so that the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid upright post.
That is, when there is only one structure to be observed in the divided wafer, one surface composed of the length and the height in the divided wafer is welded on the free grid column, and the surface composed of the width and the height in the divided wafer is thinned, so that a transmission electron microscope sample corresponding to the one structure to be observed in the divided wafer is obtained, and further, the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid column.
S108: and detecting the internal structure of the chip of the transmission electron microscope sample on each grid upright post.
Because each grid stand column is an integer, then, can remove transmission electron microscope sample on each grid stand column to transmission electron microscope department together, carry out the chip internal structure through transmission electron microscope to transmission electron microscope sample on the grid stand column one by one to confirm whether there is the bad district in each transmission electron microscope sample, and then confirm the position of structure in the chip to be observed that the bad district corresponds, thereby trace back production process, so that the analysis leads to the reason in bad district appearing.
The transmission electron microscope sample has a length of less than 100 nanometers in a first preset direction.
The embodiment of the application also provides a transmission electron microscope sample corresponding to the chip internal structure detection method provided by the embodiment, wherein the transmission electron microscope sample comprises a plurality of transmission electron microscope samples, each transmission electron microscope sample is respectively positioned on one grid upright post, and each transmission electron microscope sample corresponds to one structure to be observed.
Based on the same application conception, the embodiment of the application also provides a preparation method of a transmission electron microscope sample corresponding to the detection method of the chip internal structure provided by the embodiment, and because the principle of solving the problem by the device in the embodiment of the application is similar to that of the detection method of the chip internal structure of the embodiment of the application, the implementation of the preparation method of the transmission electron microscope sample can refer to the implementation of the detection method of the chip internal structure, and the repetition is omitted.
The preparation method of the transmission electron microscope sample comprises the following steps: digging a wafer block from a wafer sample, wherein the wafer block comprises a plurality of structures to be observed, which are arranged along a first preset direction, on the wafer sample, and the structures to be observed are correspondingly arranged in a chip; the following cutting process is performed for the workpiece to be cut: welding the target side surface of a piece to be cut on an idle grid upright post of a sample stage, wherein the piece to be cut is a wafer block during primary cutting, the target side surface is one side surface of the piece to be cut, which is close to the first side surfaces of a plurality of structures to be observed, the first side surface consists of the length and the height of the structures to be observed, cutting the piece to be cut so as to cut a split wafer from the grid upright post, reserving a structure subarea to be observed on the grid upright post, the structure subarea to be observed comprises a corresponding target structure to be observed, the split wafer comprises other structures to be observed except the target structure to be observed in the piece to be cut, thinning the thinned side surface of the sub-region of the structure to be observed in a second preset direction to obtain a transmission electron microscope sample corresponding to the target structure to be observed, wherein the second preset direction is a direction perpendicular to the first preset direction, the thinned side surface is a side surface, close to the second side surface of the target structure to be observed, of the sub-region of the structure to be observed, the second side surface consists of the height and the width of the structure to be observed, the divided wafer is used as a piece to be cut, the cutting processing is repeatedly performed until the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid upright, and the transmission electron microscope sample positioned on each grid upright is used as the transmission electron microscope sample.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again. In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily appreciate variations or alternatives within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A method for detecting an internal structure of a chip, the method comprising:
digging a wafer block from a wafer sample, wherein the wafer block comprises a plurality of structures to be observed, which are arranged along a first preset direction, on the wafer sample, and the structures to be observed are correspondingly arranged in a chip;
the following cutting process is performed for the workpiece to be cut: welding the target side surface of the workpiece to be cut on an idle grid upright post of the sample stage, wherein the workpiece to be cut is a wafer block during primary cutting, the target side surface is a side surface, close to first side surfaces of a plurality of structures to be observed, in the workpiece to be cut, the first side surfaces consist of the lengths and the heights of the structures to be observed,
cutting the piece to be cut to cut the divided wafer from the grid upright post so as to reserve a structure subarea to be observed on the grid upright post, wherein the structure subarea to be observed comprises a corresponding target structure to be observed, the divided wafer comprises other structures to be observed except the target structure to be observed in the piece to be cut,
Thinning the thinned side surface of the sub-region of the structure to be observed in a second preset direction to obtain a transmission electron microscope sample corresponding to the target structure to be observed, wherein the second preset direction is a direction perpendicular to the first preset direction, the thinned side surface is a side surface, close to a second side surface of the target structure to be observed, of the sub-region of the structure to be observed, and the second side surface consists of the height and the width of the structure to be observed;
taking the divided wafer as a piece to be cut, and repeatedly executing the cutting treatment until the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid upright;
and detecting the internal structure of the chip of the transmission electron microscope sample on each grid upright post.
2. The method according to claim 1, characterized in that the piece to be cut is cut by:
taking a structure to be observed on any side of the piece to be cut as a target structure to be observed;
cutting the target structure to be observed and the corresponding adjacent structure to be observed in a second preset direction according to marking lines in a spacing area between the target structure to be observed and the corresponding adjacent structure to be observed, wherein the marking lines are used for marking the positions of the structures to be observed;
And cutting welding positions except for the projection of the first side surface of the target structure to be observed in the welding positions of the target side surface and the corresponding grid upright columns along a first preset direction.
3. The method of claim 2, wherein the marker line is already present between two adjacent structures to be observed before the wafer block is excavated, the marker line comprising a parallel marker line, which is any one line located at a spacing region between the adjacent structures to be observed and parallel to a width of the structures to be observed;
alternatively, the marker lines include distance marker lines for marking the separation distance between adjacent structures to be observed, the distance marker lines being parallel to the length of the structures to be observed.
4. A method according to claim 3, wherein the marker lines comprise parallel marker lines, the cutting between the target structure to be observed and a corresponding adjacent structure to be observed being performed by:
cutting a first length along the parallel marking lines to divide the part between the sub-region of the structure to be observed and the divided wafer, wherein the ratio of the first length to the width of the piece to be cut is a preset ratio;
And cutting a second length along the parallel mark lines so as to divide the region of the structure to be observed and the divided wafer completely.
5. A method according to claim 3, wherein the marker lines comprise distance marker lines, the target structure to be observed and the corresponding adjacent structure to be observed being cut by:
performing first cutting on the interval region between the target structure to be observed and the corresponding adjacent structure to be observed according to the distance mark line so as to divide the part between the sub-region of the structure to be observed obtained by cutting and the divided wafer;
and cutting the interval area between the target structure to be observed and the corresponding adjacent structure to be observed for the second time according to the distance mark line so as to lead the sub-area of the structure to be observed and the division wafer to be completely divided.
6. A method according to claim 3, wherein the wafer blocks are excavated from the wafer sample by:
determining a target area of a wafer sample, wherein the target area comprises a plurality of structures to be observed which are arranged on a chip along a first preset direction, and projections of the structures to be observed along the first preset direction in a second preset direction are overlapped;
Determining mark lines of a spacing region between adjacent structures to be observed in the target region;
after etching the marking line, depositing a protective layer on the surface of the target area, and exposing the etched marking line part outside the protective layer;
and extracting the target area after the deposition of the protective layer from the wafer sample to obtain a wafer block.
7. The method of claim 6, wherein the marker line is determined by:
and determining mark lines between the adjacent structures to be observed according to interval line segments between the adjacent structures to be observed, wherein the interval line segments are used for representing the distance between the adjacent structures to be observed in the direction of the length of the structures to be observed.
8. The method according to claim 1, wherein the method further comprises:
and when the number of other structures to be observed corresponding to the divided wafer is one, welding one side surface, close to the first side surface, of the corresponding structure to be observed in the divided wafer on one idle grid stand column of the sample stage, thinning one side surface, close to the second side surface, of the target structure to be observed in the divided wafer in a second preset direction to obtain a transmission electron microscope sample corresponding to the divided wafer, so that the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid stand column.
9. A transmission electron microscope specimen, characterized in that the transmission electron microscope specimen comprises a plurality of transmission electron microscope samples, each transmission electron microscope sample is respectively located on a grid column, and each transmission electron microscope sample corresponds to a structure to be observed.
10. A method of preparing a transmission electron microscope specimen, the method comprising:
digging a wafer block from a wafer sample, wherein the wafer block comprises a plurality of structures to be observed, which are arranged along a first preset direction, on the wafer sample, and the structures to be observed are correspondingly arranged in a chip;
the following cutting process is performed for the workpiece to be cut: welding the target side surface of the workpiece to be cut on an idle grid upright post of the sample stage, wherein the workpiece to be cut is a wafer block during primary cutting, the target side surface is a side surface, close to first side surfaces of a plurality of structures to be observed, in the workpiece to be cut, the first side surfaces consist of the lengths and the heights of the structures to be observed,
cutting the piece to be cut to cut the divided wafer from the grid upright post so as to reserve a structure subarea to be observed on the grid upright post, wherein the structure subarea to be observed comprises a corresponding target structure to be observed, the divided wafer comprises other structures to be observed except the target structure to be observed in the piece to be cut,
Thinning the thinned side surface of the sub-region of the structure to be observed in a second preset direction to obtain a transmission electron microscope sample corresponding to the target structure to be observed, wherein the second preset direction is a direction perpendicular to the first preset direction, the thinned side surface is a side surface, close to a second side surface of the target structure to be observed, of the sub-region of the structure to be observed, the second side surface consists of the height and the width of the structure to be observed,
and taking the divided wafer as a piece to be cut, and repeatedly executing the cutting treatment until the transmission electron microscope sample corresponding to each structure to be observed in the wafer block is reserved on the corresponding grid upright, and taking the transmission electron microscope sample on each grid upright as the transmission electron microscope sample.
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| CN104979151A (en) * | 2014-04-14 | 2015-10-14 | Fei公司 | High Capacity TEM Grid |
| CN105158516A (en) * | 2015-08-20 | 2015-12-16 | 上海华力微电子有限公司 | Preparation method of planar transmission electron microscope sample in integrated circuit analysis |
| CN114858828A (en) * | 2022-02-23 | 2022-08-05 | 厦门士兰集科微电子有限公司 | Preparation method of transmission electron microscope sample |
| CN115931933A (en) * | 2023-01-06 | 2023-04-07 | 长鑫存储技术有限公司 | Manufacturing method and structure of transmission electron microscope grid oxygen sample |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979151A (en) * | 2014-04-14 | 2015-10-14 | Fei公司 | High Capacity TEM Grid |
| CN105158516A (en) * | 2015-08-20 | 2015-12-16 | 上海华力微电子有限公司 | Preparation method of planar transmission electron microscope sample in integrated circuit analysis |
| CN114858828A (en) * | 2022-02-23 | 2022-08-05 | 厦门士兰集科微电子有限公司 | Preparation method of transmission electron microscope sample |
| CN115931933A (en) * | 2023-01-06 | 2023-04-07 | 长鑫存储技术有限公司 | Manufacturing method and structure of transmission electron microscope grid oxygen sample |
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