CN116996813A - Analog audio input amplitude limiting circuit for sound equipment - Google Patents
Analog audio input amplitude limiting circuit for sound equipment Download PDFInfo
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- CN116996813A CN116996813A CN202311254512.6A CN202311254512A CN116996813A CN 116996813 A CN116996813 A CN 116996813A CN 202311254512 A CN202311254512 A CN 202311254512A CN 116996813 A CN116996813 A CN 116996813A
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- 239000003990 capacitor Substances 0.000 claims abstract description 23
- 230000005236 sound signal Effects 0.000 abstract description 4
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R3/00—Circuits for transducers, loudspeakers or microphones
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
- H03G11/02—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general by means of diodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R2420/00—Details of connection covered by H04R, not provided for in its groups
- H04R2420/01—Input selection or mixing for amplifiers or loudspeakers
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- Engineering & Computer Science (AREA)
- Acoustics & Sound (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses an analog audio input amplitude limiting circuit for sound equipment, which relates to the technical field of communication and comprises a first chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first triode, a first capacitor and a first pin, wherein one end of the first resistor is connected with one end of the second resistor and a power supply, the other end of the first resistor is connected with one end of the first capacitor, a base electrode of the first triode and one end of the third resistor, and the other end of the first capacitor is connected with the first pin. The invention can limit the amplitude of the audio signal and simultaneously remove the problem of output drift caused by no coupling.
Description
Technical Field
The invention relates to the technical field of communication, in particular to an analog audio input amplitude limiting circuit for sound equipment.
Background
Publication No.: CN115767371a discloses an analog audio input limiter circuit for sound equipment, which amplifies an audio signal by the closed loop gain of an op amp, and the diodes are connected in series to limit the amplitude, but the amplitude limit is not adjustable and can only be used in the amplitude range, and then the direct closed loop amplification by the op amp can cause output drift when no signal is coupled, so that the output drift is separated from a linear section when static state.
Disclosure of Invention
The invention aims to provide an analog audio input amplitude limiting circuit for sound equipment, which comprises a first chip U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first triode Q1, a first capacitor C1 and a first pin PA_1, wherein one end of the first resistor R1 is connected with one end of the second resistor R2 and a power supply, the other end of the first resistor R1 is connected with one end of the first capacitor C1, the base of the first triode Q1 and one end of the third resistor R3, the other end of the first capacitor C1 is connected with the first pin PA_1, the first pin PA_1 is connected with the 41 pin of the first chip U1, the collector of the first triode Q1 is connected with the other end of the second resistor R2, the emitter of the first triode Q1 is connected with one end of the fourth resistor R4, and the other end of the third resistor R3 is connected with the ground.
Further, the circuit further comprises a second operational amplifier U2, a fifth resistor R5, a sixth resistor R6 and a second pin PA_2, wherein the in-phase end of the second operational amplifier U2 is connected with the emitter of the first triode Q1, the inverting end of the second operational amplifier U2 is connected with one end of the fifth resistor R5 and one end of the sixth resistor R6, the other end of the fifth resistor R5 is connected with the output end of the second operational amplifier U2 and the second pin PA_2, the second pin PA_2 is connected with the 42 pin of the first chip U1, and the other end of the sixth resistor R6 is connected with the ground.
Further, the circuit further comprises a seventh potentiometer R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a third operational amplifier U3, a fourth operational amplifier U4 and a third pin PA_3, wherein the in-phase end of the third operational amplifier U3 is connected with the emitter of the first triode Q1, the output end of the third operational amplifier U3 is connected with the 5 pin of the seventh potentiometer R7, the 3 pin of the seventh potentiometer R7 is connected with the third pin PA_3, the third pin PA_3 is connected with the 43 pin of the first chip U1, the 4 pin of the seventh potentiometer R7 is connected with a power supply, the inverting end of the third operational amplifier U3 is connected with one end of the eighth resistor R8, the in-phase end of the fourth operational amplifier U4, the 10 pin of the seventh potentiometer R7 is connected with the 11 pin of the seventh potentiometer R7, the 12 pin of the seventh potentiometer R7 is connected with the power supply, the inverting end of the fourth operational amplifier U4 is connected with one end of the ninth resistor R9, the other end of the tenth resistor R10 is connected with the output end of the fourth resistor R9 and the eighth resistor R8, and the other end of the eighth resistor R8 is connected with the other end of the eighth resistor R8.
Further, the circuit further comprises an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14 and a fifth operational amplifier U5, wherein one end of the eleventh resistor R11 is connected with the output end of the fourth operational amplifier U4, the other end of the eleventh resistor R11 is connected with one end of the twelfth resistor R12 and the inverting end of the fifth operational amplifier U5, the other end of the twelfth resistor R12 is connected with the output end of the fifth operational amplifier U5, the same-phase end of the fifth operational amplifier U5 is connected with one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14, the other end of the thirteenth resistor R13 is connected with the 42 pin of the first chip U1, and the other end of the fourteenth resistor R14 is connected with the grounding end.
Further, the circuit further comprises a fifteenth resistor R15, a sixteenth potentiometer R16, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth operational amplifier U8, a fourth pin PA_4, a fifth pin PA_5 and a sixth pin PA_6, wherein the non-inverting terminal of the sixth operational amplifier U6 is connected with the output terminal of the fifth operational amplifier U5, the inverting terminal of the sixth operational amplifier U6 is connected with one end of the fifteenth resistor R15, the 10 pin and the 11 pin of the sixteenth potentiometer R16, the twelfth resistor R12 pin of the sixteenth potentiometer R16 is connected with the output terminal of the sixth operational amplifier U6, the non-inverting terminal of the seventh operational amplifier U7, the fourth pin PA_4 and the inverting terminal of the eighth operational amplifier U8, the output terminal of the eighth operational amplifier U8 is connected with the output terminal of the seventh operational amplifier U7, the 5 pin of the sixteenth potentiometer R16, the 3 pin of the sixteenth potentiometer R16 is connected with the fifth PA_5, the 4 pin of the sixteenth potentiometer R16 is connected with the sixth pin 6_5, and the fifth pin of the sixteenth potentiometer R16 is connected with the pa_1 chip 7 and the sixth pin of the sixteenth chip PA 1.
Further, the circuit further comprises a seventeenth resistor R17, an eighteenth resistor R18 and a nineteenth resistor R19, wherein one end of the seventeenth resistor R17 is connected with a power supply, the other end of the seventeenth resistor R17 is connected with the same-phase end of the eighth operational amplifier U8 and one end of the eighteenth resistor R18, the other end of the eighteenth resistor R18 is connected with the inverting end of the seventh operational amplifier U7 and one end of the nineteenth resistor R19, and the other end of the nineteenth resistor R19 is connected with a grounding end.
Further, the power supply circuit further comprises a twentieth resistor R20 and a second capacitor C2, one end of the twentieth resistor R20 is connected with a power supply, the other end of the twentieth resistor R20 is connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is connected with a ground terminal.
Further, the LED chip further comprises a first diode D1 and a seventh pin PA_7, wherein the anode of the first diode D1 is connected with the output end of the eighth operational amplifier U8 and the seventh pin PA_7, the cathode of the first diode D1 is connected with the output end of the seventh operational amplifier U7, and the seventh pin PA_7 is connected with the 49 pins of the first chip U1.
Compared with the prior art, the invention has the beneficial effects that:
the invention can remove the problem of output drift caused by direct closed loop of the operational amplifier while limiting the audio signal, and prevent the audio signal from deviating from the linear amplification section when no output exists.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the prior art and the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a clipping circuit according to the present invention.
Fig. 2 is a schematic diagram of the amplitude limiting circuit and the connection pins of the control chip U1 according to the present invention.
Detailed Description
In order that the objects and advantages of the invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings, it being understood that the following text is only intended to describe one or more specific embodiments of the invention and is not intended to limit the scope of the invention as defined in the appended claims.
Referring to fig. 1 and 2 (fig. 1 is a amplitude limiting circuit, wherein pa_ series numbers correspond to pa_ series pins of U1 in fig. 2, pa_ is underlined in the middle and is distinguished as a jump pin number after being plated), the invention is an analog audio input amplitude limiting circuit for sound, which comprises a first chip U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first triode Q1, a first capacitor C1, a first pin pa_1, wherein one end of the first resistor R1 is connected with one end of the second resistor R2, a power supply is connected, the other end of the first resistor R1 is connected with one end of the first capacitor C1, a base electrode of the first triode Q1, one end of the third resistor R3 are connected, the other end of the first capacitor C1 is connected with the first pin pa_1 is connected with a pin 41 of the first chip U1, a collector electrode of the first triode Q1 is connected with the other end of the second resistor R2, one end of the first triode Q1 is connected with the fourth resistor R4, and the other end of the fourth resistor R3 is connected with the other end of the fourth resistor R4.
Specifically, the circuit further comprises a second operational amplifier U2, a fifth resistor R5, a sixth resistor R6 and a second pin PA_2, wherein the in-phase end of the second operational amplifier U2 is connected with the emitter of the first triode Q1, the inverting end of the second operational amplifier U2 is connected with one end of the fifth resistor R5 and one end of the sixth resistor R6, the other end of the fifth resistor R5 is connected with the output end of the second operational amplifier U2 and the second pin PA_2, the second pin PA_2 is connected with the 42 pin of the first chip U1, and the other end of the sixth resistor R6 is connected with the ground.
Specifically, the circuit further comprises a seventh potentiometer R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a third operational amplifier U3, a fourth operational amplifier U4 and a third pin PA_3, wherein the in-phase end of the third operational amplifier U3 is connected with the emitter of the first triode Q1, the output end of the third operational amplifier U3 is connected with the 5 pin of the seventh potentiometer R7, the 3 pin of the seventh potentiometer R7 is connected with the third pin PA_3, the third pin PA_3 is connected with the 43 pin of the first chip U1, the 4 pin of the seventh potentiometer R7 is connected with a power supply, the inverting end of the third operational amplifier U3 is connected with one end of the eighth resistor R8, the in-phase end of the fourth operational amplifier U4, the 10 pin of the seventh potentiometer R7 is connected with the 11 pin of the seventh potentiometer R7, the 12 pin of the seventh potentiometer R7 is connected with the power supply, the inverting end of the fourth operational amplifier U4 is connected with one end of the ninth resistor R9, the other end of the tenth resistor R10 is connected with the output end of the fourth resistor R9 and the eighth resistor R8, and the other end of the eighth resistor R8 is connected with the other end of the eighth resistor R8.
Specifically, the circuit further comprises an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14 and a fifth operational amplifier U5, wherein one end of the eleventh resistor R11 is connected with the output end of the fourth operational amplifier U4, the other end of the eleventh resistor R11 is connected with one end of the twelfth resistor R12 and the inverting end of the fifth operational amplifier U5, the other end of the twelfth resistor R12 is connected with the output end of the fifth operational amplifier U5, the same-phase end of the fifth operational amplifier U5 is connected with one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14, the other end of the thirteenth resistor R13 is connected with the 42 pin of the first chip U1, and the other end of the fourteenth resistor R14 is connected with the grounding end.
Specifically, the circuit further comprises a fifteenth resistor R15, a sixteenth potentiometer R16, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth operational amplifier U8, a fourth pin PA_4, a fifth pin PA_5 and a sixth pin PA_6, wherein the non-inverting terminal of the sixth operational amplifier U6 is connected with the output terminal of the fifth operational amplifier U5, the inverting terminal of the sixth operational amplifier U6 is connected with one end of the fifteenth resistor R15, the 10 pin and the 11 pin of the sixteenth potentiometer R16, the twelfth resistor R12 pin of the sixteenth potentiometer R16 is connected with the output terminal of the sixth operational amplifier U6, the non-inverting terminal of the seventh operational amplifier U7, the fourth pin PA_4 and the non-inverting terminal of the eighth operational amplifier U8, the output terminal of the eighth operational amplifier U8 is connected with the output terminal of the seventh operational amplifier U7, the 5 pin of the sixteenth potentiometer R16 is connected with the fifth PA_5, the 4 pin of the sixteenth potentiometer R16 is connected with the sixth pin 6_5, and the fifth pin 4 pin of the sixteenth potentiometer R16 is connected with the sixth pin 6_6 and the sixth pin of the PA 1 chip is connected with the PA 1.
Specifically, the circuit further comprises a seventeenth resistor R17, an eighteenth resistor R18 and a nineteenth resistor R19, wherein one end of the seventeenth resistor R17 is connected with a power supply, the other end of the seventeenth resistor R17 is connected with the same-phase end of the eighth operational amplifier U8 and one end of the eighteenth resistor R18, the other end of the eighteenth resistor R18 is connected with the inverting end of the seventh operational amplifier U7 and one end of the nineteenth resistor R19, and the other end of the nineteenth resistor R19 is connected with a grounding end.
Specifically, the capacitor further comprises a twentieth resistor R20 and a second capacitor C2, one end of the twentieth resistor R20 is connected with a power supply, the other end of the twentieth resistor R20 is connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is connected with a ground terminal.
Specifically, the circuit further comprises a first diode D1 and a seventh pin PA_7, wherein the anode of the first diode D1 is connected with the output end of the eighth operational amplifier U8 and the seventh pin PA_7, the cathode of the first diode D1 is connected with the output end of the seventh operational amplifier U7, and the seventh pin PA_7 is connected with the 49 pins of the first chip U1.
In this embodiment, considering the problem of deviation from the linear interval when no signal is input, the reference fixed bias potential of the first triode Q1 is set by the voltage division of the first resistor R1 and the third resistor R3, so that the first triode Q1 enters an amplifying state, when an analog signal is input, the first triode Q1 is coupled to the first capacitor C1 through the first pin pa_1, the first triode Q1 amplifies in the bias state, the power signal at the end of the second resistor R2 is fed back to the end of the fourth resistor R4 through the collector and the emitter of the first triode Q1 and converted into a voltage signal, and the voltage signal is amplified through the second operational amplifier U2, the fifth resistor R5 and the sixth resistor R6 and fed back to the second pin pa_2 to complete the output.
In this embodiment, considering the correction problem when the reference bias signal is offset, the signal fed back to the second operational amplifier U2 by the first triode Q1 is also fed back to the non-inverting terminal of the third operational amplifier U3, the signal input correction is performed on the non-inverting terminal of the fourth operational amplifier U4 by the seventh potentiometer R7 and the eighth resistor R8, the configuration of the ninth resistor R9 and the tenth resistor R10 is the same as that of the fifth resistor R5 and the sixth resistor R6, the correction signal before the analog signal input is provided by the third pin pa_3, when the correction signal is input by the third pin pa_3, the signal output to the 5 pin of the seventh potentiometer R7 is based on the inverting terminal and the non-inverting terminal input, so that the signal is in a high or low potential signal state, and meanwhile, the 4 pin power signal of the seventh potentiometer R7 is fed back to the inverting terminal of the third operational amplifier U3 via the seventh potentiometer R7 and the eighth resistor R8, so that the signal input to the non-inverting terminal of the fourth operational amplifier U4 is corrected, and the correction signal before the analog signal input is performed by the analog signal is the correction signal before the analog signal is input by the fourth amplifier U4 and the reference bias signal is obtained, and the correction signal is output after the synchronization signal is obtained by the second operational amplifier U2.
In this embodiment, considering that the output of the second pin pa_2 is not high in accuracy, the bias of the first triode Q1 needs to remove the amplified signal of the basic bias signal output by the fourth operational amplifier U4, so that the output of the fourth operational amplifier U4 is connected to the eleventh resistor R11, the signal is fed back to the inverting terminal of the fifth operational amplifier U5 through one path of the eleventh resistor R11, the other path is fed back to the output terminal of the fifth operational amplifier U5 through the twelfth resistor R12, the thirteenth resistor R13 is connected to the 42 pin of the first chip U1, that is, the second pin pa_2, and the signal directly fed back to the non-inverting terminal of the fifth operational amplifier U5 through the second pin pa_2 and the thirteenth resistor R13 when the output of the second operational amplifier U2, that is, the signal output by the fifth operational amplifier U5 is differential-processed to the signal output by the second operational amplifier U2 and the signal of the basic bias output by the fourth operational amplifier U4, and the output of the fifth operational amplifier U5 is directly implemented from the fifth operational amplifier pa_2 instead of the second pin pa_2 of the first chip U1.
In this embodiment, it is considered that, at this time, if the output of the fifth operational amplifier U5 is limited by changing the bias of the first triode Q1 through the first resistor R1 and the third resistor R3, the output of the fifth operational amplifier U5 is still reduced in accuracy, so that the limited non-chopped actual amplified signal is obtained by separating the limited and bias signals, the amplified signal directly output by the fifth operational amplifier U5 is removed first, the output of the fifth operational amplifier U5 is fed back to the sixth operational amplifier U6, the inverting terminal of the sixth operational amplifier U6 is output followed by the fifteenth resistor R15 and the sixteenth potentiometer R16, the inverting terminal of the seventh operational amplifier U7 is used for setting the first limiting threshold, the non-inverting terminal of the eighth operational amplifier U8 is set with the second limiting threshold, the output of the eighth operational amplifier U8 is connected in parallel with the sixteenth potentiometer R16, when the output of the sixth operational amplifier U6 is in any output state of the seventh operational amplifier U7 and the eighth operational amplifier U8, the output of the sixteenth potentiometer R16 is changed, the output of the signal is output from the seventh operational amplifier U7 to the sixteenth amplifier U6 through the sixteenth resistor R3, and the signal is output of the sixteenth amplifier U6 is output of the sixteenth PA 1 through the sixteenth resistor R3, the inverting terminal of the sixteenth operational amplifier U8 is output of the sixteenth PA 1 is adjusted, and the signal is output from the output of the sixteenth amplifier U6 is output of the sixteenth signal is adjusted.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (8)
1. The analog audio input amplitude limiting circuit for the sound equipment is characterized by comprising a first chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first triode, a first capacitor and a first pin, wherein one end of the first resistor is connected with one end of the second resistor and a power supply, the other end of the first resistor is connected with one end of the first capacitor, a base electrode of the first triode and one end of the third resistor, the other end of the first capacitor is connected with the first pin, the first pin is connected with a pin 41 of the first chip, a collector electrode of the first triode is connected with the other end of the second resistor, an emitter electrode of the first triode is connected with one end of the fourth resistor, and the other end of the third resistor, the other end of the fourth resistor are connected with a grounding end.
2. The analog audio input limiter circuit of claim 1, further comprising a second operational amplifier, a fifth resistor, a sixth resistor, a second pin, wherein the second operational amplifier is connected to the first triode emitter at its in-phase end, the second operational amplifier is connected to the fifth resistor at its inverting end and one end, the sixth resistor at its one end, the fifth resistor at its other end is connected to the second operational amplifier output, the second pin is connected to pin 42 of the first chip, and the sixth resistor at its other end is connected to ground.
3. The analog audio input limiting circuit for sound according to claim 1, further comprising a seventh potentiometer, an eighth resistor, a ninth resistor, a tenth resistor, a third operational amplifier, a fourth operational amplifier, and a third pin, wherein the third operational amplifier has an in-phase end connected to the emitter of the first triode, the third operational amplifier output end connected to the 5 pin of the seventh potentiometer, the seventh potentiometer has a 3 pin connected to the third pin, the third pin is connected to the 43 pin of the first chip, the seventh potentiometer has a 4 pin connected to the power supply, the third operational amplifier has an inverting end connected to the eighth resistor, the fourth operational amplifier has an in-phase end connected to the 10 pin of the seventh potentiometer, the seventh potentiometer has an 11 pin connected to the power supply, the fourth operational amplifier has an inverting end connected to the one end of the ninth resistor, the ninth resistor has another end connected to the output end of the fourth operational amplifier, the eighth resistor has another end connected to the other end of the eighth resistor, and the eighth resistor another end connected to the ground.
4. The analog audio input limiter circuit for acoustic equipment of claim 3, further comprising an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifth operational amplifier, wherein one end of the eleventh resistor is connected to the output end of the fourth operational amplifier, the other end of the eleventh resistor is connected to one end of the twelfth resistor, the inverting end of the fifth operational amplifier is connected to the output end of the fifth operational amplifier, the same phase end of the fifth operational amplifier is connected to one end of the thirteenth resistor, one end of the fourteenth resistor is connected to the 42 pin of the first chip, the other end of the thirteenth resistor is connected to the ground terminal.
5. The analog audio input limiting circuit for acoustic equipment according to claim 4, further comprising a fifteenth resistor, a sixteenth potentiometer, a sixth operational amplifier, a seventh operational amplifier, an eighth operational amplifier, a fourth pin, a fifth pin, and a sixth pin, wherein the sixth operational amplifier is connected to the fifth operational amplifier output terminal at the same phase end, the sixth operational amplifier is connected to the fifteenth resistor at one end, the sixteenth potentiometer is connected to the 10 pin and the 11 pin, the sixteenth potentiometer is connected to the sixth operational amplifier output terminal at the twelfth resistor, the seventh operational amplifier is connected to the same phase end, the fourth pin, and the eighth operational amplifier is connected to the eighth operational amplifier output terminal at the same phase end, the sixteenth potentiometer is connected to the 5 pin, the sixteenth potentiometer is connected to the fifth pin at the 3 pin, the sixteenth potentiometer is connected to the sixth pin, the fifth pin is connected to the 45 pin of the first chip, and the sixth potentiometer is connected to the 46 pin of the first chip.
6. The analog audio input limiter circuit for acoustic equipment of claim 4, further comprising a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, wherein one end of the seventeenth resistor is connected to a power supply, the other end of the seventeenth resistor is connected to the in-phase end of the eighth operational amplifier, one end of the eighteenth resistor is connected to the inverting end of the seventh operational amplifier, one end of the nineteenth resistor is connected to a ground terminal, and the other end of the nineteenth resistor is connected to a ground terminal.
7. The analog audio input limiter circuit of claim 1, further comprising a twentieth resistor connected at one end to a power supply, a second capacitor connected at the other end to one end of the second capacitor, and a ground terminal connected at the other end to the second capacitor.
8. The analog audio input limiter circuit of claim 5, further comprising a first diode connected with the anode of the first diode and the output of the eighth operational amplifier and a seventh pin connected with the cathode of the first diode and the output of the seventh operational amplifier, and a seventh pin connected with the 49 pin of the first chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311254512.6A CN116996813B (en) | 2023-09-27 | 2023-09-27 | Analog audio input amplitude limiting circuit for sound equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311254512.6A CN116996813B (en) | 2023-09-27 | 2023-09-27 | Analog audio input amplitude limiting circuit for sound equipment |
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| Publication Number | Publication Date |
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| CN116996813A true CN116996813A (en) | 2023-11-03 |
| CN116996813B CN116996813B (en) | 2024-01-26 |
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| CN202311254512.6A Active CN116996813B (en) | 2023-09-27 | 2023-09-27 | Analog audio input amplitude limiting circuit for sound equipment |
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| CN117498509A (en) * | 2023-12-29 | 2024-02-02 | 广州市锐丰音响科技股份有限公司 | Automatic charging circuit of stereo set |
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| CN102854378A (en) * | 2011-06-30 | 2013-01-02 | 海洋王照明科技股份有限公司 | Current testing circuit |
| CN102769729A (en) * | 2012-06-21 | 2012-11-07 | 深圳创维－Rgb电子有限公司 | Television and audio external play control circuit thereof |
| CN210157375U (en) * | 2019-09-24 | 2020-03-17 | Tcl通力电子（惠州）有限公司 | Microphone reverberation circuit and electronic equipment |
| CN217088099U (en) * | 2022-04-18 | 2022-07-29 | 深圳市诺威达电汽有限公司 | Audio signal processing circuit and vehicle navigation equipment |
| CN217283386U (en) * | 2022-05-19 | 2022-08-23 | 广东得胜电子有限公司 | Audio detection circuit and device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117498509A (en) * | 2023-12-29 | 2024-02-02 | 广州市锐丰音响科技股份有限公司 | Automatic charging circuit of stereo set |
| CN117498509B (en) * | 2023-12-29 | 2024-04-09 | 广州市锐丰音响科技股份有限公司 | Automatic charging circuit of stereo set |
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| CN116996813B (en) | 2024-01-26 |
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