CN116995090A - Super-junction IGBT device and manufacturing method thereof - Google Patents

Super-junction IGBT device and manufacturing method thereof Download PDF

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Publication number
CN116995090A
CN116995090A CN202311078030.XA CN202311078030A CN116995090A CN 116995090 A CN116995090 A CN 116995090A CN 202311078030 A CN202311078030 A CN 202311078030A CN 116995090 A CN116995090 A CN 116995090A
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type
region
channel region
gate
trench
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李�昊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

The invention discloses a super-junction IGBT device, which comprises a device unit structure including a first NMOS tube and a second PMOS tube. The first NMOS tube comprises a first channel region doped with P type, a first grid structure and an emitting region doped with N+; the first channel region is formed in a selected region of the top of the N-type column of the superjunction structure; the emission region is formed on the surface of the first channel region and is self-aligned with the first gate structure; the P-type pillar is electrically isolated from the first channel region. The second PMOS transistor includes: an N-type doped second channel region, a second gate structure and a P+ doped second drain region; the second channel region is formed in a selected region at the top of the P-type column; the second drain region is formed on the surface of the second channel region and is self-aligned with the second gate structure; the N-type pillar is electrically isolated from the second channel region. The second PMOS tube is turned off in the forward direction and turned on in the reverse direction, and the first NMOS tube is opposite. The invention also discloses a manufacturing method of the super-junction IGBT device. The invention can reduce the turn-off time and turn-off loss.

Description

Super-junction IGBT device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a Super Junction (SJ) insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) device. The invention also relates to a manufacturing method of the super-junction IGBT.
Background
IGBTs are voltage controlled MOS and bipolar composite devices that have the main advantages of both bipolar junction power transistors and power MOSFETs: the IGBT becomes one of important switching components for controlling and converting the energy of the power electronic system, and the performance of the IGBT directly influences the conversion efficiency, volume and weight of the power electronic system.
The IGBT structure is very similar to the VDMOS structure, and an N+ doped drain region is changed into a P+ doped collector region on the basis of the VDMOS structure, and holes can be injected into a drift region by the collector region, so that conductivity modulation can be realized on the drift region, the on-state voltage drop of the device can be reduced, and the current density of the device can be improved.
And setting a super-junction structure in a drift region of the IGBT device to obtain a super-junction IGBT (SJ-IGBT) device. The SJ-IGBT utilizes the SJ and IGBT process capability, combines the characteristics of two devices, can greatly improve the forward conduction performance of the devices and greatly increase the power density of the devices.
As shown in fig. 1, the structure of the prior art super-junction IGBT device is schematically shown; the prior first super junction IGBT device comprises:
The super junction structure is formed by alternately arranging a plurality of N-type columns and P-type columns (pilar) 209, and one N-type column and one adjacent P-type column 209 form a corresponding super junction unit.
The super junction structure is formed in a first N-type epitaxial layer 202, a P-type doped collector region 201 is formed at the bottom of the first N-type epitaxial layer 202, and the back surface of the collector region 201 is connected with a collector consisting of a back metal layer.
The P-type pillars 209 are composed of a P-type epitaxial layer filled in super junction trenches formed in the first N-type epitaxial layer 202, and the N-type pillars are composed of the first N-type epitaxial layer 202 between the P-type pillars 209.
The first N-type epitaxial layer 202 is formed on a surface of a semiconductor substrate (not shown). The semiconductor substrate is removed in a backside thinning process and is not shown in fig. 1.
The bottom of the P-type pillars 209 and the top surface of the collector region 201 have a spacing.
A top N-type epitaxial layer 208 is formed on top of the superjunction structure.
In the device cell region 201a, a device cell structure of an IGBT device formed by connecting a plurality of the device cell structures in parallel is formed in the top N-type epitaxial layer 208 of the top region of each of the superjunction cells.
The device cell structure includes:
a P-doped body region 206, the body region 206 being formed in a surface region of the top N-type epitaxial layer 208.
A trench gate, which is composed of a gate dielectric layer 204 and a gate conductive material layer 205 filled in a gate trench 203, the gate trench 203 is located in a top region of the N-type pillar and the gate trench 203 passes through the body region 206.
The surface of the body region 206 covered by the trench gate sides is used to form a channel; the drift region is comprised of the first N-type epitaxial layer 202 and the top N-type epitaxial layer 208 at the bottom of the body region 206.
An emitter region 207 consisting of an n+ region is formed on the surface of the body region 206 at the side of the trench gate.
A first contact hole 211 is formed at the top of the emitter region 207, the bottom of the first contact hole 211 simultaneously contacts the emitter region 207 and the body region 206, and the top of the first contact hole 211 is connected to an emitter composed of a front metal layer 212.
An N-doped electric field stop layer 214 is formed in the first N-type epitaxial layer 202 on the front surface of the collector region 201, the doping concentration of the electric field stop layer 214 is greater than that of the first N-type epitaxial layer 202, and a space is provided between the top surface of the electric field stop layer 214 and the bottom surface of the P-type pillar 209.
The trench gate also extends into a gate lead-out region 201b, in which gate lead-out region 201b a second contact hole (not shown) is formed on top of the gate conductive material layer 205, the top of which is connected to a gate electrode composed of a front side metal layer 212.
A passivation layer 213 is further formed on the surface of the front metal layer 212.
The first contact hole 211 and the second contact hole pass through the interlayer film 210.
Typically, the collector region 201 is formed by a P-type doped back ion implantation region formed at the bottom of the first N-type epitaxial layer 202 after the back surface of the semiconductor substrate is thinned.
The P-type column 209 and the body region 206 are isolated by a top N-type epitaxial layer 208 when the device is turned on in the forward direction.
As shown in fig. 2, the structure of the conventional second super-junction IGBT device is schematically shown; the existing second super-junction IGBT device comprises:
the super junction structure is formed by alternately arranging a plurality of N-type columns and P-type columns 309, and one N-type column and one adjacent P-type column 309 form a corresponding super junction unit.
The super junction structure is formed in a first N-type epitaxial layer 302, a P-type doped collector region 301 is formed at the bottom of the first N-type epitaxial layer 302, and the back surface of the collector region 301 is connected with a collector consisting of a back metal layer.
The P-type pillars 309 are composed of a P-type epitaxial layer filled in super junction trenches formed in the first N-type epitaxial layer 302, and the N-type pillars are composed of the first N-type epitaxial layer 302 between the P-type pillars 309.
The first N-type epitaxial layer 302 is formed on a surface of a semiconductor substrate (not shown). The semiconductor substrate is removed in a backside thinning process and is not shown in fig. 2.
The bottom of the P-type pillars 309 and the top surface of the collector region 301 have a spacing.
In the device unit area, a device unit structure of an IGBT device is formed in the top area of each super-junction unit, and the IGBT device is formed by connecting a plurality of device unit structures in parallel.
The device cell structure includes:
a P-doped body region 306, the body region 306 being formed in the top region of the superjunction cell, i.e. in the top regions of the N-type and P-type pillars 309.
The trench gate is composed of a gate dielectric layer 304 and a gate conductive material layer 305 filled in the gate trench 303. The gate trench 303 is located in the top region of the N-type pillar and the gate trench 303 passes through the body region 306.
The surface of the body region 306 covered by the trench gate sides is used to form a channel; the drift region is comprised of the first N-type epitaxial layer 302 at the bottom of the body region 306.
Two of the gate trenches 303 are formed in the top region of the same N-type pillar.
An emitter region 307 consisting of an n+ region is formed on the surface of the body region 306 at the second side of the trench gate.
A first contact hole 311 is formed at the top of the emitter region 307, the bottom of the first contact hole 311 simultaneously contacts the emitter region 307 and the body region 306, and the top of the first contact hole 311 is connected to an emitter composed of a front metal layer 312.
The body region 306 at the bottom of the first contact hole 311 is also formed with a body extraction region 308 composed of a p+ region.
As can be seen from fig. 2, the P-type pillar 309 is located outside the first side of the trench gate, and the conductive path between the P-type pillar 309 and the second side of the trench gate, the emitter region 307, the first contact hole 311 and the emitter electrode is broken by the trench gate, since the first side and the second side of the trench gate are electrically isolated. In the structure shown in fig. 2, the top of the N-type pillar has two trench gates, which are dual gate structures, and the isolation of the P-type pillar 309 and the channel region formed by the body region 306 is achieved by the dual gate structure.
An N-doped electric field stop layer 314 is formed in the first N-type epitaxial layer 302 on the front surface of the collector region 301, the doping concentration of the electric field stop layer 314 is greater than that of the first N-type epitaxial layer 302, and a space is provided between the top surface of the electric field stop layer 314 and the bottom surface of the P-type column 309.
A passivation layer 313 is also formed on the surface of the front side metal layer 312.
The first contact hole 311 and the second contact hole pass through the interlayer film 310.
Typically, the collector region 301 is formed by a P-type doped back ion implantation region formed at the bottom of the first N-type epitaxial layer 302 after the back surface of the semiconductor substrate is thinned.
As can be seen from fig. 1 and fig. 2, after the super junction structure is introduced, in order to improve forward conduction current, the IGBT device needs to prevent the P-type Pillar from being grounded, otherwise, holes in the drift region leak to the ground through the P-type Pillar, so that the hole concentration in the drift region is reduced, and the forward current capability is greatly reduced, so that floating (floating) of the P-type Pillar is required, that is, floating pilar is adopted. In fig. 1, the isolation between the P-type pillar 209 and the body region 206 is achieved by the top N-type epitaxial layer 208, which prevents the P-type pillar 209 from being connected to the body region 206, which is grounded, and thus forms a hole leakage path, i.e., the floating of the P-type pillar 209 needs to be achieved by an additional top N-type epitaxial layer 208, which increases the process cost. In fig. 2, floating arrangement of the P-type pillars is achieved by dual gate.
Although the forward conduction performance of the device can be improved by the floating pilar arrangement, when the device is in the reverse direction, holes in the drift region cannot be extracted to the ground through the P-type column because the P-type column does not have a grounding path, so the hole extraction in the drift region is difficult, the carrier removal time of the drift region is longer, and the turn-off time is prolonged and the turn-off energy consumption is increased.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a super-junction IGBT device, which can increase the hole concentration of a drift region in the forward direction and increase the extraction speed of holes of the drift region in the reverse direction, so that the forward on performance of the device can be improved, and meanwhile, the turn-off time and the turn-off loss (Eoff) can be reduced. Therefore, the invention also provides a manufacturing method of the super-junction IGBT device.
In order to solve the above technical problems, the super-junction IGBT device provided by the invention includes:
forming a plurality of P-type columns in the first N-type epitaxial layer, forming N-type columns by the first N-type epitaxial layer among the P-type columns, and alternately arranging the P-type columns and the N-type columns to form a super junction structure; and forming a superjunction unit by one P-type column and one adjacent N-type column.
And a collector region doped with P type is formed on the back surface of the first N-type epitaxial layer.
The device unit structure of the super-junction IGBT device is formed on the super-junction structure and comprises a first NMOS tube and a second PMOS tube.
The first NMOS transistor comprises: a P-type doped first channel region, a first gate structure, an n+ doped emitter region; the first channel region is formed in a selected area of the top of the N-type column, and the surface of the first channel region covered by the first gate structure is used for forming a first channel; the emission region is formed on the surface of the first channel region and is self-aligned with the first gate structure; an electrical isolation between the P-type pillar and the first channel region; a drift region is formed from the first N-type epitaxial layer between the first channel region and the collector region.
The second PMOS transistor includes: an N-type doped second channel region, a second gate structure and a P+ doped second drain region; the second channel region is formed in a selected region of the top of the P-type column, and the surface of the second channel region covered by the second gate structure is used for forming a second channel; the second drain region is formed on the surface of the second channel region and is self-aligned with the second gate structure; the N-type pillar is electrically isolated from the second channel region.
When the device is conducted in the forward direction, the first grid structure enables the first channel to be formed and connect the emitting region and the N-type column, and the first NMOS tube is conducted; and the second grid structure enables the second channel to be disconnected, the second PMOS tube is cut off, and the P-type column floats and accordingly hole carrier concentration in the drift region is improved.
When the device is turned off reversely, the first grid structure enables the first channel to be disconnected, and the first NMOS tube is turned off; and the second grid structure enables the second channel to form and connect the second drain region and the P-type column, and the second PMOS tube is conducted and realizes hole carrier discharge in the drift region.
A further improvement is that the first gate structure and the second gate structure share the same trench gate.
The trench gate comprises a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench.
The depth of the gate trench is greater than the depth of the first channel region and the depth of the gate trench is greater than the depth of the second channel region.
The first side surface of the trench gate covers the first channel region, and the emitting region and the first side surface of the trench gate are self-aligned;
The second side of the trench gate overlies the second channel region, and the second drain region and the second side of the trench gate are self-aligned.
Two of the trench gates are included in one of the superjunction cells.
And at the top of the N-type column, the first channel region is positioned between the first sides of the two trench gates, so that the isolation between the first channel region and the P-type column is realized.
And the second channel region is positioned between the second sides of the two trench gates at the top of the P-type column, so that the isolation between the second channel region and the N-type column is realized.
In a further improvement, in each superjunction unit, the trench gate spans the interface of the corresponding P-type column and the corresponding N-type column, the first side face of the trench gate is located in the N-type column, and the second side face of the trench gate is located in the P-type column.
In a further improvement, in each superjunction unit, the trench gate is located in the N-type column; forming a P-type well in the top area of the super junction structure, wherein the P-type well between the first side surfaces of the two trench gates forms the first channel region; the second channel region is formed in the top region of the P-type well between the second sides of the two trench gates, and the junction depth of the second channel region is smaller than that of the P-type well.
Or, in each superjunction unit, the trench gate is located in the P-type column; forming an N-type well in the top area of the super junction structure, wherein the N-type well between the second side surfaces of the two trench gates forms the second channel region; the first channel region is formed in the top region of the N-type well between the first sides of the two trench gates, and the junction depth of the first channel region is smaller than that of the N-type well.
A further development is that the emitter region is connected to the emitter consisting of the front metal layer by means of a corresponding contact hole at the top.
The second drain region is connected to the emitter electrode through a contact hole corresponding to the top.
The grid electrode conductive material layer is connected to a grid electrode formed by the front metal layer through a contact hole corresponding to the top.
The collector region is formed with a collector electrode composed of a backside metal layer on the backside.
The further improvement is that a P+ doped body contact region is formed at the bottom of the contact hole corresponding to the emitting region, and the first channel region is connected with the contact hole at the top through the body contact region.
In a further improvement, when the super-junction IGBT device works, the emitter is grounded, and the collector is connected with a positive voltage.
When the device is conducted in the forward direction, the grid electrode is connected with a positive voltage; and when the device is reversely turned off, the grid electrode is connected with negative voltage.
In order to solve the technical problems, the manufacturing method of the super-junction IGBT device provided by the invention comprises the following steps:
forming a plurality of P-type columns in a first N-type epitaxial layer, forming N-type columns by the first N-type epitaxial layer among the P-type columns, and alternately arranging the P-type columns and the N-type columns to form a super junction structure; and forming a superjunction unit by one P-type column and one adjacent N-type column.
Step two, performing a front process to form a device unit structure of the super-junction IGBT device on the super-junction structure, wherein the device unit structure comprises a first NMOS tube and a second PMOS tube, and the method comprises the following sub-steps:
forming a P-type doped first channel region in a selected region at the top of the N-type pillar; the P-type pillar is electrically isolated from the first channel region.
Forming an N-type doped second channel region in a selected region at the top of the P-type column; the N-type pillar is electrically isolated from the second channel region.
Forming a first gate structure and a second gate structure; the surface of the first channel region covered by the first gate structure is used to form a first channel and the surface of the second channel region covered by the second gate structure is used to form a second channel.
And forming an N+ doped emission region on the surface of the first channel region, wherein the emission region and the first gate structure are self-aligned.
And forming a second P+ doped drain region on the surface of the second channel region, wherein the second drain region and the second grid structure are self-aligned.
The first NMOS transistor includes the first channel region, the first gate structure, and the emitter region.
The second PMOS tube comprises the second channel region, the second grid structure and the second drain region.
Step three, carrying out a back process, which comprises the following steps:
and (5) performing a back thinning process.
Forming a collector region on the back surface of the thinned first N-type epitaxial layer; a drift region is formed from the first N-type epitaxial layer between the first channel region and the collector region.
When the device is conducted in the forward direction, the first grid structure enables the first channel to be formed and connect the emitting region and the N-type column, and the first NMOS tube is conducted; and the second grid structure enables the second channel to be disconnected, the second PMOS tube is cut off, and the P-type column floats and accordingly hole carrier concentration in the drift region is improved.
When the device is turned off reversely, the first grid structure enables the first channel to be disconnected, and the first NMOS tube is turned off; and the second grid structure enables the second channel to form and connect the second drain region and the P-type column, and the second PMOS tube is conducted and realizes hole carrier discharge in the drift region.
In the second step, the first gate structure and the second gate structure share the same trench gate.
The forming step of the trench gate comprises the following steps:
forming a gate trench, the depth of the gate trench being greater than the depth of the first channel region and the depth of the gate trench being greater than the depth of the second channel region; a first side of the gate trench overlies the first channel region and a second side of the gate trench overlies the second channel region.
And forming a gate dielectric layer on the inner side surface of the gate trench.
And filling a gate conductive material layer in the gate trench.
In the second step, the emitter region and the first side surface of the gate trench are self-aligned.
The second drain region and the second side of the gate trench are self-aligned.
A further improvement is to include two of said trench gates in one of said superjunction cells.
And at the top of the N-type column, the first channel region is positioned between the first sides of the two trench gates, so that the isolation between the first channel region and the P-type column is realized.
And the second channel region is positioned between the second sides of the two trench gates at the top of the P-type column, so that the isolation between the second channel region and the N-type column is realized.
In a further improvement, in each superjunction unit, the trench gate spans the interface of the corresponding P-type column and the corresponding N-type column, the first side face of the trench gate is located in the N-type column, and the second side face of the trench gate is located in the P-type column.
In the second step, the step of forming the first channel region and the second channel region includes:
forming a P-type well, wherein the P-type well is positioned in the top area of the N-type column or positioned in the top area of the N-type column and extends to part or all of the area of the P-type column; after the trench gate is formed, the first channel region is formed due to the P-type well located between the first sides of the two trench gates.
Forming an N-type well, wherein the N-type well is positioned in the top area of the P-type column; when the P-type well extends to the top of the P-type column, the junction depth of the N-type well is smaller than that of the P-type well, and the second channel region is formed by the N-type well between the second side surfaces of the two groove gates.
In a further improvement, in each superjunction unit, the trench gate is located in the N-type column; in the second step, the step of forming the first channel region and the second channel region includes:
Forming a P-type well, wherein the P-type well is positioned in the top area of the super junction structure; after the trench gate is formed, the first channel region is formed due to the P-type well located between the first sides of the two trench gates.
And forming an N-type well, wherein the N-type well is positioned in the top area of the P-type column and extends into the N-type column, the junction depth of the N-type well is smaller than that of the P-type well, and the second channel region is formed by the N-type well positioned between the second side surfaces of the two trench gates.
Or, in each superjunction unit, the trench gate is located in the P-type column; in the second step, the step of forming the first channel region and the second channel region includes:
and forming an N-type well in the top area of the super junction structure, wherein the N-type well positioned between the second side surfaces of the two groove gates forms the second channel region.
And forming a P-type well, wherein the P-type well is positioned in the top area of the N-type column and extends into the P-type column, the junction depth of the P-type well is smaller than that of the N-type well, and the P-type well positioned between the first sides of the two trench gates forms the first channel region.
In a further improvement, in the second step, the front-side process further includes:
Forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form an emitter and a grid.
The contact hole passes through the interlayer film.
The emitter region is connected to the emitter electrode through a top corresponding contact hole.
The second drain region is connected to the emitter through a contact hole corresponding to the top.
The gate conductive material layer is connected to the gate electrode through a top corresponding contact hole.
In the third step, the back surface process further includes:
and forming a back metal layer on the back surface of the collector region, and forming a collector by the back metal layer.
In a further improvement, the forming process of the contact hole comprises the following steps:
a contact hole opening is formed.
And filling a metal layer in the contact hole opening to form the contact hole.
After the opening of the contact hole corresponding to the emission area is opened and after the metal is filled, the method further comprises the following steps: and P+ injection is carried out to form a body contact region, and the first channel region is connected with the contact hole at the top through the body contact region.
In a further improvement, when the super-junction IGBT device works, the emitter is grounded, and the collector is connected with a positive voltage.
When the device is conducted in the forward direction, the grid electrode is connected with a positive voltage; and when the device is reversely turned off, the grid electrode is connected with negative voltage.
According to the invention, the first NMOS tube and the second PMOS tube are simultaneously arranged in the device unit structure, the first NMOS tube is positioned at the top of the N-type column, the first channel region is electrically isolated from the P-type column, the second PMOS tube is positioned at the top of the P-type column, the second channel region is electrically isolated from the N-type column, the first NMOS tube is conducted and the second PMOS tube is cut off in the forward direction through grid control, and the second PMOS tube is cut off, and the P-type column is isolated from the first channel region and the second channel region is isolated from the N-type column, so that the top of the P-type column is not connected with a fixed potential, the P-type column is in a floating state, holes in the drift region are not leaked from the top of the P-type column, the concentration of the holes in the drift region is improved, and the forward conduction performance of the device is improved.
When the first NMOS tube is turned off and the second PMOS tube is turned on in the reverse direction, after the second PMOS tube is turned on, holes in the drift region can leak through a conduction path formed by the second PMOS tube, so that the extraction speed of the holes in the drift region can be improved, the turn-off time is shortened, and the turn-off loss is reduced.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a schematic structural diagram of a conventional first superjunction IGBT device;
Fig. 2 is a schematic structural diagram of a second conventional superjunction IGBT device;
fig. 3 is a schematic structural diagram of a superjunction IGBT device according to an embodiment of the present invention;
fig. 4 is a simulation diagram of a transfer characteristic curve of a superjunction IGBT device according to an embodiment of the present invention;
FIG. 5 is a simulation plot of collector emitter voltage (Vce) and collector current (Ic) over time for a superjunction IGBT device of an embodiment of the invention;
fig. 6 is a simulation plot of off power (Poff) versus time for a superjunction IGBT device according to an embodiment of the invention.
Detailed Description
Fig. 3 is a schematic structural diagram of a superjunction IGBT device according to an embodiment of the present invention; the super-junction IGBT device of the embodiment of the invention comprises:
a plurality of P-type columns 102 are formed in the first N-type epitaxial layer 101, N-type columns are formed by the first N-type epitaxial layer 101 between the P-type columns 102, and super junction structures are formed by alternately arranging the P-type columns 102 and the N-type columns; a superjunction unit is formed by one of the P-type columns 102 and an adjacent one of the N-type columns.
A collector region (not shown) doped with P-type is formed on the back surface of the first N-type epitaxial layer 101. Since the front structure of the superjunction IGBT device is mainly improved in the embodiment of the present invention, for a clearer and clearer understanding of the technical solution of the embodiment of the present invention, only the structure above the top region of the superjunction structure is shown in fig. 3, and the bottom region of the superjunction structure and the structure at the bottom of the superjunction structure, such as the collector region, are omitted and are indicated by the dashed box 113. The structure in the dashed box 113 can be any of the structures already disclosed in the prior art, and can be modified in various ways, and in any case the structure of the embodiment of the present invention can be applied to various bottom structures.
The device unit structure of the super-junction IGBT device is formed on the super-junction structure and comprises a first NMOS tube and a second PMOS tube.
The first NMOS transistor comprises: a P-doped first channel region 105, a first gate structure, an n+ doped emitter region 106; the first channel region 105 is formed in a selected region of the top of the N-type pillar, and the surface of the first channel region 105 covered by the first gate structure is used to form a first channel; the emitter region 106 is formed on the surface of the first channel region 105 and is self-aligned to the first gate structure; electrical isolation between the P-type pillar 102 and the first channel region 105; a drift region is formed by the first N-type epitaxial layer 101 between the first channel region 105 and the collector region.
The second PMOS transistor includes: an N-doped second channel region 107, a second gate structure, and a p+ doped second drain region 108; the second channel region 107 is formed in a selected region on top of the P-type pillar 102, and the surface of the second channel region 107 covered by the second gate structure is used to form a second channel; the second drain region 108 is formed on the surface of the second channel region 107 and is self-aligned with the second gate structure; the N-type pillars are electrically isolated from the second channel region 107.
When the device is turned on in the forward direction, the first gate structure forms the first channel and connects the emitter region 106 and the N-type column, and the first NMOS transistor is turned on; the second gate structure turns off the second channel, the second PMOS transistor turns off, and the P-type column 102 floats and thereby increases the hole carrier concentration in the drift region.
When the device is turned off reversely, the first grid structure enables the first channel to be disconnected, and the first NMOS tube is turned off; the second gate structure enables the second channel to form and connect the second drain region 108 and the P-type pillar 102, and the second PMOS transistor is turned on and realizes hole carrier discharge in the drift region.
It can be seen that, in the embodiment of the present invention, the second PMOS transistor is provided to control the conduction and floating states of the P-type column 102, so that the P-type column 102 in the embodiment of the present invention is also referred to as a gate P-type column.
In the embodiment of the invention, the first gate structure and the second gate structure share the same trench gate.
The trench gate includes a gate dielectric layer (not shown) formed on the inner side surface of the gate trench 103 and a gate conductive material layer 104 filled in the gate trench 103. In some embodiments, the gate dielectric layer is a gate oxide layer; the gate conductive material layer 104 is a polysilicon gate.
The depth of the gate trench 103 is greater than the depth of the first channel region 105 and the depth of the gate trench 103 is greater than the depth of the second channel region 107.
The first side of the trench gate covers the first channel region 105, and the emitter region 106 and the first side of the trench gate are self-aligned.
The second side of the trench gate overlies the second channel region 107, and the second drain region 108 and the second side of the trench gate are self-aligned.
In the present application, the first side of the trench gate is the first side of the gate trench 103, and the second side of the trench gate is the second side of the gate trench 103. Since the trench gate has two sides, a first side of the trench gate is the first gate structure when it covers the first channel region 105; and a second side of the trench gate overlies the second channel region 107, as the second gate structure.
In the embodiment of the present application, as shown in fig. 3, two trench gates are included in one super junction unit.
At the top of the N-type pillar, the first channel region 105 is located between the first sides of the two trench gates, so as to isolate the first channel region 105 from the P-type pillar 102.
At the top of the P-type pillar 102, the second channel region 107 is located between the second sides of the two trench gates, so as to isolate the second channel region 107 from the N-type pillar.
In the embodiment of the present invention, in each superjunction unit, the trench gate spans the interface between the corresponding P-type pillar 102 and the N-type pillar, the first side of the trench gate is located in the N-type pillar, and the second side of the trench gate is located in the P-type pillar 102.
In some alternative embodiments can also be: in each superjunction unit, the trench gate is located in the N-type column, and the double gate structure is similar to that shown in fig. 2; a P-type well is formed in the top area of the super junction structure, and the P-type well located between the first sides of the two trench gates forms the first channel region 105; the second channel region 107 is formed in the top region of the P-type well between the second sides of the trench gates, and the junction depth of the second channel region 107 is smaller than that of the P-type well, at this time, the source region of the second PMOS transistor is composed of the P-type well located at the bottom of the second channel region 107 and the P-type pillar 102 together.
In some alternative embodiments can also be: in each superjunction cell, the trench gate is located in the P-type column 102; an N-type well is formed in the top area of the super junction structure, and the N-type well located between the second side surfaces of the two trench gates forms the second channel region 107; the first channel region 105 is formed in the top region of the N-type well between the first sides of the two trench gates, and the junction depth of the first channel region 105 is smaller than that of the N-type well. In this case, the drain region of the first NMOS transistor is composed of the N-type well and the N-type pillar at the bottom of the first channel region 105.
In the embodiment of the present invention, the emitter region 106 is connected to the emitter electrode formed by the front metal layer 112 through the contact hole 111 corresponding to the top. A p+ doped body contact region 109 is formed at the bottom of the contact hole 111 corresponding to the emitter region 106, and the first channel region 105 is connected to the top contact hole 111 through the body contact region 109.
The second drain region 108 is connected to the emitter electrode through a top corresponding contact hole 111.
The gate conductive material layer 104 is connected to a gate electrode (not shown) composed of the front side metal layer 112 through a top corresponding contact hole 111.
The collector region is formed with a collector electrode composed of a backside metal layer on the backside.
When the super-junction IGBT device works, the emitter is grounded, and the collector is connected with a positive voltage.
When the device is conducted in the forward direction, the grid electrode is connected with a positive voltage; and when the device is reversely turned off, the grid electrode is connected with negative voltage.
According to the embodiment of the invention, the first NMOS tube and the second PMOS tube are simultaneously arranged in the device unit structure, the first NMOS tube is positioned at the top of the N-type column, the first channel region 105 is electrically isolated from the P-type column 102, the second PMOS tube is positioned at the top of the P-type column 102, the second channel region 107 is electrically isolated from the N-type column, and the first NMOS tube is conducted and the second PMOS tube is cut off in the forward direction through grid control, and the second PMOS tube is cut off, and the P-type column 102 is isolated from the first channel region 105 and the second channel region 107 is isolated from the N-type column, so that the top of the P-type column 102 is not connected with a fixed potential, the P-type column 102 is in a floating state, and therefore, holes in a drift region cannot leak from the top of the P-type column 102, the concentration of holes in the drift region can be improved, and the forward direction conduction performance of the device is improved.
When the first NMOS tube is turned off and the second PMOS tube is turned on in the reverse direction, after the second PMOS tube is turned on, holes in the drift region can leak through a conduction path formed by the second PMOS tube, so that the extraction speed of the holes in the drift region can be improved, the turn-off time is shortened, and the turn-off loss is reduced.
The manufacturing method of the super-junction IGBT device provided by the invention comprises the following steps:
step one, forming a plurality of P-type columns 102 in a first N-type epitaxial layer 101, wherein N-type columns are formed by the first N-type epitaxial layer 101 between the P-type columns 102, and super junction structures are formed by alternately arranging the P-type columns 102 and the N-type columns; a superjunction unit is formed by one of the P-type columns 102 and an adjacent one of the N-type columns.
Step two, performing a front process to form a device unit structure of the super-junction IGBT device on the super-junction structure, wherein the device unit structure comprises a first NMOS tube and a second PMOS tube, and the method comprises the following sub-steps:
forming a P-doped first channel region 105 in a selected region of the top of the N-type pillar; the P-type pillars 102 are electrically isolated from the first channel region 105.
Forming a second channel region 107 of N-type doping in a selected region on top of the P-type pillar 102; the N-type pillars are electrically isolated from the second channel region 107.
Forming a first gate structure and a second gate structure; the surface of the first channel region 105 covered by the first gate structure is used to form a first channel and the surface of the second channel region 107 covered by the second gate structure is used to form a second channel.
An n+ doped emitter region 106 is formed on a surface of the first channel region 105, the emitter region 106 and the first gate structure being self-aligned.
A second drain region 108 doped with p+ is formed on the surface of the second channel region 107, and the second drain region 108 and the second gate structure are self-aligned.
The first NMOS transistor includes the first channel region 105, the first gate structure, and the emitter region 106.
The second PMOS transistor includes the second channel region 107, the second gate structure, and the second drain region 108.
In the method of the embodiment of the invention, the first gate structure and the second gate structure share the same trench gate.
The forming step of the trench gate comprises the following steps:
forming a gate trench 103, the depth of the gate trench 103 being greater than the depth of the first channel region 105 and the depth of the gate trench 103 being greater than the depth of the second channel region 107; a first side of the gate trench 103 covers the first channel region 105 and a second side of the gate trench 103 covers the second channel region 107.
A gate dielectric layer is formed on the inner side surface of the gate trench 103.
A gate conductive material layer 104 is filled in the gate trench 103.
The emitter region 106 and the first side of the gate trench 103 are self-aligned.
The second drain region 108 and the second side of the gate trench 103 are self-aligned.
In the method of the embodiment of the invention, two trench gates are included in one superjunction unit.
At the top of the N-type pillar, the first channel region 105 is located between the first sides of the two trench gates, so as to isolate the first channel region 105 from the P-type pillar 102.
At the top of the P-type pillar 102, the second channel region 107 is located between the second sides of the two trench gates, so as to isolate the second channel region 107 from the N-type pillar.
In each superjunction unit, the trench gate spans the interface between the corresponding P-type pillar 102 and the N-type pillar, the first side of the trench gate is located in the N-type pillar, and the second side of the trench gate is located in the P-type pillar 102. The step of forming the first channel region 105 and the second channel region 107 includes:
forming a P-type well located at the top region of the N-type column or located at the top region of the N-type column and extending to part or all of the region of the P-type column 102; after the trench gate formation, the first channel region 105 is formed due to the P-type well located between the first sides of the two trench gates.
Forming an N-type well, wherein the N-type well is positioned in the top area of the P-type column 102; when the P-well extends to the top of the P-pillar 102, the junction depth of the N-well is smaller than the junction depth of the P-well, and the second channel region 107 is formed by the N-well between the second sides of the trench gates.
In the method of the embodiment of the invention, the front-side process further comprises:
an interlayer film, a contact hole 111 and a front metal layer 112 are formed, and the front metal layer 112 is patterned to form an emitter and a gate.
The contact hole 111 penetrates the interlayer film.
The emitter region 106 is connected to the emitter via a top corresponding contact hole 111.
The second drain region 108 is connected to the emitter through a top corresponding contact hole 111.
The gate conductive material layer 104 is connected to the gate through a top corresponding contact hole 111.
The process for forming the contact hole 111 includes:
a contact hole 111 is formed to open.
And filling a metal layer in the opening of the contact hole 111 to form the contact hole 111.
After the opening of the contact hole 111 corresponding to the emitter region 106 is opened and after the metal is filled, the method further includes: a P + implant is performed to form a body contact region 109 and the first channel region 105 is connected through the body contact region 109 and a top contact hole 111.
Step three, carrying out a back process, which comprises the following steps:
and (5) performing a back thinning process.
Forming a collector region on the back surface of the thinned first N-type epitaxial layer 101; a drift region is formed by the first N-type epitaxial layer 101 between the first channel region 105 and the collector region.
In the method of the embodiment of the invention, the back surface process further comprises the following steps:
and forming a back metal layer on the back surface of the collector region, and forming a collector by the back metal layer.
When the device is turned on in the forward direction, the first gate structure forms the first channel and connects the emitter region 106 and the N-type column, and the first NMOS transistor is turned on; the second gate structure turns off the second channel, the second PMOS transistor turns off, and the P-type column 102 floats and thereby increases the hole carrier concentration in the drift region.
When the device is turned off reversely, the first grid structure enables the first channel to be disconnected, and the first NMOS tube is turned off; the second gate structure enables the second channel to form and connect the second drain region 108 and the P-type pillar 102, and the second PMOS transistor is turned on and realizes hole carrier discharge in the drift region.
In some embodiments, the method can also be: in each superjunction unit, the trench gate is positioned in the N-type column; in the second step, the step of forming the first channel region 105 and the second channel region 107 includes:
Forming a P-type well, wherein the P-type well is positioned in the top area of the super junction structure; after the trench gate formation, the first channel region 105 is formed due to the P-type well located between the first sides of the two trench gates.
An N-well is formed, the N-well is located at the top region of the P-type pillar 102 and extends into the N-type pillar, the junction depth of the N-well is smaller than the junction depth of the P-well, and the second channel region 107 is formed by the N-well located between the second sides of the trench gates.
In other example methods, it can also be: in each superjunction cell, the trench gate is located in the P-type column 102; in the second step, the step of forming the first channel region 105 and the second channel region 107 includes:
an N-type well is formed in the top region of the superjunction structure, and the N-type well located between the second sides of the two trench gates forms the second channel region 107.
A P-well is formed, the P-well is located in the top region of the N-type pillar and extends into the P-type pillar 102, the junction depth of the P-well is smaller than the junction depth of the N-type well, and the P-well located between the first sides of the two trench gates forms the first channel region 105.
Fig. 4 is a simulation diagram of a transfer characteristic curve of the superjunction IGBT device according to the embodiment of the invention; curve 402 is a transfer characteristic curve of the superjunction IGBT device according to the embodiment of the present invention, the voltage on the abscissa is the gate emitter junction voltage, vge, and the current on the ordinate is the collector current, ic.
Curves 401 and 403 are also shown in fig. 4 for comparison;
curve 401 is a transfer characteristic curve of the super-junction IGBT device corresponding to the second channel region 107, the second drain region 108, and the contact hole 111 at the top of the second drain region 108, which is removed on the basis of fig. 3, and the P-type pillar of the super-junction IGBT device corresponding to curve 401 is a floating arrangement, so is also called a floating P-type pillar. As shown in comparison curves 401 and 402, the difference between the two is very small, so that the forward conduction current of the device is not affected after the super-junction IGBT device is introduced into the second PMOS tube, namely after the grid-control P-type column is realized.
The curve 403 is removed on the basis of fig. 3, but the contact hole 111 at the top of the second drain region 108 remains, and it can be seen that the forward conduction current of the curve 403 is greatly reduced, because the P-type column will not float but will be grounded during forward conduction, so that the hole concentration in the drift region will leak to ground through the P-type column, so that the forward conduction current is greatly reduced.
As shown in fig. 5, a simulation curve of the collector emitter voltage (Vce) and collector current (Ic) of the superjunction IGBT device according to the embodiment of the present invention over time; in fig. 5, the abscissa indicates time, the left ordinate indicates current, and the right ordinate indicates voltage.
Curve 404a is a current time-dependent curve of the superjunction IGBT device according to the embodiment of the present invention, and curve 404b is a voltage time-dependent curve of the superjunction IGBT device according to the embodiment of the present invention;
curve 405a is a current versus time curve of the superjunction IGBT device employing a floating P-type pillar corresponding to curve 401 in fig. 4, and curve 404b is a voltage versus time curve of the superjunction IGBT device corresponding to curve 405 a.
Curve 406 is a turn off curve (turn off curve) of the superjunction IGBT device according to the embodiment of the invention, when the device is turned off, the current gradually decreases to 0A, and the voltage gradually increases to a high voltage corresponding to the operating voltage.
Curve 407 is the turn-off curve of the superjunction IGBT device corresponding to curve 405 a.
It can be seen that the turn-off time of the superjunction IGBT device of the embodiment of the invention is 4.8E-8 seconds, and the turn-off time corresponding to the curve 407 is 7.5E-8 seconds, so the turn-off speed of the superjunction IGBT device of the embodiment of the invention is faster, and the switching speed is improved by more than 36%.
As shown in fig. 6, the simulation curve of the turn-off power of the superjunction IGBT device according to the embodiment of the invention with time is formed by multiplying the voltage and the current in the turn-off process, curve 408 is the simulation curve of the turn-off power of the superjunction IGBT device according to the embodiment of the invention with time, and curve 409 is the simulation curve of the turn-off power of the superjunction IGBT device corresponding to curve 405a with time. The turn-off power multiplied by time is turn-off loss, that is, poff in curve 408 or 409 is integrated with time to obtain corresponding turn-off loss, and it can be seen that the turn-off loss of the superjunction IGBT device according to the embodiment of the invention is lower, and can be reduced by more than 20%.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (15)

1. A superjunction IGBT device, comprising:
forming a plurality of P-type columns in the first N-type epitaxial layer, forming N-type columns by the first N-type epitaxial layer among the P-type columns, and alternately arranging the P-type columns and the N-type columns to form a super junction structure; forming a superjunction unit by one P-type column and one adjacent N-type column;
A collector region doped with P type is formed on the back surface of the first N-type epitaxial layer;
the device unit structure of the super-junction IGBT device is formed on the super-junction structure and comprises a first NMOS tube and a second PMOS tube;
the first NMOS transistor comprises: a P-type doped first channel region, a first gate structure, an n+ doped emitter region; the first channel region is formed in a selected area of the top of the N-type column, and the surface of the first channel region covered by the first gate structure is used for forming a first channel; the emission region is formed on the surface of the first channel region and is self-aligned with the first gate structure; an electrical isolation between the P-type pillar and the first channel region; forming a drift region from the first N-type epitaxial layer between the first channel region and the collector region;
the second PMOS transistor includes: an N-type doped second channel region, a second gate structure and a P+ doped second drain region; the second channel region is formed in a selected region of the top of the P-type column, and the surface of the second channel region covered by the second gate structure is used for forming a second channel; the second drain region is formed on the surface of the second channel region and is self-aligned with the second gate structure; an electrical isolation between the N-type pillar and the second channel region;
When the device is conducted in the forward direction, the first grid structure enables the first channel to be formed and connect the emitting region and the N-type column, and the first NMOS tube is conducted; the second grid structure enables the second channel to be disconnected, the second PMOS tube is cut off, and the P-type column floats and accordingly hole carrier concentration in the drift region is improved;
when the device is turned off reversely, the first grid structure enables the first channel to be disconnected, and the first NMOS tube is turned off; and the second grid structure enables the second channel to form and connect the second drain region and the P-type column, and the second PMOS tube is conducted and realizes hole carrier discharge in the drift region.
2. The superjunction IGBT device of claim 1, wherein: the first grid structure and the second grid structure share the same trench gate;
the trench gate comprises a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench;
the depth of the gate trench is greater than the depth of the first channel region and the depth of the gate trench is greater than the depth of the second channel region;
the first side surface of the trench gate covers the first channel region, and the emitting region and the first side surface of the trench gate are self-aligned;
The second side surface of the trench gate covers the second channel region, and the second drain region and the second side surface of the trench gate are self-aligned;
two trench gates are included in one of the superjunction cells;
the first channel region is positioned between the first sides of the two trench gates at the top of the N-type column, so that the isolation between the first channel region and the P-type column is realized;
and the second channel region is positioned between the second sides of the two trench gates at the top of the P-type column, so that the isolation between the second channel region and the N-type column is realized.
3. The superjunction IGBT device of claim 2, wherein: in each superjunction unit, the trench gate spans the interface of the corresponding P-type column and the corresponding N-type column, a first side face of the trench gate is located in the N-type column, and a second side face of the trench gate is located in the P-type column.
4. The superjunction IGBT device of claim 2, wherein: in each superjunction unit, the trench gate is positioned in the N-type column; forming a P-type well in the top area of the super junction structure, wherein the P-type well between the first side surfaces of the two trench gates forms the first channel region; forming the second channel region in the top region of the P-type well between the second side surfaces of the two trench gates, wherein the junction depth of the second channel region is smaller than that of the P-type well;
Or, in each superjunction unit, the trench gate is located in the P-type column; forming an N-type well in the top area of the super junction structure, wherein the N-type well between the second side surfaces of the two trench gates forms the second channel region; the first channel region is formed in the top region of the N-type well between the first sides of the two trench gates, and the junction depth of the first channel region is smaller than that of the N-type well.
5. The superjunction IGBT device of claim 2, wherein: the emitting region is connected to an emitter consisting of a front metal layer through a contact hole corresponding to the top;
the second drain region is connected to the emitter through a contact hole corresponding to the top;
the grid electrode conductive material layer is connected to a grid electrode formed by the front metal layer through a contact hole corresponding to the top;
the collector region is formed with a collector electrode composed of a backside metal layer on the backside.
6. The superjunction IGBT device of claim 5 wherein: and a P+ doped body contact region is formed at the bottom of the contact hole corresponding to the emission region, and the first channel region is connected with the contact hole at the top through the body contact region.
7. The superjunction IGBT device of claim 5 wherein: when the super-junction IGBT device works, the emitter is grounded, and the collector is connected with a positive voltage;
when the device is conducted in the forward direction, the grid electrode is connected with a positive voltage; and when the device is reversely turned off, the grid electrode is connected with negative voltage.
8. The manufacturing method of the super-junction IGBT device is characterized by comprising the following steps of:
forming a plurality of P-type columns in a first N-type epitaxial layer, forming N-type columns by the first N-type epitaxial layer among the P-type columns, and alternately arranging the P-type columns and the N-type columns to form a super junction structure; forming a superjunction unit by one P-type column and one adjacent N-type column;
step two, performing a front process to form a device unit structure of the super-junction IGBT device on the super-junction structure, wherein the device unit structure comprises a first NMOS tube and a second PMOS tube, and the method comprises the following sub-steps:
forming a P-type doped first channel region in a selected region at the top of the N-type pillar; an electrical isolation between the P-type pillar and the first channel region;
forming an N-type doped second channel region in a selected region at the top of the P-type column; an electrical isolation between the N-type pillar and the second channel region;
Forming a first gate structure and a second gate structure; a surface of the first channel region covered by the first gate structure is used to form a first channel, and a surface of the second channel region covered by the second gate structure is used to form a second channel;
forming an N+ doped emission region on the surface of the first channel region, wherein the emission region and the first gate structure are self-aligned;
forming a second P+ doped drain region on the surface of the second channel region, wherein the second drain region and the second grid structure are self-aligned;
the first NMOS transistor comprises the first channel region, the first gate structure and the emission region;
the second PMOS tube comprises the second channel region, the second grid structure and the second drain region;
step three, carrying out a back process, which comprises the following steps:
carrying out a back thinning process;
forming a collector region on the back surface of the thinned first N-type epitaxial layer; forming a drift region from the first N-type epitaxial layer between the first channel region and the collector region;
when the device is conducted in the forward direction, the first grid structure enables the first channel to be formed and connect the emitting region and the N-type column, and the first NMOS tube is conducted; the second grid structure enables the second channel to be disconnected, the second PMOS tube is cut off, and the P-type column floats and accordingly hole carrier concentration in the drift region is improved;
When the device is turned off reversely, the first grid structure enables the first channel to be disconnected, and the first NMOS tube is turned off; and the second grid structure enables the second channel to form and connect the second drain region and the P-type column, and the second PMOS tube is conducted and realizes hole carrier discharge in the drift region.
9. The method for manufacturing the super-junction IGBT device according to claim 8, wherein: in the second step, the first gate structure and the second gate structure share the same trench gate;
the forming step of the trench gate comprises the following steps:
forming a gate trench, the depth of the gate trench being greater than the depth of the first channel region and the depth of the gate trench being greater than the depth of the second channel region; a first side of the gate trench covers the first channel region, and a second side of the gate trench covers the second channel region;
forming a gate dielectric layer on the inner side surface of the gate trench;
filling a gate conductive material layer in the gate trench;
in the second step, the emitting region and the first side surface of the grid electrode groove are self-aligned;
the second drain region and the second side of the gate trench are self-aligned.
10. The method for manufacturing the super-junction IGBT device according to claim 9, wherein: two trench gates are included in one of the superjunction cells;
the first channel region is positioned between the first sides of the two trench gates at the top of the N-type column, so that the isolation between the first channel region and the P-type column is realized;
and the second channel region is positioned between the second sides of the two trench gates at the top of the P-type column, so that the isolation between the second channel region and the N-type column is realized.
11. The method for manufacturing the super-junction IGBT device according to claim 10, wherein: in each superjunction unit, the trench gate spans the interface of the corresponding P-type column and the corresponding N-type column, a first side face of the trench gate is located in the N-type column, and a second side face of the trench gate is located in the P-type column;
in the second step, the step of forming the first channel region and the second channel region includes:
forming a P-type well, wherein the P-type well is positioned in the top area of the N-type column or positioned in the top area of the N-type column and extends to part or all of the area of the P-type column; after the trench gates are formed, the first channel region is formed due to the P-type well positioned between the first side surfaces of the two trench gates;
Forming an N-type well, wherein the N-type well is positioned in the top area of the P-type column; when the P-type well extends to the top of the P-type column, the junction depth of the N-type well is smaller than that of the P-type well, and the second channel region is formed by the N-type well between the second side surfaces of the two groove gates.
12. The method for manufacturing the super-junction IGBT device according to claim 10, wherein: in each superjunction unit, the trench gate is positioned in the N-type column; in the second step, the step of forming the first channel region and the second channel region includes:
forming a P-type well, wherein the P-type well is positioned in the top area of the super junction structure; after the trench gates are formed, the first channel region is formed due to the P-type well positioned between the first side surfaces of the two trench gates;
forming an N-type well, wherein the N-type well is positioned in the top area of the P-type column and extends into the N-type column, the junction depth of the N-type well is smaller than that of the P-type well, and the second channel region is formed by the N-type well positioned between the second side surfaces of the two trench gates;
or, in each superjunction unit, the trench gate is located in the P-type column; in the second step, the step of forming the first channel region and the second channel region includes:
Forming an N-type well in the top area of the super junction structure, wherein the N-type well between the second side surfaces of the two trench gates forms the second channel region;
and forming a P-type well, wherein the P-type well is positioned in the top area of the N-type column and extends into the P-type column, the junction depth of the P-type well is smaller than that of the N-type well, and the P-type well positioned between the first sides of the two trench gates forms the first channel region.
13. The method for manufacturing the super-junction IGBT device according to claim 9, wherein: in the second step, the front side process further includes:
forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form an emitter and a grid;
the contact hole penetrates through the interlayer film;
the emitter region is connected to the emitter electrode through a contact hole corresponding to the top;
the second drain region is connected to the emitter through a contact hole corresponding to the top;
the grid electrode conductive material layer is connected to the grid electrode through a corresponding contact hole at the top;
in the third step, the back surface process further includes:
and forming a back metal layer on the back surface of the collector region, and forming a collector by the back metal layer.
14. The method for manufacturing the super-junction IGBT device according to claim 13, wherein: the forming process of the contact hole comprises the following steps:
forming a contact hole opening;
filling a metal layer in the contact hole opening to form the contact hole;
after the opening of the contact hole corresponding to the emission area is opened and after the metal is filled, the method further comprises the following steps: and P+ injection is carried out to form a body contact region, and the first channel region is connected with the contact hole at the top through the body contact region.
15. The method for manufacturing the super-junction IGBT device according to claim 13, wherein: when the super-junction IGBT device works, the emitter is grounded, and the collector is connected with a positive voltage;
when the device is conducted in the forward direction, the grid electrode is connected with a positive voltage; and when the device is reversely turned off, the grid electrode is connected with negative voltage.
CN202311078030.XA 2023-08-24 2023-08-24 Super-junction IGBT device and manufacturing method thereof Pending CN116995090A (en)

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