CN116994969A - Method for forming conductive circuit of semiconductor chip package with improved package electrical property by using crystal grain layer - Google Patents
Method for forming conductive circuit of semiconductor chip package with improved package electrical property by using crystal grain layer Download PDFInfo
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- CN116994969A CN116994969A CN202310472455.2A CN202310472455A CN116994969A CN 116994969 A CN116994969 A CN 116994969A CN 202310472455 A CN202310472455 A CN 202310472455A CN 116994969 A CN116994969 A CN 116994969A
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- 229910000679 solder Inorganic materials 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 20
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 12
- 238000007639 printing Methods 0.000 claims description 5
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- 238000004528 spin coating Methods 0.000 claims description 3
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- 238000004806 packaging method and process Methods 0.000 description 17
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- 238000007772 electroless plating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
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- SLGWESQGEUXWJQ-UHFFFAOYSA-N formaldehyde;phenol Chemical compound O=C.OC1=CC=CC=C1 SLGWESQGEUXWJQ-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a method for forming a conductive circuit of a semiconductor chip package with improved package electrical property by a crystal grain layer, which comprises the steps of coating a first dielectric layer on the surface of a welding pad of a semiconductor chip, and forming a first groove on the first dielectric layer; filling conductive metal into the first groove to form a first conductive connection line; coating a second dielectric layer; forming a third groove in the second dielectric layer by utilizing positive photoresist, wherein the angle of the inner wall of the section is smaller than 90 degrees, sputtering conductive metal in the third groove to form a second conductive connection circuit, and filling conductive metal in the fourth groove of each circuit to form each third conductive connection circuit respectively; coating a third dielectric layer on the second dielectric layer and each third conducting wire; forming a fifth groove on the third dielectric layer, and filling welding spots in the fifth groove; therefore, the electrical property of the conductive connection circuit is improved, the power consumption is reduced, the process efficiency is improved, the chip package is high in density, and the whole structure is smaller.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a method for forming a conductive connection circuit of a semiconductor chip package with improved package electrical property by a crystal grain layer.
Background
Semiconductor packaging conventionally refers to the process of processing a wafer that passes testing to obtain individual chips according to product model and functional requirements. The packaging process is as follows: the wafer from the wafer front process is cut into small chips (Die) through the dicing process, then the cut chips are attached to the corresponding islands of the substrate (Lead frame) frame by glue, and then the bonding pads (bond pads) of the chips are connected to the corresponding pins (Lead) of the substrate by using ultra-fine metal (gold tin copper aluminum) wires or conductive resin, and the required circuit is formed; and then packaging and protecting the independent wafer by using a plastic shell, performing a series of operations after plastic packaging, performing finished product testing after packaging, generally performing procedures such as checking in, testing Test and packaging, and finally warehousing and delivering.
Flip chip, which is also called flip chip, is to deposit tin-lead balls on I/Opad, then flip chip is heated to replace conventional wire bonding by combining molten tin-lead balls with ceramic substrate, so that the flip chip becomes the main packaging flow in the future, and is mainly applied to CPU, GPU (graphics processor Unit), chipset and other products with high clock. Compared with COB, the chip structure and I/O terminals (solder balls) of the packaging form are downward, and the I/O terminals are distributed on the whole chip surface, so that the flip chip reaches a peak in packaging density and processing speed, and particularly, the flip chip can be processed by adopting a means similar to SMT technology, thus the packaging form is the final direction of chip packaging technology and high-density mounting. Flip chip connections have three main types C4 (controlledslapsechipconnection), DCA (Directchipattach) and FCAA (FlipChipAdhesiveAttachement).
Another important advantage of Flip-Chip packaging is electrical performance. Wire bonding processes have become a bottleneck for high frequency and certain applications, and the use of Flip-Chip packaging techniques improves electrical performance.
After the dielectric layer is used for defining the circuit, when the grain layer is sputtered, uneven and irregular sputtered particles and burrs are produced on the edge due to the fact that the sputtering is carried out on the inner edge of the dielectric layer, the uniformity of the subsequent conductive circuit constructed on the grain layer can be affected, the electric performance is weakened, and the chip power consumption is higher due to the fact that the electric property is poorer and the resistivity is higher.
Disclosure of Invention
The present invention is directed to a method for forming a conductive trace of a semiconductor chip package with improved package electrical characteristics by using a die layer, and aims to solve the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions: a method for forming conductive lines of a semiconductor chip package with improved package electrical properties by a die layer, the semiconductor chip package being mounted and bonded on a substrate to be electrically connected with a plurality of pads disposed on the substrate, comprises:
a semiconductor chip having a bonding pad surface with a plurality of bonding pads;
at least one dielectric layer coated on the surface of the bonding pad of the semiconductor chip;
and at least one conductive circuit arranged in the dielectric layer, wherein one end of each conductive circuit is electrically connected with a welding pad on the semiconductor chip, and the other end of each conductive circuit extends outwards and is exposed out of the dielectric layer to form a welding spot which can be electrically connected with a welding spot which is arranged on a substrate in advance so as to enable the semiconductor chip to be installed and combined on the substrate; the method for forming the conductive circuit comprises the following steps:
s1: coating a first dielectric layer on the surface of the bonding pad of the semiconductor chip;
s2: forming first grooves of each bonding pad on the surface of the bonding pad on the first dielectric layer by using a photoresist and adopting an exposure development mode, so that each bonding pad can be exposed outwards through each first groove;
s3: filling conductive metal into the first grooves of each circuit to form first conductive connection circuits respectively, wherein the first conductive connection circuits and the first dielectric layer form second grooves;
s4: coating a second dielectric layer on the first dielectric layer and each first conductive wire;
s5: forming a third groove exposing the first conductive line on the second dielectric layer by using positive photoresist and exposing and developing, wherein the angle between the inner wall of the section of the second dielectric layer and the upper surface of the first dielectric layer is less than 90 degrees;
s6: sputtering conductive metal on the surface of the second dielectric layer and in the third groove to form a second conductive circuit communicated with the first conductive circuit and a fourth groove respectively;
s7: performing metal stripping process treatment on the surface of the second dielectric layer to remove sputtered conductive metal;
s8: filling conductive metal into the fourth grooves of the circuits to form third conductive connection circuits respectively;
s9: coating a third dielectric layer on the second dielectric layer and each third conducting wire;
s10: forming fifth grooves connected with one end of each third conducting wire on the third dielectric layer by using a photoresist in an exposure development mode;
s11: and filling conductive metal into each fifth groove to form a welding spot which is exposed out of the dielectric layer of the third layer and can be electrically connected to each welding pad of the chip.
Preferably, the first, second and third dielectric layers are coated by spin coating.
Preferably, the conductive metal is filled in the S3, and electroless nickel gold is adopted.
Preferably, the conductive metal is filled in the S6, and electroless nickel gold is used.
Preferably, the second conductive line thickness is less than 0.5 microns.
Preferably, the solder joint exposed outside the third dielectric layer forms a hemispherical shape protruding from the outer surface of the third dielectric layer or a metal layer shape with the top parallel to the third dielectric layer.
Preferably, solder reflow printing is adopted when the welding spot is hemispherical.
Preferably, the welding spot is formed by adopting electroless nickel gold when in a metal layer form parallel to the third dielectric layer.
Compared with the prior art, the invention provides a method for forming the conductive circuit of the semiconductor chip package with improved package electrical property by using the crystal grain layer, which has the following beneficial effects:
1. the invention forms an acute angle with the first dielectric layer, wherein the angle is smaller than 90 after the second dielectric layer is exposed and developed by adopting positive photoresist; when the conductive metal (grain layer) is sputtered subsequently, particles and burrs generated by sputtering the conductive metal (grain layer) are avoided on the inner wall of the second dielectric layer; therefore, the electric property is not weakened due to uneven circuits caused by particles and burrs when other conductive connection layers are reconstructed on the die layer in the follow-up process, and the overall efficiency of the chip is affected.
2. The packaging method is beneficial to sputtering conductive metal (grain layer) on a well-defined circuit, and the sputtering conductive metal is free from exceeding the range during sputtering, so that the sputtering mode is more flexible and changeable and easy to operate.
3. The packaging method of the invention miniaturizes the traditional wirebonding and the process of flip-chip mounting on the substrate, directly makes the circuit on the wafer, minimizes the circuit and achieves the electrical optimization; and the gold wire-bonding process is saved, and the structure of the wafer flip-chip substrate is more optimized.
4. The conducting circuit is more optimized and flexible, the wiring space is larger, the utilization rate is higher, the wafer packaging is avoided from being too large, the chip packaging high density, the whole structure is smaller and more exquisite, and the finished product qualification rate is higher.
5. The welding spot and the third dielectric layer are formed by adopting electroless nickel gold when in a metal layer form parallel to each other, so that the anisotropic conductive adhesive ACF/ACP manufacturing process in the prior requirements can be met, and the application range is wider.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and together with the embodiments of the invention and do not constitute a limitation to the invention, and in which:
FIGS. 1-2 are schematic views of S1 in the forming method according to the present invention;
FIG. 3 is a schematic diagram of S2 in the forming method according to the present invention;
FIG. 4 is a schematic view of S3 in the forming method according to the present invention;
FIG. 5 is a schematic diagram of S4 in the forming method according to the present invention;
FIG. 6 is a schematic diagram of S5 in the forming method according to the present invention;
FIG. 7 is a schematic diagram of S6 in the forming method according to the present invention;
FIG. 8 is a schematic diagram of S7 in the forming method according to the present invention;
FIG. 9 is a schematic diagram of S8 in the forming method according to the present invention;
FIG. 10 is a schematic diagram of S9 in the forming method according to the present invention;
FIG. 11 is a schematic diagram of S10 in the forming method according to the present invention;
FIG. 12 is a schematic diagram of S11 (hemispherical solder joint) in the forming method according to the present invention;
FIG. 13 is a schematic diagram of S11 (metal layer form solder joint) in the forming method according to the present invention;
FIG. 14 is a schematic view of the conductive metal sputtered at the inner wall edge of the second dielectric layer after sputtering if the prior art is used for forming S5 and S6 in the forming method according to the present invention;
in fig. 1-14: 10. semiconductor chip 11, bond pad 12, bond pad surface 20, first dielectric layer 21, first recess 22, first conductive trace 23, second recess 30, second dielectric layer 31, third recess 32, second conductive trace 33, fourth recess 34, excess conductive metal 35, third conductive trace 36, partially conductive metal 40, third dielectric layer 41, fifth recess 51, bond pad
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-10, the present invention provides the following technical solutions: a method for forming conductive lines of a semiconductor chip package with improved package electrical properties by a die layer, the semiconductor chip package being mounted and bonded on a substrate to be electrically connected with a plurality of pads disposed on the substrate, comprises:
a semiconductor chip (Die) 10 having a pad surface (Diepad) 12, the pad surface (Diepad) 12 being provided with a plurality of pads (Diepad) 11;
at least one dielectric layer (diectriclayer) coated on the pad surface (diepad) 12 of the semiconductor chip (Die) 10;
and at least one conductive circuit disposed in the dielectric layer, wherein one end of each conductive circuit is electrically connected to a pad (Diepad) 11 on the semiconductor chip (Die) 10, and the other end extends outwards and is exposed out of the dielectric layer to form a solder joint (Solderbeam) for being electrically connected to a solder joint pre-arranged on a substrate (not shown) so as to mount and combine the semiconductor chip (Die) 10 on the substrate; generally, when N bonding pads 11 are disposed on the bonding pad surface 12 of the semiconductor chip 10, N conductive traces separated from each other are properly disposed in the dielectric layer, so that one ends of the N conductive traces are electrically connected to one bonding pad 11 of the semiconductor chip 10, and the other ends of the N conductive traces extend outwards and are exposed outside the dielectric layer to form N bonding pads separated from each other for being electrically connected to N bonding pads disposed on a substrate (not shown).
The semiconductor chip package structure of the present embodiment is illustrated by taking a single semiconductor chip (Die) 10 in a Wafer (Wafer), and a plurality of pads (Die) 11 are typically disposed on the semiconductor chip (Die) 10, and one of the pads 11 of the semiconductor chip (Die) 10 is illustrated but not limited in the present embodiment.
Referring to fig. 1-10, wherein a cross-sectional view of the semiconductor chip (Die) 10 of fig. 1, a bonding pad (Die pad) 11 is shown, the method for forming the conductive trace comprises the steps of:
referring to fig. 1-2, S1: a first dielectric layer (1 st dielectric layer) 20 is coated on a pad surface (Diepad surface) 12 of a semiconductor chip (Die) 10; the first dielectric layer (1 st dielectric) 20 may be applied by spin coating, which is a prior art and is not described herein;
referring to fig. 3, S2: forming a first recess 21 corresponding to each pad 11 on the pad surface 12 on the first dielectric layer (1 st dielectric layer) 20 by using a photoresist (photoresist) such as epoxy (epoxy) or other resin, so that each pad 11 can be exposed;
referring to fig. 4, S3: filling a conductive metal layer, such as nickel-gold material, on each bonding pad 11 exposed in each first groove 21 of each circuit to serve as a protective layer of each bonding pad 11 and also serve as a conductive layer; to form each first conductive line 22;
referring to fig. 5, S4: a second dielectric layer (2 nd dielectric layer) 30 is coated on the first dielectric layer (1 st dielectric layer) 20 and each first conductive trace 22; similar to step S1, further description is omitted.
Referring to fig. 6, S5: forming a third groove 31 exposing the first conductive line 22 on the second dielectric layer (2 nd dielectric layer) 30 by using a positive photoresist (posivephosphor) such as phenol formaldehyde of a novolac resin and exposing and developing the third groove in the second dielectric layer (2 nd dielectric layer) 30, wherein the inner wall of the cross section of the second dielectric layer (2 nd dielectric layer) 30 forms an acute angle of <90 ° with the upper surface of the first dielectric layer (1 st dielectric layer) 2 due to the characteristics of the positive photoresist (posivephosphor);
referring to fig. 7, S6: sputtering (sputtering) a conductive metal (e.g., nickel-gold material or silver paste printing (silver paste printing) and other conductive metals on the surface of the second dielectric layer (2 nd dielectric layer) 30 and in the third groove 31 to form a second conductive line 32 (which is a uniform thin layer with a thickness of less than about 0.5 μm) in communication with the first conductive line 22, and forming a fourth groove 33;
referring to fig. 8, S7: performing metal stripping process (metal lift-off technology) on the surface of the second dielectric layer (2 nd dielectric layer) 30 to remove sputtered conductive metal (part of conductive metal 36);
referring to fig. 9, S8: filling the fourth grooves 33 of each line with a conductive metal such as nickel-gold (nickel-gold) to form each third conductive line 35, wherein the conductive metal is deposited in the fourth grooves 33 and is also uniformly deposited in the acute angle formed in S5;
referring to fig. 14, if the second dielectric layer (2 nd dielectric layer) 30 is formed by the prior art in steps S5 and S6, the inner wall edge of the second dielectric layer (2 nd dielectric layer) is sputtered (sputtered) to a portion of the conductive metal 36, and the portion of the conductive metal 36 is distributed on the inner wall in an uneven and relatively irregular (particle and burr) manner, which may lead to uneven cross section of the conductive metal after the conductive metal is filled in the third conductive line 35 in step S8, which may lead to increased resistance and thus reduced conductive performance. In the step S5, the inner wall of the cross section of the second dielectric layer (2 nd Dielectriclayer) 30 and the upper surface of the first dielectric layer (1 st dielectric layer) 2 form an acute angle of <90 °, and in the step S6, a part of the conductive metal 36 on the sputtered layer can be avoided, so that the reduced conductive performance of the third conductive line 35 due to the uneven cross section is avoided.
Referring to fig. 10, S9: a third dielectric layer (3 rd dielectric layer) 40 is coated on the second dielectric layer (2 nd dielectric layer) 30 and each third conductive trace 35, which is similar to steps S1 and S4 and will not be described again;
referring to fig. 11, S10: forming fifth grooves 41 connected to one end of each third conductive line 35 on the third dielectric layer (3 rd dielectric layer) 40 by using a photoresist (photoresist) such as epoxy (epoxy) or other resin, respectively, and exposing and developing;
referring to fig. 12, S11: then, the fifth grooves 41 are filled with conductive metal by various conventional methods to form a solder joint (solderboss) 51 and expose the solder joint (solderboss) 51 on the third dielectric layer (3 rdDielectric layer) 40 outside the third dielectric layer (3 rd Dielectriclayer) so that the solder joint (solderboss) 51 is exposed for being electrically connected to the pads (Diepad) 11 of the semiconductor chip (Die) 10.
Preferably, electroless nickel gold (electroless plating) or other conductive metal is used for S3 and S6.
The shape of the solder joint (solderbeam) 51 is not limited and may be set according to the structural requirements or the process equipment.
Preferably, the solder joint (solderboss) 51 exposed outside the third dielectric layer (3 rd dielectric layer) 40 forms a hemispherical shape protruding from the outer surface of the third dielectric layer (3 rdDielectric layer) 40 or a metal layer shape with the top parallel to the third dielectric layer (3 rdDielectric layer) 40.
Preferably, solder reflow printing is used when solder joints (solderbeam) 51 are hemispherical in shape.
Preferably, the solder joint (solderbeam) 51 is formed using electroless nickel (electroless plating) in a metal layer configuration parallel to the third dielectric layer (3 rd dielectric layer) 40 to more fully meet the bonding with the different conductive materials.
Referring to fig. 1 to 14 again, the first, second and third conductive traces that each Solder joint (solderboss) 51 communicates with, constitute a conductive trace provided on the pad surface 12 of the semiconductor chip 10 in the semiconductor chip package structure of the present invention, such that one end of each conductive trace is electrically connected to one pad 11 on the chip 10, and the other end is connected to a Solder joint (solderpoint) 51 that extends outwards and is exposed outside the third dielectric layer (3 rd Dielectriclayer) 40, such that each Solder joint (solderboss) 51 can be electrically connected to each pad 11 of the semiconductor chip 10, respectively, and can be electrically connected to a Solder joint (not shown) laid in advance on a substrate (not shown) so as to mount and bond the semiconductor chip 10 on the substrate; in addition, the dielectric layers in the embodiment are the first, second and third dielectric layers, the thickness is not limited, and the thickness can be set according to the structural requirement or the manufacturing equipment; also, the thicknesses of the first, second, and third conductive paths are not particularly limited.
The forming method of the invention is not affected by the position of the welding pad 11 in the X axis direction on the vertical section (as shown in figure 1) of the semiconductor chip 10; for example, when the area of the bonding pad surface 12 is too small to be laid out or when the process and equipment are difficult to be matched, the X-axis positions of the different bonding pads 11 are different, and the forming method of the invention can be used for packaging.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A method for forming conductive lines of a semiconductor chip package with improved package electrical properties by a die layer, the semiconductor chip package being mounted and bonded on a substrate to be electrically connected with a plurality of pads disposed on the substrate, comprises:
a semiconductor chip having a bonding pad surface with a plurality of bonding pads;
at least one dielectric layer coated on the surface of the bonding pad of the semiconductor chip;
and at least one conductive circuit arranged in the dielectric layer, wherein one end of each conductive circuit is electrically connected with a welding pad on the semiconductor chip, and the other end of each conductive circuit extends outwards and is exposed out of the dielectric layer to form a welding spot which can be electrically connected with a welding spot which is arranged on a substrate in advance so as to enable the semiconductor chip to be installed and combined on the substrate; the method for forming the conductive connection circuit is characterized by comprising the following steps:
s1: coating a first dielectric layer on the surface of the bonding pad of the semiconductor chip;
s2: forming first grooves of each bonding pad on the surface of the bonding pad on the first dielectric layer by using a photoresist and adopting an exposure development mode, so that each bonding pad can be exposed outwards through each first groove;
s3: filling conductive metal into the first grooves of each circuit to form first conductive connection circuits respectively, wherein the first conductive connection circuits and the first dielectric layer form second grooves;
s4: coating a second dielectric layer on the first dielectric layer and each first conductive wire;
s5: forming a third groove exposing the first conductive line on the second dielectric layer by using positive photoresist and exposing and developing, wherein the angle between the inner wall of the section of the second dielectric layer and the upper surface of the first dielectric layer is less than 90 degrees;
s6: sputtering conductive metal on the surface of the second dielectric layer and in the third groove to form a second conductive circuit communicated with the first conductive circuit and a fourth groove respectively;
s7: performing metal stripping process treatment on the surface of the second dielectric layer to remove sputtered conductive metal;
s8: filling conductive metal into the fourth grooves of the circuits to form third conductive connection circuits respectively;
s9: coating a third dielectric layer on the second dielectric layer and each third conducting wire;
s10: forming fifth grooves connected with one end of each third conducting wire on the third dielectric layer by using a photoresist in an exposure development mode;
s11: and filling conductive metal into each fifth groove to form a welding spot which is exposed out of the dielectric layer of the third layer and can be electrically connected to each welding pad of the chip.
2. The method of forming conductive traces of a die attach layer-enhanced packaged electrical semiconductor die package of claim 1, wherein: the first, second and third dielectric layers are coated by spin coating.
3. The method of forming conductive traces of a die attach layer-enhanced packaged electrical semiconductor die package of claim 1, wherein: and S3, filling conductive metal, and adopting electroless nickel gold.
4. The method of forming conductive traces of a die attach layer-enhanced packaged electrical semiconductor die package of claim 1, wherein: and S6, filling conductive metal, and adopting electroless nickel gold.
5. The method of forming conductive traces of a die attach layer-enhanced packaged electrical semiconductor die package of claim 1, wherein: the second conductive line thickness is less than 0.5 microns.
6. The method of forming conductive traces of a die attach layer-enhanced packaged electrical semiconductor die package of claim 1, wherein: the welding spots exposed outside the third dielectric layer form a hemispherical shape protruding out of the outer surface of the third dielectric layer or a metal layer shape with the top parallel to the third dielectric layer.
7. The method of forming conductive traces of a die attach layer-enhanced packaged electrical semiconductor die package of claim 6, wherein: and when the welding spots are hemispherical, adopting solder reflow printing.
8. The method of forming conductive traces of a die attach layer-enhanced packaged electrical semiconductor die package of claim 6, wherein: the welding spots are formed by adopting electroless nickel gold when in a metal layer form parallel to the third dielectric layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310472455.2A CN116994969A (en) | 2023-04-27 | 2023-04-27 | Method for forming conductive circuit of semiconductor chip package with improved package electrical property by using crystal grain layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310472455.2A CN116994969A (en) | 2023-04-27 | 2023-04-27 | Method for forming conductive circuit of semiconductor chip package with improved package electrical property by using crystal grain layer |
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| CN116994969A true CN116994969A (en) | 2023-11-03 |
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| CN202310472455.2A Pending CN116994969A (en) | 2023-04-27 | 2023-04-27 | Method for forming conductive circuit of semiconductor chip package with improved package electrical property by using crystal grain layer |
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