CN116991780A

CN116991780A - Data processing system and method based on PCIe bus and storage medium

Info

Publication number: CN116991780A
Application number: CN202311014090.5A
Authority: CN
Inventors: 张天发
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-08-11
Filing date: 2023-08-11
Publication date: 2023-11-03

Abstract

The embodiment of the application provides a data processing system and method based on a PCIe bus and a storage medium, wherein the system comprises the following components: the method comprises the steps that a processor, a PCIe bus, an FPGA component and a Flash memory are used for generating a data processing request, wherein the data processing request is a request supporting PCIe bus transmission; the PCIe bus is connected with the processor and the FPGA component; the FPGA component receives a data processing request sent by a processor through a PCIe bus, and converts the data processing request into a target data processing request, wherein the target data processing request is a data request identifiable by a FLASH memory; the FLASH memory receives a target data processing request transmitted by the FPGA component. The application solves the problem that the data processing speed of the Flash memory in the related technology can not meet the data processing speed of the processor.

Description

Data processing system and method based on PCIe bus and storage medium

Technical Field

The embodiment of the application relates to the field of computers, in particular to a data processing system and method based on a PCIe bus and a storage medium.

Background

The embedded Flash memory is a low-speed memory device compared to the higher operating frequency of the processor, and since the 80 s of the 20 th century, the processor performance has been improved at a rate of 60% per year, with an improvement in memory access time of approximately 7% per year. Compared with a processor, the performance of the Flash memory can be improved by parallel instruction sets, superscalar design and large-scale use of registers, and the improvement of the performance of the Flash memory can only depend on methods such as process improvement. For example, in the prior art, the flow of Flash memory access includes: 1) The host system sends a read or write command and associated address and data to the controller of the Flash memory. 2) The controller parses the instruction and performs the corresponding operation. For a read operation, the controller sends a read request to the memory chip and transmits the read data back to the host system. For a write operation, the controller writes data to the corresponding location of the memory chip. 3) The controller performs data transmission and communication with the host system through the I/O interface. This may involve data caching, error detection and correction, and transport protocol operations. Therefore, the speed of the Flash memory reading process in the prior art can not meet the requirement of the CPU processing speed.

In view of the above technical problems, no effective solution has been proposed in the related art.

Disclosure of Invention

The embodiment of the application provides a data processing system and method based on a PCIe bus and a storage medium. At least solving the problem that the data processing speed of the Flash memory in the related art can not meet the data processing speed of the processor.

According to one embodiment of the application, there is provided a PCIe bus-based data processing system including: the device comprises a processor, a PCIe bus, an FPGA component and a FLASH memory, wherein the processor is used for generating a data processing request, and the data processing request is a request supporting the PCIe bus transmission; the PCIe bus is used for connecting the processor and the FPGA component; the FPGA component is used for receiving the data processing request sent by the processor through the PCIe bus and converting the data processing request into a target data processing request, wherein the target data processing request is a data request identifiable by the FLASH memory; and the FLASH memory is used for receiving the target data processing request transmitted by the FPGA component and executing data processing operation according to the target data processing request.

In one exemplary embodiment, the FPGA component includes: the device comprises a PCIe interface, a PCIe protocol conversion module and a FLASH controller, wherein the PCIe interface is used for receiving the data processing request sent by the processor through the PCIe bus and transmitting a TLP data packet to the PCIe protocol conversion module according to the transmission protocol of the PCIe bus, and the TLP data packet comprises the data processing request; the PCIe protocol conversion module is configured to convert the TLP packet into a target request signal through an FPGA bus; and the FLASH controller is used for converting the target request signal transmitted by the FPGA bus into the target data processing request and sending the target data processing request to the FLASH memory.

In an exemplary embodiment, the PCIe protocol conversion module is further configured to determine a data format and a data type of the TLP packet, determine data processing contents of the TLP packet based on the data format and the data type, and send a data request to the FPGA bus according to the data processing contents, where, when the TLP packet is a write data request, the PCIe protocol conversion module is configured to record a write address of data to be written in the TLP packet, buffer the data to be written, and send the write data request to the FPGA bus; when the TLP packet is a read data request, the PCIe protocol conversion module is configured to record a read address in the TLP packet, and send the read data request to the FPGA bus, where the data request includes the write data request and the read data request.

In an exemplary embodiment, the FPGA bus is configured to adjust, according to the data processing content corresponding to the data request, a signal state of an interface in the FPGA bus, and generate the target request signal.

In an exemplary embodiment, the FPGA bus is configured to adjust a chip select signal and a write signal of a write data interface in the interfaces when the data request is the write data request, and set data to be written in the TLP data on the write data interface to obtain the target request signal; or, the FPGA bus is configured to adjust a chip select signal and a read signal of a read data interface in the upper interface when the data request is the read data request, and set a read address in the TLP data on the read data interface, so as to obtain the target request signal.

In an exemplary embodiment, the FLASH controller includes a register, and a request processing state machine, where the register is configured to cache the target request signal; the request processing state machine is used for converting the target request signal into the target data processing request corresponding to the request type according to the request type of the target request signal, and sending the target data processing request into a corresponding memory in the FLASH memory.

According to another embodiment of the present application, there is provided a data processing method based on a PCIe bus, including: receiving a data processing request sent by a processor through a PCIe bus, wherein the data processing request is a request for supporting the PCIe bus transmission, and the data processing request is generated by the processor; converting the data processing request into a target data processing request, wherein the target data processing request is a data request identifiable by a FLASH memory; and sending the target data processing request to the FLASH memory to instruct the FLASH memory to execute data processing operation according to the target data processing request.

In one exemplary embodiment, converting the data processing request into a target data processing request includes: transmitting a TLP packet to the PCIe protocol conversion module through a PCIe interface, where the TLP packet includes the data processing request, and the TLP packet is determined according to a transmission protocol of the PCIe bus, where the PCIe interface is disposed on the PCIe bus; converting the TLP data packet into a target request signal through an FPGA bus in the PCIe protocol conversion module; and converting the target request signal into the target data processing request through a FLASH controller, wherein the FLASH controller is connected with the FPGA bus.

In an exemplary embodiment, before converting the TLP packet into the target request signal through the FPGA bus in the PCIe protocol conversion module, the method further includes: determining a data format and a data type of the TLP data packet through the PCIe protocol conversion module, determining data processing content of the TLP data packet based on the data format and the data type of the TLP data packet, and sending a data request to the FPGA bus according to the data processing content; when the TLP data packet is a data writing request, recording a writing address of data to be written in the TLP data packet through the PCIe protocol conversion module, caching the data to be written, and sending the data writing request to the FPGA bus; when the TLP packet is a read data request, recording, by the PCIe protocol conversion module, a read address in the TLP packet, and sending the read data request to the FPGA bus, where the data request includes the write data request and the read data request.

In an exemplary embodiment, converting the TLP packet into the target request signal through the FPGA bus in the PCIe protocol conversion module includes: and adjusting the signal state of an interface in the FPGA bus according to the data processing content corresponding to the data request through the FPGA bus to generate the target request signal.

In an exemplary embodiment, the adjusting, by the FPGA bus, a signal state of an interface in the FPGA bus according to data processing content corresponding to the data request, to generate the target request signal includes: when the data request is the data writing request, adjusting a chip selection signal and a writing signal of a data writing interface in the interfaces through the FPGA bus, and setting data to be written in the TLP data on the data writing interface to obtain the target request signal; when the data request is the read data request, the chip select signal and the read signal of the read data interface in the interfaces are adjusted through the FPGA bus, and the read address in the TLP data is set on the read data interface, so as to obtain the target request signal.

In one exemplary embodiment, receiving a data processing request sent by a processor over a PCIe bus includes: and receiving the data processing sent by the processor through a PCIe interface, wherein the PCIe interface is arranged on the PCIe bus.

According to a further embodiment of the application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the application there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

According to the application, the data processing request is transmitted between the processor and the FPGA component through the PCIe bus, so that the aim of rapidly transmitting the data processing request can be fulfilled. And an FPGA component is arranged between the processor and the FLASH memory, and the FPGA component is used for converting the data processing request and then transmitting the data processing request to the FLASH memory to execute the data processing operation, so that the FLASH memory is not required to convert the data processing request, and the speed of processing the data by the FLASH memory is further increased. Therefore, the problem that the data processing speed of the Flash memory cannot meet the data processing speed of the processor in the related technology can be solved, and the effect of improving the data processing speed of the Flash memory to meet the high-speed processing requirement of the processor is achieved.

Drawings

FIG. 1 is a block diagram of the hardware architecture of a PCIe bus-based data processing system in accordance with an embodiment of the present application;

FIG. 2 is a block diagram of a PCIe interface transport hierarchy in accordance with an embodiment of the present application;

FIG. 3 is a schematic diagram of the structure of a Flash controller strobe signal according to an embodiment of the present application;

FIG. 4 is a block diagram of a particular architecture of a PCIe bus-based data processing system in accordance with an embodiment of the present application;

FIG. 5 is a block diagram of the hardware architecture of a mobile terminal for a PCIe bus-based data processing method in accordance with an embodiment of the present application;

FIG. 6 is a flowchart of a method for PCIe bus-based data processing in accordance with an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

First, the related art related to the present application will be described:

PCIe (Peripheral Component Interconnect express): high-speed serial computer expansion bus standard;

AGP (Accelerated Graphics Port): accelerating an image interface;

flash (Flash memory): an electronic erasable programmable read-only memory;

NOR Flash: a nonvolatile flash memory technology;

EPROM (Erasable Programmable Read-Only-Memory): an electrically programmable read only memory;

FPGA (Field Programmable Gate Array): a field programmable gate array;

DMA (Direct Memory Access): direct memory access;

TLP (Transaction Layer Packet): PCIe transport layer packets;

axi4_stream interface: for transmitting high-speed data streams;

FMT and Type fields: the bus transaction currently used by the TLP may be validated;

CE (Chip Select) signal: chip select signal.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

In this embodiment, a PCIe bus-based data processing system running on a mobile terminal is provided, and fig. 1 is a hardware structural block diagram of a PCIe bus-based data processing system according to an embodiment of the present application, as shown in fig. 1, where the system includes:

processor, PCIe bus, FPGA component, FLASH memory, wherein,

a processor for generating a data processing request, wherein the data processing request is a request to support PCIe bus transmission;

PCIe bus for connecting the processor and FPGA components;

the FPGA component is used for receiving a data processing request sent by the processor through the PCIe bus and converting the data processing request into a target data processing request, wherein the target data processing request is a data request identifiable by the FLASH memory;

And the FLASH memory is used for receiving the target data processing request transmitted by the FPGA component and executing data processing operation according to the target data processing request.

According to the system, the data processing request is transmitted between the processor and the FPGA component through the PCIe bus, so that the aim of rapidly transmitting the data processing request can be fulfilled. And an FPGA component is arranged between the processor and the FLASH memory, and the FPGA component is used for converting the data processing request and then transmitting the data processing request to the FLASH memory to execute the data processing operation, so that the FLASH memory is not required to convert the data processing request, and the speed of processing the data by the FLASH memory is further increased. Therefore, the problem that the data processing speed of the Flash memory cannot meet the data processing speed of the processor in the related technology can be solved, and the effect of improving the data processing speed of the Flash memory to meet the high-speed processing requirement of the processor is achieved.

Alternatively, the processor may be a device with processing capability, e.g. CPU, GPU, microprocessor (Advanced RISC Machine, abbreviated as ARM) divided into: the system comprises a classical ARM processor, an ARM Cortex embedded processor, an ARM Cortex real-time embedded processor, an ARM Cortex application embedded processor and an ARM Cortex expert processor.

Optionally, the PCIe bus includes multiple types of buses, including, for example, but not limited to, any bus between PCI Express x1 and PCI Express x32, capable of meeting the transmission needs of low-speed devices and high-speed devices that occur at a time in the future.

Alternatively, the Flash memory may be any type of memory with storage capabilities, such as NOR Flash. According to the internal architecture and implementation technology, the memory can be divided into nonvolatile memory, nonvolatile flash memory and other types of memories.

Optionally, the FPGA component is a programmable logic array, so that the problem of fewer gates of the original device can be effectively solved. Basic structure of FPGA: the programmable memory comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block random access memory RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional unit.

In one exemplary embodiment, an FPGA component includes: PCIe interface, PCIe protocol conversion module, FLASH controller, wherein,

the PCIe interface is used for receiving the data processing request sent by the processor through the PCIe bus and transmitting the TLP data packet to the PCIe protocol conversion module according to the transmission protocol of the PCIe bus, wherein the TLP data packet comprises the data processing request;

The PCIe protocol conversion module is used for converting the TLP data packet into a target request signal through the FPGA bus;

the FLASH controller is used for converting the target request signal transmitted by the FPGA bus into a target data processing request and sending the target data processing request to the FLASH memory.

Alternatively, the PCIe interface may be an axi4_stream bus protocol interface, and the data processing request may be a complete TLP packet.

Optionally, in a specific embodiment, based on the PCIe bus protocol, the PCIe interface may adopt a design manner of a transport hierarchy, as shown in fig. 2, and may be divided into 4 layers from top to bottom, which are an application layer, a transaction layer, a data link layer, and a physical layer respectively; transport layering can be divided into 3 layers, a transaction layer, a data link layer, and a physical layer, respectively. The data transmission between the CPU and the FPGA is four-wire transmission.

Optionally, the PCIe interface includes a variety of interface cores. For example, the PCIe interface may choose the IP core (PCIe interface core) that the interface transmits as a transport layer packet TLP. Mainly because many functions in the PCIe protocol are not required in the design, the IP core can analyze on demand. The PCIe interface core is a core with simple functions, is suitable for cutting part of functions contained in the PCIe protocol on the basis of the core, and avoids resource waste on the FPGA component.

Optionally, PCIe interfaces may be categorized into the following:

universal interface: including clock signals, reset signals, PCIe bus signals, etc.

And (3) a transmitting interface: including PCIe bus data transmit interfaces. The PCIe bus data sending interface is an axi4_stream bus protocol interface, and data to be sent is a complete TLP packet.

Receiving interface: including PCIe bus data receiving interfaces. The PCIe bus data receiving interface is an axi4_stream bus protocol interface, and the data to be received is a complete TLP packet.

Physical layer interface: allowing the user to view and control the status of the connection Link.

Configuration interface: allowing the user to view the PCIe configuration space when the PCIe interface is the end node.

Interrupt interface: for controlling the transmission of interrupts, etc.

Error reporting interface: for providing error information recorded by the PCIe interface.

Dynamic configuration interface: allowing the user to dynamically alter the parameter configuration of the PCIe interface. Optionally, in this embodiment, the sending interface and the receiving interface in the PCIe interface may be an axi4_stream interface, where the data bit width of the PCIe interface is 64 bits. The data packet is transmitted and received by adopting a big end arrangement specified by PCIe protocol.

The data processing request transmitted by the PCIe bus can be received quickly through the PCIe interface connected in the FPGA component. The PCIe interface core is a core with simple functions, is suitable for cutting part of functions contained in the PCIe protocol on the basis of the core, and avoids resource waste on an FPGA chip.

Optionally, the PCIe protocol conversion module is further configured to determine a data format and a data type of the TLP packet, determine data processing contents of the TLP packet based on the data format and the data type, and send a data request to the FPGA bus according to the data processing contents, where, when the TLP packet is a write data request, the PCIe protocol conversion module is configured to record a write address of data to be written in the TLP packet, buffer the data to be written, and send the write data request to the FPGA bus; when the TLP packet is a read data request, the PCIe protocol conversion module is configured to record a read address in the TLP packet, and send the read data request to the FPGA bus, where the data request includes the write data request and the read data request.

Optionally, the data format and TYPE (format FMT and TYPE) of the TLP packet are shown in table 1:

table 1:

optionally, in a specific embodiment, the PCIe protocol conversion module converts the TLP packet received by the PCIe interface to a data request transmitted by the FPGA bus specifically as follows:

the PCIe protocol conversion module analyzes the contents of the FMT and the TYPE according to the TLP data packet received from the PCIe interface, and judges the format and the TYPE of the TLP data packet according to the contents of the FMT and the TYPE; determining whether the received TLP data packet is a read data request or a write data request according to the format and type of the TLP data packet; if the TLP packet contains data, it is necessary to determine where the data is located in the TLP packet. If the TLP packet is a data writing request, an access address included in the TLP packet is recorded, data in the subsequently received TLP packet is cached, and a state of the DW BE is recorded, and is used when the FPGA bus is sent. After the TLP packet is received, a write data request operation is initiated to the FPGA bus. If the received request is a read data request, the access address of the TLP data packet is recorded, and the read data request is initiated to the FPGA bus. And simultaneously notifying a TLP data packet sending module, and preparing a packet header of a response data packet according to the packet header content of the received TLP data reading request. The PCIe protocol conversion module comprises a buffer area, and the FPGA bus stores the received effective data into the buffer area. When the FPGA bus receives complete response data from the FLASH memory, the response data are filled into a data area of the response data packet, and the response data packet is sent to the PCIe interface.

In this embodiment, the PCIe protocol conversion module converts the data processing request, so that correctness and validity of the TLP packet are guaranteed.

In an exemplary embodiment, the FPGA bus is configured to adjust a signal state of an interface in the FPGA bus according to a data processing content corresponding to the data request, and generate the target request signal.

Optionally, the FPGA bus is configured to adjust a chip select signal and a write signal of a write data interface in the interfaces when the data request is the write data request, and set data to be written in the TLP data on the write data interface, so as to obtain the target request signal; or, the FPGA bus is configured to adjust a chip select signal and a read signal of a read data interface in the interfaces when the data request is the read data request, and set a read address in the TLP data on the read data interface to obtain the target request signal.

Optionally, in a specific embodiment, the FPGA bus supports both single-beat read-write access in the data request and continuous Burst read-write access in the data request, and may be hooked up to various hardware resources inside the cpu_fpga. The signal definition of the FPGA bus is shown in table 2:

Table 2:

when the TLP packet is a write DATA request, the FPGA bus interface sets the cs_n signal and the wr_n signal low, and places the 1 st write DATA on the wr_data interface, and places the address information on the ADDR interface. If the length of the write DATA request received IN the TLP packet exceeds the DATA width of the FPGA bus wr_data, the burst_ N, BUSRT _start_n signal is set low at the same time, and the DATA length to be transmitted is put on the burst_index interface, the burst_start_n continues for only one beat, the burst_in-DEX signal is effectively decremented as the wr_ack_n signal becomes low, the ADDR signal is effectively incremented as the wr_ack_n signal becomes low, and the wr_data signal is effectively updated as the wr_ack_n signal becomes low. This BURST write operation transmission ends when the burst_index signal decreases to 0.

When the TLP packet is a read data request, the FPGA bus interface sets the cs_n signal and the rd_n signal low, and puts the read address information on the ADDR interface. If the received read DATA length in the TLP packet exceeds the DATA width of the FPGA bus rd_data, the burst_ N, BUSRT _start_n signal is set low at the same time, and the DATA length to be received is put on the burst_index interface, where the burst_start_n is only one beat, and the burst_index signal decreases with the clock cycle and the ADDR signal increases with the clock cycle. When the burst_index signal decreases to 0, this BURST read operation request transmission ends.

Optionally, after cs_n and rd_n are both low, starting to monitor the state of the rd_ack_n signal; when RD_ACK_N is active low, it indicates that the DATA on the RD_DATA interface is the corresponding valid read DATA. And after the FPGA bus receives the complete reading response number, ending the reading operation.

The embodiment realizes the control of signals and the correct reception of data through the conversion of the TLP data packet and the FPGA bus interface.

Optionally, in a specific embodiment, the Flash controller mainly completes conversion from FPGA bus requests to NOR requests. In this embodiment, the Flash memory includes 4 slices of NOR Flash, and the data width of each slice of NOR Flash is 16 bits. The 4-chip NOR Flash shares a group of address lines and partial control signals, and realizes word enabling read-write access of 64-bit data through gating of CE signals. The structure of the Flash controller strobe signal is shown in FIG. 3.

When executing the data processing request of the read operation, the Flash controller cannot continuously reply the read data to the FPGA bus because the read period of the Flash controller is longer than the frequency of the internal processing of the FPGA bus. Therefore, in the Flash controller, after receiving a read data request initiated by an FPGA bus, the Flash controller latches address information and Burst related information of the read data request; and sequentially sending read data requests to an external Flash memory according to the latched address and the Burst length (if the request is a Burst request) so as to acquire read data. In order to improve the read access speed, when a Burst read data request is performed, a plurality of independent read data requests sent to the NOR Flash chip are combined into a plurality of page read data requests, so that the data reading time of the NOR Flash can be greatly reduced, and the reading efficiency is improved.

When a data processing request of a writing operation is executed, the writing operation is carried out on a single NOR Flash chip, and a writing operation sequence of the corresponding chip needs to be executed, namely, fixed operands need to be written into fixed addresses in the FLASH memory before expected data is written into the expected addresses. Similar to the write operation, the erase operation on a single NOR Flash chip requires that the sequence of erase operations on the corresponding chip be performed, i.e., that a fixed operand be written to some fixed address before the data of the intended sector is erased.

In performing the data processing request of the erase operation, similar to the data processing request of the write operation, the erase operation is performed on a single NOR Flash chip, and the sequence of the erase operation of the corresponding chip needs to be performed, i.e. a fixed operand needs to be written to some fixed address before the data of the intended sector is erased. This operation is similar to the Flash write operation and will not be described again here.

The embodiment uses the read operation, the write operation and the erase operation of the NOR Flash chip. The conversion from FPGA bus requests to NOR requests is realized.

Optionally, in a specific embodiment, as shown in fig. 4, in a case that the processor is a CPU and the FLASH memory is a NOR FLASH, the interaction procedure between the CPU, the PCIe bus, each component in the FPGA component, and the FLASH memory is as follows: the CPU performs data calculation first and obtains result data to be stored in the NOR Flash. The data is then transferred to the FPGA component over the PCIe bus. And a PCIe interface in the FPGA component receives the PCIe request sent by the processor and transmits the request command, the address and the data to the interior of the FPGA component. And a PCIe protocol conversion module in the FPGA component analyzes the request and acquires the command, the address and the data information. According to the analysis result, flash in the FPGA generates a read-write control signal for an external NOR Flash memory.

The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking the mobile terminal as an example, fig. 5 is a block diagram of a hardware structure of a mobile terminal according to a PCIe bus-based data processing method according to an embodiment of the present application. As shown in fig. 5, the mobile terminal may include one or more processors 502 (only one is shown in fig. 5) (the processor 502 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 504 for storing data, wherein the mobile terminal may further include a transmission device 506 for communication functions and an input-output device 508. It will be appreciated by those skilled in the art that the structure shown in fig. 5 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 5, or have a different configuration than shown in fig. 5.

The memory 505 may be used to store a computer program, for example, a software program of an application software and a module, such as a computer program corresponding to a PCIe bus-based data processing method in an embodiment of the present application, and the processor 502 executes the computer program stored in the memory 505 to perform various functional applications and data processing, that is, implement the above-mentioned method. Memory 505 may include high-speed random access memory, but may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory. In some examples, the memory 505 may further comprise memory located remotely from the processor 502, the remote memory being connectable to the mobile terminal through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 506 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 506 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 506 may be a Radio Frequency (RF) module, which is used to communicate with the internet wirelessly.

In this embodiment, a PCIe bus-based data processing method running on a mobile terminal is provided, and fig. 6 is a flowchart of a PCIe bus-based data processing method according to an embodiment of the present application, as shown in fig. 6, where the flowchart includes the following steps:

step S602, receiving a data processing request sent by a processor through a PCIe bus, wherein the data processing request is a request for supporting the PCIe bus transmission, and the data processing request is generated by the processor;

step S604, converting the data processing request into a target data processing request, wherein the target data processing request is a data request identifiable by a FLASH memory;

Step S606, the target data processing request is sent to the FLASH memory, so as to instruct the FLASH memory to execute a data processing operation according to the target data processing request.

The main execution body of the steps may be an FPGA component, and the FPGA component may include a processor, a processing device, or the like, but is not limited thereto.

Through the steps, the data processing request sent by the processor is received through the PCIe bus, so that the aim of quickly transmitting the data processing request can be fulfilled. And the data processing request is converted into a target data processing request and then transmitted to the FLASH memory to execute data processing operation, so that the FLASH memory is not required to convert the data processing request, and the data processing speed of the FLASH memory is further increased. Therefore, the problem that the data processing speed of the Flash memory cannot meet the data processing speed of the processor in the related technology can be solved, and the effect of improving the data processing speed of the Flash memory to meet the high-speed processing requirement of the processor is achieved.

In one exemplary embodiment, converting a data processing request to a target data processing request includes: transmitting a TLP packet to the PCIe protocol conversion module through a PCIe interface, where the TLP packet includes the data processing request, and the TLP packet is determined according to a transmission protocol of the PCIe bus, where the PCIe interface is disposed on the PCIe bus; converting the TLP data packet into a target request signal through an FPGA bus in the PCIe protocol conversion module; and converting the target request signal into the target data processing request through a FLASH controller, wherein the FLASH controller is connected with the FPGA bus. The PCIe bus protocol and PCIe interface adopt the design mode of transmission layered structure.

Optionally, PCIe interfaces may be categorized into the following:

Interrupt interface: for controlling the transmission of interrupts, etc.

In an exemplary embodiment, before converting the TLP packet into the target request signal through the FPGA bus in the PCIe protocol conversion module, the method further includes: determining a data format and a data type of the TLP data packet through the PCIe protocol conversion module, determining data processing content of the TLP data packet based on the data format and the data type of the TLP data packet, and sending a data request to an FPGA bus according to the data processing content; when the TLP data packet is a data writing request, recording a writing address of data to be written in the TLP data packet through the PCIe protocol conversion module, caching the data to be written, and sending the data writing request to the FPGA bus; when the TLP packet is a read data request, recording, by the PCIe protocol conversion module, a read address in the TLP packet, and sending the read data request to the FPGA bus, where the data request includes the write data request and the read data request.

table 1:

Optionally, adjusting, by the FPGA bus, a signal state of an interface in the FPGA bus according to data processing content corresponding to the data request, to generate the target request signal, including: when the data request is the data writing request, adjusting a chip selection signal and a writing signal of a data writing interface in the interfaces through the FPGA bus, and setting data to be written in the TLP data on the data writing interface to obtain the target request signal.

Optionally, receiving, via the PCIe bus, a data processing request sent by the processor, including: and receiving the data processing sent by the processor through a PCIe interface, wherein the PCIe interface is arranged on the PCIe bus.

table 2:

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

An embodiment of the application also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.

Claims

1. A PCIe bus-based data processing system, comprising: processor, PCIe bus, FPGA component, FLASH memory, wherein,

The processor is configured to generate a data processing request, where the data processing request is a request for supporting transmission of the PCIe bus;

the PCIe bus is used for connecting the processor and the FPGA component;

the FPGA component is used for receiving the data processing request sent by the processor through the PCIe bus and converting the data processing request into a target data processing request, wherein the target data processing request is a data request identifiable by the FLASH memory;

2. The system of claim 1, wherein the FPGA component comprises: PCIe interface, PCIe protocol conversion module, FLASH controller, wherein,

the PCIe interface is configured to receive, through the PCIe bus, the data processing request sent by the processor, and transmit a TLP packet to the PCIe protocol conversion module according to a transmission protocol of the PCIe bus, where the TLP packet includes the data processing request;

The PCIe protocol conversion module is configured to convert the TLP packet into a target request signal through an FPGA bus;

the FLASH controller is used for converting the target request signal transmitted by the FPGA bus into the target data processing request and sending the target data processing request to the FLASH memory.

3. The system of claim 2, wherein the system further comprises a controller configured to control the controller,

the PCIe protocol conversion module is further configured to determine a data format and a data type of the TLP packet, and determine data processing contents of the TLP packet based on the data format and the data type, send a data request to the FPGA bus according to the data processing contents, wherein,

when the TLP data packet is a data writing request, the PCIe protocol conversion module is configured to record a writing address of data to be written in the TLP data packet, cache the data to be written, and send the data writing request to the FPGA bus;

when the TLP packet is a read data request, the PCIe protocol conversion module is configured to record a read address in the TLP packet, and send the read data request to the FPGA bus, where the data request includes the write data request and the read data request.

4. The system of claim 3, wherein the system further comprises a controller configured to control the controller,

and the FPGA bus is used for adjusting the signal state of an interface in the FPGA bus according to the data processing content corresponding to the data request to generate the target request signal.

5. The system of claim 3 or 4, wherein the system comprises a plurality of sensors,

the FPGA bus is configured to adjust a chip select signal and a write signal of a write data interface in the interface when the data request is the write data request, and set data to be written in the TLP data on the write data interface, so as to obtain the target request signal; or alternatively, the process may be performed,

the FPGA bus is configured to adjust a chip select signal and a read signal of a read data interface in the interface when the data request is the read data request, and set a read address in the TLP data on the read data interface, so as to obtain the target request signal.

6. The system of claim 2, wherein said FLASH controller comprises a register, a request processing state machine, wherein,

the register is used for caching the target request signal;

the request processing state machine is used for converting the target request signal into the target data processing request corresponding to the request type according to the request type of the target request signal, and sending the target data processing request to a corresponding memory in the FLASH memory.

7. A PCIe bus-based data processing method, comprising:

receiving a data processing request sent by a processor through a PCIe bus, wherein the data processing request is a request for supporting the PCIe bus transmission, and the data processing request is generated by the processor;

converting the data processing request into a target data processing request, wherein the target data processing request is a data request identifiable by a FLASH memory;

and sending the target data processing request to the FLASH memory to instruct the FLASH memory to execute data processing operation according to the target data processing request.

8. The method of claim 7, wherein converting the data processing request to a target data processing request comprises:

transmitting a TLP data packet to a PCIe protocol conversion module through a PCIe interface, wherein the TLP data packet comprises the data processing request, and the TLP data packet is determined according to a transmission protocol of the PCIe bus, and the PCIe interface is arranged on the PCIe bus;

converting the TLP data packet into a target request signal through an FPGA bus in the PCIe protocol conversion module;

And converting the target request signal into the target data processing request through a FLASH controller, wherein the FLASH controller is connected with the FPGA bus.

9. The method of claim 8, wherein prior to converting the TLP packet to a target request signal over an FPGA bus in the PCIe protocol conversion module, the method further comprises:

determining a data format and a data type of the TLP data packet through the PCIe protocol conversion module, determining data processing content of the TLP data packet based on the data format and the data type of the TLP data packet, and sending a data request to the FPGA bus according to the data processing content; wherein, the liquid crystal display device comprises a liquid crystal display device,

when the TLP data packet is a data writing request, recording a writing address of data to be written in the TLP data packet through the PCIe protocol conversion module, caching the data to be written, and sending the data writing request to the FPGA bus;

when the TLP data packet is a read data request, recording, by the PCIe protocol conversion module, a read address in the TLP data packet, and sending the read data request to the FPGA bus, where the data request includes the write data request and the read data request.

10. The method of claim 9, wherein converting the TLP packet to a target request signal over an FPGA bus in the PCIe protocol conversion module comprises:

and adjusting the signal state of an interface in the FPGA bus through the FPGA bus according to the data processing content corresponding to the data request, and generating the target request signal.

11. The method of claim 10, wherein adjusting, by the FPGA bus, a signal state of an interface in the FPGA bus according to data processing content corresponding to the data request, generating the target request signal, comprises:

when the data request is the data writing request, adjusting a chip selection signal and a writing signal of a data writing interface in the interfaces through the FPGA bus, and setting data to be written in the TLP data on the data writing interface to obtain the target request signal;

when the data request is the read data request, chip selection signals and read signals of a read data interface in the interfaces are adjusted through the FPGA bus, and read addresses in the TLP data are set on the read data interface to obtain the target request signals.

12. The method of claim 7, wherein receiving the data processing request sent by the processor over the PCIe bus comprises:

and receiving the data processing sent by the processor through a PCIe interface, wherein the PCIe interface is arranged on the PCIe bus.

13. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, wherein the computer program, when executed by a processor, implements the method of any of the claims 7 to 12.

14. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 7 to 12.