CN116991339B

CN116991339B - Hybrid memory based on SCM and SSD, hybrid memory system and method

Info

Publication number: CN116991339B
Application number: CN202311265466.XA
Authority: CN
Inventors: 方浩俊; 陈飞
Original assignee: Shenzhen Dapu Microelectronics Co Ltd
Current assignee: Shenzhen Dapu Microelectronics Co Ltd
Priority date: 2023-09-28
Filing date: 2023-09-28
Publication date: 2023-12-22
Anticipated expiration: 2043-09-28
Also published as: CN116991339A

Abstract

The embodiment of the application relates to the field of solid state disk application, and discloses a hybrid memory, a hybrid memory system and a hybrid memory method based on SCM and SSD, wherein the hybrid memory comprises: an SSD memory comprising a flash memory granule array; an SCM memory comprising an array of SCM particles; a hybrid storage controller, the hybrid storage controller comprising: the flash memory controller is connected with the SSD memory and used for controlling the SSD memory; the SCM controller is connected with the SCM memory and used for controlling the SCM memory; the flash memory controller is connected with the SCM controller, the dump device is used for data interaction between the SSD memory and the SCM memory, the host can simultaneously and respectively read and write access to the SCM memory and the SSD memory by keeping independent access paths of the two memories, and the data dump between the SCM memory and the SSD is completed by the inside of the hybrid memory.

Description

Hybrid memory based on SCM and SSD, hybrid memory system and method

Technical Field

The application relates to the field of solid state disk applications, in particular to a hybrid memory based on SCM and SSD, a hybrid memory system and a hybrid memory method.

Background

The solid state disk (Solid State Drives, SSD) is a hard disk made of a solid state electronic memory chip array, and the solid state disk comprises a control unit and a memory unit (FLASH memory chip or DRAM memory chip). Flash memory (NAND Flash) is the primary storage medium for solid state disks.

At present, the solid state disk comprises an SSD memory and an SCM memory, wherein the SCM memory and the SSD memory are independent, when a data interaction relationship exists between the SCM memory and the SSD memory, the CPU acquires data from one memory and then dumps the data to the other memory, and the operation inevitably uses the memory and a bus of the whole system, so that the loads of the memory and the bus are large.

Disclosure of Invention

The embodiment of the application aims to provide a hybrid memory, a hybrid storage system and a hybrid storage method based on SCM and SSD, which solve the problem that the load of a memory and a bus of the system is large due to the current data dump, and reduce the data transmission pressure between a host and the memory.

In order to solve the technical problems, the embodiment of the application provides the following technical scheme:

in a first aspect, embodiments of the present application provide a hybrid memory based on SCM and SSD, the hybrid memory comprising:

An SSD memory comprising a flash memory granule array;

an SCM memory comprising an array of SCM particles;

a hybrid storage controller, the hybrid storage controller comprising:

the flash memory controller is connected with the SSD memory and used for controlling the SSD memory;

the SCM controller is connected with the SCM memory and used for controlling the SCM memory;

the transfer memory is connected with the flash memory controller and the SCM controller, and the dump device is used for data interaction between the SSD memory and the SCM memory;

the flash memory controller comprises an SSD subsystem, wherein the SSD subsystem is connected with the flash memory particle array, and the SSD subsystem is used for writing data into the flash memory particle array or reading data of the flash memory particle array;

the dump device comprises a dump system;

the SSD subsystem includes:

the first front-end module is connected with the dump system and is used for processing a first host command;

the first data path module is connected with the first front end module and is used for processing a data stream corresponding to the first host command;

the first algorithm module is connected with the first data path module and the dump system and is used for processing address mapping of data corresponding to the first host command;

the first back-end module is connected with the first algorithm module and the flash memory particle array and is used for processing data reading and writing of the flash memory particle array.

In some embodiments, the SSD memory includes a plurality of flash memory granule arrays, each flash memory granule array corresponding one-to-one to a flash memory channel, the hybrid memory controller accessing the flash memory granule arrays through the flash memory channels;

the SCM memory comprises a plurality of SCM particle arrays, each SCM particle array corresponds to one SCM channel one by one, and the mixed memory controller accesses the SCM particle arrays through the SCM channels.

In some embodiments, the SCM controller includes an SCM subsystem connected to the SCM particle array, the SCM subsystem for writing data to or reading data from the SCM particle array;

the dump system is connected with the SSD subsystem and the SCM subsystem and is used for data dump between the SCM subsystem and the SCM subsystem.

In some embodiments, the SCM subsystem comprises:

the second front-end module is connected with the dump system and is used for processing a second host command;

the second data access module is connected with the second front-end module and is used for processing a data stream corresponding to a second host command;

the second algorithm module is connected with the second data path module and the dump system and is used for processing address mapping of data corresponding to the second host command;

and the second back-end module is connected with the second algorithm module and the SCM particle array and is used for processing data reading and writing of the SCM particle array.

In some embodiments, a dump system includes:

the subsystem front end interface module is connected with the first front end module and the second front end module and is used for processing data dump between the first front end module and the second front end module;

the subsystem algorithm interface module is connected with the first algorithm module and the second algorithm module and is used for processing data dump between the first algorithm module and the second algorithm module;

the address management module is used for address management of the host command during data dump;

the cache management module is used for managing application or release of the cache;

the operation management module is used for processing data operation between the SSD subsystem and the SCM subsystem;

the command analysis module is connected with the operation management module, the subsystem front-end interface module and the subsystem algorithm interface module and is used for analyzing commands of the dump system.

In some embodiments, the operations management module comprises:

the cross-system shearing management module is used for processing data shearing between the SSD subsystem and the SCM subsystem;

and the cross-system copy management module is used for processing data copy between the SSD subsystem and the SCM subsystem.

In a second aspect, an embodiment of the present application provides a hybrid storage system based on SCM and SSD, the system including:

The SCM and SSD-based hybrid memory of the first aspect;

the host comprises a host system for interfacing the SSD memory and the SCM memory.

In some embodiments, a host system includes:

the SSD management system is used for interfacing with the SSD memory;

the SCM management system is used for interfacing with the SCM memory;

the SCM and SSD-based hybrid memory includes a hybrid memory controller including:

the flash memory controller comprises an SSD subsystem, and is connected with an SSD management system, and the SSD management system is used for carrying out data interaction with the SSD subsystem;

the SCM controller comprises an SCM subsystem, and is connected with an SCM management system, and the SCM management system is used for carrying out data interaction with the SCM subsystem;

the dump device comprises a dump system, the dump system is connected with the SSD subsystem and the SCM subsystem, and the dump system is used for data dump between the SCM subsystem and the SCM subsystem.

In some embodiments, the SSD subsystem includes:

the first front-end module is connected with the dump system and the SSD management system and is used for processing a first host command;

In some embodiments, the SCM subsystem comprises:

the second front-end module is connected with the dump system and the SCM management system and is used for processing a second host command;

In a third aspect, an embodiment of the present application provides a hybrid storage method based on SCM and SSD, which is applied to the hybrid storage system based on SCM and SSD as in the second aspect, and the method includes:

obtaining a host command, wherein the host command comprises a source storage identifier and a target storage identifier;

determining a source memory and a target memory according to a source memory identifier and a target memory identifier, wherein the source memory and the target memory are respectively one of an SSD memory and an SCM memory;

The source memory forwards the host command to the transfer memory;

the transfer memory analyzes the host command and determines the operation type of the host command;

the dump device initiates a read operation to the source memory and a write operation request to the target memory according to the operation type of the host command to complete the host command.

In some embodiments, the dump comprises a dump system;

the source memory comprises a source subsystem and the target memory comprises a target subsystem, wherein the source subsystem and the target subsystem are respectively one of an SSD subsystem and an SCM subsystem;

the operation type of the host command comprises a copy operation, the dump device initiates a read operation to the source memory and initiates a write operation request to the target memory according to the operation type of the host command to complete the host command, and the method comprises the following steps:

the dump system initiates a read operation to a front-end module of the source subsystem, wherein the read operation comprises a source data address and a target cache address corresponding to a host command;

after the front end module of the source subsystem receives the read operation, the source data corresponding to the host command is read from the particle array corresponding to the source memory through the data path module, the algorithm module and the back end module of the source subsystem according to the source data address;

The front-end module of the source subsystem stores source data corresponding to the host command into a cache space corresponding to the target cache address according to the target cache address;

the dump system initiates a write operation request to a front-end module of the target subsystem, wherein the write operation request comprises a target storage address corresponding to a host command;

the front-end module of the target subsystem reads the source data from the cache space corresponding to the target cache address according to the target storage address, and writes the source data into the particle array corresponding to the target memory through the data path module, the algorithm module and the back-end module of the target subsystem.

In some embodiments, the operation type of the host command includes a cut operation, the dump initiating a read operation to the source memory and a write operation request to the target memory according to the operation type of the host command to complete the host command, comprising:

the dump system initiates a read operation to an algorithm module of the source subsystem, wherein the read operation comprises a source data address and a target cache address corresponding to a host command;

after the algorithm module of the source subsystem receives the reading operation, reading source data corresponding to a host command from the particle array corresponding to the source memory through the back-end module of the source subsystem according to the source data address;

The algorithm module of the source subsystem stores source data corresponding to the host command into a cache space corresponding to the target cache address according to the target cache address;

the dump system initiates a write operation request to an algorithm module of the target subsystem, wherein the write operation request comprises a target storage address corresponding to a host command;

the algorithm module of the target subsystem reads the source data from the cache space corresponding to the target cache address according to the target storage address, and writes the source data into the particle array corresponding to the target memory through the back-end module of the target subsystem;

after source data is written into a particle array corresponding to a target memory, a dump system initiates an erase operation to an algorithm module of a source subsystem, wherein the erase operation comprises a source data address corresponding to a host command;

after the algorithm module of the source subsystem receives the erasing operation, the data corresponding to the source data address is erased through the back-end module of the source subsystem.

The beneficial effects of the embodiment of the application are that: in contrast to the prior art, the embodiment of the present application provides a hybrid memory, a hybrid memory system and a method based on SCM and SSD, where the hybrid memory includes: an SSD memory comprising a flash memory granule array; an SCM memory comprising an array of SCM particles; a hybrid storage controller, the hybrid storage controller comprising: the flash memory controller is connected with the SSD memory and used for controlling the SSD memory; the SCM controller is connected with the SCM memory and used for controlling the SCM memory; the transfer memory is connected with the flash memory controller and the SCM controller, and the dump device is used for data interaction between the SSD memory and the SCM memory.

By maintaining independent access paths of the two memories so that the host can simultaneously and respectively perform read-write access to the SCM memory and the SSD memory, and by performing data dump between the SCM and the SSD by the interior of the hybrid memory, the data transmission pressure between the host and the memory can be reduced.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

Fig. 1 is a schematic structural diagram of a solid state hard disk hardware framework provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a solid state disk provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a host and a memory according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a host accessing SSD memory and SCM memory provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a host and a memory according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a hybrid memory according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of interaction between a hybrid memory and a host according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a data channel between a hybrid storage host controller, SSD memory, SCM memory, according to an embodiment of the present application;

FIG. 9 is a schematic diagram illustrating interaction between a host and a hybrid storage controller according to an embodiment of the present application;

FIG. 10 is a schematic diagram of an SSD subsystem according to an embodiment of the present application;

FIG. 11 is a schematic diagram of an SCM subsystem according to an embodiment of the present application;

FIG. 12 is a schematic diagram of interaction between a host system and a memory according to an embodiment of the present application;

FIG. 13 is a schematic diagram illustrating an internal structure of a dump system according to an embodiment of the present disclosure;

fig. 14 is a flow chart of a hybrid storage method based on SCM and SSD according to an embodiment of the disclosure;

fig. 15 is a schematic diagram of a refinement flow of step S1401 provided in the embodiment of the present application;

fig. 16 is another refinement flowchart of step S1401 provided in the embodiment of the present application.

Reference numerals illustrate:

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In addition, technical features described below in the various embodiments of the present application may be combined with each other as long as they do not conflict with each other.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a solid state disk hardware frame provided in an embodiment of the present application;

as shown in fig. 1, the solid state disk (Solid State Drives, SSD) generally includes a solid state disk Controller, i.e., an SSD Controller (SSD Controller), a Connector (Connector), a flash memory array, a cache unit, and other peripheral units.

The solid state disk controller is used as a control operation unit for managing an SSD internal system;

among them, a Flash Array (NAND Flash Array), which is used as a storage unit for storing data, including user data and system data, generally presents a plurality of Channels (CH), and one Channel is independently connected to a group of Flash arrays, for example: channel 0, channels 1, … …, channel x are each independently connected to a set of flash memory arrays. It will be appreciated that the nature of Flash (NAND Flash) is that prior to writing, it must be erased and that each Flash has a limited number of erases;

the cache unit is used for caching the mapping table, and the cache unit is typically a dynamic random access memory (Dynamic Random Access Memory, DRAM).

Wherein, connector (Connector) is used for connecting the host computer, for example: a PC or a server.

Other peripheral units may include serial ports (Serial Peripheral Interface, SPI), sensors (Sensor), registers, universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART), power chips, other interfaces, such as: JTAG interface, etc.

Referring to fig. 2 again, fig. 2 is a schematic structural diagram of a solid state disk according to an embodiment of the present application;

as shown in fig. 2, the solid state disk includes a flash memory medium and a solid state disk controller connected to the flash memory medium. The solid state disk is in communication connection with the host in a wired or wireless mode and is used for realizing data interaction.

The Flash memory medium, which is also called as Flash memory, flash memory or Flash particles, belongs to one type of memory device, is a nonvolatile memory, can store data for a long time even without current supply, and has storage characteristics equivalent to a hard disk, so that the Flash memory medium becomes the basis of the storage medium of various portable digital devices.

The structure of the memory cell is very similar to that of a common semiconductor transistor, the Flash memory medium (NAND Flash) is characterized in that the single transistor of the NAND Flash is added with a floating gate and a control gate, the floating gate is used for storing electrons, the surface of the floating gate is covered by a layer of silicon oxide insulator and is coupled with the control gate through a capacitor, when negative electrons are injected into the floating gate under the action of the control gate, the storage state of a single crystal of the NAND Flash is changed from '1' to '0', and when the negative electrons are removed from the floating gate, the storage state is changed from '0' to '1', and the insulator covered on the surface of the floating gate is used for trapping the negative electrons in the floating gate, so that data storage is realized. That is, the memory cells of NAND Flash are floating gate transistors, which are used to store data in the form of charges. The amount of charge stored is related to the magnitude of the voltage applied by the floating gate transistor.

One NAND Flash includes at least one Chip, each Chip is composed of a plurality of Block physical blocks, and each Block physical Block includes a plurality of Page pages. The Block physical Block is the minimum unit of the NAND Flash for executing the erasing operation, the Page is the minimum unit of the NAND Flash for executing the reading and writing operation, and the capacity of one NAND Flash is equal to the number of the Block physical Block and the number of Page pages contained in the Block physical Block and the capacity of one Page. Specifically, the flash memory medium can be classified into SLC, MLC, TLC and QLC according to different levels of voltages of memory cells.

The solid state disk controller, namely the master control, comprises a data converter, a processor, a buffer, a flash memory controller and an interface.

And the data converter is respectively connected with the processor and the flash memory controller and is used for converting binary data into hexadecimal data and converting hexadecimal data into binary data. Specifically, when the flash memory controller writes data to the flash memory medium, binary data to be written is converted into hexadecimal data by the data converter, and then written to the flash memory medium. When the flash memory controller reads data from the flash memory medium, hexadecimal data stored in the flash memory medium is converted into binary data by the data converter, and then the converted data is read from the binary data page register. The data converter may include a binary data register and a hexadecimal data register, among others. Binary data registers may be used to hold data converted from hexadecimal to binary, and hexadecimal data registers may be used to hold data converted from binary to hexadecimal.

And the processor is respectively connected with the data converter, the buffer, the flash memory controller and the interface, wherein the processor is connected with the data converter, the buffer, the flash memory controller and the interface through buses or other modes and is used for running nonvolatile software programs, instructions and modules stored in the buffer, so that any method embodiment of the application is realized.

The buffer is mainly used for buffering read/write instructions sent by the host and read data or write data obtained from the flash memory medium according to the read/write instructions sent by the host. The buffer is used as a non-volatile computer readable storage medium for storing non-volatile software programs, non-volatile computer executable programs and modules. The buffer may include a storage program area that may store an operating system, an application program required for at least one function. In addition, the buffer may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the buffer may optionally include memory located remotely from the processor. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The buffer may be static random access memory (Static Random Access Memory, SRAM) or coupled memory (Tightly Coupled Memory, TCM) or double rate synchronous dynamic random access memory (Double DataRate Synchronous Dynamic Random Access Memory, DDR SRAM).

The flash memory controller is connected with the flash memory medium, the data converter, the processor and the buffer and is used for accessing the flash memory medium at the rear end and managing various parameters and data I/O of the flash memory medium; or, the interface and the protocol for providing access are used for realizing a corresponding SAS/SATA target protocol end or NVMe protocol end, acquiring an I/O instruction sent by the host, decoding and generating an internal private data result, and waiting for execution; or for taking care of the core processing of the flash translation layer (Flash translation layer, FTL).

The interface is connected with the host and the data converter, the processor and the buffer and is used for receiving data sent by the host or receiving data sent by the processor and realizing data transmission between the host and the processor, and the interface can be a SATA-2 interface, a SATA-3 interface, a SAS interface, a MSATA interface, a PCIe interface, an NGFF interface, a CFast interface, an SFF-8639 interface and an M.2 NVME/SATA protocol.

Referring to fig. 3 again, fig. 3 is a schematic diagram of a host and a memory according to an embodiment of the present disclosure;

as shown in fig. 3, the host includes a processor, a memory Controller (Memory Controller), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a storage class memory (Storage Class Memory, SCM), and an IO Controller (IO Controller).

Wherein, inside the host, the SCM is used as a cache of the DRAM, at this time, the memory controller is connected with the DRAM, and the DRAM is connected with the SCM; alternatively, the SCM is directly used as the memory, and at this time, the memory controller is directly connected to the SCM.

The memory comprises a memory controller, a SAS SSD, an NVMe SSD, an SCM or an HDD. At this time, the SCM is part of the memory, i.e., the SCM is juxtaposed with the SAS SSD, NVMe SSD, or HDD.

Referring to fig. 4 again, fig. 4 is a schematic diagram of a host accessing an SSD memory and an SCM memory according to an embodiment of the application;

as shown in fig. 4, when a Host (Host) accesses an SSD memory and an SCM memory, the SSD memory and the SCM memory are accessed through ports provided by respective independent masters, wherein a path of the Host accessing the SSD memory is a path (1), a path of the Host accessing the SCM memory is a path (2), the path (1) includes the Host (Host), a first Host port, an NVMe controller, an algorithm, and a backend system, the path (2) includes the Host (Host), a second Host port, the NVMe controller, the algorithm, and the backend system, wherein the NVMe controller is responsible for implementing an application-level communication protocol with the Host, the first Host port and the second Host port each include a PCIe controller/PHY (Physical Layer), and in the embodiment of the present application, the NVMe protocol is a protocol that allows the Host software to communicate with the nonvolatile memory subsystem, and the two memories of the SSD memory and the SCM memory each adopt the NVMe protocol. In a host system, there is a data dump between an SSD memory and an SCM memory, the data dump path comprising a path (3), the path (3) being: an algorithm and a back-end system in an SSD memory, an NVMe controller, a first Host port, a Host (Host), an algorithm and a back-end system in an SCM memory, the NVMe controller, a second Host port; when the SCM memory is used as a cache for the SSD memory, there are two data interaction processes: the SCM in-memory cache data is either flushed (Flush) into the SSD memory for saving or loaded (Load) from the SSD memory into the SCM memory. Both of the above-described data interaction processes are by way of a host's path dump, i.e., reading data from one memory into the host and then writing data from the host to the other memory.

However, since the SCM memory and the SSD memory are independent, when there is a data interaction relationship between the SCM memory and the SSD memory, the CPU fetches data from one memory and then dumps the data to the other memory, and the operation must use the memory and the bus of the whole system, which results in a large load of the memory and the bus.

In view of this, the embodiments of the present application provide a hybrid memory based on SCM and SSD, which is internally completed by the hybrid memory through data dump between SCM and SSD, reducing data transfer pressure between host and memory. Meanwhile, the method still maintains independent access paths of the two memories, so that the host can simultaneously and respectively perform read-write access on the SCM memory and the SSD memory.

Referring to fig. 4 and fig. 5 together, fig. 5 is a schematic diagram of a host and a memory according to an embodiment of the present disclosure;

as shown in fig. 5, path (1) and path (2) in fig. 5 are identical to path (1) and path (2) in fig. 4, that is, the scheme in fig. 5 uses dual ports of the master, still keeps both SCM memory and SSD memory independent, while both fig. 4 and 5 differ in that: path (3) in fig. 5 is an SSD memory, a dump system, an SCM memory, that is, when there is a data interaction relationship between the SCM memory and the SSD memory, the data is no longer streamed into the host, but is dumped by a dump within the hybrid memory.

Referring to fig. 6 again, fig. 6 is a schematic structural diagram of a hybrid memory according to an embodiment of the present application;

as shown in fig. 6, the hybrid memory 100 includes an SSD memory 101, an SCM memory 102, and a hybrid memory controller 103.

Wherein SSD memory 101 includes a flash memory granule array 1011; the SCM memory 102 includes an SCM particle array 1021.

Wherein the hybrid storage controller 103 includes:

a flash memory controller 131 connected to the SSD memory 101, the flash memory controller 131 being configured to control the SSD memory;

an SCM controller 132 connected to the SCM memory 102, the SCM controller 132 for controlling the SCM memory;

a dump 133, which connects the flash controller 131 and the SCM controller 132, the dump 133 is used for data interaction between the SSD memory and the SCM memory.

Referring to fig. 7 again, fig. 7 is a schematic diagram illustrating interaction between a hybrid memory and a host according to an embodiment of the present application;

as shown in fig. 7, the hybrid memory 100 includes a first host port 104 and a second host port 105, wherein the first host port 104 connects the SSD memory 101 and the host 110, and the first host port is used for data interaction between the SSD memory and the host; the second host port 105 connects the SCM memory 102 and the host 110, the second host port 105 being for data interaction between the SCM memory and the host.

The first host port and the second host port are also used to implement an underlying communication protocol between the hybrid memory and the host, wherein the underlying communication protocol includes, but is not limited to, a PCIe interface protocol. It will be appreciated that the first host port and the second host port are provided for the purpose of enabling independent access to the host for both the SSD memory and the SCM memory to enable the host to access the SCM grain array in the SCM memory and the flash memory grain array in the SSD memory, respectively.

Referring to fig. 8 again, fig. 8 is a schematic diagram of a data channel among a hybrid memory host controller, an SSD memory, and an SCM memory according to an embodiment of the disclosure;

as shown in fig. 8, the hybrid memory 100 includes an SSD memory 101, an SCM memory 102, and a hybrid memory controller 103, where the hybrid memory controller 103 accesses the SSD memory 101 and the SCM memory 102 through flash channels and SCM channels, respectively, and specifically, the SSD memory includes a plurality of flash granule arrays 1011, each of which corresponds to one flash channel one by one, and the hybrid memory controller 103 accesses the flash granule arrays through the flash channels; the SCM memory includes a plurality of SCM particle arrays 1021, each SCM particle array having a one-to-one correspondence to an SCM channel, through which the hybrid memory controller 103 accesses the SCM particle arrays.

In the embodiment of the present application, the hybrid memory controller 103 can be connected to the plurality of flash granule arrays 1011 in the SSD memory 101 through a plurality of flash channels, wherein the number of flash granule arrays 1011 is set according to specific needs, for example: the flash memory particle array 1011 is provided in four.

Similarly, the hybrid storage controller 103 is connected to the plurality of SCM particle arrays 1021 in the SCM memory 102 through a plurality of SCM channels, where the number of SCM particle arrays 1021 is set according to specific needs, for example: the SCM particle array 1021 is provided in four.

In the embodiment of the application, by arranging the hybrid memory controller, the hybrid memory controller corresponds to a plurality of flash memory channels and a plurality of SCM channels, so that the channels can access the storage medium in parallel, and the read-write performance of the hybrid memory is improved.

Referring to fig. 9 again, fig. 9 is a schematic diagram illustrating interaction between a host and a hybrid storage controller according to an embodiment of the present disclosure;

as shown in fig. 9, the hybrid storage controller 103 includes a flash controller 131, a flash memory 133, and an SCM controller 132, where the flash controller 131 includes an SSD subsystem 1301, the SSD subsystem 1301 is connected to the flash grain array 1011, and the SSD subsystem 1301 is used for writing data into the flash grain array or reading data from the flash grain array; the SCM controller 132 includes an SCM subsystem 1302, the SCM subsystem 1302 being connected to the SCM particle array 1021, the SCM subsystem 1302 being for writing data to the SCM particle array 1021 or reading data from the SCM particle array; the dump device comprises a dump system, wherein the dump system is connected with the SSD subsystem and the SCM subsystem and is used for data dump between the SCM subsystem and the SCM subsystem.

In this embodiment of the present application, the host 110 includes a host system 1101, where the host system 1101 includes an SSD management system 111 and an SCM management system 112, where the SSD management system 111 is connected to an SSD subsystem 1301 in the flash memory controller 131 through a first host port, and the SSD management system 111 is used to manage the SSD subsystem 1301; the SCM management system 112 is connected to the SCM system 1302 in the SCM controller 132 through a second host port, and the SCM management system 111 is configured to manage the SCM subsystem 1302.

Referring to fig. 10 again, fig. 10 is a schematic structural diagram of an SSD subsystem according to an embodiment of the disclosure;

as shown in fig. 10, SSD subsystem 1301 includes a first front end module 1311, a first data path module 1312, a first algorithm module 1313, a first back end module 1314.

The first front end module 1311 is connected to the dump system 1303 and is configured to process a first host command, where the first host command includes a source storage identifier and a target storage identifier, and specifically, the first front end module is configured to receive a first host command sent by a host, parse the command, and send the parsed command to the dump system;

the first data path module 1312 is connected to the first front end module 1311, and is configured to process a data stream corresponding to the first host command, where the data stream corresponding to the first host command includes a source data address and a target cache address;

The first algorithm module 1313 is connected to the first data path module 1312 and the dump system 1303, and is configured to process an address mapping of data corresponding to the first host command, specifically, obtain a mapping relationship between the data corresponding to the first host command and a source data address, and send the mapping relationship to the first back-end module;

the first back-end module 1314 is connected to the first algorithm module 1313 and the flash memory granule array 1011, and is used for processing data read/write of the flash memory granule array.

Referring to fig. 11 again, fig. 11 is a schematic structural diagram of an SCM subsystem according to an embodiment of the present application;

as shown in fig. 11, the SCM subsystem includes a second front end module 1321, a second data path module 1322, a second algorithm module 1323, and a second back end module 1324.

The second front end module 1321 is connected to the dump system 1303, and is configured to process a second host command, specifically, the second front end module is configured to receive the second host command sent by the host, parse the command, and send the parsed command to the dump system;

the second data path module 1322 is connected to the second front end module 1321, and is configured to process a data stream corresponding to the second host command;

the second algorithm module 1323 is connected to the second data path module 1322 and the dump system 1303, and is configured to process an address mapping of data corresponding to the second host command, specifically, obtain a mapping relationship between the data corresponding to the second host command and a source data address, and send the mapping relationship to the second back-end module;

The second back-end module 1324 is connected to the second algorithm module 1323 and the SCM particle array 1021, and is configured to process data read and write of the SCM particle array.

In the embodiment of the application, the host provides the source data address, the target cache address and the data length through the host command, wherein the host command comprises a Flush command, and defines the device IDs of the source memory and the target memory at the host end as a mode for identifying the source memory and the target memory. When the host needs to perform a dump operation, the host sends a host command to any one port of the hybrid memory, wherein the port comprises a first host port and a second host port, and when a front end module of any subsystem in the hybrid memory receives the host command, the data is dumped through a dump system.

Referring to fig. 12 again, fig. 12 is an interaction schematic diagram of a host system and a memory according to an embodiment of the present application;

as shown in fig. 12, the data interaction between the host system, the SSD subsystem, the SCM subsystem, the dump system, the flash memory granule array, and the SCM granule array includes four paths, namely, path (1), path (2), path (3), and path (4). The path (1) comprises a host system, a front end module of an SSD subsystem, a data path module, an algorithm module, a back end module and a flash memory particle array, in the path (1), the host sends a host command to the SSD subsystem, the flash memory particle array is accessed through the first front end module, the first data path module, the first algorithm module and the first back end module, the path (2) comprises the host system, the front end module of the SCM subsystem, the data path module, the algorithm module, the back end module and the SCM particle array, in the path (2), the host sends the host command to the SCM subsystem, and the SCM particle array is accessed through the second front end module, the second data path module, the second algorithm module and the second back end module. It will be appreciated that the role of paths (1) and (2) is to provide a path for host access to the flash memory particle array and SCM particle array.

Path (3) includes an SSD subsystem, an SCM subsystem, a dump system, a flash granule array, and an SCM granule array, path (4) includes an SSD subsystem, an SCM subsystem, a dump system, a flash granule array, and an SCM granule array, in path (3) and path (4), when the SCM memory is a source memory and the SSD memory is a target memory, the dump system initiates a read operation to a second front-end module of the SCM subsystem, the second front-end module receives the read operation, processes the read operation through a second data path module, a second algorithm module, and a second back-end module, reads data from the SCM granule array, and places the data into a buffer space according to the target buffer address, and then the dump system initiates a write operation request to the SSD subsystem, which receives the write operation request, and writes the data into the flash granule array. It will be appreciated that the role of paths (3) and (4) is to dump data in the flash granule array and SCM granule array by a dump system.

Referring to fig. 13 again, fig. 13 is a schematic diagram illustrating an internal structure of a dump system according to an embodiment of the present disclosure;

as shown in FIG. 13, the dump system includes a subsystem front-end interface module 1331, a subsystem algorithm interface module 1332, an address management module 1333, a cache management module 1334, an operation management module 1335, and a command resolution module 1336.

The subsystem front-end interface module 1331 is connected with the first front-end module and the second front-end module and is used for processing data dump between the first front-end module and the second front-end module;

the subsystem algorithm interface module 1332 is connected with the first algorithm module and the second algorithm module and is used for processing data dump between the first algorithm module and the second algorithm module;

the address management module 1333 is connected to the cross-system clipping management module 1351 in the operation management module 1335 for address management of host commands at the time of data dump;

the cache management module 1334 is connected to the cross-system copy management module 1352 in the operation management module 1335, and is configured to manage application or release of a cache, and specifically, the cache management module manages application or release of the cache according to a target cache address in a host command, for example, if the SCM memory is a source memory and the SSD memory is a target storage area, when data is read from the SCM granule array, the data can be temporarily stored in a cache space applied by the cache management module, and after the data is written into the flash granule array, the cache management module can release the cache space.

An operation management module 1335 for handling data operations between the SSD subsystem and the SCM subsystem; wherein the operation management module 1335 includes: the cross-system shearing management module 1351 is used for processing data shearing between the SSD subsystem and the SCM subsystem, wherein the data shearing process specifically comprises a read operation, a write operation and an erase operation; a cross-system copy management module 1352 for handling data copying between the SSD subsystem and the SCM subsystem;

The command parsing module 1336 is connected to the operation management module, the subsystem front-end interface module, and the subsystem algorithm interface module, and is used for command parsing of the dump system.

Referring to fig. 14 again, fig. 14 is a flow chart of a hybrid storage method based on SCM and SSD according to an embodiment of the disclosure;

in an embodiment of the present application, the dump comprises a dump system; the source memory comprises a source subsystem and the target memory comprises a target subsystem, wherein the source subsystem and the target subsystem are respectively one of an SSD subsystem and an SCM subsystem; the operation type of the host command includes a copy operation.

As shown in fig. 14, the flow of the mixed storage method based on SCM and SSD includes:

step S1401: the dump device initiates a read operation to the source memory and initiates a write operation request to the target memory according to the operation type of the host command so as to complete the host command;

referring to fig. 15 again, fig. 15 is a schematic diagram of a refinement flow of step S1401 provided in the embodiment of the present application;

in this embodiment of the present application, the operation type of the host command includes a copy operation, where the copy operation refers to that data is stored in a source memory, and in a dump process, the data is retained in the source memory, and then a copy of data identical to the data is stored in a target memory, and it may be understood that in a process of performing data dump between an SCM memory and an SSD memory, the SCM memory may be used as the source memory, and the SSD memory may be used as the target memory; the SSD memory may be used as a source memory and the SCM memory may be used as a target memory.

As shown in fig. 15, step S1401: the dump device initiates a read operation to the source memory and a write operation request to the target memory according to the operation type of the host command to complete the host command, and the dump device comprises:

step S1411: the dump system initiates a read operation to a front-end module of the source subsystem, wherein the read operation comprises a source data address and a target cache address corresponding to a host command;

specifically, when the operation type of the host command is a copy operation and the SCM memory is used as a source memory and the SSD memory is used as a target memory, the dump system initiates a read operation to a front end module of the SCM subsystem in the SCM memory, wherein the read operation includes a source data address and a target cache address corresponding to the host command, and performs address flattening processing on the source data address and the target cache address. It should be noted that the source data address and the destination cache address are logical block addresses (Logical Block Address, LBA), and the address flattening process is to unify the source data address and the destination cache address into a flushing-LBA in the memory, i.e. after the LBA of one memory is shifted to the LBA of another memory, a similar continuous LBA is formed.

Similarly, the host command includes a Flush command, the host provides a source data address and a target cache address through the Flush command, and when the SSD memory is used as the source memory and the SCM memory is used as the target memory, the dump system initiates a read operation to a front end module of the SSD subsystem in the SSD memory, wherein the read operation includes the source data address and the target cache address corresponding to the host command.

Step S1412: after the front end module of the source subsystem receives the read operation, the source data corresponding to the host command is read from the particle array corresponding to the source memory through the data path module, the algorithm module and the back end module of the source subsystem according to the source data address;

specifically, after the front-end module of the SCM subsystem receives the read operation, similar to the read operation of a common host, the front-end module of the SCM subsystem instructs the corresponding source data from the particle array corresponding to the SCM memory after passing through the data path module, the algorithm module and the back-end module of the source subsystem according to the source data address.

Similarly, when the SSD memory is used as the source memory and the SCM memory is used as the target memory, the front-end module of the SSD subsystem receives the read operation, and then commands the corresponding source data from the corresponding grain array of the SSD memory through the data path module, the algorithm module and the back-end module of the source subsystem according to the source data address, similar to the read operation of a common host.

Step S1413: the front-end module of the source subsystem stores source data corresponding to the host command into a cache space corresponding to the target cache address according to the target cache address;

specifically, the front end module of the SCM subsystem stores source data corresponding to the host command into a buffer space corresponding to the target buffer address according to the target buffer address, and returns a message that the source data is stored into the buffer space to the dump system to indicate that the read operation is finished.

Similarly, when the SSD memory is used as the source memory and the SCM memory is used as the target memory, the front end module of the SSD subsystem stores the source data corresponding to the host command into the buffer space corresponding to the target buffer address according to the target buffer address, and returns a message that the source data is stored into the buffer space to the dump system to indicate that the read operation is finished.

Step S1414: the dump system initiates a write operation request to a front-end module of the target subsystem, wherein the write operation request comprises a target storage address corresponding to a host command;

specifically, after the read operation is finished, the dump system initiates a write-once operation request to a front-end module of the SSD subsystem, wherein the write operation request includes a target storage address and a data length corresponding to the host command.

Similarly, when the SSD memory is used as the source memory and the SCM memory is used as the target memory, after the read operation is finished, the dump system initiates a write-once operation request to the front-end module of the SCM subsystem, wherein the write operation request includes the target memory address and the data length corresponding to the host command.

Step S1415: the front end module of the target subsystem reads source data from a cache space corresponding to the target cache address according to the target storage address, and writes the source data into a particle array corresponding to the target memory through the data path module, the algorithm module and the back end module of the target subsystem;

specifically, after the SSD subsystem receives the write operation request, the front end module of the SSD subsystem reads the source data from the buffer space corresponding to the target buffer address according to the target storage address, writes the source data into the flash memory grain array through the data path module, the algorithm module and the back end module of the SSD subsystem, and returns a message that the source data has been written into the flash memory grain array to the dump system to indicate that the write operation is finished. When the read operation and the write operation are finished, the dump system is indicated to finish the copy operation corresponding to the host command, at this time, the dump system returns a message for finishing the copy operation corresponding to the host command to the front end module of the SCM subsystem, and finally the front end module of the SCM subsystem feeds back the copy operation corresponding to the host command to the host.

Similarly, when the SSD memory is used as the source memory and the SCM memory is used as the target memory, after the SCM subsystem receives the write operation request, the front end module of the SCM subsystem reads the source data from the cache space corresponding to the target cache address according to the target storage address, writes the source data into the SCM particle array through the data path module, the algorithm module and the back end module of the SCM subsystem, and returns a message that the source data is written into the SCM particle array to the dump system so as to indicate that the write operation is finished. When the read operation and the write operation are finished, the dump system is indicated to finish the copy operation corresponding to the host command, at this time, the dump system returns a message for finishing the copy operation corresponding to the host command to the front end module of the SSD subsystem, and finally the front end module of the SSD subsystem feeds back the copy operation corresponding to the host command to the host.

Referring to fig. 16 again, fig. 16 is a schematic diagram of another refinement flow of step S1401 provided in the embodiment of the present application;

in the embodiment of the present application, the operation type of the host command includes a cut operation, where the cut operation refers to that data is stored in a source memory, during a dump process, the data is moved from the source memory to a target memory, and the data is not retained in the source memory, and it may be understood that during a data dump process between the SCM memory and the SSD memory, the SCM memory may be used as the source memory, and the SSD memory may be used as the target memory; the SSD memory may be used as a source memory and the SCM memory may be used as a target memory.

As shown in fig. 16, step S1401: the dump device initiates a read operation to the source memory and a write operation request to the target memory according to the operation type of the host command to complete the host command, and the dump device comprises:

step S1416: the dump system initiates a read operation to an algorithm module of the source subsystem, wherein the read operation comprises a source data address and a target cache address corresponding to a host command;

specifically, when the operation type of the host command is a cut operation and the SCM memory is used as a source memory and the SSD memory is used as a target memory, the dump system initiates a read operation to a front end module of the SCM subsystem in the SCM memory, wherein the read operation includes a source data address and a target cache address corresponding to the host command and performs address flattening processing on the source data address and the target cache address. It should be noted that the source data address and the destination cache address are logical block addresses (Logical Block Address, LBA), and the address flattening process is to unify the source data address and the destination cache address into a flushing-LBA in the memory, i.e. after the LBA of one memory is shifted to the LBA of another memory, a similar continuous LBA is formed.

Similarly, when the SSD memory is used as the source memory and the SCM memory is used as the target memory, the dump system initiates a read operation to the front end module of the SSD subsystem in the SSD memory, wherein the read operation includes a source data address and a target cache address corresponding to the host command.

Step S1417: after the front end module of the source subsystem receives the read operation, the source data corresponding to the host command is read from the particle array corresponding to the source memory through the data path module, the algorithm module and the back end module of the source subsystem according to the source data address;

Step S1418: the front-end module of the source subsystem stores source data corresponding to the host command into a cache space corresponding to the target cache address according to the target cache address;

Step S1419: the dump system initiates a write operation request to a front-end module of the target subsystem, wherein the write operation request comprises a target storage address corresponding to a host command;

Step S1420: the front end module of the target subsystem reads source data from a cache space corresponding to the target cache address according to the target storage address, and writes the source data into a particle array corresponding to the target memory through the data path module, the algorithm module and the back end module of the target subsystem;

specifically, after the SSD subsystem receives the write operation request, the front end module of the SSD subsystem reads the source data from the buffer space corresponding to the target buffer address according to the target storage address, writes the source data into the flash memory grain array through the data path module, the algorithm module and the back end module of the SSD subsystem, and returns a message that the source data has been written into the flash memory grain array to the dump system to indicate that the write operation is finished.

Similarly, when the SSD memory is used as the source memory and the SCM memory is used as the target memory, after the SCM subsystem receives the write operation request, the front end module of the SCM subsystem reads the source data from the cache space corresponding to the target cache address according to the target storage address, writes the source data into the SCM particle array through the data path module, the algorithm module and the back end module of the SCM subsystem, and returns a message that the source data is written into the SCM particle array to the dump system so as to indicate that the write operation is finished.

Step S1421: after source data is written into a particle array corresponding to a target memory, a dump system initiates an erase operation to an algorithm module of a source subsystem, wherein the erase operation comprises a source data address corresponding to a host command;

specifically, after the source data is written into the grain array corresponding to the SSD memory, after the dump system receives the write operation of the cut operation corresponding to the host command, an erase operation of the cut operation is initiated to the algorithm module of the SCM subsystem so as to target storage address and data length in the host command.

Similarly, after the source data is written into the grain array corresponding to the SCM memory, after the dump system receives the write operation of the cut operation corresponding to the host command, the erase operation of the cut operation is initiated to the algorithm module of the SSD subsystem, so as to target storage address and data length in the host command.

Step S1422: after the algorithm module of the source subsystem receives the erasing operation, the data corresponding to the source data address is erased through the back-end module of the source subsystem;

specifically, after the algorithm module of the SCM subsystem receives the erase operation of the cut operation, after the operation of the back-end module, the data on the SCM granule array corresponding to the source data address is erased, the data is deleted after being dumped, the data on the SCM granule array corresponding to the source data address is not reserved, and a message of the data corresponding to the erased source data address is returned to the dump system to indicate that the erase operation is finished. After the dump system receives the data message corresponding to the erased source data address, the host command corresponding cutting operation is ended, and the message for ending the host command corresponding cutting operation is reported to the front-end module of the SCM subsystem, and the front-end module feeds back the completion of the host command corresponding cutting operation to the host.

Similarly, after the algorithm module of the SSD subsystem receives the erasing operation of the cutting operation, the algorithm module erases the data on the flash memory particle array corresponding to the source data address after the operation of the back end module, and returns a message of the data corresponding to the erased source data address to the dump system to indicate that the erasing operation is finished. After the dump system receives the data message corresponding to the erased source data address, the host command corresponding cutting operation is ended, and the data message corresponding to the host command corresponding cutting operation is reported back to the front-end module of the SSD subsystem, and the front-end module feeds back the completion of the host command corresponding cutting operation to the host.

In an embodiment of the present application, by providing a hybrid storage method based on SCM and SSD, the method includes: obtaining a host command, wherein the host command comprises a source storage identifier and a target storage identifier; determining a source memory and a target memory according to a source memory identifier and a target memory identifier, wherein the source memory and the target memory are respectively one of an SSD memory and an SCM memory; the source memory forwards the host command to the transfer memory; the transfer memory analyzes the host command and determines the operation type of the host command; the dump device initiates a read operation to the source memory and a write operation request to the target memory according to the operation type of the host command to complete the host command. The method and the device can reduce the data transmission pressure between the host and the storage by completing data dump between the SCM storage and the SSD storage inside the hybrid storage.

Embodiments of the present application also provide a non-volatile computer-readable storage medium storing computer-executable instructions that are executable by one or more processors, such that the one or more processors may perform the SCM and SSD-based hybrid storage method in any of the method embodiments described above.

In an embodiment of the present application, the non-transitory computer readable storage medium may include: any entity or device capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the non-volatile computer readable storage medium may include content that is subject to appropriate increases and decreases as required by jurisdictions and by jurisdictions in which such non-volatile computer readable storage medium does not include electrical carrier signals and telecommunications signals.

The apparatus or device embodiments described above are merely illustrative, in which the unit modules illustrated as separate components may or may not be physically separate, and the components shown as unit modules may or may not be physical units, may be located in one place, or may be distributed over multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the objective of the embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., and include several instructions for up to a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method of each embodiment or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as above, which are not provided in details for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A hybrid memory based on SCM and SSD, the hybrid memory comprising:

an SSD memory, the SSD memory comprising a flash memory granule array;

an SCM memory, the SCM memory comprising an array of SCM particles;

a hybrid storage controller, the hybrid storage controller comprising:

the flash memory controller is connected with the SSD memory and is used for controlling the SSD memory;

The SCM controller is connected with the SCM memory and is used for controlling the SCM memory;

a flash memory, connected to the flash memory controller and the SCM controller, the flash memory being used for interaction between the SSD memory and the SCM memory;

the dump device comprises a dump system;

the SSD subsystem includes:

the first data path module is connected with the first front-end module and is used for processing a data stream corresponding to the first host command;

and the first back-end module is connected with the first algorithm module and the flash memory particle array and is used for processing data reading and writing of the flash memory particle array.

2. The mixed SCM and SSD-based memory of claim 1, wherein the memory is configured to store the data,

The SSD memory comprises a plurality of flash memory particle arrays, each flash memory particle array corresponds to one flash memory channel one by one, and the hybrid memory controller accesses the flash memory particle arrays through the flash memory channels;

3. The mixed SCM and SSD-based memory of claim 1 or 2, characterized in that,

the SCM controller comprises an SCM subsystem, wherein the SCM subsystem is connected with the SCM particle array and is used for writing data into the SCM particle array or reading data of the SCM particle array;

4. The mixed SCM and SSD-based memory of claim 3, wherein,

the SCM subsystem includes:

the second data path module is connected with the second front-end module and is used for processing the data stream corresponding to the second host command;

5. The mixed SCM and SSD-based memory of claim 4, wherein,

the dump system includes:

and the command analysis module is connected with the operation management module, the subsystem front-end interface module and the subsystem algorithm interface module and is used for analyzing the commands of the dump system.

6. The mixed SCM and SSD-based memory of claim 5, wherein,

the operation management module comprises:

a cross-system shear management module for processing data shear between the SSD subsystem and the SCM subsystem;

7. A hybrid storage system based on SCM and SSD, the system comprising:

the SCM and SSD-based hybrid memory of any one of claims 1-6;

8. The mixed SCM and SSD-based storage system of claim 7, wherein,

the host system includes:

the SSD management system is used for interfacing the SSD memory;

the SCM management system is used for interfacing the SCM memory;

the SCM and SSD-based hybrid memory includes a hybrid memory controller, the hybrid memory controller including:

the flash memory controller comprises an SSD subsystem, and is connected with the SSD management system, and the SSD management system is used for carrying out data interaction with the SSD subsystem;

The SCM controller comprises an SCM subsystem, and is connected with the SCM management system, and the SCM management system is used for carrying out data interaction with the SCM subsystem;

the dump device comprises a dump system, wherein the dump system is connected with the SSD subsystem and the SCM subsystem and is used for data dump between the SCM subsystem and the SCM subsystem.

9. The SCM and SSD-based hybrid storage system of claim 8, wherein the SSD subsystem includes:

10. The SCM and SSD-based hybrid storage system of claim 8 or 9, wherein the SCM subsystem comprises:

11. A mixed storage method based on SCM and SSD, characterized in that it is applied to the mixed storage system based on SCM and SSD according to any one of claims 7 to 10, said method comprising:

determining a source memory and a target memory according to the source memory identification and the target memory identification, wherein the source memory and the target memory are respectively one of an SSD memory and an SCM memory;

the source memory forwards the host command to the dump;

The dump device analyzes the host command and determines the operation type of the host command;

and the dump device initiates a read operation to the source memory and a write operation request to the target memory according to the operation type of the host command so as to complete the host command.

12. The method for mixed storage based on SCM and SSD of claim 11, characterized in that,

the dump device comprises a dump system;

the source memory comprises a source subsystem, the target memory comprises a target subsystem, and the source subsystem and the target subsystem are respectively one of an SSD subsystem and an SCM subsystem;

the operation type of the host command comprises a copy operation, the dump device initiates a read operation to the source memory and a write operation request to the target memory according to the operation type of the host command to complete the host command, and the method comprises the following steps:

the dump system initiates a read operation to a front-end module of the source subsystem, wherein the read operation comprises a source data address and a target cache address corresponding to the host command;

the dump system initiates a write operation request to a front-end module of the target subsystem, wherein the write operation request comprises a target storage address corresponding to the host command;

and the front-end module of the target subsystem reads the source data from the cache space corresponding to the target cache address according to the target storage address, and writes the source data into the particle array corresponding to the target memory through the data path module, the algorithm module and the back-end module of the target subsystem.

13. The method for mixed storage based on SCM and SSD of claim 12, characterized in that,

the operation type of the host command comprises a cut operation, the dump device initiates a read operation to the source memory and a write operation request to the target memory according to the operation type of the host command so as to complete the host command, and the method comprises the following steps:

the dump system initiates a read operation to an algorithm module of the source subsystem, wherein the read operation comprises a source data address and a target cache address corresponding to the host command;

After the algorithm module of the source subsystem receives the reading operation, reading the source data corresponding to the host command from the particle array corresponding to the source memory through the back-end module of the source subsystem according to the source data address;

the dump system initiates a write operation request to an algorithm module of the target subsystem, wherein the write operation request comprises a target storage address corresponding to the host command;

after the source data is written into the grain array corresponding to the target memory, the dump system initiates an erase operation to an algorithm module of the source subsystem, wherein the erase operation comprises a source data address corresponding to the host command;