CN116991010A

CN116991010A - Array substrate and display panel

Info

Publication number: CN116991010A
Application number: CN202311254616.7A
Authority: CN
Inventors: 曹军红; 袁海江
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2023-09-27
Filing date: 2023-09-27
Publication date: 2023-11-03
Anticipated expiration: 2043-09-27
Also published as: CN116991010B

Abstract

The application discloses an array substrate and a display panel, which mainly relate to the technical field of display, wherein the array substrate comprises a substrate, an active switch and a pixel electrode layer, the active switch and the pixel electrode layer are sequentially arranged on the substrate, the array substrate also comprises a plurality of scanning lines and a plurality of data lines, the scanning lines and the data lines are vertically and horizontally arranged on the substrate and divide a plurality of pixel unit areas, and the active switch is connected with the scanning lines and corresponds to the pixel unit areas one by one; the active switch comprises a first sub-active switch and a second sub-active switch which are arranged at intervals, the pixel electrode layer comprises a plurality of first gaps and a plurality of second gaps, the first gaps correspond to the first sub-active switch, and the second gaps correspond to the second sub-active switch. Through the design, the problem that dark spots appear on the display panel is avoided, the display effect is improved, and the optical taste of the display panel is improved on the basis that the charging capability of the active switch is not affected.

Description

Array substrate and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate and a display panel.

Background

With the development of digital technology, more and more display devices are going into people's lives, such as Electronic Paper (EP). Electronic paper displays are becoming popular because they can maintain their display for a long period of time in the event of a power failure, and have the advantages of light weight, thinness, low power consumption, simple process, etc.

The conventional electronic paper type display panel comprises a data line, a scanning line, a pixel electrode, electrophoretic particles and a common electrode, wherein the pixel electrode layer and the active switch are not overlapped due to the influence of parasitic capacitance, so that the electrophoretic particles in the area above the active switch are not controlled, dark spots appear in the display process, and the display effect is influenced; the pixel electrode layer and the active switch are overlapped, and an insulating layer is added between the pixel electrode layer and the active switch to reduce parasitic capacitance, or the pixel electrode layer and the active switch are not overlapped, but the size of the active switch is reduced, but the charging capability of the active switch is affected by the reduction of the size of the active switch.

Disclosure of Invention

The application aims to provide an array substrate and a display panel, which can avoid dark spots of the display panel and improve the display effect without reducing the size of an active switch.

The application discloses an array substrate, which comprises a substrate, an active switch and a pixel electrode layer, wherein the active switch and the pixel electrode layer are sequentially arranged on the substrate, the array substrate also comprises a plurality of scanning lines and a plurality of data lines, the scanning lines and the data lines are vertically and horizontally arranged on the substrate and divide a plurality of pixel unit areas, and the active switch is connected with the scanning lines and corresponds to the pixel unit areas one by one; the active switch comprises a first sub-active switch and a second sub-active switch which are arranged at intervals, the pixel electrode layer comprises a plurality of first gaps and a plurality of second gaps, the first gaps correspond to the first sub-active switch, and the second gaps correspond to the second sub-active switch.

Optionally, the pixel electrode layer includes a plurality of pixel electrodes, and the plurality of pixel electrodes are in one-to-one correspondence with the pixel unit areas;

the drain electrode of the first sub-active switch and the drain electrode of the second sub-active switch are connected to the same pixel electrode;

the first notch and the second notch are arranged on the same pixel electrode, and the first sub-active switch and the second sub-active switch are positioned on the same side of the scanning line.

Optionally, the pixel electrode layer includes a plurality of pixel electrodes, the plurality of pixel electrodes are in one-to-one correspondence with the pixel unit areas, the plurality of pixel electrodes are divided into a first pixel electrode and a second pixel electrode, and the first pixel electrode and the second pixel electrode respectively correspond to two pixel unit areas divided by two adjacent scanning lines;

the drain electrode of the first sub-active switch and the drain electrode of the second sub-active switch are connected with the same pixel electrode;

the first notch is arranged on the first pixel electrode, and the second notch is arranged on the second pixel electrode; the first sub-active switch and the second sub-active switch are respectively positioned at different sides of the scanning line.

Optionally, the pixel electrode layer includes a plurality of pixel electrodes, and the plurality of pixel electrodes are in one-to-one correspondence with the pixel unit areas; the plurality of pixel electrodes are divided into a third pixel electrode and a fourth pixel electrode, and the third pixel electrode and the fourth pixel electrode respectively correspond to two pixel unit areas divided by two adjacent scanning lines;

the active switch further comprises a third sub-active switch, a fourth sub-active switch, a fifth sub-active switch and a sixth sub-active switch which are arranged at intervals, wherein the third sub-active switch and the fourth sub-active switch are both positioned on one side of the scanning line, and the fifth sub-active switch and the sixth sub-active switch are both positioned on the other side of the scanning line;

the drain electrode of the third sub-active switch, the drain electrode of the fourth sub-active switch, the drain electrode of the fifth sub-active switch and the drain electrode of the sixth sub-active switch are connected with the same pixel electrode;

the pixel electrode layer further comprises a third notch, a fourth notch, a fifth notch and a sixth notch, wherein the third notch and the fourth notch are arranged on the third pixel electrode, and the fifth notch and the sixth notch are arranged on the fourth pixel electrode;

the third notch corresponds to the third sub-active switch, the fourth notch corresponds to the fourth sub-active switch, the fifth notch corresponds to the fifth sub-active switch, and the sixth notch corresponds to the sixth sub-active switch;

the sum of the area of the third notch, the area of the fourth notch, the area of the fifth notch and the area of the sixth notch is equal to the sum of the area of the first notch and the area of the second notch.

Optionally, the source of the third sub-active switch, the source of the fourth sub-active switch, the source of the fifth sub-active switch and the source of the sixth sub-active switch are connected with the same data line;

the distance between the third sub-active switch and the corresponding data line is unequal to the distance between the fifth sub-active switch and the corresponding data line; the distance between the third sub-active switch and the corresponding data line is unequal to the distance between the sixth sub-active switch and the corresponding data line;

the distance between the fourth sub-active switch and the corresponding data line is unequal to the distance between the fifth sub-active switch and the corresponding data line; the distance between the fourth sub-active switch and the corresponding data line is not equal to the distance between the sixth sub-active switch and the corresponding data line.

Optionally, a distance between the third sub-active switch and the fifth sub-active switch, a distance between the fifth sub-active switch and the fourth sub-active switch, and a distance between the fourth sub-active switch and the sixth sub-active switch are equal.

Optionally, the array substrate includes a first connecting line, a second connecting line and a bridging line, two ends of the first connecting line are respectively connected with the gate of the third sub-active switch and the gate of the fourth sub-active switch, two ends of the second connecting line are respectively connected with the gate of the fifth sub-active switch and the gate of the sixth sub-active switch, and two ends of the bridging line are respectively connected with the first connecting line and the second connecting line.

Optionally, the array substrate further includes a third connection line and a fourth connection line, where a drain electrode of the fourth sub-active switch is connected to the corresponding pixel electrode through the third connection line, and a drain electrode of the sixth sub-active switch is connected to the corresponding pixel electrode through the fourth connection line.

The application also discloses a display panel which comprises an electronic paper film, a public electrode layer and an array substrate, wherein the electronic paper film and the public electrode layer are sequentially arranged on one side, away from the substrate, of the pixel electrode layer.

Optionally, the electronic paper film includes a plurality of capsules, the capsules are uniformly arranged between the pixel electrode layer and the common electrode layer, a plurality of electrophoretic particles are arranged in the capsules, the capsules include a first capsule and a second capsule, the volume of the first capsule is larger than that of the second capsule, and the projection of the second capsule on the substrate coincides with the projection of the pixel electrode on the substrate;

the projection of the first capsule on the substrate covers the projection of the active switch on the substrate, and the projection of the active switch on the substrate is smaller than the corresponding projection of the first capsule on the substrate.

Compared with the scheme that the active switch is made small, so that the size of an avoidance area formed by the pixel electrode for avoiding the active switch is reduced, the first sub-active switch and the second sub-active switch are arranged at intervals, and the first notch and the second notch are respectively arranged at positions of the pixel electrode layer corresponding to the first sub-active switch and the second sub-active switch, which is equivalent to dividing an original large-area avoidance area into two small-area avoidance areas, so that the problem that dark spots appear on a display panel due to the fact that electrophoretic particles corresponding to the large-area avoidance areas cannot move is avoided, the display effect of the display panel is improved, the size of the active switch does not need to be reduced, the charging capacity of the active switch is not affected, and the optical taste of the display panel is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is evident that the figures in the following description are only some embodiments of the application, from which other figures can be obtained without inventive effort for a person skilled in the art. In the drawings:

fig. 1 is a schematic view of a display panel according to a first embodiment of the present application;

fig. 2 is a schematic view of an array substrate according to a first embodiment of the present application;

fig. 3 is a schematic view of a pixel electrode according to a first embodiment of the present application;

FIG. 4 is a schematic view of an array substrate according to a second embodiment of the present application;

FIG. 5 is a schematic view of an array substrate according to a third embodiment of the present application;

fig. 6 is a schematic view of an array substrate according to a fourth embodiment of the present application;

fig. 7 is a schematic view of an array substrate according to a fifth embodiment of the present application.

10, a display panel; 100. an electronic paper film; 110. a capsule; 111. a first capsule; 112. a second capsule; 120. electrophoresis particles; 200. an array substrate; 210. a substrate; 300. an active switch; 310. a first sub-active switch; 320. a second sub-active switch; 330. a third sub-active switch; 340. a fourth sub-active switch; 350. a fifth sub-active switch; 360. a sixth sub-active switch; 400. a pixel electrode layer; 410. a pixel electrode; 411. a first pixel electrode; 412. a second pixel electrode; 413. a third pixel electrode; 414. a fourth pixel electrode; 421. a first notch; 422. a second notch; 423. a third notch; 424. a fourth notch; 425. a fifth notch; 426. a sixth notch; 430. a pixel branch electrode; 500. a common electrode layer; 510. a common electrode; 520. a common branch electrode; 610. a scanning line; 620. a data line; 630. a pixel unit area; 710. a first connecting line; 720. a second connecting line; 730. a third connecting line; 740. a fourth connecting line; 750. and (5) bridging lines.

Detailed Description

It is to be understood that the terminology used herein, the specific structural and functional details disclosed are merely representative for the purpose of describing particular embodiments, but that the application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or implicitly indicating the number of technical features indicated. Thus, unless otherwise indicated, features defining "first", "second" may include one or more such features either explicitly or implicitly; the meaning of "plurality" is two or more. The terms "comprises," "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or groups thereof may be present or added.

In addition, terms of the azimuth or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are described based on the azimuth or relative positional relationship shown in the drawings, are merely for convenience of description of the present application, and do not indicate that the apparatus or element referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present application.

Furthermore, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

The application is described in detail below with reference to the attached drawings and alternative embodiments.

Example 1:

fig. 1 is a schematic diagram of a display panel according to a first embodiment of the present application, and as shown in fig. 1, the present application discloses a display panel 10, wherein the display panel 10 includes an electronic paper film 100, a common electrode layer 500, and the array substrate 200, and the electronic paper film 100 and the common electrode layer 500 are sequentially disposed on a side of the pixel electrode layer 400 on the array substrate 200 facing away from the substrate 210.

The electronic paper film 100 includes a plurality of capsules 110, the capsules 110 are uniformly arranged between the pixel electrode layer 400 and the common electrode layer 500, a plurality of electrophoretic particles 120 are disposed in the capsules 110, and the pixel electrode layer 400 and the common electrode layer 500 drive the electrophoretic particles 120 in the electronic paper film 100 to move so as to display a picture.

The electrophoretic particles 120 include black electrophoretic particles 120, white electrophoretic particles 120, and color electrophoretic particles 120, which are not limited herein.

Wherein the capsule 110 comprises a first capsule 111 and a second capsule 112, the volume of the first capsule 111 is larger than the volume of the second capsule 112, and the projection of the second capsule 112 on the substrate 210 coincides with the projection of the pixel electrode 410 on the substrate 210.

The projection of the first capsule 111 onto the substrate 210 covers the projection of the active switch 300 onto the substrate 210, the projection of the active switch 300 onto the substrate 210 being smaller than the corresponding projection of the first capsule 111 onto the substrate 210.

In this way, a part of the electrophoretic particles 120 in the first capsule 111 are located between the pixel electrode 410 and the common electrode 510, and when the pixel electrode 410 and the common electrode 510 work, a part of the electrophoretic particles 120 in the first capsule 111 located between the pixel electrode 410 and the common electrode 510 participate in movement, so that the problem of dark spots corresponding to the positions of the active switches 300 is relieved.

The embodiment also discloses an array substrate 200, the array substrate 200 can be used in the display panel 10, and the application provides the following design for the array substrate 200:

fig. 2 is a schematic diagram of an array substrate according to a first embodiment of the present application, and as shown in fig. 1 and 2, the present embodiment discloses an array substrate 200, where the array substrate 200 includes a substrate 210, an active switch 300, and a pixel electrode layer 400, the active switch 300 and the pixel electrode layer 400 are sequentially disposed on the substrate 210, the array substrate 200 further includes a plurality of scan lines 610 and a plurality of data lines 620, the scan lines 610 and the data lines 620 are disposed on the substrate 210 in a vertically and horizontally arrangement, and a plurality of pixel unit areas 630 are divided, and the active switch 300 is connected with the scan lines 610 and corresponds to the pixel unit areas 630 one by one.

The active switch 300 includes a first sub-active switch 310 and a second sub-active switch 320 that are disposed at intervals, the pixel electrode layer 400 includes a plurality of first gaps 421 and a plurality of second gaps 422, the first gaps 421 correspond to the first sub-active switch 310, and the second gaps 422 correspond to the second sub-active switch 320.

Compared with the scheme that the active switch 300 is made small, so that the size of an avoidance area formed by the pixel electrode layer 400 for avoiding the active switch 300 is reduced, the display effect of the display panel 10 is improved by arranging the first sub-active switch 310 and the second sub-active switch 320 at intervals, and arranging the first notch 421 and the second notch 422 at positions of the pixel electrode layer 400 corresponding to the first sub-active switch 310 and the second sub-active switch 320 respectively is equivalent to dividing an original large-area avoidance area into two small-area avoidance areas, so that the problem that dark spots appear on the display panel 10 due to the fact that electrophoretic particles 120 corresponding to the large-area avoidance areas cannot move is avoided, the size of the active switch 300 is not required to be reduced, the charging capability of the active switch 300 is not influenced, and the optical taste of the display panel 10 is improved.

Compared with the scheme that the active switch 300 and the pixel electrode layer 400 are not arranged in an avoidance mode, and the insulating layer is arranged between the active switch 300 and the pixel electrode layer 400 to reduce the parasitic capacitance problem caused by overlapping of the active switch 300 and the pixel electrode layer 400, the scheme of the application does not need an additional film layer manufacturing process, has lower cost and is simpler in preparation scheme.

The pixel electrode layer 400 includes a plurality of pixel electrodes 410, and the plurality of pixel electrodes 410 are in one-to-one correspondence with the pixel unit areas 630; the gates of the first sub-active switch 310 and the second sub-active switch 320 are connected to the same scan line 610, the sources of the first sub-active switch 310 and the second sub-active switch 320 are connected to the same data line 620, and the drains of the first sub-active switch 310 and the second sub-active switch 320 are connected to the same pixel electrode 410. The first notch 421 and the second notch 422 are disposed on the same pixel electrode 410, and the first sub-active switch 310 and the second sub-active switch 320 are located on the same side of the scan line 610.

In this embodiment, taking the example that the first sub-active switch 310 and the second sub-active switch 320 are located in the pixel unit area 630 corresponding to the pixel electrode 410 connected to the first sub-active switch 310 and the second sub-active switch 320 are located above the scan line 610. Of course, the first sub-active switch 310 and the second sub-active switch 320 may also be located in the pixel unit area 630 corresponding to the pixel electrode 410 below the scan line 610.

Fig. 3 is a schematic view of a pixel electrode according to a first embodiment of the present application, as shown in fig. 3, the pixel electrode layer 400 further includes a plurality of pixel stem electrodes 430, the pixel stem electrodes 430 are disposed on edges of the first notch 421 and the second notch 422 to form a tooth-shaped structure, and a projection of the pixel stem electrodes 430 on the substrate 210 overlaps a projection of the active switch 300 on the substrate 210.

The common electrode layer 500 includes a plurality of common electrodes 510, and the plurality of common electrodes 510 are in one-to-one correspondence with the pixel unit areas 630; the common electrode 510 is also provided with notches corresponding to the first notch 421 and the plurality of second notches 422 of the pixel electrode layer 400, and the common electrode layer 500 further includes a plurality of common branch electrodes 520, where the plurality of common branch electrodes 520 are in one-to-one correspondence with the pixel branch electrodes 430, and the projection of the common branch electrodes 520 on the substrate 210 coincides with the projection of the pixel branch electrodes 430 on the substrate 210.

By adopting the design of the plurality of pixel branch electrodes 430, on the basis of reducing the overlapping area of the pixel electrode layer 400 and the active switch 300 in the avoidance area and reducing the parasitic capacitance between the active switch 300 and the pixel electrode 410, the electrophoretic particles 120 in the corresponding avoidance area can be controlled by the electric field between the pixel branch electrodes 430 and the common branch electrode 520, and the problem of dark spots of the display panel 10 is avoided.

Example 2:

fig. 4 is a schematic diagram of an array substrate according to a second embodiment of the present application, as shown in fig. 4, the array substrate 200 according to this embodiment may be used in the display panel 10 according to the first embodiment, and unlike the first embodiment, the first sub-active switch 310 and the second sub-active switch 320 are respectively located on different sides of the scan line 610.

The pixel electrode layer 400 includes a plurality of pixel electrodes 410, the plurality of pixel electrodes 410 are in one-to-one correspondence with the pixel unit areas 630, the plurality of pixel electrodes 410 are divided into a first pixel electrode 411 and a second pixel electrode 412, and the first pixel electrode 411 and the second pixel electrode 412 respectively correspond to two pixel unit areas 630 divided by two adjacent scan lines 610.

The gates of the first sub-active switch 310 and the second sub-active switch 320 are connected to the same scan line 610, the sources of the first sub-active switch 310 and the second sub-active switch 320 are connected to the same data line 620, and the drains of the first sub-active switch 310 and the second sub-active switch 320 are connected to the same pixel electrode 410; the first notch 421 is disposed on the first pixel electrode 411, and the second notch 422 is disposed on the second pixel electrode 412; the first sub-active switch 310 and the second sub-active switch 320 are respectively located at different sides of the scan line 610.

Compared with the first embodiment, in this embodiment, the first sub-active switch 310 and the second sub-active switch 320 are respectively disposed on the upper side and the lower side of the scan line 610, so that the distance between the first sub-active switch 310 and the second sub-active switch 320 is further pulled, and the influence on the display effect of the display panel 10 due to the excessive concentration of the area where dark spots may occur is avoided; in addition, the first sub-active switch 310 and the second sub-active switch 320 are located on the upper and lower sides of the scan line 610, and the first sub-active switch 310 is located above the scan line 610, and the second sub-active switch 320 is located below the scan line 610, where the second sub-active switch 320 is located in the pixel unit area 630 defined by the next row of scan line 610, and since the scan line 610 is scanned one row by one row, when the first sub-active switch 310 and the second sub-active switch 320 are turned on, no oblique parasitic capacitance occurs between the second sub-active switch 300 and the pixel electrode 410 in the pixel unit area 630 defined by the next row of scan line 610, thereby further alleviating the influence of the parasitic capacitance on the display effect of the display panel 10.

It is also possible that the first sub-active switch 310 is located below the scan line 610, and the second sub-active switch 320 is located above the scan line 610, which is not limited herein.

Example 3:

fig. 5 is a schematic diagram of an array substrate according to a third embodiment of the present application, as shown in fig. 5, the array substrate 200 according to the present embodiment may be used in the display panel 10 according to the first embodiment, unlike the first embodiment, in which two active switches 300 are changed into four active switches 300 without changing the overall area of the active switches 300, and two of the four active switches 300 are disposed on the same side of the scan line 610, and the other two are disposed on the other side of the scan line 610, specifically.

The pixel electrode layer 400 includes a plurality of pixel electrodes 410, and the plurality of pixel electrodes 410 are in one-to-one correspondence with the pixel unit areas 630; the plurality of pixel electrodes 410 are divided into a third pixel electrode 413 and a fourth pixel electrode 414, and the third pixel electrode 413 and the fourth pixel electrode 414 respectively correspond to two pixel unit areas 630 divided by two adjacent scan lines 610.

The active switch 300 further includes a third sub-active switch 330, a fourth sub-active switch 340, a fifth sub-active switch 350 and a sixth sub-active switch 360 that are disposed at intervals, where the third sub-active switch 330 and the fourth sub-active switch 340 are both located at one side of the scan line 610, and the fifth sub-active switch 350 and the sixth sub-active switch 360 are both located at the other side of the scan line 610.

The gate of the third sub-active switch 330, the gate of the fourth sub-active switch 340, the gate of the fifth sub-active switch 350, and the gate of the sixth sub-active switch 360 are connected to the same scan line 610; the source of the third sub-active switch 330, the source of the fourth sub-active switch 340, the source of the fifth sub-active switch 350 and the source of the sixth sub-active switch 360 are connected to the same data line 620; the drain electrode of the third sub-active switch 330, the drain electrode of the fourth sub-active switch 340, the drain electrode of the fifth sub-active switch 350, and the drain electrode of the sixth sub-active switch 360 are connected to the same pixel electrode 410.

The pixel electrode layer 400 further includes a third notch 423, a fourth notch 424, a fifth notch 425, and a sixth notch 426, where the third notch 423 and the fourth notch 424 are disposed on the third pixel electrode 413, and the fifth notch 425 and the sixth notch 426 are disposed on the fourth pixel electrode 414.

The third notch 423 corresponds to the third sub-active switch 330, the fourth notch 424 corresponds to the fourth sub-active switch 340, the fifth notch 425 corresponds to the fifth sub-active switch 350, the sixth notch 426 corresponds to the sixth sub-active switch 360.

The sum of the area of the third notch 423, the area of the fourth notch 424, the area of the fifth notch 425, and the area of the sixth notch 426 is equal to the sum of the area of the first notch 421 and the area of the second notch 422.

Compared to the first embodiment, the present embodiment is equivalent to arranging the first sub-active switch 310 and the second sub-active switch 320 as four sub-active switches 330, 340, 350 and 360, respectively, and the sum of the areas of the third sub-active switch 330, 340, 350 and 360 is equal to the sum of the areas of the first sub-active switch 310 and the second sub-active switch 320, so that the original charging capability is not reduced, and the avoidance area is divided into smaller areas, further reducing the possibility that the display panel 10 may appear dark spots.

The array substrate 200 includes a first connection line 710, a second connection line 720, and a bridge line 750, wherein two ends of the first connection line 710 are connected to the gate electrode of the third sub-active switch 330 and the gate electrode of the fourth sub-active switch 340, two ends of the second connection line 720 are connected to the gate electrode of the fifth sub-active switch 350 and the gate electrode of the sixth sub-active switch 360, and two ends of the bridge line 750 are connected to the first connection line 710 and the second connection line 720. The array substrate 200 further includes a third connection line 730 and a fourth connection line 740, the drain electrode of the fourth sub-active switch 340 is connected to the corresponding pixel electrode 410 through the third connection line 730, and the drain electrode of the sixth sub-active switch 360 is connected to the corresponding pixel electrode 410 through the fourth connection line 740.

Thus, if any one of the third sub-active switch 330, the fourth sub-active switch 340, the fifth sub-active switch 350 and the sixth sub-active switch 360 has a problem, the repair can be performed by cutting the connection line.

For example, if the third sub-active switch 330 is abnormal, the laser machine is used to cut off the position between the third sub-active switch 330 and the bridging line 750 on the first connecting line 710, and the fourth sub-active switch 340, the fifth sub-active switch 350 and the sixth sub-active switch 360 may still be normal; if the fourth sub-active switch 340 is abnormal, the laser machine is used to cut off the position between the fourth sub-active switch 340 and the bridging line 750 on the first connecting line 710, and the third sub-active switch 330, the fifth sub-active switch 350 and the sixth sub-active switch 360 can still be normal; if the fifth sub-active switch 350 is abnormal, the laser machine is used to cut off the position between the fifth sub-active switch 350 and the bridging line 750 on the second connecting line 720, and the third sub-active switch 330, the fourth sub-active switch 340 and the sixth sub-active switch 360 can still be normal; if the sixth sub-active switch 360 is abnormal, the laser machine is used to cut off the position between the sixth sub-active switch 360 and the bridging line 750 on the second connecting line 720, and the third sub-active switch 330, the fourth sub-active switch 340 and the fifth sub-active switch 350 can still be normal.

If the third sub-active switch 330 and the fourth sub-active switch 340 are abnormal at the same time, the bridge wire 750 is only required to be cut off through the laser machine, and the fifth sub-active switch 350 and the sixth sub-active switch 360 can still be normal; if the fifth sub-active switch 350 and the sixth sub-active switch 360 are abnormal at the same time, the bridge 750 is only cut off by the laser machine, and the third sub-active switch 330 and the fourth sub-active switch 340 can still be normal.

Example 4:

fig. 6 is a schematic diagram of an array substrate according to a fourth embodiment of the present application, as shown in fig. 6, in which the array substrate 200 according to the present embodiment can be used in the display panel 10 according to the first embodiment, unlike the third embodiment, the present embodiment is equivalent to that the third sub-active switch 330 and the fourth sub-active switch 340 located on the same side of the scan line 610 and the fifth sub-active switch 350 and the sixth sub-active switch 360 located on the other side of the scan line 610 are arranged in a staggered manner, and the length direction of the data line 620 is taken as the first direction, so that any one of the third sub-active switch 330 and the fourth sub-active switch 340 is not on the same line as any one of the fifth sub-active switch 350 and the sixth sub-active switch 360 in the first direction.

The distance between the third sub-active switch 330 and the corresponding data line 620 is not equal to the distance between the fifth sub-active switch 350 and the corresponding data line 620; the distance between the third sub-active switch 330 and the corresponding data line 620 and the distance between the sixth sub-active switch 360 and the corresponding data line 620 are not equal.

The distance between the fourth sub-active switch 340 and the corresponding data line 620 is not equal to the distance between the fifth sub-active switch 350 and the corresponding data line 620; the distance between the fourth sub-active switch 340 and the corresponding data line 620 and the distance between the sixth sub-active switch 360 and the corresponding data line 620 are not equal.

Compared to the solution of the third embodiment, in this embodiment, the avoidance areas in the two adjacent pixel unit areas 630 in the first direction are not connected together, that is, any notch in the third notch 423 and the fourth notch 424 in the first pixel unit and any notch in the fifth notch 425 and the sixth notch 426 in the second pixel unit are not connected together, so that two avoidance areas are avoided to be close to form a large avoidance area, and the problem that the display panel 10 has dark spots is avoided.

Further, the distance between the third sub-active switch 330 and the fifth sub-active switch 350, the distance between the fifth sub-active switch 350 and the fourth sub-active switch 340, and the distance between the fourth sub-active switch 340 and the sixth sub-active switch 360 are equal. That is, the length direction of the scan line 610 is taken as the second direction, and in the second direction, the third sub-active switch 330, the fourth sub-active switch 340, the fifth sub-active switch 350 and the sixth sub-active switch 360 are equidistantly arranged, so that the third notch 423, the fourth notch 424, the fifth notch 425 and the sixth notch 426 are distributed more uniformly, and the display effect of the picture is improved.

Example 5:

fig. 7 is a schematic diagram of an array substrate according to a fifth embodiment of the present application, as shown in fig. 7, the array substrate 200 according to the present embodiment may be used in the display panel 10 according to the first embodiment, and the difference between the first embodiment and the fourth embodiment is that the third sub-active switch 330, the fourth sub-active switch 340, the fifth sub-active switch 350 and the sixth sub-active switch 360 are all located on the same side of the scan line 610, may be located above the scan line 610 or below the scan line 610, and is not limited thereto, and the third sub-active switch 330, the fourth sub-active switch 340, the fifth sub-active switch 350 and the sixth sub-active switch 360 are all located on the upper side of the scan line 610.

The active switch 300 further includes a third sub-active switch 330, a fourth sub-active switch 340, a fifth sub-active switch 350 and a sixth sub-active switch 360 that are disposed at intervals, where the third sub-active switch 330, the fourth sub-active switch 340, the fifth sub-active switch 350 and the sixth sub-active switch 360 are all located at the same side of the scan line 610.

The pixel electrode layer 400 further includes a third notch 423, a fourth notch 424, a fifth notch 425, and a sixth notch 426, where the third notch 423, the fourth notch 424, the fifth notch 425, and the sixth notch 426 are all disposed on the third pixel electrode 413.

Compared to the fourth embodiment, in this embodiment, after any one or more of the third sub-active switch 330, the fourth sub-active switch 340, the fifth sub-active switch 350 and the sixth sub-active switch 360 are abnormal, the connection between the corresponding active switch 300 and the pixel electrode 410 is only required to be disconnected to ensure that other normal active switches 300 are continuously used, and since the third sub-active switch 330, the fourth sub-active switch 340, the fifth sub-active switch 350 and the sixth sub-active switch 360 are all located on the same side of the scan line 610, the preparation is also simpler.

It should be noted that, the inventive concept of the present application can form a very large number of embodiments, but the application documents are limited in space and cannot be listed one by one, so that on the premise of no conflict, the above-described embodiments or technical features can be arbitrarily combined to form new embodiments, and after the embodiments or technical features are combined, the original technical effects will be enhanced.

The above description of the application in connection with specific alternative embodiments is further detailed and it is not intended that the application be limited to the specific embodiments disclosed. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.

Claims

1. The array substrate comprises a substrate, an active switch and a pixel electrode layer, wherein the active switch and the pixel electrode layer are sequentially arranged on the substrate, the array substrate further comprises a plurality of scanning lines and a plurality of data lines, the scanning lines and the data lines are vertically and horizontally arranged on the substrate and divide a plurality of pixel unit areas, and the active switch is connected with the scanning lines and corresponds to the pixel unit areas one by one; the pixel electrode layer comprises a plurality of first gaps and a plurality of second gaps, wherein the first gaps correspond to the first sub-active switches, and the second gaps correspond to the second sub-active switches.

2. The array substrate of claim 1, wherein the pixel electrode layer includes a plurality of pixel electrodes, the plurality of pixel electrodes being in one-to-one correspondence with the pixel unit areas;

3. The array substrate of claim 1, wherein the pixel electrode layer includes a plurality of pixel electrodes, the plurality of pixel electrodes are in one-to-one correspondence with the pixel unit areas, the plurality of pixel electrodes are divided into a first pixel electrode and a second pixel electrode, and the first pixel electrode and the second pixel electrode respectively correspond to two pixel unit areas divided by two adjacent scan lines;

4. The array substrate of claim 1, wherein the pixel electrode layer includes a plurality of pixel electrodes, the plurality of pixel electrodes being in one-to-one correspondence with the pixel unit areas; the plurality of pixel electrodes are divided into a third pixel electrode and a fourth pixel electrode, and the third pixel electrode and the fourth pixel electrode respectively correspond to two pixel unit areas divided by two adjacent scanning lines;

5. The array substrate of claim 4, wherein the source of the third sub-active switch, the source of the fourth sub-active switch, the source of the fifth sub-active switch, and the source of the sixth sub-active switch are connected to the same data line;

6. The array substrate of claim 5, wherein a pitch between the third and fifth sub-active switches, a pitch between the fifth and fourth sub-active switches, and a distance between the fourth and sixth sub-active switches are equal.

7. The array substrate of claim 4, wherein the array substrate comprises a first connection line, a second connection line, and a bridge line, wherein two ends of the first connection line are respectively connected with the gate electrode of the third sub-active switch and the gate electrode of the fourth sub-active switch, two ends of the second connection line are respectively connected with the gate electrode of the fifth sub-active switch and the gate electrode of the sixth sub-active switch, and two ends of the bridge line are respectively connected with the first connection line and the second connection line.

8. The array substrate of claim 7, further comprising a third connection line and a fourth connection line, wherein a drain electrode of the fourth sub-active switch is connected to the corresponding pixel electrode through the third connection line, and a drain electrode of the sixth sub-active switch is connected to the corresponding pixel electrode through the fourth connection line.

9. A display panel comprising an electronic paper film and a common electrode layer, characterized in that the display panel further comprises an array substrate according to any one of claims 1-8, wherein the electronic paper film and the common electrode layer are sequentially disposed on a side of the pixel electrode layer facing away from the substrate.

10. The display panel according to claim 9, wherein the electronic paper film includes a plurality of capsules uniformly arranged between the pixel electrode layer and the common electrode layer, a plurality of electrophoretic particles are provided in the capsules, the capsules include a first capsule and a second capsule, a volume of the first capsule is larger than a volume of the second capsule, and a projection of the second capsule on the substrate coincides with a projection of a pixel electrode on the substrate;