CN116978889A

CN116978889A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN116978889A
Application number: CN202210435693.1A
Authority: CN
Inventors: 邵光速; 杨蒙蒙; 郁梦康; 尤康
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-04-24
Filing date: 2022-04-24
Publication date: 2023-10-31
Also published as: WO2023206803A1

Abstract

The semiconductor structure comprises a substrate and at least one memory unit, wherein each memory unit comprises a plurality of active strips and at least one group of stacked capacitors, the plurality of active strips are arranged above the substrate in an array manner and are parallel to the substrate, and any two adjacent active strips are separated by a first groove; any two adjacent active stripes are separated by a second trench in a plane perpendicular to the substrate; two adjacent groups of stacked capacitors are arranged at intervals, each group of stacked capacitors comprises a lower electrode, a dielectric layer and an upper electrode, the lower electrode comprises a part of structure penetrating through each active strip of the stacked capacitors, and the upper electrode covers the dielectric layer and fills the first groove and the second groove between the lower electrodes. By stacking the stacked capacitors in the vertical direction in the present disclosure, the stacked capacitors have an increased number of stacked layers, increasing the storage density of the semiconductor structure.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.

Background

In the field of integrated circuits, the performance of integrated circuits is doubled every time a semiconductor device in an integrated circuit is doubled according to moore's law, so that the size of the integrated circuit is continuously reduced and the integration level is continuously improved in order to improve the electrical performance of the integrated circuit.

Currently, the dynamic random access memory (Dynamic Random Access Memory, DRAM) is generally of a single-layer structure, and the size of the dynamic random access memory of the single-layer structure has been reduced to the limit, and it is difficult to continue the validity of the moore's law. In addition, the continuous miniaturization of the feature size of the dynamic random access memory increases the processing difficulty, and the smaller the feature size is, the lower the yield of the dynamic random access memory is.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

The present disclosure provides a semiconductor structure and a method of fabricating the semiconductor structure.

A first aspect of the present disclosure provides a semiconductor structure comprising a substrate and at least one memory cell disposed on the substrate, each memory cell comprising:

A plurality of active bars, wherein the plurality of active bars are arranged above the substrate in an array manner, each active bar extends along a first direction, any two adjacent active bars are separated by a first groove on a plane parallel to the substrate, and any two adjacent active bars are separated by a second groove on a plane perpendicular to the substrate;

at least one set of stacked capacitors, two adjacent sets of stacked capacitors are arranged at intervals, each set of stacked capacitors comprises a lower electrode, a dielectric layer covering the side wall of the lower electrode and an upper electrode, the lower electrode comprises a part of structure penetrating through each active strip of the stacked capacitors, and the upper electrode covers the dielectric layer and fills the first groove and the second groove between the lower electrodes.

According to some embodiments of the present disclosure, the semiconductor structure includes a plurality of memory cells, the plurality of memory cells being cyclically arranged on the substrate along the first direction.

According to some embodiments of the present disclosure, the semiconductor structure further comprises:

a support structure disposed on the substrate, the support structure disposed between adjacent ones of the memory cells, the support structure connecting two stacked capacitors of adjacent ones of the memory cells.

According to some embodiments of the disclosure, the material of the support structure comprises an insulating material.

According to some embodiments of the disclosure, the stacked capacitor further comprises:

the plurality of concave parts are arranged at one end, close to the supporting structure, of the stacked capacitor, each concave part is arranged between two adjacent active strips, and each concave part faces the supporting structure.

According to some embodiments of the disclosure, the support structure further comprises:

the protruding portions are arranged on the side walls of the supporting structure, each protruding portion is arranged corresponding to the corresponding recessed portion, and each protruding portion is embedded into the corresponding recessed portion.

According to some embodiments of the disclosure, each of the memory cells further comprises:

the array area is arranged between two adjacent groups of stacked capacitors and is connected with the stacked capacitors through a plurality of active strips.

According to some embodiments of the disclosure, the array region comprises:

a plurality of word lines, each of the word lines being vertically disposed on the substrate, any adjacent two of the word lines being disposed between the lines on a plane parallel to the substrate, each of the word lines intersecting a portion of the active bars of the plurality of active bars, and each of the word lines covering a portion of sidewalls of the active bars;

A plurality of bit lines, each bit line extending along a second direction, the second direction being in a plane parallel to the substrate and perpendicular to the first direction, any adjacent two bit lines being spaced apart on a plane perpendicular to the substrate, each bit line intersecting a portion of the active bars of the plurality of active bars and each bit line covering a portion of sidewalls of the active bars;

the plurality of word lines and the plurality of bit lines are separated by isolation structures.

According to some embodiments of the disclosure, in the first direction, each of the memory cells includes two sets of the stacked capacitors symmetrically disposed on both sides of the array region.

A second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method for manufacturing a semiconductor structure including:

providing a first structure, wherein the first structure comprises a capacitor region, the first structure comprises a substrate and a plurality of active strips, the active strips are arranged above the substrate in an array manner, each active strip extends along a first direction, in the capacitor region, any two adjacent active strips are separated by a first groove on a plane parallel to the substrate, any two adjacent active strips are separated by a second groove on a plane perpendicular to the substrate, and the second groove is communicated with the first groove and exposes the side wall of the active strip positioned in the capacitor region;

Forming a dielectric layer in the capacitor region, wherein the dielectric layer covers the exposed side wall of the active strip;

forming an upper electrode in the capacitor region, wherein the upper electrode covers the dielectric layer and fills the first groove and the second groove in the capacitor region;

and taking a part of structure of each active strip in the capacitance area as a lower electrode, wherein the upper electrode, the dielectric layer and the lower electrode form a stacked capacitor vertically stacked on the substrate.

According to some embodiments of the present disclosure, there is provided a first structure comprising:

providing a substrate, and forming a stacking structure on the substrate, wherein the stacking structure comprises an active layer and a sacrificial layer which are alternately stacked in sequence;

forming a plurality of first trenches in the stacked structure, wherein each first trench extends along the first direction, and in the direction perpendicular to the substrate, each first trench penetrates through the stacked structure, and the reserved active layer is divided into a plurality of active strips by the first trenches;

and removing part of the sacrificial layer, forming the second groove in the capacitor region, wherein the first groove is communicated with the second groove, and exposing the side wall of the active strip in the capacitor region.

According to some embodiments of the disclosure, the first structure further includes a first region, the capacitance region is located in the first region, and the manufacturing method further includes:

and forming a supporting structure in the first region, wherein the supporting structure extends along a second direction and penetrates through the first structure, the second direction is parallel to the plane of the substrate, the second direction is perpendicular to the first direction, and the supporting structure divides the first region into two independently arranged capacitor regions.

According to some embodiments of the present disclosure, forming a support structure includes:

etching the first region, forming a channel groove in the first region, wherein the channel groove extends along the second direction and penetrates through the first structure, and the channel groove exposes part of the substrate;

and depositing insulating material to fill the channel grooves to form the support structure.

According to some embodiments of the present disclosure, when the first region is etched, an etching speed of etching the sacrificial layer is greater than an etching speed of etching the active bars, a plurality of concave portions are formed in the groove wall of the channel groove, and each concave portion is transversely recessed between two adjacent active bars;

A portion of the insulating material fills the recess, forming a plurality of protrusions on the sidewalls of the support structure.

According to some embodiments of the disclosure, the first structure further includes an array region, the providing the first structure further includes:

removing the sacrificial layer in the array region;

forming a plurality of word lines in the array region, wherein each word line is vertically arranged on the substrate, any two adjacent word lines are arranged between the two word lines on a plane parallel to the substrate, each word line intersects with part of the active strips in the plurality of active strips, and each word line covers part of the side walls of the active strips;

and forming a plurality of bit lines in the array region, wherein each bit line extends along a second direction, the second direction is positioned in a plane parallel to the substrate, the second direction is perpendicular to the first direction, any two adjacent bit lines are arranged between the bit lines on the plane perpendicular to the substrate, each bit line is intersected with part of the active strips in the plurality of active strips, and each bit line covers part of the side walls of the active strips.

According to some embodiments of the disclosure, the providing a first structure further includes:

And forming an isolation structure in the array region, wherein the isolation structure fills gaps between a plurality of word lines and a plurality of bit lines.

In the semiconductor structure and the manufacturing method of the semiconductor structure provided by the embodiment of the disclosure, the stacked capacitor stacked in the vertical direction is added, so that the semiconductor structure is provided with the 3D framework with a plurality of layers stacked, the storage density of the semiconductor structure is increased, and the stacked capacitor is provided with the number of stacked layers which can be increased, so that the semiconductor structure provided by the disclosure is provided with the storage density which can be increased continuously, and the electrical property of the semiconductor structure is greatly improved.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.

Fig. 1 is a side view of a semiconductor structure shown in accordance with an exemplary embodiment.

Fig. 2 is a top view of region a of fig. 1, shown according to an exemplary embodiment.

Fig. 3 is a cross-sectional view of the a-a plane of fig. 2.

Fig. 4 is a cross-sectional view of the b-b plane of fig. 2.

Fig. 5 is a cross-sectional view of the c-c plane of fig. 2.

Fig. 6 is a sectional view of the d-d plane of fig. 2.

Fig. 7 is a flowchart illustrating a method of fabricating a semiconductor structure, according to an exemplary embodiment.

Fig. 8 is a top view of a formed stacked structure, according to an example embodiment.

FIG. 9 is a cross-sectional view of a-a, b-b, c-c, d-d of FIG. 8.

Fig. 10 is a top view illustrating formation of a first trench according to an exemplary embodiment.

FIG. 11 is a cross-sectional view of a-a, b-b, c-c, d-d of FIG. 10.

Fig. 12 is a top view illustrating formation of a third trench according to an exemplary embodiment.

FIG. 13 is a cross-sectional view of a-a, b-b, d-d of FIG. 12.

Fig. 14 is a top view illustrating the formation of an initial gate oxide layer according to an exemplary embodiment.

FIG. 15 is a cross-sectional view of a-a, b-b, d-d of FIG. 14.

Fig. 16 is a top view illustrating the formation of an initial high-K dielectric layer according to an exemplary embodiment.

FIG. 17 is a cross-sectional view of a-a, b-b, d-d of FIG. 16.

Fig. 18 is a top view of a formed word line, according to an example embodiment.

FIG. 19 is a cross-sectional view of a-a, b-b, d-d of FIG. 18.

Fig. 20 is a top view of a portion of an active strip shown removed from an array region according to an exemplary embodiment.

FIG. 21 is a cross-sectional view of a-a, b-b, d-d of FIG. 20.

Fig. 22 is a top view illustrating the formation of source and drain layers according to an example embodiment.

FIG. 23 is a cross-sectional view of a-a, b-b, d-d of FIG. 22.

Figure 24 illustrates a top view of forming a first isolation layer, according to an example embodiment.

FIG. 25 is a cross-sectional view of a-a, b-b, d-d of FIG. 24.

Fig. 26 illustrates a top view of forming a bit line trench, according to an example embodiment.

FIG. 27 is a cross-sectional view of a-a, b-b, d-d of FIG. 26.

Fig. 28 illustrates a top view of forming a bit line according to an example embodiment.

Fig. 29 is a cross-sectional view of a-a, b-b, d-d of fig. 28.

Fig. 30 illustrates a top view of forming isolation structures according to an example embodiment.

FIG. 31 is a cross-sectional view of a-a, b-b, d-d of FIG. 30.

Fig. 32 illustrates a top view of a first region according to an exemplary embodiment.

Fig. 33 is a sectional view a-a of fig. 32.

Fig. 34 is a section b-b of fig. 32.

Fig. 35 is a c-c section view of fig. 32.

Fig. 36 illustrates a top view of forming a channel trench in a first region, according to an exemplary embodiment.

Fig. 37 is a sectional view a-a of fig. 36.

Fig. 38 is a section b-b of fig. 36.

Fig. 39 illustrates a top view of forming a support structure according to an exemplary embodiment.

Fig. 40 is a sectional view a-a of fig. 39.

FIG. 41 is a section b-b of FIG. 39.

Fig. 42 illustrates a top view of a sacrificial layer removing a capacitive region according to an exemplary embodiment.

FIG. 43 is a section a-a of FIG. 42.

Fig. 44 is a section b-b of fig. 42.

Fig. 45 is a c-c section view of fig. 42.

Fig. 46 illustrates a top view of forming a dielectric layer according to an exemplary embodiment.

Fig. 47 is a section a-a of fig. 46.

Fig. 48 is a section b-b of fig. 46.

Fig. 49 is a c-c section view of fig. 46.

Fig. 50 illustrates a top view of forming an upper electrode according to an exemplary embodiment.

FIG. 51 is a section a-a of FIG. 50.

Fig. 52 is a section b-b of fig. 50.

Fig. 53 is a c-c section view of fig. 50.

Reference numerals:

100. a first structure; 101. a first region; 1011. a capacitance region; 102. an array region; 110. a substrate; 120. a stacked structure; 121. a sacrificial layer; 122. an active layer; 123. a dielectric layer; 130. an active stripe; 140. a first trench; 150. a second trench; 160. a third trench; 200. a support structure; 210. a channel groove; 211. a recessed portion; 220. a boss; 300. stacking the capacitors; 310. a lower electrode; 320. a dielectric layer; 330. an upper electrode; 400. a word line; 401. an initial gate oxide layer; 402. an initial high-K dielectric layer; 410. a gate oxide layer; 420. a high-K dielectric layer; 430. a word line layer; 440. a source electrode layer; 450. a drain layer; 500. a bit line; 510. bit line trenches; 600. an isolation structure; 610. a first isolation layer; 620. a second isolation layer; 700. a memory unit;

D1, a first direction; d2, the second direction.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

The exemplary embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the semiconductor structure, wherein the semiconductor structure includes a stacked capacitor stacked in a vertical direction, which increases a storage density of the semiconductor structure, and the stacked capacitor has an increasing number of stacked layers, so that the semiconductor structure has a continuously increasing storage density, overcomes a problem that the storage density of a dynamic random access memory is difficult to continuously increase due to size shrinkage, and provides a new direction for development of the dynamic random access memory.

The exemplary embodiments of the present disclosure provide a semiconductor structure, which is not limited to the embodiment, and the semiconductor structure will be described below as a Dynamic Random Access Memory (DRAM), but the embodiment is not limited to this, and the semiconductor structure in the embodiment may be other structures.

As shown in fig. 1-6, the semiconductor structure of the present embodiment includes a substrate 110 and at least one memory cell 700 disposed on the substrate 110. Each memory cell 700 includes a plurality of active stripes 130, the plurality of active stripes 130 are arrayed over the substrate 110, each active stripe 130 extends along a first direction D1, any adjacent two active stripes 130 are separated by a first trench 140 (refer to fig. 42-45) on a plane parallel to the substrate 110, and any adjacent two active stripes 130 are separated by a second trench 150 (refer to fig. 42-45) on a plane perpendicular to the substrate 110.

Each memory cell 700 further includes at least one set of stacked capacitors 300, when the stacked capacitors 300 are provided in plurality, two adjacent sets of stacked capacitors 300 are spaced apart, each set of stacked capacitors 300 including a lower electrode 310, a dielectric layer 320 covering sidewalls of the lower electrode 310, and an upper electrode 330, wherein the lower electrode 310 includes a partial structure passing through each active stripe 130 of the stacked capacitors 300, and the upper electrode 330 covers the dielectric layer 320 and fills the first trench 140 and the second trench 150 between the lower electrodes 310 (refer to fig. 42-45).

The semiconductor structure of the embodiment breaks through the inherent single-layer framework of the current dynamic random access memory, and adds the stacked capacitor which is stacked in the vertical direction, so that the dynamic random access memory has a multi-layer stacked 3D framework, the storage density of the semiconductor structure is increased, and the stacked capacitor 300 has an increased stacking layer number, therefore, the semiconductor structure of the embodiment has an increased storage density, the problem that the storage density of the dynamic random access memory is difficult to increase continuously due to the size shrinkage is solved, and a new direction is provided for the development of the dynamic random access memory.

In some embodiments, as shown in fig. 1, the semiconductor structure includes a plurality of memory cells 700, and the plurality of memory cells 700 are circularly arranged on the substrate 110 along the first direction D1, that is, the plurality of memory cells 700 are repeatedly arranged on the substrate 110.

In some embodiments, as shown in fig. 1-6, the semiconductor structure further includes a support structure 200, the support structure 200 is disposed on the substrate 110, the support structure 200 is disposed between two adjacent memory cells 700, and the support structure 200 connects the two stacked capacitors 300 of the adjacent memory cells 700 to improve stability of the semiconductor structure and avoid toppling or collapsing of the semiconductor structure. Wherein the material of the support structure 200 comprises an insulating material.

In some embodiments, referring to fig. 36-41, as shown in fig. 1-6, the stacked capacitor 300 further includes a plurality of recesses 211, the plurality of recesses 211 being disposed at an end of the stacked capacitor 300 proximate to the support structure 200, each recess 211 being disposed between two adjacent active bars 130, each recess 211 being disposed toward the support structure 200.

As shown in fig. 1 to 4, referring to fig. 36 to 41, the support structure 200 further includes protrusions 220, the protrusions 220 are disposed on the side walls of the support structure 200, each protrusion 220 is disposed corresponding to a recess 211, and each protrusion 220 is embedded into the recess 211. The protruding portion 220 of the supporting structure 200 is embedded into the recessed portion 211 of the stacked capacitor 300, so that the contact area between the supporting structure 200 and the stacked capacitor 300 is increased, the effect of the supporting structure 200 supporting the semiconductor structure is improved, and the semiconductor structure can be effectively prevented from toppling or collapsing.

In some embodiments, as shown in fig. 1, each memory cell 700 further includes an array region 102, the array region 102 being disposed between two adjacent sets of stacked capacitors 300, the array region 102 being connected to the stacked capacitors 300 by a plurality of active stripes 130.

In some embodiments, as shown in fig. 1, each memory cell 700 includes two sets of stacked capacitors 300 in the first direction D1, and the two sets of stacked capacitors 300 are symmetrically disposed at two sides of the array region 102, further improving the integration of the memory cell 700.

In some embodiments, as shown in fig. 1-6, the array region 102 includes a plurality of word lines 400 and a plurality of bit lines 500. Each of the word lines 400 is vertically disposed on the substrate 110, any adjacent two of the word lines 400 are spaced apart on a plane parallel to the substrate 110, each of the word lines 400 intersects a portion of the active bars 130 of the plurality of active bars 130, and each of the word lines 400 covers a portion of sidewalls of the active bars 130. Each bit line 500 extends along a second direction D2, the second direction D2 is located parallel to a plane of the substrate 110, and the second direction D2 and the first direction D1 are perpendicular to each other, on a plane perpendicular to the substrate 110, any two adjacent bit lines 500 are spaced apart, each bit line 500 intersects a portion of the active bars 130 of the plurality of active bars 130, and each bit line 500 covers a portion of a sidewall of the active bar 130. The plurality of word lines 400 and the plurality of bit lines 500 are separated by isolation structures 600.

In an exemplary embodiment of the present disclosure, a method for fabricating a semiconductor structure is provided, as shown in fig. 7, fig. 7 is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure, and fig. 8 to 53 are schematic views of various stages of the method for fabricating a semiconductor structure, and the method for fabricating a semiconductor structure is described below with reference to fig. 8 to 53.

The semiconductor structure is not limited in this embodiment, and a Dynamic Random Access Memory (DRAM) will be described as an example of the semiconductor structure, but the embodiment is not limited thereto, and the semiconductor structure in this embodiment may be other structures.

As shown in fig. 7, a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure includes the following steps:

step S110: providing a first structure, wherein the first structure comprises a capacitor region, the first structure comprises a substrate and a plurality of active strips, the plurality of active strips are arranged above the substrate in an array mode, each active strip extends along a first direction, in the capacitor region, any two adjacent active strips are separated by a first groove on a plane parallel to the substrate, any two adjacent active strips are separated by a second groove on a plane perpendicular to the substrate, and the second groove is communicated with the first groove and exposes the side wall of the active strip located in the capacitor region.

As shown in fig. 42-45, first structure 100 may include one or more capacitive regions 1011, and in embodiments where first structure 100 includes a plurality of capacitive regions 1011, the plurality of capacitive regions 1011 are independently disposed in a first direction D1. The plurality of active stripes 130 are arranged in a plurality of rows along the second direction D2 on a plane parallel to the substrate 110, and the plurality of active stripes 130 are arranged in a plurality of columns on a plane perpendicular to the substrate 110, any two adjacent active stripes 130 are independently disposed, and the first trench 140 and the second trench 150 expose sidewalls of the active stripes 130 located in the capacitor region 1011.

In the present embodiment, as shown in fig. 42 to 45, the first structure 100 includes first regions 101 and array regions 102 alternately arranged along the first direction D1. The capacitor regions 1011 are located in the first regions 101, each first region 101 comprises two capacitor regions 1011 disposed independently, the first region 101 having a support structure 200 formed therein, the two capacitor regions 1011 of the first region 101 being separated by the support structure 200.

In practice, a first structure 100 is provided, comprising the steps of:

step S111: providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises active layers and sacrificial layers which are alternately stacked in sequence.

In this embodiment, as shown in fig. 8 and 9, the stacked structure 120 is formed on the substrate 110, and the following implementation may be adopted: the substrate 110 is used as a seed crystal, the substrate 110 is placed in a reaction chamber, a gas source for forming the sacrificial layer 121 and a gas source for forming the active layer 122 are alternately introduced into the reaction chamber, the sacrificial layer 121 and the active layer 122 are alternately epitaxially grown on the substrate 110 by adopting a chemical vapor deposition process (Chemical Vapor Deposition, CVD), and the sacrificial layer 121 and the active layer 122 together form a stacked structure 120. Wherein the sacrificial layer 121 and the active layer 122 of the stack structure 120 may be alternately stacked by 2 to 1024 or more layers, for example, 48, 64, 128, 256, 512, or the like layers may be alternately stacked. In this embodiment, the top layer of the stacked structure 120 is the sacrificial layer 121.

In other embodiments, the sacrificial layer 121 and the active layer 122 are sequentially deposited on the substrate 110 using any one of a chemical vapor deposition process, a physical vapor deposition process (Physical Vapor Deposition, PVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), or sputtering (sputtering).

In this embodiment, the substrate 110 may be a semiconductor substrate, which may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, or the like. The semiconductor substrate may be doped with ions, for example, the semiconductor substrate may be a P-type doped substrate or an N-type doped substrate.

The material of the sacrificial layer 121 may include germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

The material of the active layer 122 may include silicon, for example, may include one or more of monocrystalline silicon, polycrystalline silicon, or amorphous silicon, and the active layer 122 may be doped with N-type or P-type conductive dopant ions.

In this embodiment, the substrate 110 is a silicon crystal substrate, the material of the sacrificial layer 121 is silicon germanium, and the material of the active layer 122 is polysilicon.

In fig. 8, a line a-a extends through the first region 101 and the array region 102, a line b-b extends through the first region 101 and the array region 102, a line c-c is located in the capacitor region 1011, and a line d-d is located in the array region 102. It will be appreciated that references to a cross-sectional view along line a-a and a cross-sectional view along line b-b in this embodiment are not to a complete cross-sectional view of the semiconductor structure along line a-a or b-b, but rather to a partial cross-sectional view of the semiconductor structure along line a-a or a partial cross-sectional view of the semiconductor structure along line b-b.

Step S112: a plurality of first trenches are formed in the stacked structure, each first trench extends along a first direction, and in a direction perpendicular to the substrate, each first trench penetrates through the stacked structure, and the reserved active layer is divided into a plurality of active strips by the first trenches.

As shown in fig. 10 and 11, referring to fig. 8 and 9, a part of the sacrificial layer 121 and a part of the active layer 122 are sequentially etched and removed until a part of the top surface of the substrate 110 is exposed, and etching is stopped, thereby forming a plurality of first trenches 140 in the stacked structure 120. Each of the first trenches 140 extends in the first direction D1, and the remaining active layer 122 is divided into a plurality of active stripes 130 by the first trenches 140. The active stripes 130 and the first trenches 140 in the capacitive region 1011 are spaced apart on a plane parallel to the substrate 110, adjacent active stripes 130 being separated by the first trenches 140.

In this embodiment, as shown in fig. 10 and 11, in the first direction D1, the stacked structures 120 at two ends of the first trench 140 are not etched, and the stacked structures 120 at two ends of the first trench 140 are reserved as supporting frames of the semiconductor structure, so that the formed semiconductor structure is stable and has good stability.

Step S113: and forming a dielectric layer, wherein the dielectric layer at least fills the first groove positioned in the first area.

As shown in fig. 32-35, referring to fig. 10 and 11, the dielectric layer 123 fills the first trench 140 located in the first region 101, so that a subsequent step performs a processing process on the first region 101. The material of the dielectric layer 123 may include one of silicon nitride, silicon oxide, or silicon oxynitride.

Step S114: and forming a supporting structure in the first region, wherein the supporting structure extends along a second direction and penetrates through the first structure, the second direction is positioned on a plane parallel to the substrate, the second direction is perpendicular to the first direction, and the supporting structure divides the first region into two independently arranged capacitor regions.

In this embodiment, forming the support structure 200 in the first region 101 includes: as shown in fig. 36 to fig. 38, referring to fig. 32 to fig. 35, the first region 101 is etched, a portion of the dielectric layer 123, a portion of the sacrificial layer 121 and a portion of the active stripe 130 are removed, a trench 210 is formed in the first region 101, the trench 210 extends along the second direction D2 and penetrates the first structure 100, and the trench 210 exposes a portion of the substrate 110, and the trench 210 divides the first region 101 into two independently arranged capacitor regions 1011. Then, as shown in fig. 39-41, referring to fig. 36-38, an insulating material is deposited to fill the trench 210, forming a support structure 200. The support structure 200 is used for connecting two subsequently formed stacked capacitors 300 located in the same first region 101, and the support structure 200 provides good supporting force for the stacked capacitors 300, so that the stacked capacitors 300 are structurally stable, and the stacked capacitors 300 can have a higher stacking layer number.

In this embodiment, as shown in fig. 36 to 38, by controlling the etching ratio of the etching active bar 130 to the sacrificial layer 121 so that the etching speed of the etching sacrificial layer 121 is equal to the etching speed of the etching dielectric layer 123 when the first region 101 is etched, the etching speed of the etching sacrificial layer 121 is greater than the etching speed of the etching active bar 130, and a plurality of concave portions 211 are formed in the walls of the trench grooves 210, each concave portion 211 being recessed between two adjacent active bars 130 in the lateral direction. As shown in fig. 39-41, during the process of depositing the insulating material, a portion of the insulating material fills the recess 211, and a plurality of protrusions 220 are formed on the sidewall of the support structure 200, so that the support structure 200 can provide better support for the subsequently formed stacked capacitor 300, ensure the stability of the semiconductor structure, and avoid the risk of toppling or breaking of the semiconductor structure.

Step S115: and removing part of the sacrificial layer, forming a second groove in the capacitor region, wherein the first groove is communicated with the second groove, and exposing the side wall of the active strip positioned in the capacitor region.

In this embodiment, as shown in fig. 42-45, referring to fig. 39-41 and fig. 35, the capacitor region 1011 may be removed by dry etching or wet etching, and the conditions are controlled so that the etching process has a high etching selectivity to the material of the active stripe 130, all the sacrificial layer 121 and the dielectric layer 123 in the capacitor region 1011 are removed by etching, and the second trench 150 is formed in the capacitor region 1011 at the position where the sacrificial layer 121 is removed, and the second trench 150 is in communication with the first trench 140. The active stripes 130 and the second trenches 150 in the capacitive region 1011 alternate in a plane perpendicular to the substrate 110, adjacent active stripes 130 being separated by the second trenches 150.

Step S120: a dielectric layer is formed in the capacitor region, and covers the exposed side walls of the active strips.

In this embodiment, as shown in fig. 46-49, referring to fig. 42-45, a dielectric material may be deposited by an atomic layer deposition process (Atomic Layer Deposition, ALD), the dielectric material covering the sidewalls of the active stripes 130 located in the capacitor region 1011, forming a dielectric layer 320. The material of the dielectric layer 320 may include strontium titanate (SrTiO) ₃ ) Alumina (Al) ₂ O ₃ ) Zirconium oxide (ZrO) or hafnium oxide (HfO) ₂ ) At least one of them.

Step S130: an upper electrode is formed in the capacitor region, the upper electrode covers the dielectric layer and fills the first trench and the second trench in the capacitor region.

As shown in fig. 50 to 53, referring to fig. 46 to 49, an upper electrode material is deposited by any one of a chemical vapor deposition process, a physical vapor deposition process (Physical Vapor Deposition, PVD), an atomic layer deposition process, or a sputtering (sputtering) process, covers the dielectric layer 320 and fills the first trench 140 and the second trench 150 in the capacitor region 1011 to form an upper electrode 330, and the upper electrode 330, the dielectric layer 320, and the lower electrode 310 together form a stacked capacitor 300 vertically stacked on the substrate 110 with a portion of each active stripe 130 located in the capacitor region 1011 as a lower electrode 310.

As shown in fig. 50-53, the stacked capacitor formed by the method of the present embodiment has the upper electrode filled up the first trench and the second trench in the capacitor region, which increases the duty ratio of the upper electrode in the stacked capacitor, increases the storage space of the stacked capacitor, and reduces the process challenges and yield problems of the semiconductor structure with a reduced size.

This example is a further illustration of one possible implementation of the above examples. Compared with the above embodiment, the present embodiment adds the following steps: doping ions are implanted into the active stripes located in the capacitive areas by ion implantation. The step is performed after the first structure is provided in step S110, and the step is performed before the dielectric layer is formed in the capacitor region in step S120.

In this embodiment, the doping ions are implanted into the active strip 130 located in the capacitor region 1011, so as to increase the concentration of the doping ions in the material of the active strip 130 located in the capacitor region 1011, and adjust the resistance of the active strip 130 located in the capacitor region 1011, so that the stacked capacitor 300 has better electrical performance.

According to an exemplary embodiment, this embodiment is a further illustration of one possible implementation of step S110 of the above-described embodiment.

In an implementation process, the first structure is provided, and the manufacturing process further includes a manufacturing process of the array region 102, wherein the manufacturing process of the array region 102 is performed after the step S112 of forming the plurality of first trenches in the stacked structure, and the manufacturing process of the array region is performed before the step S114 of forming the support structure in the first region, and the manufacturing process of the array region includes the following steps:

step S101: and forming a plurality of word lines in the array region, wherein each word line is vertically arranged on the substrate, any two adjacent word lines are arranged at intervals on a plane parallel to the substrate, each word line is intersected with part of the active strips in the plurality of active strips, and each word line covers part of the side walls of the active strips.

In this embodiment, the plurality of word lines 400 are formed in the array region 102, which may be as follows:

first, as shown in fig. 12 and 13, referring to fig. 9 and 10, the sacrificial layer 121 located in the array region 102 is removed, and a third trench 160 is formed in the array region 102 at a position where the sacrificial layer 121 is removed, and the third trench 160 and the first trench 140 communicate with each other to expose a sidewall of the active stripe 130 located in the array region 102.

Then, as shown in fig. 14 and 15, referring to fig. 12 and 13, an initial gate oxide layer 401 is deposited and formed by any one of an atomic layer deposition process, a chemical vapor deposition process, and a physical vapor deposition process, the initial gate oxide layer 401 covering sidewalls of the active stripes 130 located in the array region 102. The material of the initial gate oxide layer 401 may include at least one of silicon oxide or silicon oxynitride.

As shown in fig. 16 and 17, referring to fig. 14 and 15, an initial high-K dielectric layer 402 is formed by deposition through any of the above deposition processes, and the initial high-K dielectric layer 402 covers the initial gate oxide layer 401. The material of the initial high-K dielectric layer 402 may include a metal silicate or a metal silicon oxide. Illustratively, the material of the initial high-K dielectric layer 402 may include tantalum oxide (Ta ₂ O ₅ ) Titanium oxide (TiO) ₂ ) Zirconium oxide (ZrO) ₂ ) Alumina (Al) ₂ O ₃ ) Hafnium silicon oxide (HfSiO) ₂ ) Or hafnium oxide (HfO) ₂ ) At least one of them.

An initial wordline layer (not shown) is then deposited by any of the deposition processes described above, the initial wordline layer overlying the initial high-K dielectric layer 402 and filling the first trench 140 and the third trench 160. The material of the initial word line layer may include a conductive metal, a doped semiconductor material, or a metal-semiconductor compound material. Illustratively, the material of the initial word line layer may include one of metallic Titanium (Titanium), metallic Tantalum (Tantalum), metallic Tungsten (tunesten), or an alloy thereof, or the material of the initial word line layer may include one of doped monocrystalline silicon or polycrystalline silicon.

Then, as shown in fig. 18 and 19, referring to fig. 16 and 17, portions of the initial word line layer, the initial high-K dielectric layer 402, and the initial gate oxide layer 401 are etched away to form a plurality of independently disposed word lines 400, each word line 400 being vertically disposed on the substrate 110, any adjacent two word lines 400 being spaced apart on a plane parallel to the substrate 110, each word line 400 intersecting a portion of the active bars 130 of the plurality of active bars 130, and each word line 400 covering a portion of the sidewalls of the active bars 130. Each word line 400 includes a gate oxide layer 410, a high K dielectric layer 420, and a word line layer 430 that in turn cover the active stripes.

In this embodiment, the plurality of word lines 400 are arranged in two rows along the second direction D2, and each active bar 130 intersects with two word lines 400.

Step S102: a source layer and a drain layer are formed.

In this embodiment, the source layer 440 and the drain layer 450 are formed in the following manner:

as shown in fig. 20 and 21, referring to fig. 18 and 19, the active stripes 130 in the array region 102 may be etched based on the first trenches 140 and the third trenches 160, and after the etching process, the thickness of the active stripes 130 exposed by the first trenches 140 and the third trenches 160 in the array region 102 is thinner than the thickness of the active stripes 130 covered by the word lines 400.

Then, as shown in fig. 22 and 23, referring to fig. 20 and 21, the exposed active stripes 130 in the array region 102 are used as a seed crystal, and a source layer 440 and a drain layer 450 are formed on the active stripes 130 on both sides of the word line 400 by epitaxial growth. The source layer 440 and the drain layer 450 may cover a portion of the sidewall of the gate oxide layer 410, but the source layer 440, the drain layer 450, the high K dielectric layer 420, and the word line layer 430 are not in contact, thereby preventing the adjacent word lines 400 from being shorted.

As shown in fig. 22 and 23, in this example, the source layer 440 is shared by two word lines 400 connected to the same active stripe 130. In other examples, two word lines 400 connected to the same active strip 130 may share a drain layer 450.

In other embodiments, source and drain regions may be formed in the active bars 130 on both sides of each word line 400, respectively, through an ion implantation process.

Step S103: a first isolation layer is formed.

As shown in fig. 24 and 25, referring to fig. 22 and 23, a low-K dielectric material may be deposited by a chemical vapor deposition process or a physical vapor deposition process, and the low-K dielectric material fills at least the areas not filled in the first trench 140 and the third trench 160 of the array region 102, thereby forming a first isolation layer 610. The material of the first isolation layer 610 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the low-K dielectric material may also fill the first trench 140 located in the first region 101, forming the dielectric layer 123 in the first region 101.

Step S104: and forming a plurality of bit lines in the array region, wherein each bit line extends along a second direction, the second direction is positioned in a plane parallel to the substrate, the second direction is perpendicular to the first direction, any two adjacent bit lines are arranged between the lines on the plane perpendicular to the substrate, each bit line intersects with part of the active strips in the plurality of active strips, and each bit line covers part of the side walls of the active strips.

In this embodiment, the plurality of bit lines 500 are formed in the array region 102, which may be as follows:

first, as shown in fig. 26 and 27, referring to fig. 24 and 25, the array region 102 is etched to remove a portion of the first isolation layer 610, a portion of the source layer 440 and a portion of the active stripe 130, forming a bit line trench 510, wherein the bit line trench 510 extends along the second direction D2, and a portion of the top surface of the substrate 110 is exposed by the bit line trench 510.

Then, as shown in fig. 28 to 30, referring to fig. 26 and 27, the second isolation layers 620 and the bit lines 500 are alternately formed in the bit line trenches 510, and the second isolation layers 620 and the bit lines 500 are alternately arranged on a plane perpendicular to the top surface of the substrate 110. Wherein each bit line 500 extends along the second direction D2 and covers sidewalls of the active bars 130 located at both sides thereof.

As shown in fig. 28 to 30, the first isolation layer 610 and the second isolation layer 620 in the array region 102 together form an isolation structure 600, and the isolation structure 600 fills the gaps between the word lines 400 and 400, between the bit lines 500 and 500, and between the word lines 400 and 500, so as to prevent the devices in the array region 102 from being shorted to cause leakage of the semiconductor structure, and ensure good electrical performance of the semiconductor structure.

The semiconductor structure formed in this embodiment forms a word line vertically disposed on the substrate, and a GAA (Gate All Around) structure is formed Around a portion of the sidewall of the active strip, so as to reduce the process challenges and yield caused by the size reduction.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.

In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure comprising a substrate and at least one memory cell disposed on the substrate, each memory cell comprising:

2. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a plurality of memory cells, the plurality of memory cells being arranged in a cycle on the substrate along the first direction.

3. The semiconductor structure of claim 2, wherein the semiconductor structure further comprises:

4. The semiconductor structure of claim 3, wherein the material of the support structure comprises an insulating material.

5. The semiconductor structure of claim 3, wherein the stacked capacitor further comprises:

6. The semiconductor structure of claim 5, wherein the support structure further comprises:

7. The semiconductor structure of claim 1, wherein each of the memory cells further comprises:

8. The semiconductor structure of claim 7, wherein the array region comprises:

9. The semiconductor structure of claim 7, wherein in the first direction, each of the memory cells comprises two sets of the stacked capacitors symmetrically disposed on both sides of the array region.

10. The manufacturing method of the semiconductor structure is characterized by comprising the following steps of:

11. The method of fabricating a semiconductor structure of claim 10, wherein providing a first structure comprises:

12. The method of claim 11, wherein the first structure further comprises a first region, the capacitor region being located in the first region, the method further comprising:

13. The method of fabricating a semiconductor structure of claim 12, wherein forming a support structure comprises:

14. The method of claim 13, wherein when etching the first region, an etching rate of etching the sacrificial layer is greater than an etching rate of etching the active bars, forming a plurality of recesses in a wall of the trench, each recess being recessed between two adjacent active bars in a lateral direction;

15. The method of claim 11, wherein the first structure further comprises an array region, and wherein the providing the first structure further comprises:

removing the sacrificial layer in the array region;

16. The method of fabricating a semiconductor structure of claim 15, wherein said providing a first structure further comprises: