CN116978297A

CN116978297A - Detection circuit and electronic equipment

Info

Publication number: CN116978297A
Application number: CN202210434247.9A
Authority: CN
Inventors: 李星; 刘建锋; 王旭; 杜伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-04-24
Filing date: 2022-04-24
Publication date: 2023-10-31

Abstract

The embodiment of the application provides a detection circuit and electronic equipment, wherein the detection circuit comprises: the system comprises a first system-on-chip (SOC), a time sequence controller and a first power module; the first SOC is connected with the time schedule controller and is used for responding to a test instruction and sending a first test signal to the time schedule controller; the first power supply module is connected with the time sequence controller; the time sequence controller is used for externally connecting a display module, controlling the first power module to provide an electric signal for the display module according to the first test signal, generating a test display signal according to the first test signal, and sending the test display signal to the display module. For reducing the test cost.

Description

Detection circuit and electronic equipment

Technical Field

The application relates to the technical field of display, in particular to a detection circuit and electronic equipment.

Background

At present, with the development of technology, consumer electronic products have come into the life of people, and the reliability of consumer electronic products is relatively weak in device tolerance specification and service life compared with vehicle-mounted devices, aviation devices and the like. In order to reduce the cost, links such as production, inspection, test and the like are continuously simplified, and impact is generated on the service life of the whole machine consisting of a plurality of module devices.

Based on this, in consumer electronics, especially electronics with a lifetime of more than 1 year, such as televisions, cell phones, refrigerators, air conditioners, etc., there is a need for an efficient potential failure excitation and remote maintenance scheme to reduce maintenance costs and avoid batch recall events due to accidental risks.

In some techniques, potential failures of electronic products are stimulated by burn-in testing. For example, different time sequence controllers for aging test are arranged for different modules of the electronic product, HVS (High voltage stress, high voltage excitation) data and driving current/voltage are sent to the module to be tested through controlling the time sequence controllers, the occurrence of potential faults of the module to be tested is accelerated and excited, invalid devices are screened out, and the reliability of the product is improved. For example, as shown in fig. 1a, when performing burn-in test on a display panel in an electronic product, a timing controller for performing the burn-in test on different modules in the display panel needs to be preset. When each module is subjected to the aging test, a voltage is provided for the time schedule controller through a 12V (volt) power supply, and an HVS image signal and a driving current/voltage are sent to the time schedule controller corresponding to each module through a PG (Pattern Generator, image generator) so as to quickly excite potential faults possibly existing in each module, for example, when the display screen module is subjected to the aging test, faults caused by foreign matters of a display screen (Open-Cell, OC) are excited, or when the COF (Chip on film) module is subjected to the aging test, primary defects of the COF module are excited. Through the aging test, failure devices can be screened out from each module of the display panel, and the reliability and the yield of the display panel are improved.

However, the existing burn-in method needs to set different timing controllers for different modules, and the timing controllers are only used for burn-in test, so that the cost of the burn-in test is high.

Disclosure of Invention

In view of the above, the present application provides a detection circuit and an electronic device, so as to solve the problem of high testing cost in the prior art.

In a first aspect, an embodiment of the present application provides a detection circuit, applied to an electronic device, including: the system comprises a first system-on-chip (SOC), a time sequence controller and a first power module;

the first SOC is connected with the time schedule controller and is used for responding to a test instruction and sending a first test signal to the time schedule controller;

the first power supply module is connected with the time sequence controller; the time sequence controller is used for externally connecting a display module, controlling the first power module to provide an electric signal for the display module according to the first test signal, generating a test display signal according to the first test signal, and sending the test display signal to the display module.

In a possible implementation manner of the first aspect, the first test signal includes at least one of a first test control signal, a first test image signal, and a first detection characterization signal;

When the first test signal includes a first test control signal, the first SOC is configured to transmit the first test control signal with the timing controller through a first channel; or,

when the first test signal includes a first test image signal, the first SOC is configured to transmit the first test image signal to the timing controller through a second channel; or,

when the first test signal includes a first detection characterization signal, the first SOC is configured to transmit the first detection characterization signal through a third channel with the timing controller.

In a possible implementation manner of the first aspect, the first SOC is further configured to receive, through the first channel, a control response signal sent by the timing controller.

In a possible implementation manner of the first aspect, the method further includes: the second power module and the first voltage conversion module;

the second power supply module is connected with the input end of the first voltage conversion module; the output end of the first voltage conversion module is connected with the first power supply module;

the first voltage conversion module is used for converting a first voltage signal provided by the first power supply module into a working voltage signal of the second power supply module.

In a possible implementation manner of the first aspect, the method further includes: a first memory module connected to the first SOC;

the first SOC is used for acquiring test information and storing the test information into the first storage module; and responding to the test instruction, acquiring test information corresponding to the test instruction from the first storage module, generating a first test signal according to the test information corresponding to the test instruction, and sending the first test signal to the time sequence controller.

In a possible implementation manner of the first aspect, the method further includes: a second memory module connected to the first SOC; the second storage module is used for storing the first test signal;

the first SOC is used for responding to a test instruction, acquiring a first test signal corresponding to the test instruction from the second storage module, and sending the first test signal to the time sequence controller.

In a possible implementation manner of the first aspect, the method further includes: a counter;

the first SOC is further used for switching a state signal of the time sequence controller from a first value to a second value in a preset time period when abnormal information is detected, and sending a target signal corresponding to the abnormal information to the time sequence controller again; the target signal is any one of signals sent to the time sequence controller by the first SOC;

The counter is connected with the first SOC and is used for updating the recorded occurrence times of error signals when detecting that the state signal of the time sequence controller is switched from a first value to a second value.

In a possible implementation manner of the first aspect, the counter is further configured to clear the recorded number of occurrences of the error signal when the shutdown signal is received.

In a possible implementation manner of the first aspect, the timing controller is further configured to return the anomaly information to the first SOC when the anomaly information is detected.

In a possible implementation manner of the first aspect, the first SOC is further configured to send an operation state acquisition signal to the timing controller;

the time sequence controller is further used for responding to an operation state acquisition signal, acquiring operation state information and returning the operation state information to the first SOC;

the first SOC is further used for detecting whether abnormal information exists according to the running state information.

In a possible implementation manner of the first aspect, the method further includes:

the first SOC is also used for acquiring update indication information triggered by a user and updating target data indicated by the update indication information according to the update indication information.

In a second aspect, an embodiment of the present application provides a detection circuit, applied to an electronic device, including: the second system-on-a-chip SOC and the third power module; wherein the second SOC is connected with the third power module;

the second SOC is used for being externally connected with the display module, responding to the test instruction, determining a test signal, controlling the third power module to provide an electric signal for the display module according to the test signal, generating a test display signal according to the test signal, and sending the test display signal to the display module.

In a possible implementation manner of the second aspect, the second test signal includes at least one of a second test image signal and a second detection characterization signal;

when the second test signal includes a second test image signal, the second SOC is configured to generate a test display image signal according to the second test image signal, and send the test display image signal to the display module through a fourth channel; or,

when the second test signal includes a second detection characterization signal, the second SOC is configured to generate a test detection characterization signal according to the second detection characterization signal, and transmit the test detection characterization signal with the display module through a fifth channel.

In a possible implementation manner of the second aspect, the method further includes: a fourth power module and a second voltage conversion module; the input end of the second voltage conversion module is connected with the fourth power supply module, and the output end of the second voltage conversion module is connected with the third power supply module;

the second voltage conversion module is used for converting the second voltage signal provided by the fourth power supply module into the working voltage of the third power supply module.

In a possible implementation manner of the second aspect, the method further includes: a third memory module connected to the second SOC;

the second SOC is used for acquiring test information and storing the test information into the third storage module; and responding to the test instruction, acquiring the test information corresponding to the test instruction from the third storage module and generating a second test signal according to the test information corresponding to the test instruction.

In a possible implementation manner of the second aspect, the method further includes: a fourth memory module connected to the second SOC; the fourth storage module is used for storing the second test signal;

the second SOC is configured to respond to a test instruction, and obtain a second test signal corresponding to the test instruction in the fourth storage module.

In a possible implementation manner of the second aspect, the second test signal further includes: a second test control signal;

when the second test signal includes a second test control signal, the second SOC is configured to send the second test control signal to the fourth power module through a sixth channel; the fourth power module is used for providing an electric signal to the display module according to the second test control signal.

In a possible implementation manner of the second aspect, the second test signal further includes: a second test control signal; the third power module is connected with the fourth storage module;

and when the second test signal comprises a second test control signal, the third power supply module is used for acquiring the second test control signal from the fourth storage module and providing an electric signal for the display module according to the second test control signal.

In a possible implementation manner of the second aspect, the second SOC is further configured to obtain update indication information triggered by a user, and update target data indicated by the update indication information according to the update indication information.

In a third aspect, an embodiment of the present application provides an electronic device, including the detection circuit and the display module of any one of the first aspect or any one of the second aspect.

The scheme provided by the embodiment of the application comprises a first SOC and a time sequence controller, wherein the first SOC is connected with the time sequence controller and is used for responding to a test instruction and sending a first test signal to the time sequence controller; the time sequence controller is used for externally connecting the display module, generating a test display signal according to the first test signal, and sending the test display signal to the display module. In this way, in the embodiment of the present application, the first SOC control timing controller sends the test display signal to the display module, so as to perform a corresponding test on the display module. In the application, the display module can be tested by using the first SOC and the timing controller in the electronic equipment, and different testing devices are not required to be arranged for different modules, so that the testing cost is greatly reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1a is a schematic view of a scenario of an aging test according to an embodiment of the present application;

FIG. 1b is a schematic view of another scenario of burn-in testing according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a detection circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another detection circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another detection circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another detection circuit according to an embodiment of the present application;

FIG. 6a is a schematic diagram of another detecting circuit according to an embodiment of the present application;

fig. 6b is a schematic diagram of a signal output scenario of a detection circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of another detection circuit according to an embodiment of the present application;

FIG. 8 is a schematic diagram of another detection circuit according to an embodiment of the present application;

FIG. 9 is a schematic diagram of another detection circuit according to an embodiment of the present application;

FIG. 10 is a schematic diagram of another detection circuit according to an embodiment of the present application;

FIG. 11 is a schematic diagram of another detection circuit according to an embodiment of the present application;

FIG. 12 is a schematic diagram of another detecting circuit according to an embodiment of the present application;

FIG. 13 is a schematic diagram of another detection circuit according to an embodiment of the present application;

fig. 14a is a schematic diagram of another detection circuit according to an embodiment of the present application;

fig. 14b is a schematic structural diagram of another detection circuit according to an embodiment of the present application;

FIG. 15 is a schematic diagram of another detecting circuit according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of another detection circuit according to an embodiment of the present application.

Detailed Description

For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one way of describing an association of associated objects, meaning that there may be three relationships, e.g., a and/or b, which may represent: the first and second cases exist separately, and the first and second cases exist separately. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Before describing embodiments of the present application in detail, terms applied or likely to be applied to the embodiments of the present application will be explained first.

V-By-One, VBO for short, is a digital interface standard technology facing image information transmission. The technology can support 4.0Gbps high-speed signal transmission at maximum, and the special coding mode avoids the time lag problem between the data of the receiving end and the clock, so the VBO technology is widely applied to the field of ultra-high definition liquid crystal televisions, and the ultra-thin ultra-narrow television is possible.

In some techniques, to reduce maintenance costs and avoid batch recall events caused by accidental risk, potential failures of electronic products are often motivated by burn-in testing. For example, different time sequence controllers for aging test are arranged for different modules of the electronic product, HVS (High voltage stress, high voltage excitation) data and driving current/voltage are sent to the module to be tested through controlling the time sequence controllers, the occurrence of potential faults of the module to be tested is accelerated and excited, invalid devices are screened out, and the reliability of the product is improved. For example, as shown in fig. 1a and 1b, when burn-in testing a display panel in an electronic product, a timing controller for performing burn-in testing on different modules in the display panel needs to be preset. When each module is subjected to the aging test, a voltage is provided for the time schedule controller through a 12V (volt) power supply, and an HVS image signal and a driving current/voltage are sent to the time schedule controller corresponding to each module through a PG (Pattern Generator, image generator) so as to quickly excite potential faults possibly existing in each module, for example, when the display screen module is subjected to the aging test, faults caused by foreign matters of a display screen (Open-Cell, OC) are excited, or when the COF (Chip on film) module is subjected to the aging test, primary defects of the COF module are excited. Through the aging test, failure devices can be screened out from each module of the display panel, and the reliability and the yield of the display panel are improved.

Because the existing burn-in test method needs to set different time sequence controllers for different modules, and the time sequence controllers are only used for burn-in test, the cost of the burn-in test is high.

In view of the above problems, an embodiment of the present application provides a detection circuit, including a first SOC and a timing controller, where the first SOC is connected to the timing controller, and the first SOC is configured to send a first test signal to the timing controller in response to a test instruction; the time sequence controller is used for externally connecting the display module, generating a test display signal according to the first test signal, and sending the test display signal to the display module. In this way, in the embodiment of the present application, the first SOC control timing controller sends the test display signal to the display module, so as to test the display module. For example, when performing the burn-in test, only the first SOC control timing controller is required to send a corresponding burn-in test display signal to the display module to trigger a potential fault in the display module. In the application, the first SOC and the timing controller in the electronic equipment can be used for exciting the potential faults of the display module, and different timing controllers are not required to be arranged for different modules, so that the test cost is greatly reduced. The following is a detailed description.

Referring to fig. 2, a schematic structural diagram of a detection circuit according to an embodiment of the present application is provided. The detection circuit provided by the embodiment of the application is applied to electronic equipment. As shown in fig. 2, the detection circuit includes: a first SOC (system on chip) 21, a timing controller 22, and a first power module 23.

The first SOC21 is connected to the timing controller 22, and the first SOC21 is configured to send a first test signal to the timing controller 22 in response to a test instruction.

The first power supply module 23 is connected with the timing controller 22; the time sequence controller 22 is used for externally connecting the display module, controlling the first power module 23 to provide an electric signal for the display module according to the first test signal, generating a test display signal according to the first test signal, and sending the test display signal to the display module.

It should be noted that, in the embodiment of the present application, the detection circuit is used to perform a corresponding test on the display module. The test can be an aging test, a life test, a temperature and humidity working driving test or other related tests, and the like, and the application is not limited to the aging test. In the following embodiments of the present application, a display module is described as an example of performing an aging test. Of course, other tests are also possible, and reference may be made to burn-in tests, which are not described in detail herein.

In the embodiment of the application, the detection circuit includes a first SOC21, a timing controller 22 and a first power module 23. The timing controller 22 is used for connecting with the display module. That is, since the timing controller 22 is externally connected to the display module and can transmit the control signal and the image signal to be displayed to the display module, when the burn-in test is required for the display module, the signal related to the burn-in test can be transmitted to the display module through the timing controller 22. The first power module 23 is used for externally connecting with a display module, and provides an electric signal for the display module under the control of the timing controller 22. That is, when the display module is started, the first power module 23 is required to provide various electrical signals to the display module, and the first power module 23 provides various electrical signals to the display module according to the control command of the timing controller 22. Based on this, after the user triggers the test instruction, the first SOC21 acquires the test instruction, and in response to the test instruction, the first SOC21 determines a first test signal corresponding to the test instruction and sends the first test signal to the timing controller 22. The timing controller 22 generates a test display signal according to the first test signal, and sends the test display signal to the display module so that the display module displays an image according to the test display signal. And, the timing controller 22 determines the electrical signal to be output by the first power module 23 according to the first test signal, so as to control the first power module 23 to output the electrical signal provided for the display module.

It should be noted that, the first test signals are different, and the corresponding electrical signals of the display modules are different, so the timing controller 22 may determine the electrical signal to be output by the first power module 23 according to the obtained first test signal.

For example, the user triggers a burn-in command, the first SOC21 acquires the burn-in command, and in response to the burn-in command, the first SOC21 acquires a corresponding burn-in signal and sends the burn-in signal to the timing controller 22. The aging test signal sent by the first SOC21 may be a control signal for outputting an HVS (High voltage stress, high voltage excitation) image display signal, or may be an HVS image display signal or an electrical signal required by a display module. After receiving the aging test signal, the timing controller 22 may generate an HVS image display signal according to the control signal if the aging test signal is a control signal for outputting the HVS image display signal, determine an electrical signal required by the display module, send the HVS image display signal as the test display signal to the display module, and transmit the electrical signal required by the display module to the first power module 23, where the first power module 23 provides the electrical signal for the display module according to the electrical signal required by the display module, so as to quickly excite a potential failure or defect in the display module. Or, after the timing controller 22 receives the aging test signal, if the aging test signal is an HVS image display signal and an electrical signal required by the display module, the timing controller 22 may convert the HVS image display signal into a display signal corresponding to the display module, and send the display signal converted by the HVS image display signal to the display module as a test display signal. And transmits the electric signal required by the display module to the first power module 23, and the first power module 23 provides the electric signal for the display module according to the electric signal required by the display module.

It should be noted that, in the embodiment of the present application, the communication between the first SOC21 and the timing controller 22 may use VBO (V-by-One) signal transmission protocol, and the communication between the timing controller 22 and the display module uses LVDS (Low-Voltage Differential Signaling, low voltage differential signaling) transmission protocol. Therefore, when receiving the first test signal transmitted by the first SOC21, the timing controller 22 needs to perform a corresponding protocol format conversion on the first test signal when the first test signal is a test image signal, and cannot directly forward the first test signal.

As one possible implementation manner, the first test signal includes at least one of a first test control signal, a first test image signal and a first detection characterization signal; when the first test signal includes a first test control signal, the first SOC21 is configured to transmit the first test control signal through the first channel and the timing controller 22; alternatively, when the first test signal includes the first test image signal, the first SOC21 is configured to transmit the first test image signal to the timing controller 22 through the second channel; alternatively, when the test signal includes a detection characterization signal, the first SOC21 is configured to transmit the first detection characterization signal through the third channel and the timing controller 22, as shown in fig. 3.

In the embodiment of the present application, in order to facilitate the transmission of different types of test signals, the first SOC21 and the timing controller 22 are connected through different channels to transmit different types of test signals. The first test signal includes at least one of a first test control signal, a first test image signal and a first detection characterization signal, so that the first SOC21 and the timing controller 22 are connected through a first channel, a second channel and a third channel to respectively transmit the first test control signal, the first test image signal and the first detection characterization signal. That is, when the first test signal includes the first test control signal, the first SOC21 transmits the first test control signal to the timing controller 22 through the first channel. When the first test signal includes the first test image signal, the first SOC21 transmits the first test image signal to the timing controller 22 through the second channel. When the first test signal includes a first detection characterization signal, the first SOC21 is configured to transmit the first detection characterization signal through the third channel and the timing controller 22.

The first detection characterization signal is used for characterizing whether an abnormality exists in signal transmission between the first SOC21 and the timing controller 22. When the first detection characterization signal is a third value, it is characterized that the signal transmission between the first SOC21 and the timing controller 22 is not abnormal, and when the detection characterization signal is a fourth value, it is characterized that the signal transmission between the first SOC21 and the timing controller 22 is abnormal.

The third value and the fourth value are preset, for example, the third value is 0, the fourth value is 1, and of course, other values can be also used, which is not limited by the present application.

That is, when it is necessary to realize the control of the timing controller 22 by the first SOC21, a first channel may be established between the first SOC21 and the timing controller 22 to transmit a related control signal through the first channel, by which the control of the timing controller 22 by the first SOC21 is realized. For example, when performing the burn-in test, it is necessary to adjust the timing signal of the timing controller 22, at this time, the first SOC21 acquires the timing adjustment control signal and transmits the timing adjustment control signal as the first test control signal to the timing controller 22 through the first channel. The timing controller 22 adjusts the timing signal accordingly according to the received timing adjustment control signal, and may return the adjusted response signal to the first SOC21 through the first channel.

Alternatively, when the timing controller 22 is implemented to control the display module to display the image signal, and the first SOC21 is required to transmit the image signal to be displayed to the timing controller 22, a second channel may be established between the first SOC21 and the timing controller 22, so that the first SOC21 transmits the first test image signal to the timing controller 22 through the second channel. For example, when performing the burn-in test, the first SOC21 determines, in response to the burn-in test, an HVS image signal to be displayed by the display module corresponding to the burn-in test, and the first SOC21 may send the HVS image signal to the timing controller 22 through the second channel. After receiving the HVS image signals, the timing controller 22 may convert the HVS image signals into a protocol format corresponding to a data transmission channel between the display modules, and send the HVS image signals with the protocol format converted through the data transmission channel between the display modules, so that the display modules perform corresponding image display.

Or, when the first SOC21 needs to detect the operation state of the timing controller 22 or the display module, a third channel may be established between the first SOC21 and the timing controller 22, so as to send a detection characterization signal through the third channel, where the detection characterization signal is used to characterize whether the signal transmitted between the first SOC21 and the timing controller 22 is abnormal. The first SOC21 may send an acquiring signal of the operation state to the timing controller 22 through the first channel to acquire the operation state information of the timing controller 22 or the display module, so as to monitor whether the timing controller 22 or the display module is abnormal. For example, when performing the burn-in test, the first SOC21 may send an acquisition signal of an operation state to the timing controller 22 through the first channel, the timing controller 22 may acquire operation state information of itself or a display module according to the acquisition signal of the operation state, and return the operation state information of the timing controller 22 itself or the operation state information of the display module to the first SOC21 through the first channel as a response signal, so that the first SOC21 detects whether the timing controller 22 or the display module is abnormal according to the acquired operation state information, and if there is an abnormality, may send a detection characterization signal of a fourth value to the timing controller 22 through the third channel. If no abnormality exists, a third value of the detection characterization signal is sent to the timing controller 22 through a third channel. For example, the first SOC21 may compare the acquired operation state of the display module with a preset corresponding threshold value, so as to determine whether the display module is abnormal.

It should be noted that the first channel, the second channel and the third channel are different channels.

As one possible implementation, the first channel includes an I2C (Inter-Integrated Circuit, two-wire serial bus) channel. The second channel includes a data channel. The third channel includes an HTPDN (Hot Plug Detect Signal) channel or a locksignal (locksignal) channel, which is the detection characterization Signal, i.e., an HTPDN Signal or a locksignal.

The first test control signal generally includes a clock signal and a control data signal, and the first channel includes a first sub-channel and a second sub-channel. The first SOC21 transmits a clock signal to the timing controller 22 through a first sub-channel and a control data signal through a second sub-channel. For example, when performing the burn-in test, the timing signal of the timing controller 22 needs to be adjusted if necessary. At this time, the first SOC21 may transmit a clock signal for adjusting the timing signal through the first sub-channel and transmit an adjustment value of the timing signal through the second sub-channel.

The timing controller 22 generates a test display signal according to the first test signal after receiving the different types of test signals, where the generated test display signal includes at least one of a display control signal, a display image signal, and a display detection characterization signal. The driving electric signal of the display module comprises at least one of a display synchronous signal, a display clock signal, a gray scale voltage signal and a common voltage signal. Of course, the test display signal may also include other signals sent to the display module, which the present application is not limited to.

It should be noted that the first test signal may include an electrical signal required by the display module, or may be preset according to different first test signals to correspond to the display module required by different first test signals. In this way, the timing controller 22 can determine, according to the first test signal, an electrical signal that needs to be provided by the first power module 23 to the display module.

Different channels are provided between the timing controller 22 and the display module for transmitting different types of test display signals. For example, the timing controller 22 and the display module transmit display image signals through a data channel, transmit display control signals through an SPI (Serial Peripheral Interface ) channel, and transmit detection characterization signals through a LOCKN channel, although other channels may be provided between the timing controller 22 and the display module to transmit test display signals, which is not limited in this application.

As a possible implementation, the first SOC21 is further configured to receive the control response signal sent by the timing controller 22 through the first channel.

As a possible implementation, the timing controller 22 may transmit the detection characterization signal to the first SOC21 through the third channel.

That is, the first channel and the third channel are both bidirectional transmission channels. When the timing controller 22 returns a control response signal to the first SOC21, it transmits the control response signal to the first SOC21 through the first channel. The timing controller 22 may also send the detection characterization signal to the first SOC21, and may send the detection characterization signal to the first SOC21 through the third channel.

It should be noted that, in the embodiment of the present application, whether the signal transmission between the first SOC21 and the timing controller 22 is abnormal is detected by the characterization signal. When the first SOC21 detects that there is an abnormality, the detection characterization signal may be switched from the third value to the fourth value, and transmitted to the timing controller 22 through the third channel. When the timing controller 22 detects an abnormality, the detection characterization signal may be switched from the third value to the fourth value and transmitted to the first SOC21 through the third channel. After the anomaly is eliminated, the detection characterization signal may be switched from the fourth value back to the third value.

When the detection circuit starts to operate, the first SOC21 sets the detection-characterization signal to a third value, and transmits the detection-characterization signal to the timing controller 22 through a third channel. In this way, the first SOC21 and the timing controller 22 can detect whether the abnormal information exists in real time, and when the abnormal information is detected, the detected characterization signal is switched from the third value to the fourth value and transmitted to the opposite terminal through the third channel, so as to inform the opposite terminal of the existence of the abnormal information. After the anomaly is eliminated, the detection characterization signal may be switched from the fourth value back to the third value.

As a possible implementation manner, as shown in fig. 4, the detection circuit further includes: a first memory module 24 connected to the first SOC21.

The first SOC21 is configured to acquire first test information and store the first test information in the first storage module 24; and responding to the test instruction, acquiring test information corresponding to the test instruction from the first storage module 24, generating a first test signal according to the test information corresponding to the test instruction, and sending the first test signal to the time schedule controller 22.

In the embodiment of the present application, the user may preset the test information according to the actual requirement, and transmit the test information to the first SOC21. After the first SOC21 receives the test information, the test information may be stored in the first storage module 24. When the user transmits the test information to the first SOC21, the test information may be preset in the external device, and the external device may be triggered to transmit the test information to the first SOC21. At this time, the external device may transmit the test information to the first SOC21 through an HDMI (High Definition Multimedia Interface, high-definition multimedia interface) interface or a network port or wireless communication or other means. The first SOC21, upon receiving the test information, may store the test information into the first memory module 24. The test information is related information of a preset test. When the first SOC21 receives the test instruction, it obtains the test instruction, determines the test information corresponding to the test instruction from the test information, and further generates a first test signal according to the test information corresponding to the test instruction. For example, the test information is recorded with information such as test parameters, target addresses, used channels, etc., and the test information corresponding to different test instructions may be different. After receiving the test instruction, the first SOC21 may find the test information corresponding to the test instruction, and then package the information such as the test parameter and the target address in the test information into the protocol format signal corresponding to the channel according to the protocol format required by the channel according to the test information corresponding to the test instruction, that is, the first test signal.

In the above manner, the test information stored in the first storage module 24 is not the encapsulated first test signal according to the protocol format requirement corresponding to the transmission channel. The first SOC21 needs to be self-packaged, increasing the workload of the first SOC 21. In order to reduce the processing load of the first SOC21, the protocol encapsulation of the test information corresponding to the different instructions may be completed in the external device, and the first test signals corresponding to the different test instructions may be generated, and only the test signals may be stored in the detection circuit. Based on this, the detection circuit further includes, as shown in fig. 5: and a second memory module 25 connected to the first SOC 21. The second memory module 25 stores therein first test signals corresponding to different test instructions. The first SOC21 is configured to obtain a first test signal corresponding to the test instruction from the second storage module 25 in response to the test instruction, and send the first test signal to the timing controller 22. In this way, after the first SOC21 receives the test instruction, the first test signal corresponding to the test instruction may be found out from the first test signals stored in the second storage module 25 according to the test instruction, and the first SOC21 may directly obtain the first test signal corresponding to the test instruction from the second storage module 25 and send the first test signal to the timing controller 22.

It should be noted that, when the second storage module 25 stores the first test signal, the first SOC21 may learn, by detecting the protocol format of the first test signal, which channel is used to transmit the first test signal, or may instruct the channel transmitting the first test signal in the test instruction when the first test signal is acquired and the first test signal is transmitted to the timing controller 21.

As one possible implementation, the first SOC21 is connected to the first memory module 24 or the second memory module 25 through an SPI channel.

As a possible implementation manner, as shown in fig. 6a, the detection circuit further includes: the second power module 26, the first power module 23 and the first voltage conversion module 27.

The second power module 26 is connected with the input end of the first voltage conversion module 27; the output end of the first voltage conversion module 27 is connected with the first power supply module 23; the timing controller 22 is connected to the first power supply module 23.

The first voltage conversion module 27 is configured to convert the first voltage signal provided by the second power module 26 into an operating voltage signal of the first power module 23.

The timing controller 22 is further configured to control the first power module 23 to provide an electrical signal to the display module.

In the embodiment of the present application, the first power module 23 is used to provide an electrical signal to the display module. When the first power module 23 can receive the external voltage and convert the external voltage into the display module to provide the electric signal, the first power module 23 is not required to be connected with other power supply modules. When the first power module 23 cannot be directly connected to the external power source, the power supply module is required to provide the working voltage for the first power module 23. At this time, the second power module 26 in the detection circuit supplies the first power module 23 with the operating voltage. Since the first voltage provided by the second power module 26 may be greater than or less than the voltage required by the first power module 23, the first voltage conversion module 27 is required to perform voltage conversion at this time. That is, the input end of the first voltage conversion module 27 is connected to the second power module 26, and the output end of the first voltage conversion module 27 is connected to the first power module 23, so as to convert the first voltage signal provided by the second power module 26 into the working voltage signal of the first power module 23, and provide the working voltage signal to the first power module 23. The timing controller 22 determines an electrical signal to be output by the first power module 23 according to the received first test signal, and further controls the first power module 23 to output the electrical signal provided for the display module.

As a possible implementation manner, since the display module at least needs a power voltage, a common voltage, a gray scale (Gamma) voltage and a common voltage when displaying an image. At this time, the first power module 23 needs to provide at least a power voltage, a common voltage, a gray scale voltage and a common voltage for the display module. Therefore, the first power module 23 includes a power voltage sub-module, a common voltage sub-module, a gray scale voltage sub-module and a common voltage sub-module. Since the required operating voltages are different for each sub-module, at this time, the first voltage conversion module 27 converts the first voltage signal output by the second power module 26 into the operating voltage signal of the first power module 23, and then converts the first voltage signal output by the second power module 26 into the operating voltages of the power voltage sub-modules, the common voltage sub-module, the gray scale voltage sub-module and the common voltage sub-module included in the first power module 23. After receiving the first test signal, the timing controller 22 can determine the power voltage sub-module, the common voltage sub-module, the gray-scale voltage sub-module and the electric signal to be output of the common voltage sub-module included in the first power module 23 according to the first test signal, and the timing controller 22 sends the determined power voltage sub-module, the common voltage sub-module, the gray-scale voltage sub-module and the electric signal to be output of the common voltage sub-module included in the first power module 23 to the first power module 23. The first power module 23 receives the power voltage sub-module, the common voltage sub-module, the gray-scale voltage sub-module and the electric signal to be output of the common voltage sub-module contained in the first power module 23 and sent by the time schedule controller 22, and then adjusts the power voltage sub-module, the common voltage sub-module, the electric signal to be output of the gray-scale voltage sub-module and the common voltage sub-module according to the power voltage sub-module, the electric signal to be output of the common voltage sub-module, the electric signal to be output of the gray-scale voltage sub-module and the common voltage sub-module, so as to transmit the electric signal to the display module to supply power to the display module.

As a possible implementation, the second power module 26 is integrated with the first SOC21 on a motherboard, so that the first power module 23 is powered by the motherboard without the need for an additional power supply. Thus, the motherboard where the first SOC21 is located may provide signals such as a power signal, a control signal, and a test image signal for the timing controller 22, as shown in fig. 6 b.

As a possible implementation, the timing controller 22 is integrated with the first power module 23 on one motherboard.

As a possible implementation manner, referring to fig. 6a, the detection circuit further includes: a fifth memory module 28. The fifth storage module 28 is connected to the timing controller 22, and is configured to store electrical signals output by the first power module 23 corresponding to preset different first test signals. Thus, after receiving the test signal, the timing controller 22 may determine, in the fifth storage module 28, the electrical signal output by the first power module 23 corresponding to the received first test signal according to the first test signal.

As a possible implementation manner, as shown in fig. 7, the detection circuit further includes: a counter 29.

The first SOC21 is further configured to switch the status signal of the timing controller 22 from the first value to the second value in a preset period of time when the abnormality information is detected, and resend the target signal corresponding to the abnormality information to the timing controller 22; the target signal is any one of signals transmitted from the first SOC21 to the timing controller 22.

The counter 29 is connected to the first SOC21, and is configured to update the number of occurrences of the error signal when detecting that the status signal of the timing controller 22 is switched from the first value to the second value.

The first value and the second value are preset values, for example, the first value is 0, the second value is 1, or the first value is 1, the second value is 0, but may be other values, which is not limited by the present application.

The detection circuit may also detect the operational status of the timing controller 22 and/or the display module in embodiments of the present application. When detecting that there is an abnormality in the operation state of the timing controller 22 or the display module, for example, an unlock abnormality, an error code, or when the signal received by the timing controller 22 is an error signal, the first SOC21 may detect that there is abnormality information. At this time, the first SOC21 may detect the abnormal information by acquiring the operation state of the timing controller 22 or the display module, or may acquire the abnormal information by reporting the timing controller 22 or the display module. After detecting the abnormal information, the first SOC21 may switch the state signal of the timing controller 22 from the first value to the second value and retransmit the correct signal corresponding to the error information, so that the timing controller 22 receives the target signal corresponding to the error information again. At this time, the first SOC21 may switch the first detection-characterization signal from the third value to the fourth value to inform the timing controller 22 that the signal is abnormal. The counter 29 detects whether the status signal of the timing controller 22 is switched from the first value to the second value, and updates the number of occurrences of the error signal recorded therein, for example, accumulates 1 the number of occurrences of the error signal recorded therein, if it is detected whether the status signal of the timing controller 22 is switched from the first value to the second value. When the timing controller 22 re-receives the target signal corresponding to the error information, if the re-received target signal is a correct signal, a response signal is returned to the first SOC21, and at this time, the first SOC21 switches the state signal of the timing controller 22 from the second value to the first value, and continues data transmission. If the re-received target signal is still an error signal, the timing controller 22 returns an error message to the first SOC21 again.

As a possible implementation, the counter 29 is a shift counter, so that error information can be recorded in more detail.

Therefore, when the display module is in error, maintenance personnel can detect whether the current error information is generated due to device faults or other environmental reasons according to the recorded error times in the counter, and the maintenance is convenient.

As a possible implementation, the counter 29 is further configured to clear the recorded number of occurrences of the error signal when the shut down signal is received. Therefore, the counter can only record the error times in the current display time, so that maintenance personnel can conveniently detect the reasons for generating the error information of the current display time, and the situation that the maintenance personnel cannot detect the reasons for generating the error information of the current display time due to repeated statistics is avoided.

As a possible implementation, the timing controller 22 is further configured to return the abnormality information to the first SOC21 when the abnormality information is detected. For example, when the timing controller 22 cannot analyze the received target signal, abnormality information is returned to the first SOC 21.

As a possible implementation manner, the first SOC21 is further configured to send an operation state acquisition signal to the timing controller 22; the timing controller 22 is further configured to obtain operation state information in response to an operation state acquisition signal, and return the operation state information to the first SOC 21; the first SOC21 is also configured to detect whether abnormal information exists based on the operation state information. That is, the first SOC21 detects whether or not the operation state information of the timing controller 22 has abnormal information by acquiring the operation state information of the timing controller 22.

As a possible implementation, in the detection circuit, a status register 30 is also included, as shown in fig. 8. The status register is connected to the first SOC21, and the first SOC21 may store the value of the status signal of the timing controller 22 into the status register 30.

As a possible implementation, the state signal of the timing controller 22 of the first value is a low level signal, and the state signal of the timing controller 22 of the second value is a high level signal.

Fig. 9 is a timing diagram illustrating the operation of the detection circuit. Referring to fig. 9, the detection circuit operates with different operation timings, the transmission signals between the first SOC21 and the timing controller 22 are different. Where T1 represents the response capability of the power supply voltage, a delay of 10% -90% rise is required to be between 0.5 and 10ms (milliseconds). T2 represents a delay time of the first SOC21 for transmitting the test image signal to the timing controller 22 after the power supply path is started, for example, T2 cannot be lower than 40ms. T3 represents a waiting time for completion of data format verification and handshake success between the first SOC21 and the timing controller 22 after the first SOC21 sends the test image signal to the timing controller 22, for example, T3 is not less than 640ms. T4 indicates the time for the first SOC21 to continuously push the black frame to the timing controller 22 after the backlight unit in the display module is turned off, so as to avoid the display of the frame on the screen of the display module caused by the backlight afterglow effect. For example T4 is not less than 100ms. T5 represents a delay time from when the first SOC21 ends transmitting the test image signal to the timing controller 22 to when the power is turned off, and is required to be controlled to be between 0ms and 50 ms. T6 represents the protection time which must be reserved between the power supply and the next power supply after the power supply is turned off, and avoids abnormal display caused by the fact that other signals are not turned off or initialized due to the fact that the power supply is turned off quickly and the power supply is turned off quickly. For example, T6 is not less than 1000ms. T7 indicates the time from the power supply to the falling edge of the LOCKN signal, and is used for controlling the power-on initialization time length, so that the situation that the power-on cannot be started for a long time, and a consumer mistakenly thinks of the fault is avoided. For example, T7 does not exceed 500ms. T8 represents the relative delay time during which the I2C command can be transmitted after the image data is displayed, for monitoring the stable transmission of the I2C. For example T8 needs to be greater than 0ms. T9 represents the I2C command transmission time, which is determined by the command length and delay, and is generally not used a single time for a long time.

In this way, the first SOC21 and the timing controller 22 may refer to the above-mentioned operation timing, acquire corresponding state information, and further detect whether an abnormality exists. For example, the first SOC21 may obtain a waiting time for completion of data format verification and handshake success between the first SOC21 and the timing controller 22, detect if it is greater than 640ms, and if it is greater than it is determined that there is no anomaly. If the detected value is smaller than the preset value, determining that an abnormality exists.

As a possible implementation manner, the first SOC21 is further configured to obtain update indication information triggered by a user, and update target data indicated by the update indication information according to the update indication information.

In the embodiment of the present application, the first SOC21 may feed back the abnormality information to the user when the abnormality information is detected, and the user may analyze the cause of the abnormality when the abnormality information is acquired, and send update instruction information to the detection circuit when the data in the detection circuit needs to be updated. The first SOC21 acquires update instruction information triggered by the user and updates the target data indicated by the update instruction information according to the update instruction information so as to eliminate the abnormal information. For example, a threshold value of the electric signal between the first power supply module 23 and the display module is set in advance. At this time, the first power module 23 may detect whether the current or the voltage between the first power module 23 and the display module exceeds the threshold value in real time, and if so, the first power module 23 stops providing the electric signal to the display module. If not, continuing to provide the electric signal for the display module. When the display module sends a short circuit, the current signal between the first power module 23 and the display module will become larger, as shown in fig. 10, if the threshold value is set unreasonably, the current signal after the enlargement is not larger than the threshold value, the first power module 23 will continue to provide an electrical signal for the display module, and the display module will generate heat. At this time, the first SOC21 may detect a display module heat generation abnormality and may feed back the abnormality to the user. The user can know that the current threshold value is unreasonably set by analysis, and at the moment, update indication information for updating the current threshold value is set and sent to the detection circuit. At this time, when the first SOC21 receives the update instruction information triggered by the user, the stored current threshold value may be updated according to the update instruction information.

In the embodiment of the application, the first SOC controls the time sequence controller to send the test display signal to the display module so as to excite the potential faults in the display module. In the application, the first SOC and the timing controller in the electronic equipment can be used for exciting the potential faults of the display module, and different timing controllers are not required to be arranged for different modules, so that the test cost is greatly reduced.

Referring to fig. 11, a schematic diagram of another detection circuit according to an embodiment of the present application is shown. The detection circuit provided by the embodiment of the application is applied to electronic equipment. The difference between the embodiments of the present application and the above embodiments is that the integration of the functions of the timing controller in the first SOC is realized. As shown in fig. 11, the detection circuit includes: a second SOC11, and a third power module 12. Wherein the second SOC11 is connected to the third power module 12.

The second SOC11 is configured to externally connect the display module, determine a second test signal in response to the test instruction, control the third power module 12 to provide an electrical signal to the display module according to the second test signal, generate a test display signal according to the second test signal, and send the test display signal to the display module.

In the embodiment of the application, when the electronic equipment needs to be tested, the second SOC11 can be externally connected with the display module to be tested, and when the display mode displays, an electric signal needs to be provided for the display module. At this time, the detection circuit includes a third voltage module 12 for providing an electrical signal to the display module under the control of the second SOC 11.

The second SOC11 is externally connected to the display module, and when receiving a test instruction triggered by a user, determines a second test signal in response to the test instruction, controls the third power module 12 to provide an electrical signal for the display module according to the second test signal, generates a test display signal according to the second test signal, and sends the test display signal to the display module so as to perform a corresponding test on the display module.

In the embodiment of the present application, how the second SOC11 controls the third power module 12 to provide the electrical signal for the display module according to the second test signal may refer to the timing controller 22 in the above embodiment to control the first power module 23 to provide the electrical signal for the display module according to the first test signal, which is not described herein. After receiving the test instruction, the second SOC11 may determine a corresponding second test signal according to the test instruction, generate a test display signal in a data format required by the display mode according to the second test signal, and send the test display signal to the display module to display a corresponding image signal. The process of determining the first test signal by the second SOC11 according to the above embodiment may be referred to as the first SOC, and will not be described herein.

It should be noted that, the protocol format of the second test signal obtained by the second SOC11 is different from the protocol format of the test display signal transmitted to the display module, so when the second test signal is determined, the protocol format of the second test signal needs to be converted into the protocol format corresponding to the display module, so as to obtain the test display signal, and thus the test display signal is sent to the display module.

As one possible implementation, the second test signal includes at least one of a second test image signal and a second detection characterization signal.

When the second test signal includes a second test image signal, the second SOC11 is configured to generate a test display image signal according to the second test image signal, and send the test display image signal to the display module through the fourth channel, as shown in fig. 12. Or,

when the second test signal includes the second detection characterization signal, the second SOC11 is configured to generate a test detection characterization signal according to the second detection characterization signal, and transmit the test detection characterization signal through the fifth channel and the display module, as shown in fig. 12.

When the second SOC11 is externally connected to the display module, an image data signal may be sent to the display module, and a detection characterization signal may be sent to the display module. In order to facilitate the transmission of signals, different channels between the display module and the data of different types can be established for transmitting the signals of different types. Based on this, the second test signal includes at least one of a second test image signal and a second detection characterization signal. At this time, a fourth channel and/or a fifth channel is established between the second SOC11 and the display module. When the second test signal includes a second test image signal, the second SOC11 may generate a test display image signal according to the second test image signal and transmit the test display image signal to the display module through the fourth channel. When the second test signal includes a second detection characterization signal, a test detection characterization signal may be generated according to the second detection characterization signal, and the test detection characterization signal may be sent to the display module through the fifth channel.

Because the protocol packaging formats corresponding to the different channels are different, after the second SOC11 acquires the second test signal, the second test signal needs to be subjected to corresponding protocol packaging according to the transmission channel between the second SOC and the display module, so as to obtain the test display signal. The channels to be used for transmitting the second test signals can be preset, and the second SOC11 can determine the corresponding transmission channels according to preset information after the second test signals are acquired, so as to perform corresponding protocol encapsulation on the second test signals to obtain corresponding test display signals. And transmitting the test display signal to the display module through the corresponding transmission channel.

As a possible implementation of the gain, as shown in fig. 13, the detection circuit further includes: the fourth power module 13 and the second power conversion module 14. The input end of the second voltage conversion module 14 is connected with the fourth power module 13, and the output end of the second voltage conversion module 14 is connected with the third power module 12.

The second voltage conversion module 14 is configured to convert the second voltage signal provided by the fourth power module 13 into an operating voltage of the third power module 12.

In the embodiment of the present application, the fourth power module 13 is configured to provide an operating voltage for the third power module 12. Since the operating voltage of the third power supply module 12 is different from the voltage signal supplied from the fourth power supply module 13, a second voltage conversion module 14 is provided. The input end of the second voltage conversion module 14 is connected with the fourth power module 13, and the output end of the second voltage conversion module 14 is connected with the third power module 12. The second voltage conversion module converts the second voltage signal provided by the fourth power module 13 into an operating voltage of the third power module 12.

As a possible implementation manner, as shown in fig. 14a, the detection circuit further includes: and a third memory module 15 connected to the second SOC 11.

The second SOC11 is configured to acquire test information and store the test information into the third storage module 15; and responding to the test instruction, acquiring test information corresponding to the test instruction from the third storage module 15 and generating a second test signal according to the test information corresponding to the test instruction.

In the embodiment of the present application, when the third storage module 15 stores the test information, the second SOC11 is required to generate the second test signal, and the second test signal may be generated according to the test information by referring to the first SOC21, which is not described herein.

As a possible implementation manner, as shown in fig. 14b, the detection circuit further includes: a fourth memory module 16 connected to the second SOC 11; the fourth memory module 16 is used for storing the second test signal. And the second SOC11 is configured to obtain a second test signal corresponding to the test instruction from the fourth memory module in response to the test instruction.

At this time, the second SOC11 may directly obtain the second test signal corresponding to the test instruction from the fourth storage module 16, without generating the second test signal, thereby reducing the workload of the second SOC 11.

As a possible implementation, since the second SOC11 needs to control the third power module 12 to provide the electrical signal to the display module, the second test signal further includes: and a second test control signal.

When the second test signal includes a second test control signal, the second SOC11 is configured to send the second test control signal to the third power module 12 through the sixth channel; the third power module 12 is configured to provide an electrical signal to the display module according to the second test control signal.

In the embodiment of the present application, the second SOC11 needs to send a control signal to the third power module 12, so a sixth channel is established between the second SOC11 and the third power module 12, as shown in fig. 15. The test signal includes a second test control signal, where the second test control signal is used to indicate the magnitude of the electrical signal that needs to be provided by the third power module 12 to the display module. For example, the third power module 12 includes a power voltage sub-module, a common voltage sub-module, a gray scale voltage sub-module and a common voltage sub-module, and the second test control signal needs to indicate the power voltage sub-module, the common voltage sub-module, the gray scale voltage sub-module and the common voltage sub-module included in the third power module 12 respectively need to provide the electric signals. The second SOC12 sends the second test control signal and the sixth channel to the third power module 12, and the third power module 12 controls the power voltage sub-modules, the common voltage sub-module, the gray scale voltage sub-module and the common voltage sub-module therein according to the second test control signal to provide corresponding electrical signals and transmit the electrical signals to the display module.

In the above implementation manner, the second SOC11 needs to acquire the second control test signal from the third storage module 15 or the fourth storage module 16 first, and the operation is complex when the second control test signal is sent to the third power module 12. The third power module 12 may be made to take the second test control signal directly from the memory module in order to reduce the complexity of the operation. Based on this, as one possible implementation, the second test signal further comprises: a second test control signal; the third power module 12 is connected to the fourth memory module 16 as shown in fig. 16; when the second test signal includes a second test control signal, the third power module 12 is configured to obtain the second test control signal from the fourth memory module 16, and provide an electrical signal to the display module according to the second test control signal.

That is, when the test signal is directly stored in the fourth memory module 16, the second SOC11 may transmit a read instruction of the second control signal to the fourth memory module 16 so that the second SOC11 reads out the second test control signal. The third power module 12 and the fourth memory module 16 are connected, at this time, the third power module 12 may directly obtain the second test control signal from the fourth memory module 16, and provide an electrical signal to the display module according to the second test control signal, without sending the second test control signal through the second SOC 11.

As a possible implementation manner, the second SOC11 is further configured to obtain update indication information triggered by a user, and update target data indicated by the update indication information according to the update indication information.

Specifically, in the above embodiment, the first SOC21 obtains the update indication information triggered by the user and updates the target data indicated by the update indication information according to the update indication information, which is not described herein.

Corresponding to the embodiment, the application also provides electronic equipment, which comprises the detection circuit and the display module.

As a possible implementation manner, the electronic device further includes an audio module, a power module, a camera module, a structural support module, and the like.

As a possible implementation, the electronic device is in an online mode of operation when the detection circuit is in operation. Wherein, the electronic device being in the online working mode means that the electronic device is in the live working mode.

It will be apparent to those skilled in the art that the techniques of embodiments of the present application may be implemented in software plus a necessary general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present application may be embodied in essence or what contributes to the prior art in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the embodiments or some parts of the embodiments of the present application.

The same or similar parts between the various embodiments in this specification are referred to each other. In particular, for the device embodiment and the terminal embodiment, since they are substantially similar to the method embodiment, the description is relatively simple, and reference should be made to the description in the method embodiment for relevant points.

Claims

1. A detection circuit for use in an electronic device, the detection circuit comprising: the system comprises a first system-on-chip (SOC), a time sequence controller and a first power module;

2. The detection circuit of claim 1, wherein the first test signal comprises at least one of a first test control signal, a first test image signal, and a first detection characterization signal;

when the test signal includes a first detection characterization signal, the first SOC is configured to transmit the first detection characterization signal through a third channel with the timing controller.

3. The detection circuit of claim 2, wherein,

the first SOC is also used for receiving a control response signal sent by the time sequence controller through the first channel.

4. The detection circuit of claim 1, further comprising: the second power module and the first voltage conversion module;

5. The detection circuit of claim 1, further comprising: a first memory module connected to the first SOC;

6. The detection circuit of claim 1, further comprising: a second memory module connected to the first SOC; the second storage module is used for storing the first test signal;

7. The detection circuit according to any one of claims 1 to 6, further comprising: a counter;

the first SOC is further used for switching the state signal of the time sequence controller from a first value to a second value when abnormal information is detected, and sending a target signal corresponding to the abnormal information to the time sequence controller again; the target signal is any one of signals sent to the time sequence controller by the first SOC;

8. The detection circuit of claim 7, wherein the detection circuit comprises a logic circuit,

the counter is also used for clearing the recorded occurrence times of error signals when the closing signal is received.

9. The detection circuit of claim 7, wherein the detection circuit comprises a logic circuit,

the time sequence controller is also used for returning the abnormal information to the first SOC when the abnormal information is detected.

10. The detection circuit of claim 7, wherein the detection circuit comprises a logic circuit,

the first SOC is further used for sending an operation state acquisition signal to the time sequence controller;

11. The detection circuit of claim 7, further comprising:

12. A detection circuit for use in an electronic device, the detection circuit comprising: the second system-on-a-chip SOC and the third power module; wherein the second SOC is connected with the third power module;

the second SOC is used for externally connecting the display module, responding to the test instruction, determining a second test signal, controlling the third power module to provide an electric signal for the display module according to the second test signal, generating a second test display signal according to the second test signal, and sending the second test display signal to the display module.

13. The detection circuit of claim 12, wherein the second test signal comprises at least one of a second test image signal and a second detection characterization signal;

when the test signal comprises a second test image signal, the second SOC is used for generating a test display image signal according to the second test image signal and sending the test display image signal to the display module through a fourth channel; or,

14. The detection circuit of claim 12, further comprising: a fourth power module and a second voltage conversion module; the input end of the second voltage conversion module is connected with the fourth power supply module, and the output end of the second voltage conversion module is connected with the third power supply module;

15. The detection circuit of claim 12, further comprising: a third memory module connected to the second SOC;

16. The detection circuit of claim 12, further comprising: a fourth memory module connected to the second SOC; the fourth storage module is used for storing the second test signal;

17. The detection circuit of any one of claims 12-16, wherein the second test signal further comprises: a second test control signal;

18. The detection circuit of claim 16, wherein the second test signal further comprises: a second test control signal; the third power module is connected with the fourth storage module;

19. The detection circuit of claim 12, wherein the detection circuit comprises a logic circuit,

the second SOC is further used for acquiring update indication information triggered by a user and updating target data indicated by the update indication information according to the update indication information.

20. An electronic device comprising a display module and a detection circuit according to any one of claims 1-11 or 12-19.