CN116963503A

CN116963503A - Memory array including memory cell strings and method of forming a memory array including memory cell strings

Info

Publication number: CN116963503A
Application number: CN202310244629.XA
Authority: CN
Inventors: 王宜平; A·W·扎克斯勒; N·比利克
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2022-04-25
Filing date: 2023-03-13
Publication date: 2023-10-27
Also published as: US20230345723A1

Abstract

The present application relates to a memory array including memory cell strings and a method of forming a memory array including memory cell strings. A memory array comprising strings of memory cells includes laterally spaced apart memory blocks that individually comprise vertical stacks comprising alternating insulating and conducting layers directly above a conductor layer. The memory cell string includes a string of channel material extending through the insulating layer and the conductive layer. The string of channel material is directly electrically coupled to the conductor material of the conductor layer by the lowermost conductive material of the conductor layer. The insulating material of the insulating layer immediately above the lowermost conductive layer directly abuts the top of the conductive material of the lowermost conductive layer. The insulating material includes at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulating material. Other embodiments, including methods, are disclosed.

Description

Memory array including memory cell strings and method of forming a memory array including memory cell strings

Technical Field

Embodiments disclosed herein relate to a memory array including memory cell strings and a method for forming a memory array including memory cell strings.

Background

Memory is a type of integrated circuit system and is used in computer systems to store data. The memory may be fabricated as one or more arrays of individual memory cells. Memory cells may be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines can conductively interconnect memory cells along columns of the array, and the access lines can conductively interconnect memory cells along rows of the array. Each memory cell is uniquely addressable by a combination of sense lines and access lines.

The memory cells may be volatile, semi-volatile, or nonvolatile. Nonvolatile memory cells can store data for a long period of time without power up. Nonvolatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. Regardless, the memory cells are configured to retain or store memory in at least two different selectable states. In binary systems, the state is considered to be either a "0" or a "1". In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

Field effect transistors are one type of electronic component that can be used in memory cells. These transistors include a pair of conductive source/drain regions with a semiconductive channel region therebetween. The conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The field effect transistor may also include additional structures, such as a reversible programmable charge storage region as part of a gate construction between the gate insulator and the conductive gate.

Flash memory is a type of memory and is used in large numbers in modern computers and devices. For example, modern personal computers may have the BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in the form of solid state disks in place of conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because flash memory enables manufacturers to support new communication protocols as they become standardized, and enables manufacturers to provide the ability to remotely upgrade devices for enhanced features.

The memory arrays may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks) and memory planes, for example, as shown and described in any of us patent application publications 2015/0228651, 2016/0267984 and 2017/0140833. The memory block may at least partially define a longitudinal profile of individual word lines in an individual word line layer of vertically stacked memory cells. The connection to these word lines may occur in a so-called "stair-step structure" at the end or edge of the array of vertically stacked memory cells. The stair-step structure includes individual "steps" (alternatively referred to as "steps" or "steps") defining contact regions of individual word lines that are contacted by vertically extending conductive vias to provide electrical access to the word lines.

Disclosure of Invention

An aspect of the present disclosure provides a method for forming a memory array including a string of memory cells, wherein the method comprises: forming a lower portion of a stack comprising vertically alternating first and second levels, the first and second levels comprising different compositions relative to each other, the stack comprising laterally spaced memory block regions, the lower portion comprising: a lowermost first layer comprising a sacrificial first material; a horizontal extension line in the lowermost first level, the horizontal extension line being individually laterally between and along laterally immediately adjacent ones of the laterally spaced apart memory block regions, the horizontal extension line comprising an insulative second material having a different composition than the sacrificial first material; one of the second layers immediately above the lowermost first layer and comprising the insulating second material, the insulating second material being directly against the lowermost first layer and directly above the horizontally elongate line; and a third material directly above and directly against the insulating second material, the insulating second material directly against the lowermost first level and directly above the horizontal extension line, the third material having a different composition than the first and second materials; forming the vertically alternating first and second levels of the upper portion of the stack directly above the lower portion; forming horizontally elongated trenches into the stack, the horizontally elongated trenches individually between the laterally immediately adjacent memory block regions and extending to the horizontally elongated lines immediately thereunder; etching some of the insulating second material of the horizontally elongate lines and the insulating second material directly above and directly against the lowermost first level to expose the sacrificial first material and the third material through the horizontally elongate trenches; and etching the sacrificial first material relative to the third material through the horizontally elongated trench.

Another aspect of the present disclosure provides a memory array including a memory cell string, wherein the memory array includes: laterally spaced apart memory blocks individually comprising a vertical stack comprising alternating insulating and conducting levels directly above a conductor level, a memory cell string comprising a string of channel material extending through the insulating and conducting levels, the string of channel material being directly electrically coupled with a conductor material of the conductor level through a lowermost conductive material of the conducting level; and an insulating material immediately above the insulating layer immediately above the lowermost conductive layer, the insulating material directly abutting the top of the conductive material of the lowermost conductive layer; the insulating material includes at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulating material.

Another aspect of the present disclosure provides a memory array including a memory cell string, wherein the memory array includes: laterally spaced apart memory blocks individually comprising a vertical stack comprising alternating insulating and conducting levels directly above a conductor level, a memory cell string comprising a string of channel material extending through the insulating and conducting levels, the string of channel material being directly electrically coupled with a conductor material of the conductor level through a lowermost conductive material of the conducting level; and carbon doped polysilicon on top of and directly against the conductive material of the lowermost conductive level.

Drawings

Fig. 1 and 2 are schematic cross-sectional views of portions of a configuration of an array that will include vertically extending strings of memory cells, according to an embodiment of the invention.

Fig. 3-23 are schematic sequential cross-sectional and/or enlarged views of the constructions of fig. 1 and 2, or portions or alternatives and/or additional embodiments thereof, in process according to some embodiments of the invention.

Detailed Description

Embodiments of the present invention contemplate methods for forming memory arrays, such as NAND arrays or arrays of other memory cells with under-array peripheral control circuitry (e.g., under-array CMOS). Embodiments of the present invention contemplate so-called "back gate" or "replacement gate" processes, so-called "front gate" processes, and other processes whether existing or developed in the future that are independent of the time of formation of the transistor gate. Embodiments of the invention also contemplate memory arrays (e.g., NAND architectures) that are independent of the method of manufacture. Example method embodiments are described with reference to fig. 1-23, which may be considered a "back gate" or "replacement gate" process. Furthermore and regardless, the following sequence of processing steps is but one example, and other sequences of example processing steps (with or without other processing steps) may be used, whether or not a "backgate/replacement gate" process is used.

Fig. 1 and 2 illustrate a construction 10 having an array or array region 12 in which vertically extending strings of transistors and/or memory cells are to be formed. The construction 10 includes a base substrate 11 having any one or more of conductive/conductive, semiconductive/semiconductive or insulating/insulator/insulating (i.e., electrically therein) materials. Various materials are formed vertically above the base substrate 11. The material may be alongside, vertically inward of, or vertically outward of the material depicted in fig. 1 and 2. For example, other partially or fully fabricated components of the integrated circuit system may be provided somewhere above, around or within the base substrate 11. Control and/or other peripheral circuitry for operating components within an array of vertically extending strings of memory cells (e.g., array 12) may also be fabricated, and the system may or may not be wholly or partially within the array or sub-array. Furthermore, multiple subarrays may also be fabricated and operated independently, sequentially or otherwise with respect to each other. In this document, a "subarray" may also be considered an array.

In one embodiment, a conductor level 16 comprising a conductor material 17 has been formed over the substrate 11. The conductor material 17 as shown includes an upper conductor material 43 directly above and directly electrically coupled to (e.g., directly against) a lower conductor material 44, the lower conductor material 44 having a different composition than the upper conductor material 43. Examples of upper conductor material 43 include conductively doped semiconductive materials (e.g., n-doped or p-doped polysilicon). In one embodiment, the lower conductor material 44 comprises a metallic material (e.g., a metal silicide, such as WSi _x ). Conductor layer 16 may include portions of control circuitry (e.g., circuitry under a peripheral array and/or common source lines or plates) for controlling read and write access to transistors and/or memory cells to be formed in array 12.

A lower portion 18L of stack 18 has been formed directly above conductor level 16 (where present) and substrate 11 (as a suffix for inclusion of all such components designated by the same numeral with or without other suffixes). The stack 18 will include vertically alternating conductive levels 22 and insulating levels 20. The lower portion 18L and the conductor level 16 collectively include laterally spaced apart memory block regions 58 that would include laterally spaced apart memory blocks 58 in the finished circuitry construction. The memory block region 58 and the resulting memory block 58 (not shown) may be considered to be longitudinally elongated and oriented in parallel, e.g., horizontally, relative to one another along the direction 55.

Conductive level 22 (alternatively referred to as a first level) may not include conductive material and insulating level 20 (alternatively referred to as a second level) may not include insulating material or be insulating when processed in connection with the "back gate" or "replacement gate" example method embodiments described initially herein. In one embodiment, the lower portion 18L includes a lowermost level 20z of the second level 20 directly above (e.g., directly against) the conductor material 17. The example lower most second level 20z is insulating and may be sacrificial (e.g., in the array 12; e.g., comprising material 62 such as silicon dioxide and/or silicon nitride). In one embodiment, the next lowest second level 20x of the second levels 20 is directly above the lowest second level 20z and may be at least partially sacrificial. The lowermost level 22z of the first level 22 comprising sacrificial first material 77 (e.g., polysilicon or silicon nitride) is vertically between the lowermost second level 20z and the next lowermost second level 20 x. Horizontal extension lines 80 are in the lowermost first level 22z and are individually laterally between and along laterally immediately laterally spaced apart ones 58 of the laterally spaced apart memory block regions 58. The horizontally-extending lines 80 include an insulative second material 63 (e.g., silicon dioxide and/or silicon nitride) having a different composition than the sacrificial first material 77. In one embodiment, the horizontally-elongated lines 80 include a core material 82 (e.g., a metallic material such as W, ti, co, ta, tungsten nitride, titanium nitride, cobalt nitride, tantalum nitride, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide) having a different composition than the third material 83 (referred to as under), the second material 63, and the first material 77, wherein the insulative second material 63 of the lines 80 is laterally outward from opposite sides of the core material 82.

The next-lowest second level 20x is immediately above the lowest first level 22z (i.e., no other second level 20 is present between level 22z and level 20 x) and includes an insulating second material 63 directly against the lowest first level 22z and directly above (e.g., directly against) the horizontal extension line 80. The third material 83 is directly above and directly against the insulating second material 63, and the insulating second material 63 directly against the lowermost first level 22z and directly above the horizontally extending lines 80. The third material 83 has a different composition than the first material 77 and the second material 63. Examples include at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulating materials (e.g., any of carbon-doped silicon nitride, carbon-doped silicon dioxide, carbon-doped aluminum oxide, carbon-doped hafnium oxide, and carbon-doped zirconium oxide). An example carbon doping is 0.5 to 50.0 atomic percent, in one such embodiment no greater than 10 atomic percent, and in one such embodiment 1.0 to 10 atomic percent. In one embodiment, the next-to-lowest second level 20x includes an insulating material 24 (e.g., silicon dioxide) directly above the third material 83.

Referring to fig. 3-6, an upper portion 18U of stack 18 is formed directly above a lower portion 18L. The example upper portion 18U includes vertically alternating first and second decks 22, 20 of different compositions. The first layer 22 may be conductive and the second layer 20 may be insulating, although this need not be the case when processed in connection with the example method embodiments of "back gate" or "replacement gate" described herein. Example first and second layers 22 and 20 include different constituent materials 26 and 24 (e.g., silicon nitride and silicon dioxide), respectively. The example upper portion 18U is shown beginning above the lower portion 18L with the first level 22, although this could alternatively begin with the second level 20 (not shown) or material 24 in the next lowest second level 20x could be considered to be in the upper portion 18U (not so designated). Additionally, and by way of example, the lower portion 18L may be formed with one or more first and/or second layers as a top thereof. In any event, only a few decks 20 and 22 are shown, with the upper portion 18U (and thus the stack 18) being more likely to include tens, hundreds, or more of the iso-decks 20 and 22. In addition, other circuitry, which may or may not be part of the peripheral and/or control circuitry, may be between conductor level 16 and stack 18. By way of example only, multiple vertically alternating levels of conductive material and insulating material of such circuitry may be below the lowermost portion of conductive level 22 and/or above the uppermost portion of conductive level 22. For example, one or more select gate levels (not shown) may be between conductor level 16 and the lowermost conductive level 22, and one or more select gate levels may be above the uppermost portion of conductive level 22. Alternatively or additionally, at least one of the depicted uppermost and lowermost conductive levels 22 may be a select gate level.

The channel opening 25 has been formed (e.g., by etching) through the second level 20 and the first level 22 in the upper portion 18U to the lower portion 18L (e.g., at least to the lowermost first level 22z in the lower portion 18L). The channel openings 25 may taper radially inward or radially outward as they move deeper into the stack 18 (not shown). In some embodiments, the channel openings 25 may be shown into the conductor material 17 of the conductor level 16, or may terminate at a top (not shown). Alternatively, as an example, the channel opening 25 may terminate at the top or inside of the lowermost second level 20 z. The reason for having the channel opening 25 extend at least into the conductor material 17 of the conductor layer plane 16 is to provide an anchoring effect to the material within the channel opening 25. An etch stop material (not shown) may be in or on top of the conductor material 17 of the conductor level 16 in order to stop the etching of the channel openings 25 relative to the conductor level 16 when needed. Such etch stop materials may be sacrificial or non-sacrificial.

Transistor channel material may be formed vertically along the insulating layer and the conductive layer in individual channel openings, thus comprising individual strings of channel material directly electrically coupled with the conductor material in the conductor layer. Individual memory cells of the example memory array being formed can include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material (e.g., floating gate material, such as doped or undoped silicon, or charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cells is vertically along the individual charge blocking regions. An insulating charge transport material (e.g., a band gap engineered structure with a nitrogen-containing material [ e.g., silicon nitride ] sandwiched between two insulator oxides [ e.g., silicon dioxide ]) is laterally between the channel material and the memory material.

In one embodiment and as shown, charge blocking material 30, storage material 32, and charge transfer material 34 are formed vertically along insulating layer 20 and conductive layer 22 in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell material) may be formed, for example, by depositing their respective thin layers over stack 18 and in respective openings 25, and then planarizing such thin layers back at least to the top surfaces of stack 18.

Channel material 36, which is a string of channel material 53, is also formed vertically in channel opening 25 along insulating layer level 20 and conductive layer level 22 in memory block region 58. Materials 30, 32, 34, and 36 are collectively represented as material 37, and are designated in some figures as material 37 only due to scale. Example channel material 36 includes a suitably doped crystalline semiconductor material, such as one or more of silicon, germanium, and so-called group III/V semiconductor materials (e.g., gaAs, inP, gaP and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. A punch etch may be performed to remove materials 30, 32, and 34 from the base of trench opening 25 to expose conductor level 16 such that trench material 36 is directly against conductor material 17 of conductor level 16. Such punch etching may occur separately (as shown) with respect to each of materials 30, 32, and 34, or may occur with respect to only some of them (not shown). Alternatively, and by way of example only, no punch etch may be performed, and the channel material 36 may be directly electrically coupled to the conductor material 17 of the conductor layer 16 only through a separate conductive interconnect (not shown). Radial center solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and/or silicon nitride) is shown in channel opening 25. Alternatively, and by way of example only, a radially central portion in the channel opening 25 may include void spaces (not shown) and/or be free of solid material (not shown).

Horizontally elongated trenches 40 are formed (e.g., by anisotropic etching) into the stack 18. Such horizontally elongated trenches 40 are individually located between laterally immediately adjacent memory block regions 58 and extend to horizontally elongated lines 80 immediately thereunder. An optional thin sacrificial liner 81 (e.g., hafnium oxide, aluminum oxide, multiple layers of the same or other materials, [ e.g., silicon dioxide and silicon nitride ], etc.) is then formed in trench 40, followed by a punch etch through the optional thin sacrificial liner 81 to expose the material of horizontally-extending lines 80. The trenches 40 may taper laterally inward or laterally outward to move deeper into the stack 18 (not shown). By way of example only and for brevity, the channel openings 25 are shown as being arranged in groups or columns of staggered rows of four and five channel openings 25 per row. Trench 40 is typically wider (e.g., 2 to 5 times wider) than channel opening 25. Any alternative existing or future developed arrangement and configuration may be used. Trench 40 and trench opening 25 may be formed in any order or simultaneously with respect to each other.

Referring to fig. 7 and 8, the core material 82 (now not shown when present) is etched away.

Referring to fig. 9 and 10, the insulative second material 63 of the horizontal extension lines 80 (neither now shown) and some of the insulative second material 63 directly above and directly against the lowermost first level 22z (e.g., in the next-to-lowermost second level 20 x) are etched through the horizontally elongated trenches 40 to expose the sacrificial first material 77 and the third material 83.

Referring to fig. 11 and 12, sacrificial first material 77 (not shown) is etched through horizontally elongated trenches 40 selectively to third material 83. For example, liquid or gas phase H ₃ PO ₄ May be used as the main etchant in which material 77 is silicon nitride, or tetramethyl ammonium hydroxide TMAH in which material 77 is polysilicon]. Each of which may be used to provide a third material relative to the examples provided hereinMaterial 83 (e.g., aluminum oxide, hafnium oxide, zirconium oxide, carbon doped silicon nitride, carbon doped silicon dioxide, carbon doped aluminum oxide, carbon doped hafnium oxide, and carbon doped zirconium oxide) selectively etches example sacrificial material 77. The skilled person is able to select other chemistries to selectively etch the other material 77 with respect to the same or other third material 83. Liner 81 desirably is resistant to the etching fluid used during flow, as are materials 62 and 63.

Referring to fig. 13-15, and in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in level 22z to expose sidewalls 41 of channel material 36 of channel material string 53 in the lowermost first level 22 z. Any of materials 30, 32, and 34 in layer 22z may be considered sacrificial materials therein. For example, consider an embodiment in which liner 81 is one or more insulating oxides (other than silicon dioxide), and memory cell materials 30, 32, and 34 are one or more of silicon dioxide and silicon nitride layers, respectively. In such examples, the depicted construction may be produced by using a modified or different chemistry to etch silicon dioxide and silicon nitride selectively in sequence relative to another chemistry. As an example, a 100:1 (by volume) solution of water and HF will selectively etch silicon dioxide with respect to silicon nitride, while a 1000:1 (by volume) solution of water and HF will selectively etch silicon nitride with respect to silicon dioxide. Thus, and in such examples, such etching chemistries may be used in an alternating fashion, where it is desirable to achieve the configuration depicted by the examples. In one embodiment and as shown, this etch has been performed selectively (when present) with respect to liner 81. In one embodiment, materials 62 and 63 (not shown in memory block region 58) are also removed. Such materials, when so removed, may be removed when materials 30, 32, and 34 are removed, such as where materials 62 and 63 comprise one or both of silicon dioxide and silicon nitride. Alternatively, such materials may be removed separately (e.g., by isotropic etching) when so removed. The skilled person is able to select other chemicals for etching other different materials in case a configuration as shown is desired.

After exposing the sidewalls 41, a conductive material 42 (e.g., conductively doped polysilicon) is formed in the lowermost first level 22z and, in one embodiment, directly against the sidewalls 41 of the channel material 36. In one embodiment and as shown, such material is formed directly against the bottom of the third material 83 and directly against the top of the conductor material 43 of the conductor level 16, thereby directly electrically coupling the channel material 36 of the individual channel material strings 53 with the conductor material 43 of the conductor level 16.

Referring to fig. 16 and 17, conductive material 42 is removed from trench 40 by having sacrificial liner 81 (not shown here). The sacrificial liner 81 (when present) may be removed before or after the formation of the conductive material 42.

Referring to fig. 18-22, material 26 of conductive layer 22 in array region 12 is removed (e.g., liquid or gaseous H is to be removed), such as by isotropically etching away through trench 40, desirably selectively with respect to other exposed materials ₃ PO ₄ Used as the main etchant, wherein material 26 is silicon nitride and the other material includes one or more oxides or polysilicon). In an example embodiment, material 26 in conductive layer 22 in array region 12 is sacrificial and has been replaced with conductive material 48 and thereafter removed from trench 40, thus forming vertically extending strings 49 of individual conductive lines 29 (e.g., word lines) and individual transistors and/or memory cells 56.

A thin insulating liner (e.g., al) ₂ O ₃ Not shown). The approximate locations of some transistors and/or some memory cells 56 are indicated with brackets or with dashed outlines, where the transistors and/or memory cells 56 are substantially annular or ring-shaped in the depicted example. Alternatively, the transistors and/or memory cells 56 may not be fully surrounded relative to the individual channel openings 25 such that each channel opening 25 may have two or more vertically extending strings 49 (e.g., in an individual conductive level, multiple transistors and/or memory cells surrounding an individual channel opening, where it may be in an individual conductive level)Multiple word lines per channel opening, not shown). Conductive material 48 may be considered to have ends 50 corresponding to control gate regions 52 of individual transistors and/or memory cells 56. In the depicted embodiment, the control gate regions 52 include individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be considered a memory structure 65 located laterally between control gate region 52 and channel material 36. In one embodiment and as shown with respect to the example "back gate" process, the conductive material 48 of the conductive layer 22 is formed after the openings 25 and/or trenches 40 are formed. Alternatively, the conductive material of the conductive layer may be formed (not shown) prior to forming the channel openings 25 and/or trenches 40, for example, as opposed to a "gate-first" process.

A charge blocking region (e.g., charge blocking material 30) is between the memory material 32 and each control gate region 52. The charge barrier may have the following functions in the memory cell: in the programming mode, the charge blocker may prevent charge carriers from exiting the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate, and in the erase mode, the charge blocker may prevent charge carriers from flowing from the control gate into the charge storage material. Thus, the charge blocking member may be used to block charge migration between the control gate regions and the storage material of the individual memory cells. The example charge blocking region as shown includes an insulator material 30. By way of further example, the charge blocking region may include a laterally (e.g., radially) outer portion of a storage material (e.g., material 32), where such storage material is insulating (e.g., in the absence of any different composition material between insulating storage material 32 and conductive material 48). Regardless, as an additional example, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any single constituent insulator material 30. Further, the interface bonding insulator material 30 of the conductive material 48 and the material 30 (if present) may act together as a charge blocking region and may alternatively or additionally act as a laterally outer region of an insulating memory material, such as silicon nitride material 32. Example material 30 is one or more of hafnium oxide and silicon dioxide.

The intervening material 57 has been formedIn the trench 40, and thus laterally between laterally adjacent memory blocks 58, and longitudinally along the laterally adjacent memory blocks 58. The intervening material 57 may provide lateral electrical isolation (insulation) between laterally immediately adjacent memory blocks. This may include one or more of insulating, semiconducting, and conducting materials, and in any event may help prevent shorting of the conductive layers 22 relative to one another in the finished circuit system configuration. An example insulating material is SiO ₂ 、Si ₃ N ₄ And Al ₂ O ₃ One or more of the following. The intervening material 57 may include a through array via (not shown).

Any other attribute or aspect as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, the third material 83 is formed to include carbon doped polysilicon 83, for example as shown in fig. 23 with respect to construction 10 a. The same reference numerals of the above-described embodiments are used where appropriate, with some construction differences being indicated with the suffix "a" or with different numerals. In construction 10a, only the lower-most insulating layer 20 is designated 20x (e.g., as in construction 10) as compared to insulating material 24 and material 83 below the lower-most insulating layer 20, because the layer in which carbon-doped polysilicon 83 is received is not inherently insulating. TMAH may be used to selectively etch non-carbon doped polysilicon relative to carbon doped polysilicon. Any other attribute or aspect as shown and/or described herein with respect to other embodiments may be used.

Alternative embodiment constructions may be produced by the method embodiments described above or in other ways. Regardless, embodiments of the present invention encompass memory arrays independent of the method of manufacture. Nonetheless, such memory arrays may have any of the attributes as described herein in method embodiments. Also, the method embodiments described above may incorporate, form and/or have any of the attributes described with respect to the device embodiments.

In one embodiment, a memory array (e.g., 12) including a string (e.g., 49) of memory cells (e.g., 56) includes laterally spaced apart memory blocks (e.g., 58) individually including a vertical stack (e.g., 18 x) including alternating insulating layers (e.g., 20) and conductive layers (e.g., 22) directly above a conductive layer (e.g., 16). The string (e.g., 49) of memory cells (e.g., 56) includes a string of channel material (e.g., 53) extending through the insulating layer and the conductive layer. The string of channel material is directly electrically coupled to the conductor material (e.g., 17) of the conductor layer by the conductive material (e.g., 42) of the lowermost portion (e.g., 22 z) of the conductor layer. The insulating material of the insulating layer immediately above the lowermost conductive layer (e.g., 83 of construction 10) directly abuts the top (e.g., 85) of the conductive material of the lowermost conductive layer. The insulating material includes at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulating material. Any other attribute or aspect as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a memory array (e.g., 12) including a string (e.g., 49) of memory cells (e.g., 56) includes laterally spaced apart memory blocks (e.g., 58) individually including a vertical stack (e.g., 18 x) including alternating insulating layers (e.g., 20) and conductive layers (e.g., 22) directly above a conductive layer (e.g., 16). The string (e.g., 49) of memory cells (e.g., 56) includes a string of channel material (e.g., 53) extending through the insulating layer and the conductive layer. The string of channel material is directly electrically coupled to the conductor material (e.g., 17) of the conductor layer by the conductive material (e.g., 42) of the lowermost portion (e.g., 22 z) of the conductor layer. Carbon doped polysilicon (e.g., 83 of construction 10 a) is directly over and directly against the top (e.g., 85) of the conductive material of the lowest conductive level. In one embodiment, the carbon doped polysilicon is conductive, and in one embodiment, semi-conductive. Any other attribute or aspect as shown and/or described herein with respect to other embodiments may be used.

The use of a material 83 having a different composition than the sacrificial material 77 may reduce or prevent etching of the material immediately above the sacrificial material 77 when etching away the material, particularly if the line 80 includes a liner 63 having the same composition as the layer 63 immediately above the sacrificial material 77.

The above-described processes or configurations may be considered relative to an array of components formed as or within a single stack or single stack of such components over or as part of an underlying base substrate (although a single stack/stack may have multiple layers). Control and/or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the final construction, and in some embodiments may be underneath the array (e.g., CMOS underneath the array). Regardless, one or more additional such stacks/stacks may be provided or fabricated above and/or below the stacks/stacks shown en route or described above. Furthermore, the arrays of components may be the same or different relative to each other in different stacks/stacks, and the different stacks/stacks may have the same thickness or different thicknesses relative to each other. An intervening structure may be provided between vertically immediately adjacent stacks/stacks (e.g., additional circuitry and/or dielectric layers). Also, the different stacks/stacks may be electrically coupled with respect to each other. The multiple stacks/stacks may be manufactured separately and sequentially (e.g., one on top of the other), or two or more stacks/stacks may be manufactured substantially simultaneously.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated in electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic system may be any of the following broad range of systems: such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular telephones, personal computers, automobiles, industrial control systems, aircraft, and the like.

In this document, unless otherwise indicated, "vertical," "higher," "upper," "lower," "top," "bottom," "above," "below," "under … …," "below," "upward" and "downward" refer generally to vertical directions. "horizontal" refers to a general direction along the surface of the primary substrate (i.e., within 10 degrees) that the handle substrate may be opposite during fabrication, and vertical is a direction generally orthogonal thereto. "exactly horizontal" is the direction along the major substrate surface that may be opposite (i.e., not angled) to the process substrate during fabrication. Further, "vertical" and "horizontal" as used herein are generally vertical directions relative to one another and independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to directions that deviate from exactly horizontal by at least 45 °. Further, "vertically extending", "horizontally extending" and the like with respect to the field effect transistor are orientations of the channel length of the reference transistor along which in operation current flows between the source/drain regions. For bipolar junction transistors, "vertically extending", "horizontally extending" and the like are orientations with reference to the substrate length along which current flows between the emitter and collector in operation. In some embodiments, any component, feature, and/or region that extends vertically or within 10 ° of vertical.

Furthermore, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated regions/materials/components relative to each other. Moreover, the use of "over" that was not previously "positive" merely requires that some portion of a stated region/material/component above another stated region/material/component be vertically outward from the other stated region/material/component (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Similarly, the use of "under" and "below" that is not "directly" before requires only that a certain portion of a stated region/material/component below/beneath another stated region/material/component be vertically inward of the other stated region/material/component (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be uniform or non-uniform, and may be continuous or discontinuous over any material overlying it in any event. When one or more example compositions are provided for any material, the material may include, consist essentially of, or consist of such one or more compositions. In addition, unless otherwise indicated, each material may be formed using any suitable existing or future developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

In addition, "thickness" (the foregoing nondirectional adjective) used alone is defined as the average linear distance perpendicular through a given material or region from the nearest surface of an immediately adjacent material or immediately adjacent region having a different composition. In addition, the various materials or regions described herein may have a substantially constant thickness or have a variable thickness. If there is a variable thickness, thickness refers to the average thickness unless indicated otherwise, and the material or region will have some minimum thickness and some maximum thickness due to the variable thickness. As used herein, "different compositions" only require those portions of two stated materials or regions that can be directly abutted against each other to be chemically and/or physically different, for example, where such materials or regions are not uniform. If two stated materials or regions are not directly against each other, then where such materials or regions are not uniform, the "different compositions" only require that those portions of the two stated materials or regions that are closest to each other be chemically and/or physically different. In this document, when a stated material, region, or structure is in at least some physical contact with respect to each other, the material, region, or structure is "directly against" another material, region, or structure. In contrast, "over" … …, "on" … …, "adjacent," "along," and "against" are not preceded by "positive" and encompass "directly against" and configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical contact with each other.

Herein, zone-material-components are "electrically coupled" with respect to each other if, in normal operation, current is able to flow continuously from one zone-material-component to another zone-material-component, and the flow is primarily by the movement of subatomic positive and/or negative charges when they are sufficiently generated. Another electronic component may be between and electrically coupled to the region-material-components. In contrast, when a region-material-component is referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

Any use of "rows" and "columns" herein is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along the "rows" and "columns. "row" and "column" are used synonymously with any series of regions, components, and/or features, regardless of function. Regardless, the rows may be straight and/or curved and/or parallel and/or non-parallel with respect to each other, as may the columns. Further, the rows and columns may intersect at 90 ° or at one or more other angles (i.e., in addition to the flat angle) relative to each other.

The composition of any of the conductive/conductor/conductive materials herein may be a conductive metallic material and/or a conductively doped semiconductive/semiconductor/semiconductive material. A "metallic material" is an elemental metal, any mixture or alloy of two or more elemental metals, and any one or combination of any one or more metal compounds.

Any use of "selectivity" in connection with etching (etching/patterning), removing, depositing, forming (forming), and/or forming (formation) is herein such an action of one stated material relative to another stated material acting in a ratio of at least 2:1 by volume. Further, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material to another or more stated materials in a ratio of at least 2:1 by volume up to at least a first 75 angstroms.

The use of "or" herein encompasses both and either unless otherwise indicated.

Conclusion(s)

In some embodiments, a method for forming a memory array including a string of memory cells includes forming a lower portion of a stack including vertically alternating first and second levels, the first and second levels including different compositions relative to one another. The stack includes laterally spaced memory block regions. The lower portion includes a lowermost first layer including a sacrificial first material. Horizontal extension lines are in the lowermost first level, the horizontal extension lines being individually laterally between and along laterally immediately adjacent ones of the laterally spaced apart memory block regions. The horizontally-elongated lines include an insulative second material having a different composition than the sacrificial first material. One of the second layers is immediately above the lowermost first layer and includes the insulating second material directly against the lowermost first layer and directly above the horizontal extension line. A third material is directly above and directly against the insulating second material, which directly abuts the lowermost first level and directly above the horizontally elongated line. The third material has a different composition than the first and second materials. Vertically alternating first and second levels of an upper portion of the stack are formed directly above the lower portion. A horizontally elongated trench is formed into the stack, the horizontally elongated trench being individually between the laterally immediately adjacent memory block regions and extending to the horizontally elongated line immediately thereunder. The method further includes etching, through the horizontally elongated trench, some of the insulating second material of the horizontally elongated line and the insulating second material directly above and directly against the lowermost first level to expose the sacrificial first material and the third material. The sacrificial first material is etched selectively relative to the third material through the horizontally elongated trenches.

In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks including a vertical stack including alternating insulating and conductive layers directly above a conductor layer. The memory cell string includes a string of channel material extending through the insulating layer and the conductive layer. The string of channel material is directly electrically coupled to the conductor material of the conductor layer by the lowermost conductive material of the conductor layer. The insulating material of the insulating layer immediately above the lowermost conductive layer directly abuts the top of the conductive material of the lowermost conductive layer. The insulating material includes at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulating material.

In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks including a vertical stack including alternating insulating and conductive layers directly above a conductor layer. The memory cell string includes a string of channel material extending through the insulating layer and the conductive layer. The string of channel material is directly electrically coupled to the conductor material of the conductor layer by the lowermost conductive material of the conductor layer. Carbon doped polysilicon is on top of and directly against the conductive material of the lowermost conductive level.

Subject matter disclosed herein has been described in terms of structural and methodological features in a more or less specific language. It is to be understood, however, that the claims are not limited to the specific features shown and described, as the devices disclosed herein include example embodiments. The claims, therefore, have the full scope as set forth in the written description and should be interpreted appropriately in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array comprising strings of memory cells, comprising:

forming a lower portion of a stack comprising vertically alternating first and second levels, the first and second levels comprising different compositions relative to each other, the stack comprising laterally spaced memory block regions, the lower portion comprising:

a lowermost first layer comprising a sacrificial first material;

a horizontal extension line in the lowermost first level, the horizontal extension line being individually laterally between and along laterally immediately adjacent ones of the laterally spaced apart memory block regions, the horizontal extension line comprising an insulative second material having a different composition than the sacrificial first material;

One of the second layers immediately above the lowermost first layer and comprising the insulating second material, the insulating second material being directly against the lowermost first layer and directly above the horizontally elongate line; and

a third material directly above and directly against the insulating second material, the insulating second material directly against the lowermost first level and directly above the horizontal extension line, the third material having a different composition than the first and second materials;

forming the vertically alternating first and second levels of the upper portion of the stack directly above the lower portion;

forming horizontally elongated trenches into the stack, the horizontally elongated trenches individually between the laterally immediately adjacent memory block regions and extending to the horizontally elongated lines immediately thereunder;

etching some of the insulating second material of the horizontally elongate lines and the insulating second material directly above and directly against the lowermost first level to expose the sacrificial first material and the third material through the horizontally elongate trenches; and

The sacrificial first material is etched selectively relative to the third material through the horizontally elongated trenches.

2. The method of claim 1, wherein the insulative second material of the horizontally elongate wire is laterally outward from opposite sides of a core material of the horizontally elongate wire, the core material having a different composition than the first, second, and third materials.

3. The method of claim 2, comprising etching the core material through the horizontally elongated trench before the etching the insulating second material of the horizontally elongated lines and some of the insulating second material directly above and directly against the lowermost first level to expose the sacrificial first material and the third material.

4. The method of claim 1, wherein the sacrificial first material comprises polysilicon.

5. The method of claim 1, wherein the insulating second material comprises silicon dioxide.

6. The method of claim 1, wherein the third material comprises at least one of aluminum oxide, hafnium oxide, zirconium oxide, carbon doped insulating material, and carbon doped polysilicon.

7. The method of claim 1, wherein,

the sacrificial first material comprises polysilicon;

the insulating second material comprises silicon dioxide; and is also provided with

The third material includes at least one of aluminum oxide, hafnium oxide, zirconium oxide, a carbon-doped insulating material, and carbon-doped polysilicon.

8. The method of claim 1, wherein the third material comprises carbon doped silicon nitride.

9. The method of claim 8 wherein the carbon doped silicon nitride has 0.5 to 50.0 atomic percent carbon therein.

10. The method of claim 9 wherein the carbon doped silicon nitride has 1.0 to 10 atomic percent carbon therein.

11. A memory array comprising a string of memory cells, comprising:

laterally spaced apart memory blocks individually comprising a vertical stack comprising alternating insulating and conducting levels directly above a conductor level, a memory cell string comprising a string of channel material extending through the insulating and conducting levels, the string of channel material being directly electrically coupled with a conductor material of the conductor level through a lowermost conductive material of the conducting level; and

An insulating material of the insulating layer immediately above the lowermost conductive layer, the insulating material directly abutting a top of the conductive material of the lowermost conductive layer; the insulating material includes at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulating material.

12. The memory array of claim 11, wherein the insulating material comprises aluminum oxide.

13. The memory array of claim 11, wherein the insulating material comprises hafnium oxide.

14. The memory array of claim 11, wherein the insulating material comprises zirconia.

15. The memory array of claim 11, wherein the insulating material comprises a carbon-doped insulating material.

16. The memory array of claim 15, wherein the carbon-doped insulating material has no less than 0.5 atomic percent carbon therein.

17. The memory array of claim 15, wherein the carbon-doped insulating material has 0.5 to 50.0 atomic percent carbon therein.

18. The memory array of claim 15, wherein the carbon-doped insulating material has no greater than 10 atomic percent carbon therein.

19. The memory array of claim 18, wherein the carbon-doped insulating material has no less than 0.5 atomic percent carbon therein.

20. The memory array of claim 19, wherein the carbon-doped insulating material has no less than 1.0 atomic percent carbon therein.

21. The memory array of claim 15, wherein the carbon-doped insulating material comprises silicon nitride.

22. The memory array of claim 15, wherein the carbon-doped insulating material comprises silicon dioxide.

23. The memory array of claim 11, wherein the insulating material comprises more than one of the aluminum oxide, hafnium oxide, zirconium oxide, and carbon doped insulating material.

24. The memory array of claim 11, wherein the conductive material comprises conductively doped polysilicon.

25. A memory array comprising a string of memory cells, comprising:

Carbon doped polysilicon on top of and directly against the conductive material of the lowermost conductive level.

26. The memory array of claim 25, wherein the carbon-doped polysilicon is semiconductive.

27. The memory array of claim 25, wherein the carbon-doped polysilicon is conductive.

28. The memory array of claim 25, wherein the conductive material comprises conductively doped polysilicon.