CN1169623A

CN1169623A - Polynomial evaluator for use in reed-solomon decoder

Info

Publication number: CN1169623A
Application number: CN 96114193
Authority: CN
Inventors: 任龙熙
Original assignee: Daewoo Electronics Co Ltd
Current assignee: WiniaDaewoo Co Ltd
Priority date: 1996-07-01
Filing date: 1996-12-27
Publication date: 1998-01-07

Abstract

A polynomial evaluator evaluates a polynomial P(X) and a differential polynomial P'(X) iteratively, by substituting X with alpha <-(N-j)> in a jth iteration, to thereby provide P( alpha <-(N-j)>) and P'( alpha <-(N-j)>), wherein the evaluator has: an initialization block; a term updating block; a multiplexer; an addition block for determining a sum of the T evaluating terms of the jth set, to thereby provide a jth sum; an adder; a multiplexer; a multiplier; and an addition block for determining a sum of the differential evaluating terms of the jth group in the jth iteration, to thereby provide P'( alpha <-(N-j)>).

Description

Be used in the polynomial evaluation device in the Read-Solomon decoder

The present invention relates to a kind of device that is used for proofreading and correct the mistake that appears at storage or transmission data; And, more specifically, relate to a kind of device that is used for calculating in the value of using Reed one Saloman (Reed-Solomon) sign indicating number employed error-locator polynomial of coded data error recovery and differential polynomial.

The noise that occurs in the process of transmission, storage or restore data can further cause the mistake in transmission, storage or the data recovered.Correspondingly, worked out have an ability of correcting this mistake be used to encode the various coding techniquess of data of to be transmitted or storage.

In these coding techniquess, additional one group of check digit constitutes a code word on one group of message or information bit.The check digit of being determined by encoder is used for detecting and error recovery.In this respect, encoder mainly will comprise the position of message position and be used as the polynomial coefficient of binary system message also by message multinomial i (x) being multiply by a sign indicating number generator polynomial g (x) or removing i (x) with g (x) and derive check digit, so that a code word multinomial c (x) to be provided thus.The option code generator polynomial is so that give its code word of carrying out computing thereon with desirable characteristics, so that belonging to a particular category of error correction binary system group code, this code word (for example sees people such as S.Lin " Error ControlCoding:Fundamentals and Applications ", Prentice-Hall, 1983).

One class error correcting code is famous BCH (Bose-Chaudhuri-Hocquenghen) sign indicating number, and it comprises Reed one Saloman (" RS ") sign indicating number.The Fundamentals of Mathematics of RS sign indicating number are at people's such as for example above-mentioned Lin list of references and " Algebraic Coding Theory " (McGraw-Hill of Berlekamp, 1968) explanation in, the latter further mentions in the U.S. Patent No. 4,162,480 of authorizing Berlekamp.

If the root of the sign indicating number generator polynomial g (x) of RS sign indicating number is 2T the continuous power of the α in the formula (1), then can proofread and correct T mistake:

Wherein α is a finite field gf (2 ^m) in a primitive element.

May some accompanied by noise have been converted to the error pattern in the code word in the process of a code word of transmitting into storage receiving or recover.In order to tackle the error pattern that is applied on the RS sign indicating number, adopt one four step process usually.When this error correction procedure is discussed, should with reference to by comprise N M bit sign (wherein K symbol be information symbol and (N-K) individual symbol be checking symbol) a RS sign indicating number of code word formation.In this case, c (X) becomes (N-1) order polynomial and 2T equals (N-K).As first error correction step, from the code word multinomial r (X) that receives, i.e. (N-1) order polynomial computing syndrome S of the sign indicating number that expression receives ₀, S ₁, S _2T-1The code word multinomial r (X) that receives is expressed as r _N-1X ^N-1+ r _N-2X ^N-2+ ... + r ₁X ¹+ r ₀, its r _j(N-j) individual symbol for code word.As second step, utilize the coefficient of these syndrome computations error-locator polynomials σ (X).In the 3rd step, separate this error-locator polynomial σ (X) in the hope of its root, the errors present in the code word that these roots are represented to receive.Particularly, if draw 0 (that is α, with the variable X among power α-j replacement error-locator polynomial σ (X) of primitive element ^-jBecome the root of σ (X)), then be illustrated in rj, in (N-j) individual symbol of code word mistake has appearred promptly.

As the 4th step, utilize this errors present and syndrome computations improper value.The mathematic(al) representation of the coefficient of syndrome and error-locator polynomial is set forth in the above-mentioned U.S. Patent No. of authorizing Berlekamp 4,162,480.

More detailed in below explanation the 4th step.

At first, the evaluation multinomial Ω (X) that can make mistake is as follows:

Ω (X)=σ (X) S (X) formula (2) wherein S (X) is that its coefficient is a correction multinomial of syndrome.

After deriving wrong evaluation multinomial Ω (X), can be with improper value e _jBe calculated as:

e _j=α ^jΩ (α ^-j)/σ ' (α ^-j) formula (3) wherein σ ' be the first derivative of error-locator polynomial σ (X) (X), α ^-jRoot for the error-locator polynomial that draws in the 3rd step; And improper value e _jCorresponding to (N-j) individual symbol, it is the errors present that draws in the 3rd step.

After the value of locating errors, can recover original code word on the corresponding symbol by improper value is added to.

As mentioned above, polynomial evaluation is used in each stage of error correction procedure, wherein for α ^-jEvaluation be meant the element α of substitution finite field in the variable X in a given multinomial p (X) ^-jAt first the value of mistake in computation locator polynomial σ (X) finds errors present in the 3rd step.In the 4th step, mistake in computation evaluation multinomial Ω (X) and differential polynomial σ ' value (X) are determined improper value.Error-locator polynomial σ (X) can be expressed as: Corresponding, for α ^-jEvaluation σ (x) provides Wherein j is an integer in 0 to the N-1 scope, and multiplication and addition are at finite field gf (2 ^m) on carry out.Can represent other polynomial result of evaluation with similar fashion.

Referring to Fig. 1, wherein show the example block diagram of disclosed traditional polynomial evaluation device 1 in the total unsettled China application No.______ of " Polynomial Evaluator for use in a Reed-Sol omon Decoder " by name.Evaluator shown in Fig. 1 comes the value of mistake in computation locator multinomial σ (X) by execution formula (5B) under the situation of T=8.

In polynomial evaluation device 1, the calculating of formula (5B) is carried out iteratively from j=N-1 to 0, and wherein an iteration is preferably in the system clock cycle and finishes.

Polynomial evaluation device 1 comprises an INIT block 10 that is used to provide initial evaluation item, an item renewal piece 30 that is used to upgrade the evaluation item, one is used for providing the multiplexer 20 that upgrades piece 30 to item heavily again with the evaluation item after initial evaluation item or the renewal, an adder block 40 that is used for the calculated value addition that to obtain iteration, an IOB 50 and a mistake are determined piece 55, and wherein the evaluation item refers to the σ that comprises in the formula (5B) _iα ^-ij, each iteration is all upgraded j, and the initial calculation value is σ _iα ^-iN

Beginning to determining σ (α ^-(N-1)) and first time of carrying out the evaluation process before the iteration use one group of 8 the initial evaluation item that provides from INIT block 10, i.e. σ _iα ^-iN(i from 1 to 8) comes initialization to be included in register the block of registers 30C that upgrades piece 30.

For initial evaluation item is provided, in being included in INIT block 10 and at finite field gf (2 ^m) go up among the multiplier 10b of computing, with each factor sigma of error-locator polynomial _iWith α ^-iNMultiply each other, i is from 1 to 8, wherein α ^-iNProvide from first input block 10a.Consequently, multiplier 10b should organize 8 initial evaluation item σ _iα ^-iNInput port 0 to MUX20 sequentially is provided.For initialization MUX20 with σ _iα ^-iNBe directed to block of registers 30C.The first initial evaluation item σ particularly ₁α ^-NSent into R by first ₁And be stored in a wherein bit clock cycle.With R ₁Content move to R ₂And be stored in the wherein next bit clock cycle, arrive R then ₃, or the like.At last, with R ₈Output port upgrade in the piece 30 and with being included at finite field gf (2 ^m) go up the multiplier 30a phase of computing: connect.

In each register, filled corresponding initial evaluation item (for example, σ ₁α ^-NAt R ₈, σ ₂α ^-2NAt R ₇In, or the like) afterwards, begin to be used for to determine the first result of evaluation σ (α ^-(N-1)) the iteration first time.

At first bit clock in the cycle of the iteration first time, multiplier 30a will be from R ₈The σ that comes is provided ₁α ^-NWith the α that sends here from second input block 30b ¹Multiply each other.The output of multiplier 30a, for example σ ₁α ^-(N-1)(or in other words, first evaluation item of first group, K group evaluation item refers to σ _iα ^{-i (N-K)}, K is 1 to N), be admitted to adder block 40, one of each bit clock cycle.

Adder block 40 comprises one two input summer 40a and a register 40c, wherein, and in the continuous addition of formula (5B), at finite field gf (2 ^m) go up same group each evaluation item that the adder 40a of computing will provide from multiplier 30a and the content addition of register 40c, and the 1st to the 7th part of the evaluation item that register 40c storage provides from adder 40a and and will part and deliver to adder 40a, L part and refer to be included in L evaluation item in same group with, L is 1 to 7.It also comprises a multiplexer 40b, be used for selectively with 0 or the output of adder 40a provide to register 40c.MUX40b each iteration begin with 0 provide to register 40c with initialization register 40c, and all the other times provide the part that provides from adder 40a and.

Particularly, when receiving σ from multiplier 30a ₁α ^-(N-1)The time, adder 40a is added to the initial content of register 40c with it, promptly on 0.Then, first and, σ ₁α ^-(N-1),, sent back to register 40c, so that for example the rising edge in the next bit clock cycle is stored in wherein by MUX40b.For this reason, MUX40b provides the output of adder 40a to register 40c.

Explanation is in passing, the σ that will provide from multiplier 30a by MUX20 ₁α ^-(N-1)Deliver to block of registers 30c, with thus for example the first time iteration the rising edge in the second bit clock cycle content of each register is moved right.

During the second bit clock cycle of the iteration first time, multiplier 30a will be from R ₈The σ that comes is provided ₂α ^-2NWith α ²Multiply each other.Multiplier 30a output at this moment, i.e. σ ₂α ^{-2 (N-1)}Be admitted to adder 40a, be added to the content of register 40c therein, i.e. σ ₁α ^-(N-1)On.Then second portion and, σ ₁α ^-(N-1)+ σ ₂α ^{-2 (N-1)}Sent back to register 40c by MUX40b, to be stored in wherein.Will be by MUX20 from the σ of multiplier 30a ₂α ^{-2 (N-1)}Deliver to block of registers 30c, to move right in the rising edge of next bit clock cycle content thus with each register.

By to the first time iteration all the other in bit clock cycles repeat said process, in adder block 40 with item σ ₁α ^-(N-1)To σ ₈α ^{-8 (N-1)}Addition.Adder 40a at last with the 8th part and, promptly first group 8 evaluation items and (σ ₁α ^-(N-1)+ σ ₂α ^{-2 (N-1)}+ ... + σ ₈α ^{-8 (N-1)}) provide to IOB 50.Should and deliver to and be stored among the R10, and deliver to adder 50a then, therein with itself and σ ₀Addition is to provide the end product of iteration, the i.e. first result of evaluation σ (α for the first time thus ^-(N-1)).The 0 initialization register 40c that while provides in order to MUX40b.

Iteration is to iteration is similar for the first time, only with second group of evaluation item σ for the second time _iα ^{-i (N-2)}Provide to adder block 40 and send register 30c again back to from multiplier 30a.Particularly, first bit clock in the cycle with σ ₁α ^-(N-1)With α ¹Multiply each other, second bit clock in the cycle with σ ₂α ^{-2 (N-1)}With α ²Multiply each other, or the like, so that second group of evaluation item to be provided.By with second group of evaluation item σ _iα ^{-i (N-2)}Addition obtains the second result of evaluation σ (α when iteration finishes in the second time ^-(N-2)).By repeating said process, in N iteration, obtain σ (α for j=N-1 to 0 ^-j).

Register R in first to everybody of iteration for the third time clock cycle ₁To R ₈And R ₉Content be illustrated in the table 1, wherein each row corresponding to everybody clock cycle.

Table 1

Iteration	???????R ₁	??????R ₂	…	???????R ₈	??????????????R ₉
Iteration	???????R ₁	??????R ₂	…	???????R ₈	??????????????R ₉	The 1st	σ ₈α ^-8Nσ ₁α ^-(N-1)????? σ ₇α ^-7(N-1)	σ ₇α ^-7Nσ ₈α ^-8N????? σ ₆α ^-6(N-1)	…	σ ₁α ^-Nσ ₂α ^-2N????? σ ₈α ^-8N	0 σ ₁α ^-(N-1)??????????????? σ ₁α ^-(N-1)+…+σ ₇α ^-7(N-1)
The 2nd	σ ₈α ^-8(N-1)σ ₁α ^-(N-2)σ ₂α ^-2(N-2)????? σ ₇α ^-7(N-2)	σ ₇α ^-7(N-1)σ ₈α ^-8(N-1)σ ₁α ^-(N-2)????? σ ₆α ^-6(N-2)	…	σ ₁α ^-(N-1)σ ₂α ^-2(N-1)σ ₃α ^-3(N-1)????? σ ₈α ^-8(N-1)	0 σ ₁α ^-(N-2)σ ₁α ^-(N-2)+σ ₂α ^-2(N-2)??????????????? σ ₁α ^-(N-2)+…+σ ₇α ^-7(N-2)	The 1st	σ ₈α ^-8Nσ ₁α ^-(N-1)????? σ ₇α ^-7(N-1)	σ ₇α ^-7Nσ ₈α ^-8N????? σ ₆α ^-6(N-1)	…	σ ₁α ^-Nσ ₂α ^-2N????? σ ₈α ^-8N	0 σ ₁α ^-(N-1)??????????????? σ ₁α ^-(N-1)+…+σ ₇α ^-7(N-1)
The 2nd	σ ₈α ^-8(N-1)σ ₁α ^-(N-2)σ ₂α ^-2(N-2)????? σ ₇α ^-7(N-2)	σ ₇α ^-7(N-1)σ ₈α ^-8(N-1)σ ₁α ^-(N-2)????? σ ₆α ^-6(N-2)	…	σ ₁α ^-(N-1)σ ₂α ^-2(N-1)σ ₃α ^-3(N-1)????? σ ₈α ^-8(N-1)		The 3rd	σ ₈α ^-8(N-2)σ ₁α ^-(N-3)σ ₂α ^-2(N-3)????? σ ₇α ^-7(N-3)	σ ₇α ^-7(N-2)σ ₈α ^-8(N-2)σ ₁α ^-(N-3)????? σ ₆α ^-6(N-3)	…	σ ₁α ^-(N-2)σ ₂α ^-2(N-2)σ ₃α ^-3(N-2)????? σ ₈α ^-8(N-2)	0 σ ₁α ^-(N-3)σ ₁α ^-(N-3)+σ ₂α ^-2(N-3)??????????????? σ ₁α ^-(N-3)+…+σ ₇α ^-7(N-3)

Result of evaluation is provided to the wrong piece 55 of determining, wherein, if σ is (α ^-j) be 0, just produce a rub-out signal, be illustrated in the respective symbol r of code word _jMistake has appearred in the place.

Referring to Fig. 2, a kind of calcspar of traditional polynomial evaluation device 2 is provided, this evaluator calculates difference multinomial σ ' (X), i.e. the value of the first derivative of error-locator polynomial σ (X).

When error-locator polynomial is 8 order polynomials that are expressed as follows

σ (X)=σ ₀+ σ ₁X+ σ ₂X ²+ σ ₃X ³+ σ ₄X ⁴+ σ ₅X ⁵+ σ ₆X ⁶+ σ ₇X ⁷+ σ ₈X ⁸During formula (6), then provide differential polynomial and be

σ ' (X)=σ ₁+ 2 σ ₂X ¹+ 3 σ ₃X ²+ 4 σ ₄X ³+ 5 σ ₅X ⁴+ 6 σ ₆X ⁵+ 7 σ 7X ⁶+ 8 σ ₈X ⁷Formula (7A) is owing to two identical numbers in finite field produce 0, and formula (7A) can further be reduced to

σ ' (X)=σ ₁+ σ ₃X ²+ σ ₅X ⁴+ σ ₇X ⁶Formula (7B)

Therefore, for α ^-jCalculating σ ' (X) provides

The structure of revising evaluator is with corresponding with formula (7C), and this makes that evaluator 2 and evaluator 1 are different.Particularly, because differential result of evaluation (result of evaluation that refers to differential polynomial) only comprises the even power of α in formula (7C), root input block 60b and 90a the even power that α is provided respectively, i.e. (α ⁰, α ², α ⁴, α ⁶) and (α ⁰, α ^-2N, α ^-4N, α ^-6N); Block of registers 60c comprises the register of half number of the evaluator 1 shown in Fig. 1; Only that odd power is inferior coefficient, for example σ ₁, σ ₃, σ ₅, σ ₇, offer multiplier 90b; And IOB 80 does not comprise adder, because 0 ordered coefficients (σ ₀) be not included in the differential result of evaluation.Except these, similar among whole computings of this evaluator and Fig. 1.As mentioned above, though the structural similarity of two evaluators, the value of Chu Liing wherein, for example evaluation item and part be different.

Incidentally, can to change power be following form to formula (7C):

From formula (7D) as can be known, the evaluation item of the odd power of error-locator polynomial can be used for the value of the formula of differentiating.

But, according to traditional polynomial evaluation device, be used to ask the evaluator of the value of error-locator polynomial and differential polynomial to provide respectively, cause the complex structure of polynomial evaluation device thus, this causes again being difficult to realizing it by use VLSI (ultra-large integrated) technology.

Therefore, main purpose of the present invention provides and a kind ofly can be simultaneously provides the polynomial evaluation device of result of evaluation for error-locator polynomial and differential polynomial.

According to the present invention, a kind of device that is used in Reed one Solomon decoder is provided, be used for by the j time iteration with α ^-(N-j)Substitution X comes respectively evaluator P (X) and differential polynomial P ' value (X) iteratively, so that j result of evaluation P (α to be provided thus ^-(N-j)) and j subdifferential result of evaluation P ' (α ^-(N-j)), wherein P (X) is a T order polynomial, and T is a positive integer, and P ' is the first derivative of P (X) (X), the integer of j from 1 to N, N is a predetermined positive integer, and α is a finite field gf (2 ^m) in a primitive element, described device comprises:

A fifo buffer with T storage device;

Updating device is used for sequentially first group element of fifo buffer content and finite field is multiplied each other, to provide the j group T evaluation item thus in the j time iteration;

Be used to generate the device of T initial evaluation item;

Be used for selectively T initial evaluation item or T evaluation item of j group being provided to fifo buffer, to be stored in device wherein;

An adder block, be used for determining T evaluation item of j group and, with provide thus j with;

An IOB is used for polynomial 0 ordered coefficients and j and addition, so that j result of evaluation to be provided thus;

An odd term is selected piece, is used for selecting odd number evaluation item the j time iteration in j group evaluation item, so that j cover odd number evaluation item sequentially to be provided thus;

An item correction block is used for the j time iteration in one j correction term and the j cover odd number evaluation item each being multiplied each other, so that j group differential evaluation item to be provided thus; And

An adder block, be used for the j time iteration determine j group differential evaluation item and, so that j differential result of evaluation to be provided thus.

Above-mentioned and other purpose of the present invention will be by becoming more obvious below in conjunction with the accompanying drawing description of preferred embodiments, wherein:

Fig. 1 illustrates the block diagram of traditional polynomial evaluation device of the value that is used for the mistake in computation locator polynomial;

Fig. 2 has described to be used for the block diagram of the polynomial traditional polynomial evaluation device of computing differential;

Fig. 3 shows the block diagram of the polynomial evaluation device of the value that is used for mistake in computation locator polynomial and differential polynomial of the present invention; And

Fig. 4 provides the odd term shown in Fig. 3 to select the more detailed block diagram of piece, a correction block, second adder block and second IOB.

Referring to Fig. 3, the block diagram of polynomial evaluation device 100 of the present invention is provided, it for j=N-1 to 0 according to

Mistake in computation evaluation multinomial σ (X) and differential polynomial σ ' value (X) wherein are made as 8 in order to illustrate with T.

In polynomial evaluation device 100, for j=N-1 to 0 calculating formula (5B) and (7D) iteratively, wherein an iteration is preferably in the system clock cycle and finishes.

Polynomial evaluation device 100 comprises that 120, one items of 110, one multiplexers of an INIT block of the value that is used for the mistake in computation locator polynomial upgrade 140, one first IOB 150 of 130, one first adder block of piece and a mistake is determined piece 155.It is identical for the relevant block of these pieces and the traditional evaluator 1 shown in Fig. 1.Therefore, the process by with reference to figure 1 explanation provides a result of evaluation σ (α from first IOB 150 ^-j) and determine that from mistake piece 155 provides a rub-out signal.

By the process with reference to figure 1 explanation, a renewal piece 130 provides every group of evaluation item for each iteration.8 the evaluation items of this group that provide from item renewal piece 130 are further used in the polynomial value of computing differential.For the polynomial value of computing differential, evaluator 100 also comprises odd term selection piece 200, one item correction block 2 10, one second adder block 170 and one second IOB 180.

At first, select piece 200 at odd term, one group 4 odd number evaluation items of selection from multinomial many 8 the evaluation items of this group of location of mistake (refer to the corresponding evaluation item of odd power item with error-locator polynomial, i.e. σ ₁α ^-j, σ ₃α ^-3j, σ ₅α ^-5j, and σ ₇α ^-7j, j is 0 to (N-1).Should organize odd number evaluation item and send into a correction block 210, wherein with each evaluation item and α ^jMultiply each other, so that one group of differential evaluation item, i.e. σ to be provided ₁α ⁰, σ ₃α ^-2jσ ₅α ^-4jAnd σ ₇α ^-6j,, j is 0 to (N-1), wherein differential evaluation item refer to comprise in the formula (7B) each.4 differential evaluation items that will provide from item correction block 210 are in 170 additions of second adder block, so that a differential result of evaluation σ ' (α to be provided thus ^-j).The differential result of evaluation is stored in second IOB 180, to be used at RS decoder error recovery.

Referring to Fig. 4, show the more detailed block diagram of the part of evaluator 100, its function is by utilizing the evaluation item that upgrades the error-locator polynomial that piece 130 provides from item to obtain the differential result of evaluation.

Odd term selects piece 200 to comprise a multiplexer 200a, and being used for selectively to provide to item correction block 210 from the evaluation item or 0 that item upgrades piece 130 and provides.Particularly, if general-odd number evaluation item provides the input port 0 to MUX200a, then it provides this odd number evaluation item to item correction block 210; Otherwise it will provide to item correction block 210 in 0 of input port 1 input.Therefore, the value that provides from MUX200a in (N-j) inferior iteration is followed successively by σ ₁α ^-j, 0, σ ₃α ^-3j, 0, σ ₅α ^-5j, 0, σ ₇α ^-7jWith 0.

Item correction block 210 comprises a register R ₁₁, be used to store a correction term, one at finite field gf (2 ^m) go up the multiplier 210b of computing, be used to upgrade correction term and one at finite field gf (2 ^m) go up the multiplier 210a of computing, be used for correction term and each odd number evaluation item of selecting piece 200 to provide from odd term are multiplied each other.Correction term refers to α ^j, it will be in multiplier 210a multiplies each other with each odd term of (N-j) inferior iteration, to form suc as formula the differential evaluation item shown in (7D).Because the initial correction item promptly is used for the correction term of iteration for the first time, is α ^-(N-1), use α before the iteration in the first time ^-(N-1)Initialization R11.When the second time, iteration began when finishing (or for the first time iteration), at multiplier 210b with initial correction item and α ^-1Multiply each other and think that iteration provides correction term for the second time, be i.e. α ^-(N-2)Similarly, each iteration is upgraded correction term once.Correction term after the renewal is sent back to R ₁₁To be stored in wherein.

As mentioned above, should organize difference evaluation item and offer adder block 170, wherein these phases be formed a differential result of evaluation σ ' (α ^-j).Adder block 170 to operate in Fig. 1 mode similar respectively to the adder block 40 shown in Fig. 2 or 70.Therefore, when (N-j) inferior iteration finished, the adder 170a that is included in the adder block 170 passed through 4 differential evaluation item σ ₁, σ ₃α ^-2j, σ ₅α ^-4jAnd σ ₇α ^-6jThe phase Calais provides j differential result of evaluation σ ' (α ^-j).R is delivered to and be stored in to this differential result of evaluation ₁₃In, to be used for error correction process.

R ₁₁And R ₁₂Content in table 2, provide.Because provide to adder 170a, R from item correction block 210 0 every a bit clock cycle ₁₂The per 2 bit clock cyclomorphosises of content once.

Though at specific embodiment the present invention is described, person skilled in the art person obviously can make various changes and modification and not break away from defined spirit and scope in the following claim.

Table 2

Iteration	??????R ₁₁	??????????????????R ₁₂
Iteration	??????R ₁₁	??????????????????R ₁₂	The 1st	α	^-(N-1)	0 σ ₁σ ₁σ ₁+σ ₃α ^-2(N-1)σ ₁+σ ₃α ^-2(N-1)σ ₁+σ ₃α ^-2(N-1)+σ ₅α ^-4(N-1)σ ₁+σ ₃α ^-2(N-1)+σ ₅α ^-4(N-1)σ ₁+α ₃α ^-2(N-1)+σ ₅α ^-4(N-1)+σ ₇α ^-6(N-1)
The 2nd	α	^-(N-2)	The 1st	α	^-(N-1)		0 σ ₁σ ₁σ ₁+σ ₃α ^-2(N-2)σ ₁+σ ₃α ^-2(N-2)σ ₁+σ ₃α ^-2(N-2)+σ ₅α ^-4(N-2)σ ₁+σ ₃α ^-2(N-2)+σ ₅α ^-4(N-2)σ ₁+σ ₃α ^-2(N-2)+σ ₅α ^-4(N-2)+σ ₇α ^-6(N-2)

Claims

1, a kind of device that is used in the Read-Solomon decoder is used for passing through α the j time iteration ^-(N-j)Substitution X comes evaluator P (X) and differential polynomial P ' value (X) iteratively, so that j result of evaluation P (α to be provided thus ^-(N-j)) and j differential result of evaluation P ' (α ^-(N-j)), wherein P (X) is a T order polynomial, and T is a positive integer, and P ' is the first derivative of P (X) (X), and j is the integer from 1 to N, N is a predetermined positive, and α is a finite field gf (2 ^m) in a primitive element, described device comprises:

Fifo buffer with T storage arrangement, T are a predetermined positive integer;

Updating device is used for sequentially the content of fifo buffer and first group element of finite field being multiplied each other during the j time iteration, to provide the j group T evaluation item thus;

Be used to generate the device of T initial evaluation item;

Device is used for selectively T initial evaluation item or T evaluation item of j group being provided to fifo buffer, to be stored in wherein;

First adder, be used for determining T evaluation item of j group and, with provide thus j with;

Device is used for polynomial 0 ordered coefficients and j and addition, so that j result of evaluation to be provided thus;

First choice device is used for selecting odd number evaluation item so that j cover odd number evaluation item sequentially to be provided thus from j group evaluation item the j time iteration;

Device, each that is used in that the j time iteration overlapped j correction term and j in the odd number evaluation item multiplies each other, and organizes differential evaluation item so that j to be provided thus; And

Second adder, be used for the j time iteration determine j group differential evaluation item and, so that j differential result of evaluation to be provided thus.

2, the device of claim 1, wherein this generating apparatus comprises:

First input unit is used for sequentially providing T element of confinement; And

Device is used for sequentially first to T multiplication of T element with the multinomial P (X) of the finite field that will provide from first input unit, so that T to be provided individual initially evaluation item thus.

3, the device of claim 1, wherein this updating device comprises:

Second input unit is used for sequentially providing T element in the confinement the j time iteration; And

Device is used for sequentially the content of fifo buffer and T element from the finite field that the 2nd input unit provides being multiplied each other the j time iteration, to provide the j group T evaluation item thus.

4, the device of claim 1, wherein this first adder comprises:

The evaluation Xiang Yuyi value of feedback addition that to provide from updating device is provided one adder, with provide thus a part and or j and;

Second choice device, be used for providing selectively this part of providing from this adder and or 0; And

Storage device, be used to store this part of providing from second choice device and or 0, and with this part with or 0 provide to adder as value of feedback.

5, the device of claim 1, wherein this first choice device comprises a multiplexer, is used for providing selectively an odd number evaluation item or 0.

6, the device of claim 1, wherein this multiplier comprises;

The first memory device is used to store a correction term;

The device, be used to each iteration to upgrade this correction term, and the correction term after will upgrading provide to the first memory device to be stored in wherein; And

Device is used for multiplying each other being stored in the correction term of first storage device and every of j group odd number evaluation item, so that j group differential evaluation item to be provided thus.

7, the device of claim 6, wherein this updating device comprises and being used for α ^-1The device that multiplies each other with the correction term that is stored in first storage device.

8, the device of claim 6, wherein this first memory device α ^N-1Initialization and j correction term is α ^(N-j)

9, the device of claim 1, wherein this second adder comprises:

The differential evaluation Xiang Yuyi value of feedback addition that to provide from multiplier is provided one adder, with provide thus a part and or j differential result of evaluation;

Choice device, be used for providing selectively this part of providing from this adder and or 0; And

Storage device, be used to store the part that provides from this choice device and or 0, and with this part with or 0 provide to adder as value of feedback.

10, the device of claim 2 is α from T the element that first input unit provides wherein ^{I, i}For from 1 to T integer.

11, the device of claim 3 is α from T the element that second input unit provides wherein ^{-1N, i}For from 1 to T integer.

12, the device of claim 1, wherein this multinomial P (X) is an error-locator polynomial of T time.

13, the device of claim 1 also comprises being used for determining whether this result of evaluation equals 0, so that the device of a rub-out signal to be provided thus.

14, a kind of device that is used in the Read-Solomon decoder is used for passing through α the j time iteration ^-(N-j)Substitution x comes evaluator P (X) and differential polynomial P ' value (X) iteratively, so that j result of evaluation P (α to be provided thus ^-(N-j)) and j differential result of evaluation P ' (α ^-(N-j)), wherein P (X) is a T order polynomial, and T is a positive integer, and P ' is the first derivative of P (X) (X), and j is the integer from 1 to N, N is a predetermined positive integer, and α is a finite field gf (2 ^m) in a primitive element, described device comprises:

Fifo buffer with T storage arrangement, T are a predetermined positive integer;

Device is used for by sequentially the initial evaluation item of T being provided to fifo buffer to come with this T initial this fifo buffer of evaluation item initialization;

Updating device is used for sequentially the content and the element of the T in the finite field of fifo buffer being multiplied each other the j time iteration, to provide the j group T evaluation item thus;

Device is used for the j time iteration T evaluation item of j group sequentially being provided to fifo buffer, to be stored in wherein;

First adder, be used for determining T evaluation of j group and, with provide thus j with;

Device is used for 0 ordered coefficients and j and addition with multinomial P (X), so that j result of evaluation to be provided thus;

First choice device is used for selecting odd number evaluation item the j time iteration from j group evaluation item, so that j cover odd number evaluation item sequentially to be provided thus;

15, the device of claim 14, wherein this updating device comprises:

First input unit is used for sequentially providing T element in the confinement the j time iteration; And

Device is used for sequentially the content of fifo buffer and T element from the finite field that first input unit provides being multiplied each other the j time iteration, to provide the j group T evaluation item thus.

16, the device of claim 14, wherein this first adder comprises:

Second choice device, be used for providing selectively the part that provides from this adder and or 0; And

Storage arrangement, be used to store the part that provides from second choice device and or 0, and with this part with or 0 provide to adder as value of feedback.

17, the device of claim 14, wherein this second adder comprises:

Choice device, be used for providing selectively this part of providing by this adder and or 0; And

Storage device is used to store the part that provides from this choice device and or 0 and will part and or 0 provide to adder as value of feedback.

18, the device of claim 14, wherein this multinomial P (X) is an error-locator polynomial of T time.

19, the device of claim 14 also comprises being used for determining whether this result of evaluation equals 0, so that the device of a rub-out signal to be provided thus.