CN1097882C - Read-solomon decoder and decoding method - Google Patents

Abstract

The present invention relates to a Reed-Solomen decoder and a decoding method. The RS decoder comprises a polynomial arithmetic device for calculating the value of a corrector and establishing a corrector polynomial according to the data of the receiving deleting position, a generator for generating the root of an initial error locator polynomial and control signals for representing the root according to the deleting information, and a first polynomial spreader and a second polynomial spreader in a series structure, wherein the first polynomial spreader and the second polynomial spreader respectively adopt the root, the control signals and the value of the corrector to spread the initial error locator polynomial and the improved corrector polynomial. The required number of a multiplier can be calculated by a minimized polynomial according to the present invention, so the circuit structure of the RS decoder is simplified.

Description

Read Solomon decoder and coding/decoding method

Invention field

The present invention relates to the error correction decoding field, particularly Read-solomon (Reed-Solomon, RS) decoder and coding/decoding method.

Background technology

In the digital communication system that adopts high definition TV (HDTV), digital universal disc (DVD) or mini disk (CD), the main RS decoder with outstanding error correcting capability that adopts is corrected the mistake that produces in the transmission.Yet the structure of RS decoder is very complicated.Usually, with the RS coded representation be RS (N, I).An information block is made of N symbol.In these symbols, I symbolic representation a piece of news, remaining N-I symbolic representation check code.Each symbol is made up of m position.

Fig. 1 is the block diagram that adopts the conventional RS decoder that improves Euclidean algorithm.This RS decoder is disclosed in being shown in " adopt the VLSI of the pipeline system RS decoder that shrinks matrix to design (" On the VLSI Design of PipelineReed-Solomon Decoder Using Systolic Arrays "; IEEE Tran.Comput; Vol37; OCT.1988, pp1273-1280) " literary composition by H.M.Shao and I.S.Reel of U.S.'s electronics and the 1273rd to 1280 page of number the 37th volume computer branch of The Institution of Electrical Engineers proceedings in October, 1998.

In Fig. 1, according to the root α of initial error positioning multinomial of the delete position information calculations of input ^-k, be imported into the first and second multinomial expanders 106 and 108.Deletion has meant mistake, and its position obtains from receive data, and mistake means mistake, and its position and size are known.

In the parallel extended method that document [1] is provided, when the number of errors that can correct is t,, make the first multinomial expander 106 must calculate 2t+1 coefficient because initial error positioning multinomial has number 2t time, so the 2t+1 register of m position (8) must exist, as shown in Figure 2.And, need 2t+1 multiplier and 2t+1 adder to expand initial error positioning multinomial.

Because of having 2t-1 number, improved syndrome multinomial must calculate 2t coefficient owing to be used to produce the polynomial second multinomial expander 108 of improved syndrome, therefore as shown in Figure 3, need be used to calculate and store 2t register, a 2t multiplier and 2t adder of 2t coefficient.The syndrome that each register is endowed a calculated in advance is with as initial value.The computing of the iterative equation shown in the equation 7 is corresponding to carrying out according to the syndrome of clock signal (CLK) input.Like this, after 2t clock time, it is obtained to improve the syndrome multinomial coefficient accordingly.

Therefore, in the RS decoder that uses general parallel extended method, the number of multipliers that is used for evaluator be correction in computed improved in the sum of the process institute use multiplier of multinomial and initial error positioning multinomial, promptly 2t+2t+1 (=4t+1).

Because the computing used in the RS decoder is carried out on finite field, so multiplier is not a general decimal multiplier but a Galois field multiplier.Like this, the structure of Galois field multiplier is just complicated.Because Galois field multiplier needs a large amount of gate circuits to realize the RS decoder integrated circuit, so, when the number of errors that can correct increases, increased complexity widely for method evaluator by parallel expansion.

Summary of the invention

For addressing the above problem, an object of the present invention is to provide a kind of RS decoder, the number of errors that this decoder is not considered to correct using improved Euclidean algorithm to adopt the multiplier of minimum number in the process of evaluator.

Another object of the present invention provides a kind of RS coding/decoding method, and this method is using improved Euclidean algorithm to use the serial expansion in the process of evaluator.

Like this, for reaching first purpose, the invention provides a kind of Reed-Solomon (RS) decoder, include the improved Euclidean algorithm processor of searching a bit-error locations and size by syndrome value, this decoder comprises: polynomial arithmetic unit is used for calculating syndrome value and structural correction submultinomial from receiving data; Generator is used for producing a root for initial error positioning multinomial and being the control signal that initial error positioning multinomial produces a new root of expression when new deletion information is transfused to from the deletion information of received data; The first multinomial expander with serial expansion structure is used to use the root of initial error positioning multinomial and control signal to expand initial error positioning multinomial and provide spreading result as processor; And the second multinomial expander with serial expansion structure, be used to use the root of syndrome value and initial error positioning multinomial and control signal to expand improved syndrome multinomial and provide spreading result as processor.

For reaching second purpose, the invention provides a kind of RS coding/decoding method that uses improved Euclidean algorithm, comprise the steps: that (a) calculates syndrome value from receive data; (b) from the deletion information that receives data, produce a root and be that initial error positioning multinomial produces a control signal of representing new root corresponding to new deletion information for the initial difference locator polynomial; (c) use the root of initial error positioning multinomial and control signal to expand the initial error locator; (d). use the root and the control signal of syndrome value, initial error positioning multinomial to expand improved syndrome multinomial; And (e) use improved Euclidean algorithm, and use expansion initial error positioning multinomial and improved syndrome multinomial, calculate and be included in position and the size that receives the mistake in the data.

Description of drawings

Above-mentioned purpose of the present invention and advantage will be more obvious after the reference accompanying drawing is elaborated, in the accompanying drawing:

Fig. 1 is the block diagram of general RS decoder;

Fig. 2 is a circuit block diagram with first multinomial expander of general parallel expansion structure shown in Figure 1;

Fig. 3 is a circuit block diagram with second multinomial expander of general parallel expansion structure shown in Figure 1;

Fig. 4 is the RS decoder side block diagram by the embodiment of the invention;

Fig. 5 is the circuit block diagram with first multinomial expander of serial expansion structure provided by the present invention shown in Figure 4; And

Fig. 6 is the circuit block diagram with second multinomial expander of serial expansion structure provided by the present invention shown in Figure 4.

Embodiment

Fig. 4 has illustrated according to RS decoder side block diagram of the present invention.Among Fig. 4, as a α ^-kGenerator 202 produces the root α of an initial error positioning multinomial from the delete position information of input ^-kWith this α of explanation ^-kWhen being a control signal (CON) that is relevant to the root of new deletion information, 206 utilizations of the first multinomial expander have been adopted from α ^kThe α of generator 202 outputs ^-kAnd the serial extended method of control signal (CON) is expanded initial error positioning multinomial (Г (x)).

First polynomial arithmetic unit 204 uses syndrome multinomial (S (x)) to calculate the syndrome value of received data.The required syndrome of decoded packet sign indicating number is defined by equation 1: " equation 1 "

S _k＝S(α ^k)＝γ(α ^k)， k＝0，1，…，2t-1

Wherein, when not producing mistake, use α ^-kReplace syndrome multinomial (S (x)) and use α ^-kReplace check polynomial (r (x)) to obtain " 0 ".

As shown in Figure 2, when v mistake produced, syndrome value can only be come out with the mistake polynomial computation of equation 3." equation 2 " $\mathrm{\&theta;}\left(x\right)={\mathrm{\&theta;}}_0{x}^{j_0}+{\mathrm{\&theta;}}_1{x}^{{\mathrm{<figure-callout\; id="1"\; label="j"\; filenames="C9812095200152.png"\; state="\{\{state\}\}">j</figure-callout>}}_1}+...+{\mathrm{\&theta;}}_V{x}^{j_V}$ " equation 3 "

S _k＝S(α ^k)＝γ(α ^k)＝c(α ^k)+θ(α ^k)＝θ(α ^k)

In a word, using the calculated syndrome value to come in the middle of all methods of the size of tick up and position the method for extensive use to be to use improved Euclidean algorithm.Because the improvement Euclidean algorithm that is used for improvement Euclidean algorithm processor 210 of the present invention is provided in document [1], it is described in detail in this and saves.In order to use improved Euclidean algorithm to carry out decoding, institute's calculated syndrome value must be expressed as polynomial coefficient.Equation 4 be a 2t-1 number be the syndrome multinomial of coefficient with the syndrome value." equation 4 "

S(x)＝S ₀+S ₁x+S ₂x ²+…+S _2t-1x ^2t-1

The second multinomial expander 208 uses by 204 calculated syndrome multinomials of first polynomial arithmetic unit (S (x)), from α ^-kThe output α of generator 2 02 ^-kAnd control signal (CON) is found the solution the solving equation of being represented by equation 5 and is expanded improved syndrome multinomial (T (x))." equation 5 "

T(x)＝S(x) Г(x)mod X ^2t

Wherein, S (x) and Г (x) represent a syndrome multinomial and an initial error positioning multinomial respectively.At this, initial error positioning multinomial Г (x) uses α by the first multinomial expander 2 06 ^-kThe α that generator 202 produces ^-kAnd control signal (CON) is expanded.Because Г (x) is the α that is calculated by input delete position information by equation 6 ^-kRepresent, thus in each input delete position information improved syndrome multinomial the computing of equation 7 obtains by for example repeating." equation 6 "

Г(x)＝∏(x-α ^-k)

Wherein, ∏ represents to multiply each other, and the root of initial error positioning multinomial Г (x) is represented the wrong position that produces.That is, if α ^-kBe root, represent that then mistake is created on central (k+1) the individual coded word of received code word.In (k+1) individual coded word, a code signing corresponding to k is arranged." equation 7 "

Iterative equation: S (x) (x-α ^-k)=xS (x)-α ^-kS (x)

The second and the 3rd polynomial arithmetic unit 212 and 214 calculates an error estimator multinomial ω (x) and an error-locator polynomial σ (x), and they are delivered to divider 216.Divider 216 calculates corresponding to α by equation 8 ^-kThe mistake size." equation 8 " ${\mathrm{\&theta;}}_k=-\frac{\mathrm{\&omega;}\left({\mathrm{\&alpha;}}^{-k}\right)}{{\mathrm{\&sigma;}}^{\&prime;}\left({\mathrm{\&alpha;}}^{-k}\right)}$

Only select output with door 218 corresponding to the divider 216 of the root of the error-locator polynomial (σ (x)) that is calculated by selected the 3rd polynomial arithmetic unit 214.Adder 222 comprises an XOR gate, this XOR gate be used to carry out the reception data that postponed by delayer 220 and by and the mistake size exported of door 218 between xor operation.Decoded data are by adder 222 outputs.At this, (c (x)) represents improved data polynomial.

The RS decoder of the improved Euclidean algorithm of use provided by the present invention is in the middle of polynomial computation, the circuit diagram of the first multinomial expander 206 that the serial extended method that adopts is realized is shown among Fig. 5, and the circuit diagram of the second multinomial expander 208 is shown in Fig. 6.

When the symbol error number that can correct is t, the first multinomial expander 206 that is used to obtain initial error positioning multinomial comprises shift register 232, single multiplier 234, adder 238 and a logical circuit (with door 236) that is used to store 2t+1 coefficient, as shown in Figure 5.Be used to obtain to improve the polynomial second multinomial expander 208 of syndrome comprise the shift register 242 that is used to store 2t coefficient, multiplier 244, adder 248 and with door 246, as shown in Figure 6.

The initial value of the shift register 232 of the first multinomial expander shown in Figure 5 is with minimum coefficient lambda ₀Initialization is made as " 1 " and replacement coefficient (reset coefficient) is made as " 0 ".Adder 238 and multiplier 234 are the operators in the finite field.Multiplier 234 has the single step pipeline organization, can carry out high speed operation like this.Adder 238 comprises an XOR gate.Owing to being different from the high reps computing, the minimum number of times computing of initial error positioning multinomial used and door 236.

That is, in the serial extended method, as α corresponding to new error message ^-kDuring input, owing to imported new α ^-kValue, an iterative computation end and next iterative computation begin, must at first be carried out as the calculating of equation 10 and so on, and the calculating of replacement equation 9.At α corresponding to next new deletion information ^-kBefore being transfused to, iteration is carried out the computing as equation 9." equation 9 "

S _i=S _iα ^-k+ S _I-1I=1,2 ..., 2t " equation 10 "

S _i＝S _iα ^-k i＝0

Wherein, the new α of expression ^-kThe control signal that value is transfused to (CON) is as shown in Figure 4 by α ^-kGenerator 202 produces, with storage α ^-kValue and it is exported one by one.In a clock cycle with α ^-kThe control signal (CON) that keeps the initial error location generator 202 generation logics " low " of a period of time is corresponding to the α of next deletion information ^-kValue is sent out, and represents this α ^-kValue is a new α ^-kThe first multinomial expander 206 uses the control signal (CON) of logic " low " to begin new α ^-kSerial expansion.

That is, multiplier 234 will be stored in the coefficient in the shift register 232 and the α of input ^-kMultiply each other.When control signal (CON) is logic " height ", adder 238 with the output of multiplier 234 be added to from the previous coefficient of door 236 outputs shown in equation 9 on, and because α ^-kBe a root, when control signal (CON) is logic " low ", transmit the output of multiplier 234 shown in equation 10 corresponding to new deletion information.The output of multiplier 234 is fed to shift register 232.

When all are stored in as shown in Figure 4 α ^-kα in the generator 202 ^-kAfter value is expanded, initial error positioning multinomial α ^-kГ (x) is obtained.α when storage ^-kThe number of value is during less than 2t, α ^-kGenerator 202 is filled to " 0 " with remaining information.Like this, when " 0 " was imported in the first multinomial expander 206, the value of the memory cell of shift register 232 was not changed.

By in the physical circuit of the second multinomial expander shown in Figure 6, the syndrome multinomial that from first polynomial arithmetic unit 204 shown in Figure 4, calculates, produce the basic conception of improved syndrome multinomial process, be the same with the process of calculating initial error positioning multinomial shown in Figure 5.That is, the initial value of the respective memory unit in shift register shown in Figure 6 242, when being filled to be by 204 calculated syndrome values of first polynomial arithmetic unit, improved syndrome multinomial coefficient can be obtained.

When the serial extended method was used in the one the second multinomial expanders 206 and 208, multiplier can be reduced to one and do not consider the number of errors that can correct in each expander.Simultaneously, need the 2t clock time to specify α to finish ^-kMultiplication.

Therefore, in adopting the one the second multinomial expanders 106 and 108 of general parallel extended method, the required processing time only is the 2t clock time.And in the one the second multinomial expanders 206 and 208 of the present invention, there is increase trend the computing relay time.That is, the computing relay time in the first multinomial expander 206 is 2t* (2t+1).The computing relay time when iterative equation is performed on a maximum 2t syndrome in the second multinomial expander 208 is 2t*2t.This trend can use quick clock to compensate.

That is, do not conflict mutually again, before the syndrome of next one grouping is calculated, must use all previously stored α with the RS grouping of continuous input for correct errors ^-kCarry out expansion.When the length of the coded word of RS grouping is N,, must increase than symbol frequency (2t) by the frequency of the first and second multinomial expanders 206 and 208 employed clock CLK1 ²Conflict between adjacent packets does not doubly take place in/N to carry out polynomial computation.This multiple value changes to some extent according to given RS sign indicating number, promptly about 2 to 4.For carrying out multiplication according to this frequency, the multiplier that uses among the present invention is the single step pipeline-type.

Table 1 has been listed provided by the present inventionly to has the one the second multinomial expanders 206 of serial structure and 208 number of multipliers and processing time.

Table 1

	General structure	According to structure of the present invention
			Number of multipliers	4t+1	2
Processing time	2t+2t	(2t) 2+(2t+1)*(2t)

According to the present invention, owing in the RS decoder that uses improved Euclidean algorithm, minimized the desired number of multipliers of evaluator, and simplified the very lagre scale integrated circuit (VLSIC) structure of RS decoder widely, correspondingly, expense reduces widely.

Claims (16)

1. Reed-Solomon, i.e. RS, decoder includes the improvement Euclidean algorithm processor that is used for by syndrome value tick up position and size, and this decoder comprises:

Polynomial arithmetic unit is used for calculating syndrome value and structural correction submultinomial from receiving data;

Generator is used for producing a root for initial error positioning multinomial and being that initial error positioning multinomial produces a control signal of representing new root when new deletion information is transfused to from the deletion information that receives data;

The first multinomial expander, it has the serial expansion structure, is used to use the root of described initial error positioning multinomial and control signal expansion initial error positioning multinomial and the result is provided to described processor; And

The second multinomial expander, it has the serial expansion structure, is used to use the root of described syndrome value, initial error positioning multinomial and control signal to expand improved syndrome multinomial and the result is provided to described processor.

2. RS decoder as claimed in claim 1, wherein the first multinomial expander comprises:

First shift register, it comprises the memory cell that is used for by 2t+1 coefficient of clock signal storage, wherein t is the number of errors that can correct;

Single first multiplier is used for the output of described first shift register and the root of described initial error positioning multinomial are multiplied each other;

First logical circuit is used for according to expression the control signal of the new root of the initial error positioning multinomial of new deletion information not being exported and is stored in the previous coefficient of described first shift register but exports previous coefficient in other cases; And

First adder is used for the output of described first logical circuit is added to the output of described first multiplier and feeds back to described first shift register.

3. RS decoder as claimed in claim 2, wherein said first multiplier has a single step pipeline organization.

4. RS decoder as claimed in claim 2, wherein said reception data are made up of the grouping that comprises N symbol, and when the number of errors that can correct was t, the frequency ratio symbol frequency of clock signal increased (2t) ²/ N doubly.

5. RS decoder as claimed in claim 2, wherein said first logical circuit comprise be used for to the previous coefficient that is stored in described first shift register and control signal carry out with computing comprise an XOR gate with door and described first adder.

6. RS decoder as claimed in claim 2 wherein is set to " 1 " and remaining coefficient is set as " 0 " at minimum coefficient described in the initial value of described first shift register.

7. RS decoder as claimed in claim 1, the wherein said second multinomial expander comprises:

Second shift register, it comprises the memory cell by 2t coefficient of clock signal storage;

Single second multiplier is used for multiplying each other being stored in the output of described second shift register and the root of described initial error positioning multinomial;

Second logical circuit is used for according to expression the control signal of the new root of the initial error positioning multinomial of new deletion information not being exported and is stored in the previous coefficient of described second shift register but exports previous coefficient in other cases; And

Second adder is used for the output of described second logical circuit is added to the output of described second multiplier and feeds back to described second shift register.

8. RS decoder as claimed in claim, wherein second multiplier has a single step pipeline organization.

9. as RS decoder as described in the claim 7, wherein said reception data are made up of the grouping that comprises N symbol, and when the number of errors that can correct was t, the frequency ratio symbol frequency of clock signal increased (2t) ²/ N doubly.

10. RS decoder as claimed in claim 7, wherein said second logical circuit comprise be used for to the previous coefficient of described second shift register output and control signal carry out with computing comprise an XOR gate with door and described second adder.

11. as RS decoder as described in the claim 7, the initial value of wherein said second shift register is set to the calculated syndrome value by described polynomial arithmetic unit institute.

12. a RS coding/decoding method that uses improved Euclidean algorithm, it comprises the steps:

(a) from receive data, calculate syndrome value;

(b) from the deletion information of described reception data, produce a root and be the control signal that initial error positioning multinomial produces a new root of expression corresponding to new deletion information for initial error positioning multinomial;

(c) use the root and the control signal of described initial error positioning multinomial to expand described initial error positioning multinomial;

(d) use the root and the control signal of syndrome value, initial error positioning multinomial to expand improved syndrome multinomial; And

(e) use improved Euclidean algorithm, use the initial error positioning multinomial of expansion and size and the position that improved syndrome polynomial computation receives the mistake that comprises in the data.

13. method as claimed in claim 12, wherein step (c) comprises the steps:

(c1) read coefficient from first shift register of 2t+1 coefficient of storage, wherein t is the number of errors that can correct, the coefficient read and the root of initial error positioning multinomial is multiplied each other, and export product; And

(c2) in described all products, minimum coefficient and the described result that obtains that multiplies each other are fed back to described first shift register and all the other results are fed back to described first shift register with current product with previous coefficient result that addition obtains.

14. method as claimed in claim 13 wherein is set as " 1 " and all the other coefficients are set as " 0 " at minimum coefficient described in the initial value of described first shift register.

15. as method as described in the claim 12, wherein step (d) comprises the steps:

(d1) from second shift register of 2t coefficient of storage, read coefficient, the coefficient read and the root of initial error positioning multinomial are multiplied each other, and export product; And

(d2) in described all products, minimum coefficient and the described result that obtains that multiplies each other are fed back to described second shift register and all the other results are fed back to described second shift register with current product with previous coefficient result that addition obtains.

16. as method as described in the claim 15, the initial value of wherein said second shift register is set as the calculated syndrome value by step (a) institute.

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