CN110007965A - Assembly line polynomial computation method and device - Google Patents
Assembly line polynomial computation method and device Download PDFInfo
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- CN110007965A CN110007965A CN201910173502.7A CN201910173502A CN110007965A CN 110007965 A CN110007965 A CN 110007965A CN 201910173502 A CN201910173502 A CN 201910173502A CN 110007965 A CN110007965 A CN 110007965A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
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Abstract
The present invention provides a kind of assembly line polynomial computation method and device, includes the following steps: step 1, to multinomial Pn(x) it is converted；Step 2, transformed multinomial P is calculatedn(x) and calculated result is exported.Compared with prior art, beneficial effects of the present invention are as follows: the form of combination multiplication is reappeared using equivalence transformation original multinomial, to keep polynomial computational solution precision controllable, the complexity of time and space are reduced, is conducive to the whole size for reducing polynomial computation.
Description
Technical field
The present invention relates to digital circuit technique field, especially a kind of assembly line polynomial computation method and device.
Background technique
General multinomial is such as: Pn(x)=a0+a1x+a2x2+…+anxnCalculating for common circuit realization be all first to count
Calculate a1Then x calculates a2x2, until by anxnIt calculates, finally results added is got up, need to take a substantial amount of time
Calculate aixiIt goes to save intermediate calculated result with circuit resource.
The prior art, Chinese invention patent " for calculating the device of associated polynomial in RS decoder " (application number:
201410119903.1) a kind of device calculated in RS decoder for syndrome is disclosed, which has smaller companion
With formula computing relay and higher decoding rate, while the device is not necessary to preposition deinterleaver.In order to realize above-mentioned mesh
, disclose a kind of method converted by syndrome calculation formula so that syndrome computing device supports multidiameter delay input.
Syndrome computing device of the present invention includes the Data Input Interface and 2t basic unit of a multidiameter delay.Each
Basic unit includes the galois field constant multiplier that several are connected with multidiameter delay input, a Galois field addition
Device, a galois field constant multiplier being connected with register, several registers and several multiplexers and demultiplexing
Device.
The circuit resource that the prior art can occupy is more, and the required polynomial clock periodicity of processing is also very big.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide one kind rapidly and efficiently, uses less circuitry resource
Assembly line polynomial computation method and device.
In order to solve the above technical problems, the present invention provides a kind of polynomial computation method, include the following steps:
Step 1, to multinomial Pn(x) it is converted；
Step 2, transformed multinomial P is calculatedn(x) and calculated result is exported.
Preferably, in step 1, by multinomial Pn(x)=a0+a1x+a2x2+…+anxnIt is transformed into Pn(x)=((k0x+b0)x
+b1)x+b2+…；
In formula, an=k0, an-1=b0, a2=bn-3, a1=bn-2, a0=bn-1, anFor known coefficient, n is positive integer.
Preferably, step 2 includes:
Step 2.1, k is obtainedn-1The value of x；
Step 2.2, k is obtainedn-1x+bn-1Value, and be denoted as kn；
Step 2.3, n value adds 1, and return step 2.1, until obtaining kn-1x+bn-1Value；
Step 2.4, k is exportedn-1x+bn-1Value.
A kind of assembly line multinomial circuit device, comprising:
Pipeline controller, for multinomial Pn(x) equivalence transformation is carried out, and controls the defeated of coefficient in multinomial engine
Enter and selects, output as a result；Wherein
By Pn(x)=a0+a1x+a2x2+…+anxnIt is transformed into Pn(x)=((k0x+b0)x+b1)x+b2+…；
In formula, an=k0, an-1=b0, a2=bn-3, a1=bn-2, a0=bn-1, anFor known coefficient, n is positive integer；
Multinomial engine is used for evaluator Pn(x) and result is exported.
Preferably, multinomial engine includes:
Multiplier, for obtaining kn-1The value of x；
Adder, for obtaining kn-1x+bn-1Value；
Pipeline register, for recording kn-1X and kn-1x+bn-1Value.
Preferably, multinomial engine further includes reduction device, the precision of the value for guaranteeing to calculate.
Preferably, multinomial engine further includes selector, for controlling kn-1x+bn-1Value output.
It preferably, further include memory, for storing polynomial coefficient an。
Preferably, memory is otp memory, MTP memory, flash storage or DRAM memory.
It preferably, further include result register, for saving final polynomial result.
Compared with prior art, beneficial effects of the present invention are as follows: reappearing combination multiplication using equivalence transformation original multinomial
Form reduce the complexity of time and space to keep polynomial computational solution precision controllable, be conducive to reduce multinomial
The whole size of calculating.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature mesh of the invention
And advantage will become more apparent upon.
Fig. 1 is the polynomial computation architecture diagram of pipeline organization；
Fig. 2 is multinomial engine unit structure chart；
Fig. 3 is Pipeline controller cellular construction figure.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
As shown in FIG. 1 to 3, the present invention is by multinomial Pn(x)=a0+a1x+a2x2+…+anxn, use equivalence transformation weight
Now combine the form P of multiplicationn(x)=((k0x+b0)x+b1)x+b2+ ... so multinomial coefficient, there is following relationship an=k0, an-1
=b0, a2=bn-3, a1=bn-2, a0=bn-1。
Then evaluator Pn(x)=((k0x+b0)x+b1)x+b2+ ..., the circuit device includes:
Memory, for storing multinomial coefficient K and B.
Multinomial engine uses the mode evaluator P of assembly linen(x)。
Pipeline controller, for controlling the input and selection of coefficient in multinomial engine, output as a result.
Result register, for saving final polynomial result.
Multinomial engine includes: multiplier, pipeline register, adder, reduction device and selector.Multiplier is used for
Calculate k0With the value of x.Adder is for calculating k0x+b0, its result is remembered into k1.So there is the first level production line to calculate k0x+b0,
Second level production line calculates k1x+b1, third level production line calculating k2x+b2, N rank multinomial can be calculated by N level production line
Final result.Reduction device is for guaranteeing kiPrecision, wherein i > 0.
Pipeline controller includes: output multinomial coefficient and X, and selection control signal S is for controlling k0And ki's
Selection.And when control will export entire polynomial calculated value.
Pipeline controller can read multinomial coefficient stored in memory by reading interface.Memory can be with
The otp memory for supporting single to rewrite, is also possible to the MTP memory for supporting repeatedly to rewrite or flash storage or DRAM is deposited
Reservoir.
While multiplier does multiplication, for saving the coefficient B obtained from Pipeline controller, bit wide > 1.
Multiplier output valve is added with the value of pipeline register, the addition comprising signed number, data format includes
Integer or floating number or fixed-point number.
Result will be done to certain processing, comprising rounding up, Overflow handling according to desired required precision.
Embodiment
Multinomial P of the inventionn(x)=((k0x+b0)x+b1)x+b2+ ..., it include multinomial engine, Pipeline control
Device and memory and result register.For ease of description, n=4, the data bit width 32 of coefficient and x are chosen in this implementation.
Pipeline controller controls signal by the memory read port of Read, Addr, Len and ReadDat, will be stored in
K in memory0, b0, b1, b2, b3It is read in register file with x, x..Bn.N accumulator can be according to the value of N by coefficient and X
It exports and is calculated to multinomial engine, form the input of flowing water line computation data.
Multinomial engine can pass through following step:
1) k is calculated0×x+b0Value, then reduction obtains intermediate result k1；
2) it will continue to calculate k after selector selection1×x+b1, then reduction obtains intermediate result k2；
3) it will continue to calculate k after selector selection2×x+b2, then reduction obtains intermediate result k3；
4) it will continue to calculate k after selector selection3×x+b3, then reduction obtains intermediate result k4；
5) condition for meeting output, by k4It is output in result register.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (10)
1. a kind of polynomial computation method, which comprises the steps of:
Step 1, to multinomial Pn(x) it is converted；
Step 2, transformed multinomial P is calculatedn(x) and calculated result is exported.
2. polynomial computation method according to claim 1, which is characterized in that in step 1, by multinomial Pn(x)=a0+
a1x+a2x2+…+anxnIt is transformed into Pn(x)=((k0x+b0)x+b1)x+b2+…；
In formula, an=k0, an-1=b0, a2=bn-3, a1=bn-2, a0=bn-1, anFor known coefficient, n is positive integer.
3. polynomial computation method according to claim 2, which is characterized in that step 2 includes:
Step 2.1, k is obtainedn-1The value of x；
Step 2.2, k is obtainedn-1x+bn-1Value, and be denoted as kn；
Step 2.3, n value adds 1, and return step 2.1, until obtaining kn-1x+bn-1Value；
Step 2.4, k is exportedn-1x+bn-1Value.
4. a kind of assembly line multinomial circuit device characterized by comprising
Pipeline controller, for multinomial Pn(x) carry out equivalence transformation, and control in multinomial engine the input of coefficient and
Selection, output as a result；Wherein
By Pn(x)=a0+a1x+a2x2+…+anxnIt is transformed into Pn(x)=((k0x+b0)x+b1)x+b2+…；
In formula, an=k0, an-1=b0, a2=bn-3, a1=bn-2, a0=bn-1, anFor known coefficient, n is positive integer；
Multinomial engine is used for evaluator Pn(x) and result is exported.
5. assembly line multinomial circuit device according to claim 4, which is characterized in that multinomial engine includes:
Multiplier, for obtaining kn-1The value of x；
Adder, for obtaining kn-1x+bn-1Value；
Pipeline register, for recording kn-1X and kn-1x+bn-1Value.
6. assembly line multinomial circuit device according to claim 5, which is characterized in that multinomial engine further includes reduction
Device, the precision of the value for guaranteeing to calculate.
7. assembly line multinomial circuit device according to claim 5 or 6, which is characterized in that multinomial engine further includes
Selector, for controlling kn-1x+bn-1Value output.
8. assembly line multinomial circuit device according to claim 4, which is characterized in that further include memory, for depositing
Store up polynomial coefficient an。
9. assembly line multinomial circuit device according to claim 8, which is characterized in that memory be otp memory,
MTP memory, flash storage or DRAM memory.
10. assembly line multinomial circuit device according to claim 4, which is characterized in that further include result register, use
In the final polynomial result of preservation.
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| CN201910173502.7A CN110007965A (en) | 2019-03-07 | 2019-03-07 | Assembly line polynomial computation method and device |
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| CN201910173502.7A CN110007965A (en) | 2019-03-07 | 2019-03-07 | Assembly line polynomial computation method and device |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1250980A (en) * | 1998-10-14 | 2000-04-19 | 三星电子株式会社 | Read-solomon decoder and decoding method |
| US20030046637A1 (en) * | 2001-08-21 | 2003-03-06 | Equator Technologies, Inc. | Even-load software reed-solomon decoder |
| CN102221990A (en) * | 2011-05-26 | 2011-10-19 | 山东大学 | Instruction optimization method and processor for AES (Advanced Encryption Standard) symmetric encryption algorithm |
| CN102684709A (en) * | 2012-05-10 | 2012-09-19 | 天津大学 | Decoding method and decoding device thereof |
| US20150012578A1 (en) * | 2006-07-25 | 2015-01-08 | Vivante Corporation | Systems and methods for computing mathematical functions |
| CN104639282A (en) * | 2013-11-14 | 2015-05-20 | 杭州海康威视数字技术股份有限公司 | RS (reed Solomon) decoding method and device thereof in communication system |
-
2019
- 2019-03-07 CN CN201910173502.7A patent/CN110007965A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1250980A (en) * | 1998-10-14 | 2000-04-19 | 三星电子株式会社 | Read-solomon decoder and decoding method |
| US20030046637A1 (en) * | 2001-08-21 | 2003-03-06 | Equator Technologies, Inc. | Even-load software reed-solomon decoder |
| US20150012578A1 (en) * | 2006-07-25 | 2015-01-08 | Vivante Corporation | Systems and methods for computing mathematical functions |
| CN102221990A (en) * | 2011-05-26 | 2011-10-19 | 山东大学 | Instruction optimization method and processor for AES (Advanced Encryption Standard) symmetric encryption algorithm |
| CN102684709A (en) * | 2012-05-10 | 2012-09-19 | 天津大学 | Decoding method and decoding device thereof |
| CN104639282A (en) * | 2013-11-14 | 2015-05-20 | 杭州海康威视数字技术股份有限公司 | RS (reed Solomon) decoding method and device thereof in communication system |
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