CN1169622A - Frequency synthesizing device - Google Patents

Frequency synthesizing device Download PDF

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Publication number
CN1169622A
CN1169622A CN 97102497 CN97102497A CN1169622A CN 1169622 A CN1169622 A CN 1169622A CN 97102497 CN97102497 CN 97102497 CN 97102497 A CN97102497 A CN 97102497A CN 1169622 A CN1169622 A CN 1169622A
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frequency
parameter
synthesizer
output
mentioned
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田岛贤一
伊东健治
西村修司
土井正幸
饭田明夫
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

The purpose of the invention is to realize low stray clutterization easily in each set parameter, thereby, deterioration of communication quality and frequency selectance is avoided. A settable variable frequency divider (13) with a frequency division number setting parameter R is arranged in a reference oscillator (1). When the frequency setting parameter K of DDS12 is selected according to the output frequency fout of PLL2 to prevent DDS12 from exporting high stray clutters in the output band of PLL2, the frequency division number setting parameter N of the variable frequency divider (24) in PLL2 and the frequency division number setting parameter R of the variable frequency divider (13) in the reference oscillator (1) are adjusted to satisfy the output frequency fout and the selected corresponding frequency setting parameter k.

Description

Frequency synthesizer
The present invention relates to have frequency synthesizer with Direct Digital synthesizer especially for the transceiver of wireless communication system etc.
In Figure 39, expressed the Direct Digital synthesizer shown in No. 4965533, the A.L.Bramble " Direct Digital Freqrency Synthesis " that is P.406 put down in writing in P.414 of the collection of thesis that uses disclosed IEEE35th.Ann.Frequency control Symposium in May, 1981 for example and the U.S. Pat etc. (Direct DigitalSynthesizer, hereinafter referred to as " DDS ".) phase-locked loop (Phase Locked Loop, hereinafter referred to as " PLL ".) the existing frequency synthesizer that constitutes.
In Figure 39, the 11st, reference clock, the 12nd, DDS, 1i are the reference oscillators as the first frequency synthesizer of being made up of DDS12 and reference clock 11.The 21st, phase comparator, the 22nd, loop filter, the 23rd, voltage-controlled oscillator (VCO), the 24th, variable frequency divider, the 2nd, as the PLL of the second frequency synthesizer of forming by phase comparator 21, loop filter 22, voltage-controlled oscillator 23 and variable frequency divider 24.Among the figure, fck is the output frequency of reference clock, and fd is the output frequency of DDS12, and fr is the incoming frequency of phase comparator 21, and fout is the output frequency of PLL2.In frequency synthesizer by existing structure shown in Figure 39, PLL2 action is not so that produced by the output wave of the VCO23 of variable frequency divider 24N frequency division and the phase difference of output wave with reference oscillator 1 of DDS12, the output wave frequency that is them is consistent, and exports with output frequency fout.
Figure 40 represents the formation of DDS12 shown in Figure 39.In Figure 40,12a is an accumulator, and 12b is a memory, and 12c is the D-A transducer, and 12d is a filter.In this DDS12, accumulator 12a adds up the long frequency setting data k in L position of input, is transformed to phase data φ output.Sinusoidal wave amplitude data sin φ is stored among the memory 12b, therefore, to phase data φ, output sin φ, 12c converts analog waveform to by the D-A transducer.Above digital operation and reference clock 11 synchronization implementations are included in reference clock 11 compositions and high order harmonic component in the output wave of the D-A transducer 12c spurious clutter composition that becomes to grade by filter 12d filtering.
Figure 41 represents another configuration example of DDS12.In this DDS12 shown in Figure 41, for fear of at high capacity as the memory 12b of the DDS12 shown in Figure 40 under the situation of high order harmonic component resolution, be provided with and utilize the sin φ computing circuit 12e of cordic algorithm etc. to replace memory 12b, obtain sin φ with digital operation.
The output frequency fd of Figure 40 and DDS12 shown in Figure 41 is generally following formula:
fd＝k·fck/2 L (1)
But fck is the output frequency of reference clock 11, and L is the figure place of the frequency setting parameter k of DDS12.
In the frequency synthesizer that the PLL of formation shown in Figure 39 constitutes, for the output frequency fout as the PLL2 of its output frequency is controlled so that by the output wave of the VCO23 of Fractional-N frequency that variable frequency divider 24 carries out with to have the output wave of reference oscillator 1 of DDS12 consistent, make fout become the N doubly (Nfd) of the output frequency fd of DDS12.Thus, in the frequency synthesizer of above formation, can count setup parameter N according to conversion and switch output frequency fout in the interval with fd, on the other hand by the change of the divider ratio N of variable frequency divider 24, can be by the frequency setting parameter k of change DDS12, with (Nfck/2 L) the interval switch output frequency fout.
As what seen, by making the word length multidigitization of frequency setting parameter k by this DDS12, and obtain being difficult for causing the high order harmonic component resolution of other characteristic degradations from the formula (1) of output frequency fd of expression DDS12.Like this, when using in PLL2 when having the reference oscillator 1 of DDS12, the switching of the frequency setting parameter k by DDS12 just can realize the trickle frequency setting of output frequency.
In Figure 42, express another configuration example of the frequency synthesizer of the PLL formation of using DDS12.In Figure 42, the 13rd, the variable frequency divider that the divider ratio R in the back segment that is located at DDS12 in reference oscillator 1j is fixing, other structure is with shown in Figure 39 identical, use same numeral and omit explanation.
In the frequency synthesizer of this formation shown in Figure 42, carried out the fr of output frequency fd of DDS12 of R frequency division by variable frequency divider 13 ' consistent so that carried out output frequency fout and the conduct of the VCO23 of Fractional-N frequency by variable frequency divider 24 for PLL2 action.Use among the IC at the PLL synthesizer of generally selling, under the situation in variable frequency divider 13 ' is located at such reference oscillator 1i, be applicable to this IC mostly with low price.
In Figure 43, express another configuration example (with reference to the Japan Patent open flat 5-67969 of communique, the flat 6-235379 of Japanese Patent Application etc.) of the frequency synthesizer of the PLL formation of using DDS12.In Figure 43, the 14th, local oscillator, the 15th, frequency mixer, the 16th, band pass filter (BPF), the 17th, amplifier (AMP) is the back segment that newly is located at DDS12 in the reference oscillator 1k.Other structure is with shown in Figure 39 identical, uses same numeral and omits explanation.
In the frequency synthesizer of this formation shown in Figure 43, PLL2 action so that undertaken by variable frequency divider 24 Fractional-N frequency VCO23 output frequency fout be the output frequency fd frequency translation of DDS12 that the fr of high frequency is consistent by frequency mixer 15.Thus, in the structure that is provided with such frequency mixer 15, compare with formation shown in Figure 39, the output frequency fd with DDS12 can be the speciality of low frequency, just can carry out the low power consumption action of DDS12.
Therefore, in the existing frequency synthesizer of above-mentioned Figure 39～shown in Figure 43, has following advantage: owing to use DDS12 as reference oscillator, with output frequency by DDS12 change frequency synthesizer, with regard to the characteristic degradation of near the phase noise the carrier wave that can not make frequency synthesizer and the switching time of frequency etc., just can easily obtain the frequency interval of narrow channel.
But, but can there be following problem:, thereby exist by this output frequency and cause quantized error etc. and occur in the situation that produces the spurious clutter (hereinafter referred to as " high spurious clutter ") of the high level more than the dysgenic predetermined level in the communication because DDS12 generates sinusoidal wave output by digital operation.In the case, when high spurious clutter is created in the output band among the PLL2, just can not in PLL2, remove high spurious clutter, the high spurious clutter of output in the carrier wave of PLL2 output, and communication quality and frequency selectance are worsened.
By equation this problem is elaborated with reference to the accompanying drawings.
In Figure 44, express an example of the output spectrum of DDS12.In Figure 44, transverse axis represents that the longitudinal axis is represented amplitude (dBc), has many spurious clutters near the output wave of DDS12 from the imbalance frequency (MHz) as the carrier wave of the output wave of PLL2.Thus, when this spurious clutter is present near the carrier wave of frequency synthesizer, this spurious clutter PLL2 shown in Figure 39 pass through only amplify 20LOG in the frequency band 10N (dB).Like this, in Figure 39, when the spurious clutter level of DDS12 is SPdds (dBc), when the spurious clutter level of synthesizer output was SPout (dBc), their relation was provided by formula (2): SPout=20LOG 10(fout/fr)+Spdds
＝20·LOG 10(N)+Spdds …(2)
Wherein, fr is that N is variable frequency divider 24 divider ratios of PLL2 as the phase comparison frequency of the incoming frequency of giving PLL2.
Therefore, consider: the mixing of nfck produces for n the high order harmonic component of the output frequency fck of the reference clock 11 of being counted mfd and DDS12 by m the high order harmonic component of the output frequency fd of DDS12 counted generally to be included in spurious clutter in the output frequency of DDS12.Thus, when the frequency of spurious clutter was fdds (Hz), fdds was provided by following formula (3), and number of times m in the case is the number of times m of spurious clutter.fdds＝|m·fd-n·fck|
＝|m·(k·fck)/2 L-n·fck|
＝|m·k/2 L-n|·fck …(3)
Therefore, because in the synthesizer of this formation, near the high low order spurious clutter frequency f dds of spurious clutter level is present in the output frequency fd of DDS12, promptly become fdds ≈ fd, high spurious clutter frequency is near the frequency of the outgoing carrier of PLL2 the time, PLL2 uses that this frequency f d near zone doubles as reference frequency etc., thereby, as Figure 45 (a) and (b) like that, the spurious clutter that just can not suppress DDS12 by filter and PLL2, and the high spurious clutter of output high level, because the output of high spurious clutter worsens communication quality and frequency selectance.
In Figure 46, express a example corresponding to the SPdds of the number of times m of the high harmonic wave of the output frequency fd of DDS12.In Figure 46, transverse axis is represented the m of its high order harmonic component, the longitudinal axis represents to be included in the spurious clutter level SPdds in the output wave of DDS12, principal elements such as non-linear and indicial response at the D-A transducer 52 (with reference to Figure 44 and Figure 45) that constitutes DDS12 are: in dominant zone than low order, spurious clutter level SPdds is a high level.Therefore, when the spurious clutter of the low order number of times m that is produced as this high level in the output band of PLL2, will export very high spurious clutter, and communication quality and frequency selectance are worsened.
Therefore, in order in the output of PLL2, not include high spurious clutter, just need, set each setup parameters such as divider ratio setup parameter and frequency setting parameter with PLL2 with respect to reference oscillator 1i etc. according to output frequency fout from PLL2 output.
But, in above-mentioned existing frequency synthesizer, as Figure 39 and Figure 42, shown in Figure 43, because setup parameter is designed to the double resonance type, promptly in reference oscillator and PLL 2, set a setup parameter respectively, when the setup parameter that determines a side with output during as the output frequency fout of target, must determine the opposing party's setup parameter, and generally in the frequency synthesizer that constitutes like this, be that DDS12 by reference oscillator 1i etc. carries out the setting of frequency, on the other hand, carry out the coarse regulation of frequency translation by PLL2, owing to compare with the setup parameter of setting to reference oscillator to the divider ratio setup parameter that PLL2 sets, get very thick value, thereby PLL2 determines two setup parameters not comprise the output frequency fout as target of high spurious clutter with output, and has very bothersome and the such problem of spended time.
In order to address the above problem, the invention provides a kind of frequency synthesizer, by without difficulty in the setting of each setup parameter and seek low spurious clutterization, just can prevent the deterioration of communication quality and frequency selectance.
In order to address the above problem, in the present invention, comprising: the first frequency synthesizer has Direct Digital synthesizer synchronous with reference clock and to export according to the frequency of frequency setting parameter; Frequency changer, the output frequency and the output of counting the above-mentioned Direct Digital synthesizer of setup parameter conversion according to conversion; The second frequency synthesizer, the output frequency and the output of counting setup parameter conversion said frequencies converter according to conversion can be counted setup parameter according to the conversion that setup parameter and above-mentioned second frequency synthesizer are counted in the conversion that the output frequency of above-mentioned second frequency synthesizer is set frequency setting parameter, the said frequencies converter of above-mentioned Direct Digital synthesizer.
In the present invention, comprising: input unit, input is corresponding to should be from the data of the output frequency of second frequency synthesizer output; The setup parameter arithmetic unit is counted in first conversion, obtains the conversion of above-mentioned second frequency synthesizer according to the above-mentioned data of above-mentioned input unit input and counts setup parameter; The setup parameter arithmetic unit is counted in second conversion, counts conversion that the setup parameter arithmetic unit obtains according to the above-mentioned data of above-mentioned input unit input and above-mentioned first conversion and counts setup parameter and obtain the conversion of said frequencies converter and count setup parameter; Frequency setting parameter arithmetic unit is counted conversion that the setup parameter arithmetic unit obtains according to above-mentioned data, above-mentioned first conversion of the input of above-mentioned input unit and is counted setup parameter and above-mentioned second conversion and count conversion that the setup parameter arithmetic unit obtains and count setup parameter and obtain the conversion of above-mentioned Direct Digital synthesizer and count setup parameter; Parameter setting apparatus is counted conversion that the setup parameter arithmetic unit obtains to above-mentioned first conversion and is counted setup parameter, above-mentioned second conversion and count conversion that the setup parameter arithmetic unit obtains and count the frequency setting parameter that setup parameter and said frequencies setup parameter arithmetic unit obtain and be individually set in above-mentioned second frequency synthesizer, said frequencies converter and the above-mentioned Direct Digital synthesizer.
In the present invention, further comprise: the parameter decision device, when frequency setting parameter arithmetic unit is obtained the frequency setting parameter, judge whether this frequency setting parameter has exported the spurious clutter more than the predetermined level from the Direct Digital synthesizer in the output band of second frequency synthesizer; The parameter modification device, when being judged to be the frequency setting parameter by the above-mentioned parameter decision maker when having exported above-mentioned spurious clutter, the change conversion is counted setup parameter and frequency setting parameter and is exported to parameter setting apparatus, so that above-mentioned spurious clutter can not be included in the output band of second frequency synthesizer.
In the present invention, further comprise storage device, store following determination information in advance: whether exported the spurious clutter more than the predetermined level from the second frequency synthesizer, it appears in the output of Direct Digital synthesizer for the frequency setting parameter that each should be set in the Direct Digital synthesizer, when the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, read above-mentioned determination information from above-mentioned storage device, and judge according to this determination information corresponding to the said frequencies setup parameter.
In the present invention, further comprise storage device, store following determination information in advance: whether exported the spurious clutter more than the predetermined level from the second frequency synthesizer, the frequency setting parameter of its Direct Digital synthesizer is as the address, according in each data storage areas of representing in its each address as the said frequencies setup parameter of each address, appear in the output of Direct Digital synthesizer, when the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, the said frequencies setup parameter is carried out access as the address to above-mentioned storage device, and read above-mentioned determination information, judge according to this determination information.
In the present invention, further comprise storage device, store following determination information in advance: whether exported the spurious clutter more than the predetermined level from the second frequency synthesizer, the upper pre-determined bit of the frequency setting parameter of its Direct Digital synthesizer is as the address, according to making the said frequencies setup parameter of each address in each data storage areas of representing in its each address as upper pre-determined bit, appear in the output of Direct Digital synthesizer, when the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, the upper pre-determined bit of said frequencies setup parameter is carried out access as the address to above-mentioned storage device, and read above-mentioned determination information, judge according to this determination information.
In the present invention, further comprise storage device, be stored in the scope of the frequency setting parameter of the corresponding direct digital synthesizer of Direct Digital synthesizer when in the output band of second frequency synthesizer, exporting parasitic more than the predetermined level in advance, when the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, read the scope of said frequencies setup parameter from above-mentioned storage device, whether belong to the scope of this frequency setting parameter of reading by the frequency setting parameter, judge.
In the present invention, further comprise storage device, store the number of times of the spurious clutter more than the predetermined level that the Direct Digital synthesizer exports in advance in the output band of second frequency synthesizer, when the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, read the number of times of above-mentioned spurious clutter from above-mentioned storage device, obtain spurious clutter frequency more than the predetermined level in the output that is included in above-mentioned Direct Digital synthesizer according to the number of times of this above-mentioned spurious clutter of reading and said frequencies setup parameter, by whether having exported this spurious clutter frequency more than predetermined level of obtaining, judge from the second frequency synthesizer.
In the present invention, the parameter decision device is judged: the amplitude of variation at the output frequency of Direct Digital synthesizer is narrower, the scope of the frequency setting parameter of the above-mentioned Direct Digital synthesizer of the spurious clutter that the appearance predetermined level is above is roughly predetermined period, and the above spurious clutter number of times of predetermined level that appears in the output of Direct Digital synthesizer is defined under the situation of specific times, the frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, in the case, obtain the predetermined period of the scope of said frequencies setup parameter according to above-mentioned specific number of times, whether belong to the scope of the said frequencies setup parameter of each this specified period of obtaining by the said frequencies setup parameter, judge.
In the present invention, further comprise: parameter adjustment controls, adjust corresponding Direct Digital synthesizer the frequency setting parameter so that the output frequency of Direct Digital synthesizer scan; Storage device, store the number of times of the spurious clutter more than the predetermined level in the output that appears at the Direct Digital synthesizer in advance, when the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, obtain the scope of the spurious clutter number of times more than the predetermined level in the output that appears at above-mentioned Direct Digital synthesizer by the adjustment of above-mentioned parameter adjusting device, simultaneously, read the number of times of above-mentioned spurious clutter from above-mentioned storage device, whether belong to the scope of above-mentioned number of times by the number of times of this spurious clutter of reading, judge.
In the present invention, count setup parameter and frequency setting parameter so that the spurious clutter more than the predetermined level can not be included in the output band of second frequency synthesizer the time in parameter modification device change conversion, at least one side scheduled volume increase and decrease in the setup parameter is counted in the conversion that makes the conversion of second frequency synthesizer count setup parameter and frequency changer, simultaneously, count the frequency setting parameter that setup parameter changes the Direct Digital synthesizer according to the conversion that makes this at least one side's increase and decrease.
In the present invention, further comprise storage device, the increase and decrease amount of at least one side in the setup parameter is counted in the conversion that setup parameter and frequency changer are counted in the conversion of storing the second frequency synthesizer in advance, setup parameter is counted in its conversion corresponding to the second frequency synthesizer, the frequency setting parameter of setup parameter and above-mentioned Direct Digital synthesizer is counted in the conversion of frequency changer, each frequency setting parameter can be from the spurious clutter more than the Direct Digital synthesizer output predetermined level in the output band of second frequency synthesizer, change that setup parameter and frequency setting parameter are counted in above-mentioned conversion so that the spurious clutter more than the predetermined level can not be included in the output band of second frequency synthesizer the time at the parameter modification device, read corresponding to the conversion of above-mentioned second frequency synthesizer from above-mentioned storage device and to count setup parameter, the above-mentioned increase and decrease amount of the frequency setting parameter of setup parameter and above-mentioned Direct Digital synthesizer is counted in the conversion of said frequencies converter, at least one side who above-mentioned conversion is counted in the setup parameter according to this increase and decrease amount increases and decreases, simultaneously, count the frequency setting parameter that setup parameter changes the Direct Digital synthesizer according to this conversion that this at least one side is increased and decreased.
In the present invention, comprising: the first frequency synthesizer has Direct Digital synthesizer synchronous with reference clock and to export according to the frequency of frequency setting parameter; Frequency changer, the output frequency and the output of counting the above-mentioned Direct Digital synthesizer of setup parameter conversion according to conversion; The second frequency synthesizer, the output frequency and the output of counting setup parameter conversion said frequencies converter according to conversion; Input unit, input and should be from the output frequency that above-mentioned second frequency synthesizer is exported corresponding data are as the address; Storage device, corresponding to should be from the data of the output frequency of above-mentioned second frequency synthesizer output as the address, spurious clutter more than the predetermined level in the output that appears at the Direct Digital synthesizer in each data storage areas that this each address is represented is not included in the output band of above-mentioned second frequency synthesizer, store the frequency setting parameter of above-mentioned second frequency synthesizer in advance with the above-mentioned Direct Digital synthesizer of above-mentioned output frequency output, the conversion of said frequencies converter is counted the conversion of setup parameter and above-mentioned second frequency synthesizer and is counted setup parameter, import by above-mentioned input unit under the situation of above-mentioned address, frequency setting parameter corresponding to the above-mentioned Direct Digital synthesizer of this address, the conversion that setup parameter and above-mentioned second frequency synthesizer are counted in the conversion of said frequencies converter is counted setup parameter and is exported to above-mentioned Direct Digital synthesizer respectively, said frequencies converter and above-mentioned second frequency synthesizer.
In the present invention, the first frequency synthesizer has variable frequency divider, as frequency changer, counts setup parameter according to conversion the output frequency of Direct Digital synthesizer is carried out frequency division.
In the present invention, the second frequency synthesizer is a phase-locked loop, at the output frequency of counting the above-mentioned first frequency synthesizer of setup parameter conversion according to conversion and when exporting, count according to above-mentioned conversion that setup parameter is exported this output frequency so that the frequency of variable frequency divider frequency division is consistent with the output frequency of above-mentioned first frequency synthesizer with should be from the output frequency of second frequency synthesizer output corresponding data.
Fig. 1 is the pie graph of the formation of expression embodiment 1;
Fig. 2 is the pie graph of the formation of expression embodiment 2;
Fig. 3 is the pie graph of formation of the parameter arithmetic processing section 3 of expression embodiment 2;
Fig. 4 is the figure that expression is stored in the content of the determination flag table T in the memory 32 of embodiment 2;
Fig. 5 is the flow chart of action of the frequency synthesizer of expression embodiment 2;
Fig. 6 is the flow chart that the change of parameter k, the R shown in the step 80 of presentation graphs 5, N is handled;
Fig. 7 is the pie graph that is applicable to the embodiment 2 of the frequency synthesizer that has many variable frequency dividers in reference oscillator;
Fig. 8 is the pie graph of formation of the parameter arithmetic processing section 3 of expression embodiment 3;
Fig. 9 is the figure of content of the memory 32 of expression embodiment 3;
Figure 10 is the figure of formation of the parameter arithmetic processing section 3 of expression embodiment 4;
Figure 11 is the figure of memory contents of the memory 32 of expression embodiment 4;
Figure 12 is the figure of formation of the parameter arithmetic processing section 3 of expression embodiment 5;
Figure 13 is the figure of memory contents of the memory 32 of expression embodiment 5;
Figure 14 is the flow chart of the determination flag output handling procedure before in the expression determination flag efferent 35;
Figure 15 is the figure of formation of the parameter arithmetic processing section 3 of expression embodiment 6;
Figure 16 is the figure of memory contents of the memory 32 of expression embodiment 6;
Figure 17 is the flow chart of the handling procedure before the determination flag output in the determination flag efferent 35 of expression embodiment 6;
Figure 18 is the figure of formation of the parameter arithmetic processing section 3 of expression embodiment 7;
Figure 19 (a) and (b) are respectively the figure of the appearance side of the characteristic frequency setup parameter ks among the expression frequency setting parameter k;
Figure 20 is the flow chart of the handling procedure before the determination flag output in the determination flag efferent 35 of expression embodiment 7;
Figure 21 is the figure of formation of the frequency synthesizer of expression embodiment 8;
Figure 22 is the figure of formation of the parameter arithmetic processing section 3 of expression embodiment 8;
Figure 23 is the figure of memory contents of the memory 32 of expression embodiment 8;
Figure 24 is the flow chart of the handling procedure before the determination flag output in the determination flag efferent 35 of expression embodiment 8;
Figure 25 is the figure of formation of the parameter arithmetic processing section 3 of expression embodiment 9;
Figure 26 is the figure of memory contents of the memory 32 of expression embodiment 9;
Figure 27 is the parameter flow chart of calculation process again in the expression parameter computing configuration part 31;
Figure 28 is the figure of the formation of expression embodiment 10;
Figure 29 is the figure of memory contents of the memory 7 of expression embodiment 10;
Figure 30 is the flow chart of the action of expression embodiment 10;
Figure 31 is the figure of the formation of expression embodiment 11;
Figure 32 is the figure that the another kind of expression embodiment 11 constitutes;
Figure 33 is the figure of the formation of expression embodiment 12;
Figure 34 is the figure that the another kind of expression embodiment 12 constitutes;
Figure 35 is the figure of the formation of expression embodiment 13;
Figure 36 is the figure that the another kind of expression embodiment 13 constitutes;
Figure 37 is the figure of the formation of expression embodiment 14;
Figure 38 is the figure that the another kind of expression embodiment 14 constitutes;
Figure 39 is the pie graph of the existing frequency synthesizer of expression;
Figure 40 is the pie graph of the existing DDS of expression;
Figure 41 is the another kind of pie graph of the existing DDS of expression;
Figure 42 is the another kind of pie graph of the existing frequency synthesizer of expression;
Figure 43 is the another kind of pie graph of the existing frequency synthesizer of expression;
Figure 44 is the figure of the output spectrum of expression DDS;
Figure 45 (a) and (b) are respectively the key diagrams of the spurious clutter frequency spectrum of untamed DDS;
Figure 46 is the figure of expression corresponding to the spurious clutter level SPdds of the number of times m of the high order harmonic component of the output frequency fd of DDS.
Embodiment 1
The embodiment 1 of frequency synthesizer of the present invention is described with reference to the accompanying drawings.
Fig. 1 is the formation of the frequency synthesizer of expression embodiment 1.In this Fig. 1, the part identical with the prior art shown in Figure 42 waits uses identical label to describe.
In Fig. 1, the frequency synthesizer of this embodiment 1 is by forming as the reference oscillator 1 of first frequency synthesizer with as the PLL2 of second frequency synthesizer, reference oscillator 1 has the reference clock 11 of the clock signal of output frequency fck, output and this clock signal are synchronously and corresponding to the DDS12 of the frequency f d of frequency setting parameter k, with as frequency division transformation of variable count setup parameter (hereinafter referred to as " divider ratio setup parameter ") R the output frequency fd of DDS12 carried out the variable frequency divider 13 of frequency division, and PLL2 has phase comparator 21, loop filter 22, voltage-controlled oscillator (VCO) 23, the output frequency fout of voltage-controlled oscillator (VCO) 23 is carried out the variable frequency divider 24 of frequency division with divider ratio setup parameter N.
The frequency synthesizer of this embodiment 1, it is characterized in that, can be by set the frequency setting parameter k of the DDS12 in the reference oscillator 1 from the setting of outside, simultaneously, can similarly set the divider ratio setup parameter N of the variable frequency divider 24 in the PLL2, and, can set the divider ratio setup parameter R of the variable frequency divider 13 in the reference oscillator 1 equally, these three setup parameters be can be according to three mode of resonance of the output frequency fout setting of PLL2.In Fig. 1, L is the figure place of the frequency setting parameter k of DDS12, and fr is that the output frequency of variable frequency divider 13 also is the incoming frequency of PLL2.
Wherein and since the output frequency fd of DDS12 be shown in the formula (1) like that, then provide the output frequency fout of the frequency synthesizer of embodiment 1 shown in Figure 1 by following formula (4):
fout＝fd·N/R
＝N·k·fck/(R·2 L) …(4)
That is, the output frequency fout of frequency synthesizer, by shown in this formula (4) like that, by the value decision of three frequency setting parameter k, R, N.Parameter k, R, N are owing to have the degree of freedom of setting separately rather than free burial ground for the destitute decision.
Then, the action of the frequency synthesizer of this embodiment 1 is described, when being set to setup parameter reference oscillator 1 and the PLL2 according to the output frequency fout that exports from PLL2, output frequency fout according to PLL2 suitably selects frequency setting parameter k so that DDS12 does not export the high spurious clutter more than the predetermined level in the output band of PLL2, but, owing to can set the frequency setting parameter k of DDS12, the divider ratio setup parameter N of variable frequency divider 24, three parameters of the divider ratio setup parameter R of variable frequency divider 13, and adjust divider ratio setup parameter N and divider ratio setup parameter R, so that should satisfy formula (4) from the output frequency fout of PLL2 output and the frequency setting parameter k of selection.
Like this, frequency synthesizer according to this embodiment 1, when suitably selecting frequency setting parameter k in the output band of output frequency fout according to PLL2 at PLL2 so that DDS12 when not exporting high spurious clutter more than the predetermined level, owing to can adjust divider ratio setup parameter N and divider ratio setup parameter R, the range of choice of frequency setting parameter k when just the energy broadening is sought to hang down spurious clutter, simultaneously, though the platform number of variable frequency divider has increased, but because as each variable frequency divider 13, the divider ratio R of 24 divider ratio setup parameter, the scope of N does not need so big, and can carry out part selection cheaply, just can under low cost as a whole, improve the setting degree of freedom of frequency parameter.
In the explanation of this embodiment 1, although understand the variable frequency divider 13 that can set divider ratio setup parameter R according to the output frequency fout of PLL2 be set in reference oscillator 1, but, in the present invention, variable frequency divider such more than two can be set in reference oscillator 1, can in PLL2, one or more be set, outside reference oscillator 1 and PLL2, also one or more can be set, main is, the quantity of the setup parameter in the frequency synthesizer that can set according to output frequency fout is if also passable more than three.
Embodiment 2
In the frequency synthesizer of this embodiment 2, also automatically carry out the setting of best setup parameter k, R, N easily not export the high spurious clutter among the embodiment 1.
Fig. 2 is the formation of the frequency synthesizer of this embodiment 2 of expression.In this Fig. 2, the part identical with Fig. 1 uses identical label to describe.
In Fig. 2, the frequency synthesizer of this embodiment 2, it is characterized in that, comprise: reference oscillator 1 that is made of reference clock 11, DDS12 and variable frequency divider 24 and the PLL2 that is made of phase comparator 21, loop filter 22, voltage-controlled oscillator (VCO) 23 and variable frequency divider 24 also comprise parameter arithmetic processing section 3, input unit 4 simultaneously.
Input unit 4 is made up of switch, numerical key, keyboard etc., wherein constitutes: the output frequency data Dout from the output frequency fd of the incoming frequency fr of output frequency fout, variable frequency divider 13 of PLL2 and DDS12 to parameter arithmetic processing section 3 input, Dr, the Dd that correspond respectively to.
Parameter arithmetic processing section 3, its structure is described by following Fig. 2, if its function of explanation, when importing each output frequency data Dout from input unit 4, Dr, during Dd, just can be from the spurious clutter more than PLL2 appears at predetermined level the output of DDS12, and, in order to export output frequency fout from PLL2 corresponding to the Dout of input, obtain divider ratio setup parameter N as the divider ratio N of variable frequency divider 24, as the divider ratio setup parameter R of the divider ratio R of variable frequency divider 13 and the frequency setting parameter k of DDS12, this each setup parameter k that obtains, R, N is individually set to variable frequency divider 24, among variable frequency divider 13 and the DDS12.In Fig. 1, fck is the output frequency of reference clock 11, and fr is that the output frequency of variable frequency divider 13 also is the incoming frequency of PLL2, and L is the figure place of the frequency setting parameter k of DDS12.
Fig. 3 represents the formation of the parameter arithmetic processing section 3 of this embodiment 2.In the figure, 311 is that the setup parameter arithmetic unit is counted in first conversion, 312 is that the setup parameter arithmetic unit is counted in second conversion, the 313rd, frequency setting parameter arithmetic unit, the 314th, the parameter decision device, the 315th, the parameter modification device, the 316th, parameter setting apparatus, the 31st, by these device 311～316 parameter computing configuration parts of forming.And, the 32nd, store the memory of determination flag table T described later, the 33rd, the determination flag of reading from the determination flag corresponding to appointed frequency setting parameter k is stored into the determination flag table T the memory 32 is read portion.
Fig. 4 represents to be stored in the content of the determination flag table T in the memory 32.In the figure, in this determination flag table T, store in advance for each 0～2 LThe frequency setting parameter k of-1 DDS12 with 0 or 1 expression each frequency setting parameter k whether corresponding to the determination flag h of the high characteristic frequency setup parameter ks of spurious clutter level.L is the figure place of the frequency setting parameter k of DDS12.
Wherein, this determination flag h takes off the value of formula (5):
h＝1(k≠ks)
h＝0(k＝ks) …(5)
The characteristic frequency setup parameter ks that becomes high spurious clutter have s=1 ..., p p.
The action of frequency synthesizer of the embodiment 2 of above formation is described with reference to the accompanying drawings.
Fig. 5 represents the action of the frequency synthesizer of this embodiment 2.
At first, in the frequency synthesizer of this embodiment 2, input unit 4 is respectively with should be from the output frequency fout of PLL2 output corresponding data Dout, be input to the parameter computing configuration part 31 (step S10) with the corresponding Dr arbitrarily of the output frequency fr of variable frequency divider 13 with the pairing any Dd of the output frequency fd of DDS12.
Like this, in parameter computing configuration part 31, first conversion is counted setup parameter arithmetic unit 311, second conversion and is counted these data Dout, Dr, the Dd that setup parameter arithmetic unit 312, frequency setting parameter arithmetic unit 313 are accepted input unit 4 inputs, carry out inverse operation and obtain the divider ratio N of variable frequency divider 24, the divider ratio R of variable frequency divider 13 and the frequency setting parameter k of DDS12 by variable frequency divider 24, promptly export the output frequency fout (step S20～50) corresponding with data Dout from PLL2 with this order.
Specifically, at first, setup parameter arithmetic unit 311 is obtained the divider ratio N that sets variable frequency divider 24 with for example following formula (6) divider ratio setup parameter N (step S20) is counted in first conversion:
N=int[Dout/Dr) or N=round[Dout/Dr] (6)
Round[wherein] be the function that the following value of the decimal point in [] is rounded up, int[] be the function that the following value of the decimal point in [] is cast out.Why use these functions, be because each setup parameter k, R, N can only round numerical value in the frequency synthesizer of this embodiment 2, self-evident, can replace with other function, and, if each setup parameter k, R, N round beyond the numerical value value, can be the function that rounds beyond the numerical value.
Then, second conversion is counted setup parameter arithmetic unit 312 and is used this divider ratio N and input data Dr, under situation corresponding to the output frequency fout of data Dout and divider ratio N, by following formula (7) obtain with should be from the corresponding Dr ' (step S30) of output frequency of variable frequency divider 13 outputs:
Dr’＝Dout/N …(7)
Wherein, because the divider ratio setup parameter R that should be set in the variable frequency divider 13 also rounds numerical value, setup parameter arithmetic unit 312 is obtained variable frequency divider 13 from Dr ' and Dd by following formula (8) divider ratio setup parameter R (step S40) is counted in second conversion:
R=int[Dr '/Dd] or R=round[Dr '/Dd] ... (8)
At last, frequency setting parameter arithmetic unit 313 is obtained the frequency setting parameter k that should be set among the DDS12, but, then obtain the frequency setting parameter k of DDS12 with following formula (9) from Dout, R and N, and export to parameter decision device 314 (step S50) according to formula (4) because this k also rounds numerical value:
K=int[(DoutR2 L)/(DckN)] or
k＝round[(Dout·R·2 L)/(Dck·N)] …(9)
Wherein, L is that Dck is the data that are equivalent to the clock frequency fck of DDS12 to the figure place of the frequency setting parameter k of DDS12 setting.L and Dck can be used as data in advance and are stored in the parameter arithmetic processing section 3, also can import from the outside.
When parameter decision device 314 when frequency setting parameter arithmetic unit 313 receives frequency setting parameter k, give determination flag this frequency setting parameter k and read portion 33, read in the portion 33 in determination flag, read determination flag h from the determination flag table T of memory shown in Figure 3 32 corresponding to this frequency setting parameter k, judge according to this determination flag h whether frequency setting parameter k does not correspond to the high characteristic frequency setup parameter ks of spurious clutter, whether is k ≠ ks (step S60) promptly.
Its result, when the determination flag h that reads is 1, k ≠ ks promptly is judged to be frequency setting parameter k when not corresponding to the high characteristic frequency setup parameter ks of spurious clutter (step S60 " YES "), and parameter decision device 314 is exported to parameter modification device 315 to this result of determination.So, parameter modification device 315 does not change and gives parameter setting apparatus 316 each setup parameter k, R, the N that is obtained by computing, and parameter setting apparatus 316 is exported to DDS12, variable frequency divider 13 and variable frequency divider 24 to this setup parameter k, R that obtains, N former state respectively and set (step S70).
In contrast, when the determination flag h that reads is 0, k=ks, when promptly being judged to be frequency setting parameter k corresponding to the high characteristic frequency setup parameter ks of spurious clutter (step S60 " NO "), parameter decision device 314 is exported to parameter modification device 315 to this result of determination.So, parameter modification device 315 is (step S60 " YES ") before becoming k ≠ ks, descend setup parameter k, the R of Fig. 6 detailed description, the change of N to handle (step S80) repeatedly, till becoming k ≠ ks (step S60 " YES "), its each setup parameter k, R, N just are fed to parameter setting apparatus 316, and parameter setting apparatus 316 is exported to DDS12, variable frequency divider 13 and variable frequency divider 24 to this each setup parameter k, R, N respectively and set (step S70).
Each setup parameter k in the parameter modification device 315 shown in the step S80 of detailed description Fig. 5, the change of R, N are handled below.
Change at setup parameter k, the R shown in the step S80 of Fig. 6 presentation graphs 5, N is handled.
In this change is handled, parameter modification device 315 by following formula (10) revise in the processing of above-mentioned steps 10, import with should be from the output frequency of PLL2 output corresponding data Dout and each setup parameter k that the processing of step 20～50, obtains, R, N in R and N (step S810, S820):
N＝N+α
R＝R+β …(10)
Wherein, α is the increment of N, and β is the increment of R, and α and β are stored in the parameter arithmetic processing section 3 in advance.Though in this embodiment 2, be to have changed R and N,, also can only change by increase and decrease N or R one side.
Above-mentioned such new R that changes and N substitution formula (9) and obtain new setup parameter k (step S830).
If such setup parameter k, R, N are carried out computing again and change its value, turn back to the processing of the step S60 of Fig. 5, carry out the judgement again of setup parameter k, before becoming k ≠ ks, make parameter N, R only increase α, β on one side, Yi Bian repeat the computing again of setup parameter k, R, N.
Like this, frequency synthesizer according to this embodiment 2, if by input unit 4 corresponding to being input to the parameter arithmetic processing section 3 from the data Dout of the output frequency fout of PLL2 output etc., parameter arithmetic processing section 3 is computing setup parameter k, R, N automatically, and be set among variable frequency divider 24,13 and the DDS12, therefore, corresponding to having become easily from setup parameter k, the R of the output frequency fout of PLL2 output, the setting operation of N.
In the frequency synthesizer of this embodiment 2, when computing setup parameter k, R, N, compare with the high ks of spurious clutter level that has stored the value of setup parameter k in advance, before becoming k ≠ ks, carry out repeatedly, and setup parameter k, R, N carried out computing again, satisfy setup parameter k, R, the N of k ≠ ks with output, thus, just can automatically avoid the use of the high ks of spurious clutter level, and make high spurious clutter in the output that appears at DDS12 away from outside the output band of PLL2.Thus, owing to can not export high spurious clutter, just can seek cost degradation from PLL2.
In the frequency synthesizer of this embodiment 2, owing in memory 32, stored setup parameter k in advance whether corresponding to the result of determination of the high ks of spurious clutter level, with judge by calculating whether setup parameter k compares corresponding to the situation of ks, just can seek to shorten the needed time in the judgement of k, i.e. needed time in the change of each setup parameter, and have the effect that improves the frequency switch speed.
Though in the frequency synthesizer of the above embodiments 2, situation with above-mentioned three each the output frequency data Dout of input unit 4 inputs, Dr, Dd is that example is illustrated, but, in the present invention, should be just enough if input unit 4 minimum inputs are represented from the output frequency data Dout of the output frequency fout of PLL2 output, so just do not need to import other output frequency data Dr, Dd.Promptly, though need be corresponding to should be from the output frequency data Dout of the output frequency fout of PLL2 output from the outside input and indicate, but because Dr and Dd can be arbitrary values, parameter computing configuration part 31 can preestablish or store fixed value etc. as initial value.
Though in the frequency synthesizer of the above embodiments 2, what illustrate is whether setup parameter k is stored in the memory 32 as determination flag table T in advance corresponding to the result of determination of the high ks of spurious clutter level, but, in the present invention, the memory 32 of such storage determination flag table T can be set, and whether in the output band of PLL2, export the spurious clutter more than the predetermined level from DDS12 by this frequency setting parameter of judgements such as arithmetic expression k.
Though in the frequency synthesizer of the above embodiments 2, be that example is illustrated with the situation that in reference oscillator 1, has a variable frequency divider 13,, even have many variable frequency dividers 13 inside and outside reference oscillator 1, this embodiment 2 also can be suitable for.
Fig. 7 represents to be applicable to the formation of frequency synthesizer of the embodiment 2 of the frequency synthesizer that has many variable frequency dividers in reference oscillator 1.In the frequency synthesizer shown in this figure, reference oscillator 1a has N platform variable frequency divider 13r1～13rn, input unit 4a, except data Dout, Dd, also handle is input among the parameter arithmetic processing section 3a corresponding to the data Dr1～Drn of the output frequency of each variable frequency divider 13r1～13rn.
For this reason, as parameter arithmetic processing section 3a when input is corresponding to the data Dr1 of the output frequency of each variable frequency divider 13r1～13rn～Drn from input unit 4a input data Dout, Dd the time, after the variable frequency divider 24 of PLL2, with variable frequency divider 13rn, variable frequency divider 13rn-1 ..., variable frequency divider 13r2, variable frequency divider 13r1 order obtain the frequency setting parameter, at last, obtain the frequency setting parameter of DDS12.So, identical with the situation of above-mentioned formation shown in Figure 1, can output to each setup parameter among many variable frequency divider 13r1～13rn and DDS12 in the variable frequency divider 24 of PLL2 and the reference oscillator 1a.
In the frequency synthesizer of the above embodiments 2, though not to counting setup parameter arithmetic unit 311 by first conversion that constitutes parameter arithmetic processing section 3, setup parameter arithmetic unit 312 is counted in second conversion, frequency setting parameter arithmetic unit 313, parameter decision device 314, parameter modification device 315, the formation that parameter computing configuration part 31 that parameter setting apparatus 316 is formed and determination flag are read portion 33 is carried out concrete description, but, also can realize by the hardware that logical circuit forms, perhaps by realizing, as long as can realize above-mentioned functions based on processing by the software of generations such as DSP and CPU.
Embodiment 3
The frequency synthesizer of this embodiment 3, identical with the foregoing description 2, the characteristic frequency setup parameter ks that uprises to avoid the spurious clutter level of computing or change setting parameter k, R, N again, but, the formation of parameter arithmetic processing section is different with the foregoing description 2, changes the storage means of the determination flag h in the memory and does not need determination flag in the parameter arithmetic processing section 3 to read the formation of portion 33.
Thus, in the frequency synthesizer of this embodiment 3, because except the storage means of the formation of parameter arithmetic processing section and the determination flag h in the memory, identical with the foregoing description 2, thereby, use the pie graph and the flow chart of the foregoing description 2 to describe.
Fig. 8 represents the formation of the parameter arithmetic processing section 3a of this embodiment 3.In the drawings, the 31st, parameter computing configuration part similarly to Example 2,32a is a memory of being stored determination flag h by following method shown in Figure 9.
Fig. 9 represents the content of the memory 32a of this embodiment 3.As shown in the figure, in this memory 32a, the frequency setting parameter k of the L position of DDS 12 is as the address, storing determination flag h in advance, this determination flag h is in order to according in the data storage areas that this each address is represented, as the said frequencies setup parameter k of each address, judge whether the output of DDS12 comprises high spurious clutter.
Specifically, the frequency setting parameter k of DDS12, be expressed as 00000,00001 ..., 01010 ..., 2 L-1 with 5 address as memory 32a, in the storage area that this address is represented, is storing the determination flag h with 0 or 1 representative.L is the figure place to the frequency setting parameter k of DDS12 output.
The following describes the action of the frequency synthesizer of this embodiment 3.
At first, in this embodiment 3, identical with the foregoing description 2, when input unit 4 input should be from the pairing data Dout of the output frequency fout of PLL2 output, each setup parameter k, R, N are obtained by the processing of the step 10 to 50 of Fig. 5 in parameter computing configuration part 31, in the processing of step 60, judge that whether this setup parameter k that obtains is corresponding to the high characteristic frequency setup parameter ks of spurious clutter level, thus, export this setup parameter k.
So, in this embodiment 3, because this setup parameter k is input among the memory 32a as the address, memory 32a exports the pairing determination flag h of setup parameter k that is stored in this address to parameter computing configuration part 31, and parameter computing configuration part 31 is judged in the same manner according to this determination flag h and the foregoing description 2.
Specifically, under the situation of the frequency setting parameter k of the DDS12 that obtains by computing for for example k=01011, because the address number 01011 at memory 32a carries out access, then as shown in Figure 9, reads the determination flag h that is stored in 0 in the address number 01011.
Thus, in the case, owing to expressed by 0 the setup parameter k that determination flag h obtained corresponding to the high characteristic frequency setup parameter ks of spurious clutter, and in the step S60 of Fig. 5, be judged to be NO, be transformed in the processing of step S80, carry out the processing of step S80 shown in Figure 6, carry out the computing again of each setup parameter k, R, N.
Like this, frequency synthesizer according to this embodiment 3, identical with embodiment 2, if output frequency fout etc. is input to the parameter arithmetic processing section 3a from outside, parameter arithmetic processing section 3a automatically obtains each setup parameter k, R, N also sets and gives DDS12 and variable frequency divider 24,13, therefore, at setup parameter k, R, just do not spend time in the setting of N, simultaneously, obtaining each setup parameter k, R, during N, judge whether setup parameter k is consistent with the high characteristic frequency setup parameter ks of spurious clutter level, and can avoid exporting characteristic frequency setup parameter ks in advance, therefore the low spurious clutterization that just can seek frequency synthesizer.
In the frequency synthesizer of this embodiment 3, because the frequency setting parameter k of DDS12 has stored in the data storage areas that this each address is represented in order to judge that frequency setting parameter k is whether corresponding to the determination flag h of characteristic frequency setup parameter ks as the address, then obtaining each setup parameter k, R, during N, just can read its determination flag h to this setup parameter k as the address, situation with above-mentioned embodiment 2 is compared, just do not need determination flag to read the formation of portion 33, then constitute and become simple, simultaneously, can also shorten the needed time in the judgement of setup parameter k.Its result according to this embodiment 3, compares with the situation of embodiment 2, just can seek to shorten the needed time in the change of each setup parameter, and can accelerate the frequency switch speed of frequency synthesizer.
In the frequency synthesizer of this embodiment 3, though explanation is whole 0～2 of frequency setting parameter k L-1 determination flag h signs in among the memory 32a, and still, in the present invention, the scope that for example can only limit to actual use is logined frequency setting parameter k.Just can prevent the increase of the capacity of memory 32a thus.
In the frequency synthesizer of this embodiment 3, though the formation to parameter computing configuration part 31 does not specifically describe, but, identical with the situation of the foregoing description 2, can be the hardware that forms by logical circuit, also can be that software by generations such as DSP and CPU is the processing on basis, as long as can realize above-mentioned functions.This scheme also is identical to the embodiment of following explanation.
Embodiment 4
The frequency synthesizer of this embodiment 4 is an improved plan, so that do not increase the capacity of the memory 32a of the foregoing description 3.Promptly, at the long L in the position of the frequency setting parameter k of DDS12 is for example under 32 the situation, in embodiment 3, because the address of this frequency setting parameter k as memory 32a, then need the capacity of the position of about 4.3G in memory 32a, this is unpractical, therefore, in this embodiment 4, has the structure of the address of memory being jumped choosing.
Thus, the frequency synthesizer of this embodiment 4, only the formation of parameter arithmetic processing section is different with the foregoing description 2, and the formation and the action of parameter arithmetic processing section mainly are described.
Figure 10 represents the formation of the parameter arithmetic processing section 3b of this embodiment 4.In the drawings, the 31st, the parameter computing configuration part identical with the foregoing description 1,32b is that be illustrated in fig. 11 shown below such compared the memory of having cut down memory capacity significantly and having stored determination flag h with embodiment 3, the 34th, the next cut-out portion cuts off frequency setting parameter k the next of the DDS12 of 31 outputs from parameter computing configuration part and exports to memory 32b.
Figure 11 represents the memory contents of the memory 32b of embodiment 4.In this memory 32b, as shown in the figure, under the situation of the frequency setting parameter k that represents DDS12 with 5, with 4 address h on it as memory, in the data storage areas that this each address is represented, storing in advance in order to according to each address as last 4 frequency setting parameter k, whether the output of differentiating DDS12 has comprised the determination flag h of high spurious clutter.Wherein, because in 5 of setup parameter k, last 4 are used as the address, and only cut-out is the most the next, then the capacity of memory 32b is 1/2 under the foregoing description 3 situations.
The following describes the action of the frequency synthesizer of this embodiment 4.
At first, in the frequency synthesizer of this embodiment 4, identical with the foregoing description 3, when 4 of input units should be input to parameter arithmetic processing section 3b from the pairing data Dout of output frequency fout of PLL2 output, each setup parameter k, R, N are obtained by the processing of the step 10 to 50 of Fig. 5 in the parameter computing configuration part 31 of parameter arithmetic processing section 3, in the processing of step 60, judge that whether setup parameter k is corresponding to the high characteristic frequency setup parameter ks of spurious clutter level, thus, this setup parameter k is exported to the next cut-out portion 34.
When the 34 input setup parameter k of the next cut-out portion, cut off the not enough last 4 the next of setup parameter k and export to memory 32b.Owing to memory 32b imports last 4 of setup parameter k as the address, then last 4 the pairing determination flag h with setup parameter k are exported to parameter computing configuration part 31, parameter computing configuration part 31 judges that according to this determination flag h whether setup parameter k is corresponding to the high characteristic frequency setup parameter ks of spurious clutter level.
Specifically, under the situation of the frequency setting parameter k of the DDS12 that obtains by computing for for example k=10110 or 10111, by thereon 4 be 1011, then as shown in Figure 11, output is stored in the determination flag h of 0 in the address number 1011 of memory 32b.Thus, in the case, because has expressed by 0 the setup parameter k that determination flag h obtained corresponding to the high characteristic frequency setup parameter ks of spurious clutter parameter computing configuration part 31, and in the step S60 of Fig. 5, be judged to be NO, be transformed in the processing of step S80, carry out the processing of step S80 shown in Figure 6, carry out the computing again of each setup parameter k, R, N.
Like this, frequency synthesizer according to this embodiment 4, identical with embodiment 2, if being input to the parameter arithmetic processing section 3b with should be from the output frequency fout of PLL2 output corresponding data Dout etc., parameter arithmetic processing section 3b automatically obtains each setup parameter k, R, N also sets, therefore, at setup parameter k, R, just do not spend time in the setting of N, simultaneously, obtaining each setup parameter k, R, during N, judge whether setup parameter k is consistent with the high characteristic frequency setup parameter ks of spurious clutter level, and can avoid exporting characteristic frequency setup parameter ks in advance, therefore the low spurious clutterization that just can seek frequency synthesizer.
In the frequency synthesizer of this embodiment 4, since with the last pre-determined bit of the frequency setting parameter k of DDS12 as the address and stored determination flag h, this determination flag h representative in the data storage areas that this each address is represented its address as on the frequency setting parameter k of pre-determined bit whether corresponding to characteristic frequency setup parameter ks, just can be identical with the foregoing description 3, can shorten the needed time in the judgement of k, simultaneously, compare with the situation of embodiment 3, can also cut down the capacity of memory 32b.As carry out specific description, when frequency setting parameter k be for example 32 high de-agglomeration can the time, though the capacity of memory 32b be about 4.3G position,, when its jumping is chosen for example 16 1/2 the time, the about 66k of usefulness position is just enough.Its result by cutting down the capacity of memory, just can use memory cheaply, thus, just can seek to reduce manufacturing cost.
Embodiment 5
The frequency synthesizer of this embodiment 5, identical with the foregoing description 4, constitute with the foregoing description 3 and compare the memory span of having cut down the judgement that is used for setup parameter k, but, as the foregoing description 3, frequency setting parameter k jump the choosing and as the address, rather than be stored in the determination flag h corresponding to frequency setting parameter k in the memory in advance, the scope that is characteristic frequency setup parameter ks that the spurious clutter level is uprised is stored in the memory in advance, judges that whether the frequency setting parameter k that is obtained by this scope is corresponding to ks.
Thus, the frequency synthesizer of this embodiment 5 only formation of parameter arithmetic processing section is different with the foregoing description 2～3, therefore, the formation and the action of parameter arithmetic processing section is described mainly.
Figure 12 represents the formation of the parameter arithmetic processing section 3c of this embodiment 5.In the drawings, the 31st, parameter computing configuration part same as the previously described embodiments, 32c is the memory of scope of storing the characteristic frequency setup parameter ks of the DDS that spurious clutter uprises, the 35th, judge whether do not correspond to characteristic frequency setup parameter ks and according to being stored in characteristic frequency setup parameter ks among the memory 32c the determination flag efferent of this result of determination as determination flag h output.
Figure 13 represents the memory contents of the memory 32c of embodiment 5.Corresponding to address i (i=0,1,2 ...) and in the scope of each characteristic frequency setup parameter ks, the lower limit ai of the characteristic frequency setup parameter ks in each scope and higher limit bi are stored into this memory 32c successively from a low side.Wherein, as shown in the figure, represent characteristic frequency setup parameter ks with 7.
Below, the action of the frequency synthesizer of this embodiment 5 is described with reference to accompanying drawing.
Figure 14 represents the determination flag output handling procedure before in the determination flag efferent 35.Before entering this processing, in the frequency synthesizer of this embodiment 5, identical with the situation of above-mentioned each embodiment, by input unit 4 Dout, Dr, Dd are input to parameter computing configuration part 31, and obtaining each setup parameter k, R, N, frequency setting parameter k is output in the determination flag efferent 35.
At first, when determination flag efferent 35 when parameter computing configuration part 31 receives frequency setting parameter k, memory 32c is carried out access, read the lower limit ai and the higher limit bi (step S610) of scope of the characteristic frequency setup parameter ks of address i (initial value is i=0), judge whether setup parameter k belongs between this lower limit ai and the higher limit bi (step S612).Here, the result of its judgement, being judged as ai≤k≤bi is that setup parameter k is when being between lower limit ai and the higher limit bi (step S612 " YES "), this setup parameter k is the high ks of spurious clutter level, therefore, same as the previously described embodiments, determination flag is set at 0 (step S614), the determination flag h 0 exports to parameter computing configuration part 31 (step S670).
Opposite with it, when judging that k＜ai or k＞bi are that setup parameter k is not when being between lower limit ai and the higher limit bi (step S612 " NO "), whether the value of then judging parameter k is less than the value (step S616 " NO ") of ai and bi, the judgement whether setup parameter k is in the scope of the spurious clutter that becomes high level does not also finish, thereby, i is increased+1 (step S618), carry out the processing of above-mentioned steps S610～616 once more.
On the other hand, in the value that is judged as parameter k during less than the value (step S616 " YES ") of ai and bi, the judgement whether expression setup parameter k is in the scope of the spurious clutter that becomes high level finishes, owing to be not corresponding to characteristic frequency setup parameter ks, then determination flag h is set at 1 (step S620), the determination flag h 1 exports to parameter computing configuration part 31 (step S622).
Like this, frequency synthesizer according to this embodiment 5, identical with the foregoing description 2～5, if being input to the parameter arithmetic processing section 3c with should be from the output frequency fout of PLL2 output corresponding data Dout etc., parameter arithmetic processing section 3c automatically obtains each setup parameter k according to this Dout etc., R, N also sets to DDS12 etc., thereby, at setup parameter k, R, do not spend time in the setting of N, simultaneously, obtaining each setup parameter k, R, during N, judge that setup parameter k is whether consistent with the high characteristic frequency setup parameter ks of spurious clutter level, and can avoid in advance the high characteristic frequency setup parameter ks of spurious clutter is exported to DDS12, so the low spurious clutterization that just can seek frequency synthesizer.
In the frequency synthesizer of this embodiment 5, owing in memory 32c, stored the scope of the high characteristic frequency setup parameter ks of spurious clutter, compare with the situation of embodiment 2～4, can cut down the capacity of memory 32c.Its result owing to can use memory cheaply by the reduction of memory span, just can seek the reduction of manufacturing cost.
Embodiment 6
The frequency synthesizer of this embodiment 6, it is characterized in that identical with the foregoing description 4,5, the memory span of having cut down the judgement that is used for setup parameter k constitutes like that, but, in order further to cut down the capacity of memory, the number of times of the spurious clutter more than the predetermined level that DDS12 is exported in the output band of PLL2 stores in the memory in advance, judges according to this number of times whether the frequency setting parameter k that obtains does not correspond to ks.
Thus, the frequency synthesizer of this embodiment 6 only formation of parameter arithmetic processing section is different with the foregoing description 2～5, therefore, the formation and the action of parameter arithmetic processing section is described mainly.
Figure 15 represents the formation of the parameter arithmetic processing section 3d of this embodiment 6.In the drawings, the 31st, parameter computing configuration part same as the previously described embodiments, 32d is storing the memory of the number of times m of the high spurious clutter more than the predetermined level of DDS12 output in the output band of PLL2 like that shown in Figure 16 in advance, and 35a judges the determination flag efferent whether frequency setting parameter k does not correspond to characteristic frequency setup parameter ks and its result of determination is exported as determination flag h according to the number of times m that is stored in the high spurious clutter in the memory 32.
Figure 16 represents the memory contents of the memory 32d of embodiment 6.In this memory 32d, press 2,3,4 ... login in advance address at each memory 32d (i=0,1,2 ..., appear at the number of times mi of the above high spurious clutter of predetermined level in the output of DDS12 in q).
Below to judging by the number of times m of spurious clutter whether spurious clutter becomes this point of high level and describe, generally, become the specific fd of fd ≈ fdds about equally by the output frequency fd of DDS12 and the frequency f dds of high spurious clutter, just can not in PLL2 and filter etc., suppress or remove its high spurious clutter.Therefore, the frequency f dds of high spurious clutter resembles by shown in the formula (3) and is provided by fdds=|mfd-nfck|, but, spurious clutter level SPdds corresponding to the number of times m of spurious clutter is shown in Figure 46, and the number of times m of the high spurious clutter of spurious clutter level SPdds is limited to the low specific times m of number of times.Thus, in the frequency synthesizer of this embodiment 6, the spurious clutter of only storing in memory 32d in the output that is included in DDS12 is the value of the specific times m of high level.
Below, the resolution principle in the determination flag efferent 35 of this embodiment 6 is described.
At first, owing to finally can not export high spurious clutter,, just do not satisfy formula (11) in the output band of PLL2 if the frequency f dds of the spurious clutter of the high number of times m of spurious clutter level does not exist from PLL2:
|fdds-fd|＜Δfpl1 …(11)
(still, Δ fpl1 is the output band of PLL2.)
If wushu (3) this formula of substitution (11), and become:
|(m±1)k/2 L-n|＜Δfpl1/fck …(12)
The frequency f dds of the high spurious clutter that should consider is generally below 1/2 of output frequency fck of reference clock 11.Like this, fdds is following formula (13):
fdds＝|m·fd-n·fck|＜0.5fck
＝|m·k/2 L-n|＜0.5 …(13)
If separate this formula (13) for the order of harmonic n of the output frequency f ck of reference clock 11, become following formula (14):
m·k/2 L-0.5＜n＜m·k/2 L+0.5 …(14)
Wherein, because frequency n is an integer, formula (14) is following formula (15):
n＝round[k·m/2 L] …(15)
If this formula (15) substitution formula (12), the determine type of the frequency setting parameter k of DDS12 is that following formula (16) is such:
|(m±1)k/2 L-round[k·m/2 L]|＜Δfpl1/fck…(16)
Like this, satisfy at setup parameter k under the situation of formula (16), become from PLL2 and export high spurious clutter.Thus, if store 2 in advance LValue and the value of Δ fpl1/fck, just can carry out the judgement of frequency setting parameter k from the number of times m of spurious clutter.
The frequency synthesizer of this embodiment 6 is described with reference to the accompanying drawings.
Figure 17 represents the handling procedure before the determination flag output in the determination flag efferent 35 of this embodiment 6.Before entering this processing, in the frequency synthesizer of this embodiment 6, identical with the situation of above-mentioned each embodiment, by input unit 4 Dout, Dr, Dd are input to parameter computing configuration part 31, and obtaining each setup parameter k, R, N, frequency setting parameter k is output in the determination flag efferent 35.
At first, in determination flag efferent 35a, when from parameter computing configuration part during 31 incoming frequency setup parameter k (step S630), memory 32d is carried out access, read the number of times mi (step S632) of high level of the spurious clutter of address i (initial value is i=0), k and mi substitution formula (16), compare (step S634) with Δ fpl1/fck.
Its result, when being | (mi ± 1) k/2 L-round[kmi/2 L] | during＜Δ fpl1/fck (step S634 " YES "), expression is not exported high spurious clutter with the number of times mi of this spurious clutter from PLL2, therefore, set 0 (step S636), this determination flag h=0 is exported to parameter computing configuration part 31 (step S644) as determination flag h.
In contrast, when being | (mi ± 1) k/2 L-round[kmi/2 L] | during 〉=Δ fpl1/fck (step S634 " NO "), expression is not exported high spurious clutter with the number of times mi of this spurious clutter from PLL2, therefore, owing to the number of times mi that judges whether not judge as yet, then whether the address i of the number of times mi of this judgement of judgement is less than its maximum q (step S638).Under the situation of address i (step S638 " YES ") less than its maximum q, will remain the number of times mi of the spurious clutter of not judging, therefore, address i is increased (step S640), carry out above-mentioned steps S632 according to new address i, the processing of S634, on the other hand, when address i becomes (step S638 " NO ") when equaling this maximum q,, finish to judge to being stored in the whole number of times mi among the memory 32d, but, owing in these whole number of times mi, can not export high spurious clutter, therefore from PLL2, set 1 (step S642) as determination flag, this determination flag h=1 is exported to parameter computing configuration part 31 (step S644).
Like this, frequency synthesizer according to this embodiment 6, identical with the foregoing description 2～5, if being input to the parameter arithmetic processing section 3d with should be from the output frequency fout of PLL2 output corresponding data Dout etc., parameter arithmetic processing section 3d automatically obtains each setup parameter k, R, N also sets to DDS12 etc., thereby, at setup parameter k, R, do not spend time in the setting of N, simultaneously, obtaining each setup parameter k, R, during N, judge that setup parameter k is whether consistent with the high characteristic frequency setup parameter ks of spurious clutter level, and can avoid in advance the high characteristic frequency setup parameter ks of spurious clutter is exported to DDS12, so the low spurious clutterization that just can seek frequency synthesizer.
In the frequency synthesizer of this embodiment 6, owing in memory 32d, stored the number of times of the high spurious clutter in the output that appears at DDS12, and carry out the judgement of frequency setting parameter according to this number of times, therefore, compare with the situation of embodiment 2～5, can cut down the capacity of memory 32d significantly.Its result owing to can use memory cheaply by the reduction of memory span, just can seek the reduction of manufacturing cost.Particularly, the number of the number of times m of the spurious clutter of high spurious clutter output like this is very limited as shown in Figure 46, thus, generally, just do not need to be provided for to store the private memory of the number of times m of this spurious clutter, because if be stored in other the clear area of memory just enoughly, then, private memory can reduce manufacturing cost because of not being set.
Embodiment 7
The frequency synthesizer of embodiment 7, the low spurious clutter DDS of two mode of resonance as the MW94-156 of the electronic communication association frequency of utilization converter delivered the applicant drives the PLL synthesizer " put down in writing like that, simplified the judgement that whether the frequency setting parameter k of the DDS in narrow synthesizer (Δ fd/fck=0.04% in above-mentioned document) is not corresponded to the ks that uprises of spurious clutter level to the amplitude of variation Δ fd of the output frequency fd of DDS.
Thus, in the frequency synthesizer of this embodiment 7, only the formation of parameter arithmetic processing section 3 is different with the foregoing description 2～6, therefore, the formation and the action of parameter arithmetic processing section 3 is described mainly.
Figure 18 represents the formation of the parameter arithmetic processing section 3e of this embodiment 7.In the drawings, the 31st, parameter computing configuration part same as the previously described embodiments, 35b is the determination flag efferent, the setup parameter k that exports for judgement according to parameter computing configuration part 31 judges whether this setup parameter k does not correspond to the characteristic frequency setup parameter ks of the high spurious clutter of output, and this result of determination is exported as determination flag h.
Below, the resolution principle of the determination flag efferent 35b of this embodiment 7 is described.
The relation of the characteristic frequency setup parameter ks of the frequency setting parameter k of DDS12 when the amplitude of variation Δ fd of output frequency fd of DDS12 is very narrow and the DDS12 that spurious clutter becomes high level at first, is described.
As explanation in Figure 44 and the foregoing description 6, it is exactly that the number of times of spurious clutter is when being specific number of times m that spurious clutter becomes high level.When the amplitude of variation Δ fd of the output frequency fd of DDS12 was limited to more in the narrow-band, the number of times m (hereinafter referred to as ms) that spurious clutter becomes high level was further limited.Thus, at first, suppose that ms is one, with reference to formula (3) and formula (1) and near the ks of the spurious clutter frequency f dds that obtains this specific number of times ms when the output frequency fd of DDS12, being fd ≈ fdds, and become so followingly, represent by formula (17):
fd≈fdds
fd?≈|ms·fd-n·fck|
ks·fck/2 L≈|ms·ks·fck/2 L-n·fck|
ks≈|ms·ks-n·2 L|
ks≈2 L·n/(ms±1) …(17)
Figure 19 (a) and (b) are represented the appearance situation of the characteristic frequency setup parameter ks among the frequency setting parameter k.
(a) the appearance situation of expression number of times ms ks in any case as shown in the figure, on the order of harmonic n of the output frequency fck of each reference clock 11, two ks=2 occur L(n/ms ± 1).And, near ks, spurious clutter be in PLL2 pass through export from PLL2 in the frequency band Δ fp11.
(b) expression ms " 1 o'clock the appearance situation of ks, because situation (b) is ms " 1, different with the situation shown in (a), see 2 as LN/ (ms+1) ≈ 2 LN/ (ms-1), 2 LN/ (ms ± 1) is looked at as a bit.When the spurious clutter that makes this moment is the scope of the frequency setting parameter k of high level when being Δ kz, (b) the Δ kz shown in appears among the cycle kpd, and this kpd is provided by following formula:
Kpd=2 L/ ms (still, be ms " 1) ... (18)
This formula (18) substitution formula (17), when cancellation ms, frequency n is following formula (19):
n＝int[k/k?pd] …(19)
Below, k is present in the Δ kz, and the conditional that promptly is used to export the k of high spurious clutter is provided by following formula (20):
|k-n·kpd|＜Δkz/2 …(20)
If wushu (18) and formula (19) this formula of substitution (20), the conditional that is used to export the k of high spurious clutter is provided by following formula (21): int[msk/2 L] 2L/ms-Δ kz/2≤k≤int[msk/2 L] 2 L/ ms+ Δ kz/2
…(21)
Below, the action of the frequency synthesizer of this embodiment 7 is described with reference to accompanying drawing.
Figure 20 represents the handling procedure before the determination flag output among the determination flag efferent 35b of this embodiment 7.Before entering this processing, identical with the situation of above-mentioned each embodiment, Dout, Dr, Dd are transfused to parameter computing configuration part 31, and obtain each setup parameter k, R, N, and frequency setting parameter k is output in the determination flag efferent 35.
At first, when determination flag efferent 35b from parameter computing configuration part during 31 incoming frequency setup parameter k (step S650), specific number of times ms substitution formula (18) is obtained kpd (step S652), then this k and kpd substitution formula (19), and calculating n (step S654), then, k, Δ kz and ms substitution formula (21) and to judge whether to satisfy this formula (21) be whether k is present among the Δ kz, whether high spurious clutter is output (step S656).
Its result is when judgement is int[msk/2 L] 2 L/ ms-Δ kz/2≤k≤int[msk/2 L] 2 LDuring/ms+ Δ kz/2 (step S656 " YES "), k is present in the Δ kz, under this setup parameter k, high spurious clutter is exported from PLL2, therefore, set 0 (step S658), determination flag h=0 is exported to parameter computing configuration part 31 (step S662) as determination flag h.
Otherwise, when being judged as int[msk/2 L] 2 L/ ms-Δ kz/2＞k or k＞int[msk/2 L] 2 LDuring/ms+ Δ kz/2, (step S656 " NO "), k is not present in the Δ kz, under this setup parameter k, high spurious clutter is not from PLL2 output, therefore, set 1 (step S660) as determination flag h, determination flag h=1 is exported to parameter computing configuration part 31 (step S662).
Like this, frequency synthesizer according to this embodiment 7, identical with the foregoing description 2～6, if being input to the parameter arithmetic processing section 3e from the pairing data Dout of output frequency fout of PLL2 output etc., parameter arithmetic processing section 3e automatically obtains each setup parameter k, R, N also sets to DDS12 etc., thereby, at setup parameter k, R, do not spend time in the setting of N, simultaneously, obtaining each setup parameter k, R, during N, judge that setup parameter k is whether consistent with the high characteristic frequency setup parameter ks of spurious clutter level, and can avoid in advance the high characteristic frequency setup parameter ks of spurious clutter is exported to DDS12, so the low spurious clutterization that just can seek frequency synthesizer.
Particularly, in the frequency synthesizer of this embodiment 7, because the amplitude of variation Δ fd of the output frequency fd of DDS12 is limited in the narrow-band, and further limit the number of times m and the characteristic frequency setup parameter ks of high spurious clutter, therefore, just be not provided for storing the memory of determination flag h and number of times m, only just can carry out the judgement of frequency setting parameter k by determination flag efferent 35b, compare with the situation of the foregoing description 2～6, do not need memory, just can seek to reduce by a larger margin manufacturing cost.
In the explanation of this embodiment 7, though the quantity of the number of times m of the spurious clutter of the high spurious clutter of output is described as one,,, also can play effect same as described above if be a plurality of.
Embodiment 8
In the foregoing description 2～7, expressed: in case determine under the situation of output frequency of DDS12, thereafter, the determining method of the frequency setting parameter k under the situation that this output frequency is fixed etc. and formation thereof etc.
In contrast, in the frequency synthesizer of this embodiment 8, at first, as such at the frequency synthesizer shown in the flat 6-23579 communique of Japanese patent application of the applicant's application, when transmission and reception apparatus that frequency synthesizer is used for wireless communication system etc., add the automatic frequency control apparatus (hereinafter referred to as " AFC ") that is used for transmission frequency is synthesized to the receive frequency of receiving system side, in case after having determined the output frequency fout of its frequency synthesizer, only scan the output frequency of DDS and finely tune by AFC.
Figure 21 represents the formation of the frequency synthesizer of this embodiment 8.As seeing from Figure 21, the formation of the frequency synthesizer of this embodiment 8 is to append AFC5 between reference oscillator same as the previously described embodiments 1 and the parameter arithmetic processing section 3f and the output of AFC5 is being added to adder 6 on the frequency setting parameter k of autoregressive parameter arithmetic processing section 3.
In above-mentioned such radio communication device (not shown), AFC5 send or the fine setting of receive frequency so that the receive frequency of corresponding wireless device is consistent with the transmission frequency of local exchange, therefore, in this embodiment 8, its constitute by adder 6 change should set to DDS12 frequency setting parameter k, thus, the output frequency fd of fine setting DDS12.The part identical with the structure of embodiment 2 shown in Figure 2 uses same numeral to describe.
Figure 22 represents the formation of the parameter arithmetic processing section 3f of this embodiment 8.In the drawings, the 31st, parameter computing configuration part same as the previously described embodiments, 32f is a memory of storing the number of times m of the high spurious clutter in the output that appears at DDS12 in advance, 35c is the determination flag efferent, judge according to the spurious clutter number of times m that is stored among this memory 32f whether frequency setting parameter k does not correspond to the high ks of spurious clutter level, and this result of determination is exported as determination flag h.
The following describes the resolution principle whether frequency setting parameter k in the determination flag efferent 35 of this embodiment 8 does not correspond to ks.
At first, when making maximum scan amplitude by the frequency setting parameter k of the DDS12 of scannings such as AFC5 be Δ k, from kmin (=k-Δ k/2) in the scope of k max (=k+ Δ k/2), become the output frequency fd of the frequency f dds of spurious clutter of high level and DDS12 approaching become fd ≈ fdds the time the condition of fd provide by following formula (22):
kmin·fck/2 L＜fd＜kmax·fck/2 L … (22)
In formula (3), fdds is replaced as fd and this formula of substitution (22) below,, is following formula (23) if use when representing at the conditional of the number of times m of spurious clutter at fdds:
n·2 L/kmax±1＜m＜n·2 L/k?min±1 … (23)
Wherein, because m is an integer, if consider this point, formula (23) becomes following formula (24):
int[n·2 L/kmax±1]＜m＜round[0.5+n·2 L/kmin±1… (24)
Like this, under the number of times m of the spurious clutter that satisfies this formula (24), when spurious clutter is high level, when in the scope from kmin to kmax, frequency setting parameter k being changed by AFC5, owing to high spurious clutter in the output of DDS12, occurred, by under the number of times of high spurious clutter, whether satisfying this formula (24), just can judge that whether frequency setting parameter k is corresponding to ks.
Figure 23 represents the memory contents of the memory 32f of embodiment 8.The memory contents of this memory 32f, identical with shown in the embodiment 6 shown in Figure 16 is by 2,3,4 ... login address (i=0,1 in advance at each memory 32f, 2 ..., appear at the number of times mi of the above high spurious clutter of predetermined level in the output of DDS12 in q).
The action of the frequency synthesizer of this embodiment 8 is described with reference to the accompanying drawings.
Figure 24 represents the handling procedure before the determination flag output among the determination flag efferent 35c of this embodiment 8.Before entering this processing, in the frequency synthesizer of this embodiment 8, identical with the situation of above-mentioned each embodiment, in parameter computing configuration part 31, Dout etc. are transfused to parameter computing configuration part 31, and obtaining each setup parameter k, R, N, frequency setting parameter k is exported to determination flag efferent 35.
At first, when determination flag efferent 35c imports the frequency setting parameter k of autoregressive parameter computing configuration part 31 (step S670), obtain kmin and kmax (step S672) according to the maximum scan amplitude, ao k of the frequency setting parameter k of the DDS12 that produces by the control of AFC5.Wherein, Δ k is for to sign in among the determination flag efferent 35c in advance.
Then, determination flag efferent 35c reads the number of times mi (step S674) of spurious clutter according to the address i (initial value is 0) of memory 32f, simultaneously, the order of harmonic n of the output frequency fck of reference clock 11 is set at n=0 (step S676), and whether whether the number of times mi of the spurious clutter that judgement is read satisfies formula (24) is promptly satisfied iht[n2 L/ kmax ± 1]＜mi＜round[0.5+n2 L/ kmin ± 1) (step S678).
Wherein, when the number of times mi that is judged to be the spurious clutter of reading satisfies formula (24) (step S678 " YES "), when frequency setting parameter k is changed in the scope from kmin to kmax, high spurious clutter appears in the output of DDS12, thus, determination flag h is set at 0 (the step S680) that the situation of high spurious clutter has been exported in expression, determination flag h=0 is exported to parameter computing configuration part 31 (step S692).
Opposite with it, when the number of times mi that is judged to be the spurious clutter of reading does not satisfy formula (24) (step S678 " NO "), whether then judge mi≤round[0.5+n2 L/ kmin ± 1 or mi≤int[n2 L/ kmax ± 1] (step S682), at mi 〉=round[0.5+n2 L/ kmin ± 1) and mi 〉=int [n2 L/ kmax ± 1] time (step S682 " NO "), owing to the value that has changed n is judged again,, turn back to the processing of step S678 as n=n+1 (step S684), judge once more under new n value whether the number of times mi of spurious clutter satisfies formula (24).
On the other hand, at mi≤round[0.5+n2 L/ kmin ± 1) or mi≤int[n2 L/ kmax ± 1] (step S682 " YES "), owing to do not satisfy the mi and the n of formula (24), judgement judges whether finish to the number of times mi of whole spurious clutters, thus, whether then judge address i less than its maximum q (step S686), during less than its maximum q (step S686 " YES "), address i is added+1 (step S688) at address i, return step S674, carry out processing same as described above from the number of times mi that memory 32f reads next spurious clutter according to new address i.Otherwise, when address i equals its maximum q (step S686 " YES "), because whole mi and n do not satisfy formula (24), determination flag h is set at 1 (the step S690) that the situation of high spurious clutter is not exported in expression, determination flag h=1 is exported to parameter computing configuration part 31 (step S692).
Like this, frequency synthesizer according to this embodiment 8, identical with the foregoing description 2～7, if being input to the parameter arithmetic processing section 3f from the pairing data Dout of output frequency fout of PLL2 output etc., parameter arithmetic processing section 3f automatically obtains each setup parameter k, R, N also sets to DDS12 etc., thereby, at setup parameter k, R, do not spend time in the setting of N, simultaneously, obtaining each setup parameter k, R, during N, judge that setup parameter k is whether consistent with the high characteristic frequency setup parameter ks of spurious clutter level, and can avoid in advance the high characteristic frequency setup parameter ks of spurious clutter is exported to DDS12, so the low spurious clutterization that just can seek frequency synthesizer.
In the frequency synthesizer of this embodiment 8, identical with the foregoing description 6, owing in memory 32f, only stored the number of times m of the high spurious clutter in the output that appears at DDS12, and carry out the judgement of frequency setting parameter according to this number of times m, therefore, compare with the situation of embodiment 2～5, can cut down the capacity of memory 32f significantly.Its result, identical with the foregoing description 6, owing to can use memory cheaply, just can seek the reduction of manufacturing cost by the reduction of memory span.
Embodiment 9
The frequency synthesizer of this embodiment 9, with respect to the foregoing description 2, simplified setup parameter k, the R of step S80 shown in Figure 5, the calculation process again of N, the best recruitment of storing setup parameter R, N in memory in advance uses memory to obtain k, R, N simply.Thus, in the frequency synthesizer of this embodiment 9 since structure except the parameter arithmetic processing section roughly the formation with embodiment 2 shown in Figure 1 is identical, then illustrate parameter arithmetic processing section and parameter thereof calculation process etc. again.
Figure 25 represents the formation of the parameter arithmetic processing section 3g of this embodiment 9.In the drawings, 31a is parameter computing configuration part, the memory 32a of 32g and the foregoing description 3 is identical to be the memory of storing determination flag h in advance, this determination flag h representative in each frequency setting parameter k its k whether corresponding to the ks of the high spurious clutter of output, the 36th, by the following best recruitment α of setup parameter R, N, the memory of β stored in advance like that.
Figure 26 represents the content of the memory 36 of this embodiment 9.As shown in Figure 26, recruitment α, the β of R and N in advance in this memory 36, wherein with 15 bit table current addresses, simultaneously, make 5 setup parameter k, R, N correspond respectively to the last bit address of this memory 35, middle bit address, following bit address, to the combination of each setup parameter k, R, N, in each setup parameter k, R, N, under the situation of i.e. this setup parameter k of the best, make this k and ks inconsistent.For example, be respectively at setup parameter k, R, N under 00010,00010,00010 the situation, as best recruitment α, the β of this setup parameter R, N, corresponding to 00010,00010.Below with best recruitment α, the β of α (k, R, N), β (k, R, N) expression corresponding to setup parameter R, the N of setup parameter k, R, N.
The action of the frequency synthesizer of this embodiment 9 is described with reference to the accompanying drawings.
Figure 27 represents the parameter calculation process again among the parameter modification device 315a of parameter computing configuration part 31a.
In the frequency synthesizer of this embodiment 9, before beginning this parameter calculation process shown in Figure 27, identical with the foregoing description 2, obtain setup parameter k, R, N with the processing of step S10 shown in Figure 5～50, whether carry out this setup parameter k that obtains in the step S60 that follows is the judgement of the ks (step S60 " NO ") of the high level of spurious clutter, the result of its judgement is judged to be k=ks, and begins this parameter shown in Figure 27 calculation process again.
At first, begin this parameter when becoming k=ks again during calculation process, parameter modification device 315a, at first with as last bit address, middle bit address, the address of bit address is accessed in setup parameter k, R, the N of being obtained in the processing of step S20～50 of Fig. 5 respectively in memory 36 down, reads recruitment α (k, R, N) and β (k, R, N) (step S840) corresponding to setup parameter R, the N of this setup parameter k, R, N.Then, as shown in the formula shown in (25) like that, recruitment α that reads (k, R, N) and β (k, R, N) are added to respectively on setup parameter R, the N, and change setting parameters R, N (step S850,860).
R＝R+α(k、R、N)
N＝N+β(k、R、N) …(25)
Then, identical R and the N that the such quilt shown in this formula (25) changes with the situation of embodiment 2, substitution formula (8), setup parameter k is carried out the such computing again (step S870) of following formula (26):
K=int[(RDout2 L)/(fckN)] or
k＝round[(R·Dout·2 L)/(fck·N)] …(26)
Like this, though make setup parameter k, R, N carry out computing again and change, but, because by changing R and N for such α (k, R, N) and the β (k, R, N) of k ≠ ks, and make k become k ≠ ks, therefore, different with the situation of embodiment 2 shown in Figure 5, do not turn back to the determination processing of the setup parameter k of step S60, and directly transfer to setup parameter k, the R of step S70, the output setting processing of N.
Like this, frequency synthesizer according to this embodiment 9, identical with the foregoing description 2～8, if being input to the parameter arithmetic processing section 3g with should be from the output frequency fout of PLL2 output corresponding data Dout etc., parameter arithmetic processing section 3g automatically obtains each setup parameter k, R, N also sets to DDS12 etc., thereby, at setup parameter k, R, do not spend time in the setting of N, simultaneously, obtaining each setup parameter k, R, during N, judge that setup parameter k is whether consistent with the high characteristic frequency setup parameter ks of spurious clutter level, and can avoid in advance the high characteristic frequency setup parameter ks of spurious clutter is exported to DDS12, so the low spurious clutterization that just can seek frequency synthesizer.
In the frequency synthesizer of this embodiment 9, recruitment α, the β of stored parameter R and N in advance in memory 36, so that parameters R and N the best, be that setup parameter k and ks are inconsistent, and can not export high spurious clutter from PLL2, under setup parameter k and the corresponding to situation of ks, according to best recruitment α, the β of this storage and change setting parameter k, R, N, therefore, the change of setup parameter k, R, N is only carried out once getting final product, and just can seek to shorten the needed time in the change of setup parameter k, R, N.Its result has the effect of the speed that the frequency of quickening frequency synthesizer switches.
In the frequency synthesizer of this embodiment 6, though be to have changed R and N,, also can store the side's of N or R best recruitment in advance, one side changes by increase and decrease.
Embodiment 10
In the foregoing description 2～9, parameter arithmetic processing section 3 is also imported except input and should be from the output frequency fout that PLL2 exports corresponding data Dout corresponding to the data Dr of the output frequency fr of variable frequency divider 13 and the data Dd corresponding with the output frequency fd of DDS12, to these setup parameters k, R, N carries out computing, simultaneously, under the ks corresponding to situation of setup parameter k with high spurious clutter output, further carry out each setup parameter k, R, the computing again of N, under k and the inconsistent situation of ks, export each setup parameter k, R, N, but, in the parameter arithmetic processing section, certainly exist setup parameter k, R, long-timeization of the operation time that computing and computing again produced of N and the complicated problem of circuit.
Therefore, in the frequency synthesizer of this embodiment 10, replace the parameter arithmetic processing section to solve related problem by using memory.
Figure 28 represents the formation of the frequency synthesizer of this embodiment 10.In Figure 28, the 1st, reference oscillator, the 2nd, PLL, 4b be only import with should be from the output frequency fout of PLL2 output the input unit of corresponding data Dout, 7 be illustrated in fig. 29 shown below be like that store in advance with corresponding to the data Dout of this output frequency fout corresponding setup parameter k, R, the memory of N.In Figure 28, the part identical with the formation of Fig. 1 used identical label, and omits its explanation.
Figure 29 represents the memory contents of the memory 7 of this embodiment 10.In this memory 7, as shown in the figure, with with the corresponding data Dout of the output frequency fout of the PLL2 of 5 bit representations as the address, storing for make each corresponding to not exporting high spurious clutter among the data Dout of output frequency fout setup parameter k, the R that considers, the value of N.The value of each setup parameter k, R, N according to formation of frequency synthesizer shown in Figure 28 etc., is obtained accordingly in advance with the data Dout of corresponding each output frequency fout.
Below, the action of the frequency synthesizer of this embodiment 10 is described with reference to accompanying drawing.
Figure 30 illustrates the action of the frequency synthesizer of this embodiment 10.
At first, when input unit 4 from memory 7 input (step S100) corresponding to should be the time from the data Dout of the output frequency fout of PLL2 output, from memory 7 read these data Dout as the address promptly corresponding to setup parameter k, R, the N (step S110) of these data Dout, setup parameter k, the R that is read, N export to the variable frequency divider 24 of the DDS12 of reference oscillator 1 and variable frequency divider 13, PLL2 respectively and are set (step S120).
Wherein, this setup parameter k, R, N are according to formation of frequency synthesizer etc. and obtain in advance, so that among each data Dout, can not export high spurious clutter corresponding to the output frequency fout that should export from PLL2, therefore, frequency synthesizer becomes: as such setup parameter k, R, when N is set, the Dout of input is exported as output frequency fout, can not export high spurious clutter from PLL2.
Like this, frequency synthesizer according to this embodiment 10, in memory 7, be stored in each in advance corresponding to the setup parameter k that should from the data Dout of the output frequency fout of PLL2 output, can not export high spurious clutter, R, N, under the situation of input unit 4 inputs corresponding to the data Dout of this output frequency fout, owing to exported setup parameter k corresponding to this Dout, R, N does not just need to carry out the setup parameter k corresponding to Dout etc. in that frequency synthesizer is inner, R, the computing of N and the judgement and the setup parameter k that are used for setup parameter k, R, the computing again of the change of N.
Thus, frequency synthesizer according to this embodiment 10, o'clock different with embodiment 2～9, the parameter arithmetic processing section 3 that need be made of DSP and CPU etc. does not constitute, make structure become simple, simultaneously since need be in the change of setup parameter k, R, N the needed time, just can seek to shorten the time that is used for parameter setting.Its result just can quicken the speed that the frequency of frequency synthesizer is switched.
Though, explanation is in the above description, imagination has the frequency synthesizer of a variable frequency divider 13 in reference oscillator 1, and in memory 7 storage a setup parameter R corresponding to this variable frequency divider of one 13, but, in the present invention, also n platform variable frequency divider 13 can be arranged in reference oscillator 1 as shown in Figure 7, in the case, can in memory 7, store the parameter of k, N and R1～Rn in advance.
Embodiment 11
The frequency synthesizer of this embodiment 11 is by being provided with frequency mixer equifrequent synthesizer between DDS in reference oscillator and the variable frequency divider, and changed the formation of the reference oscillator in the foregoing description 2～10, to seek the spurious clutterization lower than embodiment 2～10, therefore, go for the frequency synthesizer of the foregoing description 2～10.Below the situation that the reference oscillator of embodiment 11 is used for the reference oscillator of embodiment 2 is described.
In this embodiment 11, because the formation of reference oscillator is different with embodiment 2, the arithmetic expression of setup parameter k, R, N is different with the arithmetic expression again of setup parameter k, R, N, thereby, be that the center describes with the difference of these formulas.
Figure 31 represents the formation of the frequency synthesizer of this embodiment 11.In the frequency synthesizer of this embodiment 11,, then use identical label and omit its explanation because the formation of PLL2, parameter arithmetic processing section 3 and input unit 4 except that reference oscillator 1a is identical with the formation of the foregoing description 2.
The reference oscillator 1a of embodiment 11 and the foregoing description 2 be identical to have reference clock 11, DDS12, variable frequency divider 13, further has between DDS12 and variable frequency divider 13 simultaneously the frequency of oscillation of the output frequency fd of DDS12 and local oscillator 14 is carried out the frequency mixer 15 of mixing, exported BPF16, the amplifier (AMP) 17 of removing unwanted ripple from this mixing.The BPF18 of the high order harmonic component that suppresses variable frequency divider 13 is set at the back segment of variable frequency divider 13.Among the figure, f1 is the incoming frequency to variable frequency divider 13, and fxo is the output frequency of local oscillator 14.
Below, according to the reference oscillator 1a of this embodiment 11, seek to be lower than the content of the spurious clutterization of embodiment 2～10 with algebraic expression explanation.
At first, in the foregoing description 2, if making the spurious clutter level of DDS12 is SPdds (dBc), the spurious clutter level SPout that exports from the synthesizer of the final output of PLL2 is following formula (27):
SPout＝20·LOG 10(fout/fd)+SPdds(dBc) …(27)
Opposite with it, in this embodiment 11, the spurious clutter level SPout from the synthesizer of the final output of PLL2 is exported when the incoming frequency that makes variable frequency divider 13 is f1, is following formula (28):
SPout＝20·LOG 10(fout/f1)+SPdds(dBc) …(28)
Like this, find out, by the frequency translation of frequency mixer 15 generations, if f1 from this formula (28) " fd, then become 20LOG 10(fout/fd) " 20LOG 10(fout/f1), therefore, make the low spurious clutterization of spurious clutter level SPout of the frequency synthesizer of this embodiment 11.
The action of the parameter setting of the parameter arithmetic processing section 3 among this embodiment 11 is with the shown in Figure 5 program behavior identical with the foregoing description 2, therefore, omit its explanation, at this, exposed installation is decided change place of the calculating formula of parameter k, R, N by the formation of change reference oscillator 1 on embodiment 2.
At first, identical with the formula (5) of embodiment 2 under the situation of this embodiment 11 with formula (7), obtain parameters R, N as divider ratio.
Below, in order to obtain setup parameter k, at first, obtain D ' d from Dout, R and N by following formula (29):
D’d＝Dout·R/N …(29)
From this formula (29), just can obtain output frequency data Dd with following formula (30) corresponding to the output frequency fd of the DDS12 that should import:
Dd＝|Dxo-D’d| …(30)
Wherein, Dxo is corresponding to the output frequency data of the output frequency fxo of local oscillator 14, offers parameter arithmetic processing section 3 as data in advance.
Thus, in this embodiment 11, the frequency setting parameter k of DDS12, the formula during with embodiment 2 (8) is different, becomes by following formula (31) like that, compares with the situation of the embodiment 2 that is provided by formula (8), has improved the degree of freedom of the setting of setup parameter k:
K=int[(2 L/ Dck) | (DoutR/N)-Dxo|] or
k＝round[(2 L/Dck)·|(Dout·R/N)-Dxo|] …(31)
The method of the change that is produced by the computing again of setup parameter k, R, N is identical with the foregoing description 2, at first by α, β being added to change parameter R, N on parameters R, the N respectively, and by after changing parameters R, N substitution formula (31), and change setting parameter k.
Like this, frequency synthesizer according to this embodiment 11, by appending frequency mixer 15 etc. between DDS12 in reference oscillator 1 and the variable frequency divider 13, compare during with embodiment 2, improved the degree of freedom of setting of the frequency setting parameter k of DDS12, therefore, with regard to each setup parameter k of the spurious clutter that is used to avoid high level easily, the setting of R, N.
In the above description, though what illustrate is: as shown in Figure 31, the local oscillator 14 of frequency mixer 15 and the reference clock 11 of DDS12 are set respectively in reference oscillator 1a, but, also can be as shown in Figure 32, only as reference clock 11, and in DDS12 and frequency mixer 15, can use the output of reference clock 11 to the oscillator in the reference oscillator 1b.In the case, just there is no need in reference oscillator 1b, to be provided with local oscillator 14, just can reduce the number of oscillator, therefore, just can seek to be lower than the costization of situation shown in Figure 31.
Embodiment 12
The frequency synthesizer of this embodiment 12 is identical with the foregoing description 11, changed the formation of the reference oscillator in the foregoing description 2～10, to seek the spurious clutterization lower, therefore, go for the frequency synthesizer of the foregoing description 2～10 than embodiment 2～10.Below to the situation in the reference oscillator that is configured for embodiment 2 of the reference oscillator of the frequency synthesizer of embodiment 12 is described.
In the frequency synthesizer of this embodiment 12, because the formation of reference oscillator is different with embodiment 2, the arithmetic expression of setup parameter k, R, N is different with the arithmetic expression again of setup parameter k, R, N, thereby, be that the center describes with these differences.
Figure 33 represents the formation of the frequency synthesizer of this embodiment 12.In this embodiment 12,, then use identical label and omit its explanation because the formation of PLL2, parameter arithmetic processing section 3 and input unit 4 except that reference oscillator 1c is identical with the formation of the foregoing description 2.
The reference oscillator 1c of embodiment 12 has reference clock 11, DDS12, variable frequency divider 13, and simultaneously the back segment at variable frequency divider 13 further is in series with: suppress the high order harmonic component of variable frequency divider 13 BPF18, the output frequency fdiv of the variable frequency divider 13 by BPF18 and the frequency of oscillation fxo of local oscillator 15 are carried out BPF16, the amplifier (AMP) 17 that mixing is carried out the frequency mixer 16 of frequency translation, removes unwanted ripple from this mixing is exported.
Below, according to the reference oscillator 1c of this embodiment 12, seek to be lower than the content of the spurious clutterization of embodiment 2～10 with algebraic expression explanation.
At first, in the formation of the foregoing description 2, if making the spurious clutter level of DDS12 is SPdds (dBc), the spurious clutter level SPout that exports from the synthesizer of the final output of PLL2 is provided by formula (27).
Opposite with it, in the frequency synthesizer of this embodiment 12, the spurious clutter level SPout from the synthesizer of the final output of PLL2 is exported when the output frequency that makes frequency mixer 15 is fr, is following formula (32):
SPout＝20·LOG 10(fout/R·fr)+SPdds(dBc) …(32)
Like this, find out, by the frequency translation of 15 grades of the frequency mixer in the back segment that is located at variable frequency divider 13 generation, if be transformed into fr from this formula (32) " fd, and become 20LOG 10(fout/fd) " 20LOG 10(fout/Rfr), therefore, compare with the spurious clutter level SPout of embodiment 2, the spurious clutter level SPout of this embodiment 12 hangs down spurious clutterization.
The action of the parameter setting of the parameter arithmetic processing section 3 among this embodiment 12 is with the shown in Figure 5 program behavior identical with the foregoing description 2, therefore, omit its explanation, at this, exposed installation is decided change place of the calculating formula of parameter k, R, N by the formation of change reference oscillator 1 on embodiment 2.
At first, under the situation of this embodiment 12, equally obtain parameter N and D ' r as divider ratio from the formula (5) of embodiment 2 and formula (6).Then obtain Ddiv corresponding to the output frequency fdiv of variable frequency divider 13 by following formula (33):
Ddiv＝|D’r-Dxo| …(33)
Because parameters R is provided by the formula (7) of embodiment 2, the frequency setting parameter k of DDS12 then, the formula during with embodiment 2 (8) is different, becomes by following formula (34) such, compare with the situation of the embodiment 2 that is provided by formula (8), improved the degree of freedom of the setting of setup parameter k:
K=int[(2 LR/Dck) | (Dout/N)-Dxo|] or
k＝round[(2 L·R/Dck)·|(Dout/N)-Dxo|]?…(34)
The method of the change that is produced by the computing again of setup parameter k, R, N is identical with the foregoing description 2, at first by α, β being added to change parameter R, N on parameters R, the N respectively, and by after changing parameters R, N substitution formula (34), and change setting parameter k.
Like this, frequency synthesizer according to this embodiment 12, append frequency mixer 16 etc. in the back segment by the variable frequency divider in reference oscillator 1 13, frequency division is carried out in the output of DDS12, further constitute reference oscillator 1c so that by frequency mixer 16 conversion that makes progress, therefore, the high spurious clutter that not only can suppress DDS12, and, compare during with embodiment 2, in the power consumption that has reduced DDS12, improved the degree of freedom of setting of the frequency setting parameter k of DDS12, therefore, with regard to each setup parameter k of the spurious clutter that is used to avoid high level easily, R, the setting of N.
Owing to appended frequency mixer 16 etc. in the back segment of the variable frequency divider 13 in reference oscillator 1, can not improve the operating frequency of DDS12, and can improve the incoming frequency of giving PLL2, therefore, have the effect of the frequency multiplication number that can reduce PLL2.
In the above description, though what illustrate is: as shown in Figure 33, the local oscillator 15 of frequency mixer 16 and the reference clock 11 of DDS12 are set respectively in reference oscillator 1c, but, also can be as shown in Figure 34, oscillator in the reference oscillator 1d only as reference clock 11, and is used the output of reference clock 11 in DDS12 and frequency mixer 15.In the case, just there is no need in reference oscillator 1d, to be provided with local oscillator 14, just can reduce the number of oscillator, therefore, just can seek to be lower than the cost of situation shown in Figure 33.
Embodiment 13
The frequency synthesizer of this embodiment 13 is identical with the foregoing description 11,12, changed the formation of the reference oscillator in the foregoing description 2～10, to seek the spurious clutterization lower, therefore, go for the frequency synthesizer of the foregoing description 2～10 than embodiment 2～10.Below to the situation in the reference oscillator that is configured for embodiment 2 of the reference oscillator of the frequency synthesizer of embodiment 13 is described.
In the frequency synthesizer of this embodiment 13, because the formation of reference oscillator 1 is different with embodiment 2, the arithmetic expression of setup parameter k, R, N is different with the arithmetic expression again of setup parameter k, R, N, thereby, be that the center describes with its difference.
Figure 35 represents the formation of the frequency synthesizer of this embodiment 13.In the frequency synthesizer of this embodiment 13,, then use identical label and omit its explanation because the formation of PLL2, parameter arithmetic processing section 3 and input unit 4 except that reference oscillator 1e is identical with the formation of the foregoing description 2.
The reference oscillator 1e of embodiment 13 has reference clock 11, DDS12, two variable frequency divider 13r1,13r2, further has between variable frequency divider 13r1 and variable frequency divider 13r2 simultaneously: suppress the high order harmonic component of variable frequency divider 13r1 BPF18a, the output frequency of the variable frequency divider 13r1 by BPF18a and the frequency of oscillation fxo of local oscillator 14 are carried out BPF16, the amplifier (AMP) 17 that mixing is carried out the frequency mixer 15 of frequency translation, removes unwanted ripple from the mixing of frequency mixer 15 is exported.The BPF18b that has the high order harmonic component that suppresses variable frequency divider 13r2 at the back segment of variable frequency divider 13r2.Among the figure, fxo is the output frequency of local oscillator 15, and f2 is the incoming frequency to variable frequency divider 13r2.BPF18a, 18b can be low pass filters.
Below, according to the reference oscillator 1e of the frequency synthesizer of this embodiment 13, seek to be lower than the content of the spurious clutterization of embodiment 2～10 with algebraic expression explanation.
At first, in the formation of the foregoing description 2, if making the spurious clutter level of DDS12 is SPdds (dBc), the spurious clutter level SPout of the synthesizer of final output output is provided by formula (27).
Opposite with it, in the formation of the frequency synthesizer of this embodiment 13, the spurious clutter level SPout of synthesizer output is following formula (35):
SPout＝20·LOG 10{fout/(R·|fxo±f2|)}+SPdds(dBc)
…(35)
Like this, find out, by being located at the frequency translation of frequency mixer 15 between variable frequency divider 13r1, the 13r2 etc., if be transformed into R|fxo ± f2| from this formula (35) " fd, and become 20LOG 10(fout/fd) " 20LOG 10Fout/ (R|fxo ± f2|) }, therefore, comparing with embodiment 2, the spurious clutter level SPout of this embodiment 13 is by low spurious clutterization.
The action of the parameter setting of the parameter arithmetic processing section 3 among this embodiment 13 is with the shown in Figure 5 program behavior identical with the foregoing description 2, therefore, omit its explanation, at this, exposed installation is decided change place of the calculating formula of parameter k, R, N by the formation of change reference oscillator 1e on embodiment 2.
At first, under the situation of this embodiment 13, obtain parameter N and D ' r as the divider ratio of the variable frequency divider 24 of PLL2 from the formula (5) of embodiment 2 and formula (6).Then obtain parameters R 2 as the divider ratio of variable frequency divider 13r2 by following formula (36):
R2=int[D ' r/D2] or R2=round[D ' r/D2] ... (36)
Wherein, D2 is the data corresponding to f2.And, when using R2, D2 is calculated and obtained D ' at 2 o'clock, become following formula (37):
D’2＝D’r/R2 …(37)
Thus, obtain parameters R 1 by following formula (38) as the divider ratio of variable frequency divider 13r1:
R1=int[D ' 2/Dd] or R1=round[D ' 2/Dd] ... (38)
Thus, the frequency setting parameter k of DDS12, the formula during with embodiment 2 (8) is different, becomes by following formula (39) givenly, and is compared by the situation of the given embodiment 2 of formula (8), has improved the degree of freedom of the setting of setup parameter k:
K=int[(2 LR1/Dck) | (DoutR2/N)-Dxo|] or
k＝round[(2 L·R1/Dck)·|(Dout·R2/N)-Dxo|]…(39)
The method of the change that is produced by the computing again of setup parameter k, R, N is identical with the foregoing description 2, at first by α, β being added to change parameter R, N on parameters R, the N respectively, and by after changing parameters R, N substitution formula (39), and change setting parameter k.
Like this, frequency synthesizer according to this embodiment 13, by 2 variable frequency divider 13r1 are set, 13r2, at this variable frequency divider 13r1, frequency mixer 15 etc. is set between the 13r2, frequency division is carried out in the output of DDS12, by frequency mixer 16 conversion that makes progress, and constitute reference oscillator 1c so that further carry out frequency division, therefore, not only can suppress the high spurious clutter of DDS12, and, compare during with embodiment 12, in the power consumption that has reduced DDS12, improved the degree of freedom of setting of the frequency setting parameter k of DDS12, therefore, with regard to each setup parameter k of the spurious clutter that is used to avoid high level easily, R, the setting of N.And, can not improve the operating frequency of DDS12, and improve the incoming frequency of giving PLL2, therefore, have the effect of the frequency multiplication number that can reduce PLL2.
In the above description, though what illustrate is: as shown in Figure 35, the local oscillator 14 of frequency mixer 15 and the reference clock 11 of DDS12 are set respectively in reference oscillator 1e, but, also can be as shown in Figure 36, only as reference clock 11, and in DDS12 and frequency mixer 15, also can use the output of reference clock 11 to the oscillator in the reference oscillator 1f.In the case, just there is no need in reference oscillator 1f, to be provided with local oscillator 14, just can reduce the number of oscillator, therefore, just can seek to be lower than the cost of situation shown in Figure 35.
Embodiment 14
The frequency synthesizer of this embodiment 14 is identical with the foregoing description 12,13, changed the formation of the reference oscillator in the foregoing description 1～10, to seek the spurious clutterization lower, therefore, go for the frequency synthesizer of the foregoing description 2～10 than embodiment 2～10.Below to the situation in the reference oscillator that is configured for embodiment 2 of the reference oscillator of the frequency synthesizer of embodiment 14 is described.
In the frequency synthesizer of this embodiment 14, because the formation of reference oscillator is different with embodiment 2, the arithmetic expression of setup parameter k, R, N is different with the arithmetic expression again of setup parameter k, R, N, thereby, be that the center describes with its difference.
Figure 37 represents the formation of the frequency synthesizer of this embodiment 14.In this embodiment 14, because the formation of PLL2 except that reference oscillator 1g and parameter arithmetic processing section 3 is identical with the formation of the foregoing description 2, the identical label of use and omit its explanation.
The reference oscillator 1g of embodiment 14 setting of in the back segment of DDS12, connecting: to the output frequency fd of DDS12 carry out the mixing conversion frequency mixer 15, suppress to be included in BPF16, the amplifier (AMP) 17 of the unwanted ripple in the output of frequency mixer 15, also have: variable frequency divider 13r1, the output frequency that makes amplifier 17 is the output frequency fr of PLL12, simultaneously, according to divider ratio setup parameter R1 the output wave of reference clock 11 is carried out the reference clock that frequency division becomes DDS12; With variable frequency divider 13r2, the output wave of local oscillator 14 is carried out frequency division and exports to frequency mixer 15 according to divider ratio setup parameter R2.
The action of the parameter setting of the parameter arithmetic processing section 3 among this embodiment 14 is with the shown in Figure 5 program behavior identical with the foregoing description 2, therefore, omit its explanation, at this, exposed installation is decided change place of the calculating formula of parameter k, R, N by the formation of change reference oscillator on embodiment 2.
At first, under the situation of this embodiment 14, obtain divider ratio N and D ' r as the variable frequency divider 24 of PLL2 from the formula (5) of embodiment 2 and formula (6).Then obtain parameters R 2 as the divider ratio of the variable frequency divider 13r2 of reference oscillator If by following formula (40):
R2=int[|D ' r-Dd|/D2] or
R2＝round[|D’r-Dd|/D2] …(40)
Then, obtain parameters R 1 by following formula (41) as the divider ratio of variable frequency divider 13r1a:
R1=int[Dck/D ' ck] or
R1＝round[Dck/D’ck] …(41)
Wherein, Dck is the data corresponding to reference clock fck, and D ' ck is the data corresponding to the output frequency of variable frequency divider 13a.D ' ck is stored in the parameter arithmetic processing section 3 in advance.
Its result, the frequency setting parameter k of DDS12, the formula during with embodiment 2 (8) is different, becomes by following formula (42) givenly, and is compared by the situation of the given embodiment 2 of formula (8), has improved the degree of freedom of the setting of setup parameter k:
K=int[(2 LR1/Dck) | (Dout/N)-Dxo/R2|] or
k＝round[(2 L·R1/Dck)·|(Dout/N)-Dxo/R2|]
…(42)
The method of the change that is produced by the computing again of setup parameter k, R, N is identical with the foregoing description 2, at first by α, β being added to change parameter R, N on parameters R, the N respectively, and by after changing parameters R, N substitution formula (42), and change setting parameter k.
Like this, frequency synthesizer according to this embodiment 14, frequency mixer 15 not only is set in reference oscillator 1g, and, variable frequency divider 13r1 is set between reference clock 11 and DDS12, simultaneously, between local oscillator 14 and frequency mixer 15, variable frequency divider 13r2 is set, thus, not only can suppresses the high spurious clutter of DDS12, and, compare during with embodiment 12, in the power consumption that has reduced DDS12, improved the degree of freedom of setting of the frequency setting parameter k of DDS12, therefore, with regard to each setup parameter k of the spurious clutter that is used to avoid high level easily, R, the setting of N.And, can not improve the operating frequency of DDS12, and improve the incoming frequency of giving PLL2, therefore, have the effect of the frequency multiplication number that can reduce PLL2.
In the above description, though what illustrate is: as shown in Figure 37, the local oscillator 14 of frequency mixer 15 and the reference clock 11 of DDS12 are set respectively in reference oscillator 1g, but, also can be as shown in Figure 38, oscillator in the reference oscillator 1h only as reference clock 11, and is used the output of reference clock 11 in DDS12 and frequency mixer 15.In the case, just there is no need in reference oscillator 1h, to be provided with local oscillator 14, just can reduce the number of oscillator, therefore, just can seek to be lower than the cost of situation shown in Figure 35.
The effect of invention
As described above, according to frequency synthesizer of the present invention, according to the second frequency synthesizer Output frequency is selected the frequency setting parameter of DDS so that do not export in the situation of high spurious clutter, Because can be according to this frequency setting parameter adjust frequency converter and second frequency synthesizer The setup parameter both sides are counted in conversion, the frequency setting parameter when then just the energy broadening is sought low spurious clutter Range of choice, the setting free degree of raising frequency parameter.
According to frequency synthesizer of the present invention, if input is corresponding to failing from the second frequency synthesizer The data of the output frequency that goes out are closed owing to can come computing should be set to second frequency according to these data Grow up to be a useful person, frequency changer and the parameters among the DDS of first frequency synthesizer and set, Setting operation corresponding to the parameter of output frequency fout is become easily.
In the present invention, when obtaining the frequency setting parameter, judge that whether this frequency setting parameter exists Exported more than the predetermined level from direct digital synthesiser in the output band of second frequency synthesizer High spurious clutter, be judged to be when having exported high spurious clutter, the change conversion count setup parameter and The frequency setting parameter is set then so that do not export high spurious clutter, thus, and just can be automatically Avoid exporting from the second frequency synthesizer the high frequency setting of the possibility of high spurious clutter The use of parameter makes the high spurious clutter that appears in the DDS output move on to out and away second frequency Outside the output band of synthesizer, and can seek low spurious clutter.
In the present invention, pre-stored in each should be set to frequency setting parameter among the DDS Whether exported the judgement that appears at the high spurious clutter the DDS output from the second frequency synthesizer Information, judge the frequency setting parameter whether in the output band of second frequency synthesizer from directly When digital synthesizer has been exported the above high spurious clutter of predetermined level, because according to this determination information And judge, therefore, compare with situation about judging by calculating etc., can be at high speed Judge, can seek to shorten the needed time in the change of each setup parameter, and tool The effect of accelerating the frequency switch speed is arranged.
In the present invention, because pre-stored following determination information: with the frequency setting ginseng of DDS Number is as the address, and whether each data storage area that represents in this each address is according to each frequency setting ginseng Number is exported the high spurious clutter that occurs from the second frequency synthesizer the output of DDS, therefore, Just can judge with the speed that is higher than the invention that claim 4 put down in writing.
In the present invention, because pre-stored following determination information: with the frequency setting ginseng of DDS The upper predetermined bits of number are as the address, each data storage area that represents in this each address, whether according to The frequency setting parameter of upper pre-determined bit is carried out in each address, exist from the output of second frequency synthesizer Therefore the high spurious clutter that occurs in the output of DDS, is compared with invention claimed in claim 5, Just can cut down its memory capacity, owing to can use cheaply memory, just can cutting down cost.
In the present invention, because pre-stored from the output of second frequency synthesizer output at DDS The scope of the frequency setting parameter of this direct digital synthesiser during the middle high spurious clutter that occurs, logical Cross and whether belong to this scope and determine whether that whether to have exported high parasitism from the second frequency synthesizer assorted Therefore ripple, is compared with the described invention of claim 4～6, just can further cut down storage and hold Amount, owing to can use cheaply memory, just can further cutting down cost.
In the present invention, owing to pre-stored in DDS output, the right of high spurious clutter occur Answer the number of times of spurious clutter, obtain according to the number of times of this spurious clutter and frequency setting parameter and be included in Whether the frequency of the high spurious clutter in the output of DDS is by having exported from the second frequency synthesizer The frequency of the high spurious clutter that this is obtained and determine whether and exported high spurious clutter, therefore, with power Profit requires 4～7 described inventions to compare, and just can further cut down memory capacity, owing to can make With memory cheaply, further cutting down cost just.
In the present invention, owing to carried out following judgement: at the variation width of cloth of the output frequency of DDS Spend narrowlyer, the scope of the frequency setting parameter of the above-mentioned DDS that high spurious clutter occurs is roughly in advance Fixed cycle, and the high spurious clutter more than the predetermined level that occurs in DDS output is inferior Number is limited in the situations on the specific times, obtains the frequency setting parameter according to this specific times Scope, the frequency setting that whether belongs to this each predetermined period of obtaining by the frequency setting parameter is joined The scope of number determines whether and has exported high spurious clutter, therefore, does not just need to declare for storage The memory of the spurious clutter number of times of calibration will and DDS is with described of claim 4～8 Bright comparing just can further be sought the reduction of manufacturing cost.
In the present invention, by DDS corresponding to adjustment such as automatic frequency control apparatus (AFC) The frequency setting parameter scans with the output frequency to DDS, simultaneously, and pre-stored appearing at The number of times of the high spurious clutter in the output of DDS by the adjustment of above-mentioned parameter adjusting device, is asked Go out the model of the number of times of the high spurious clutter that in the output of above-mentioned direct digital synthesiser, occurs Enclose, simultaneously, read the number of times of above-mentioned spurious clutter from above-mentioned storage device, by posting that this is read Whether the number of times of giving birth to clutter belongs to the scope of above-mentioned number of times, determines whether that having exported high parasitism mixes Ripple, thus, even in the transceivers such as radio machine, using AFC with this device Deng situation under, also can prevent high spurious clutter.
In the present invention, changing each setup parameter so that can not export from the second frequency synthesizer In the situation of high spurious clutter, only set ginseng with the conversion number of scheduled volume increase and decrease second frequency synthesizer At least one party in the setup parameter is counted in the conversion of number and frequency changer, simultaneously, and according to having increased and decreased this The frequency setting parameter that setup parameter changes the big DDS of resolution is counted at least one party's conversion, Thus, just can easily change corresponding to exporting output frequency and not exporting high spurious clutter The value of parameters.
In the present invention, count setup parameter, frequency transformation corresponding to the conversion of second frequency synthesizer The frequency setting parameter of setup parameter and DDS is counted in the conversion of device, pre-stored each frequency setting Parameter can be not predetermined from direct digital synthesiser output in the output band of second frequency synthesizer The second frequency synthesizer of the spurious clutter that level is above and the conversion number of frequency changer are set ginseng The increase and decrease amount of at least one party in the number when each setup parameter of change, is read corresponding to each and is established Decide the above-mentioned increase and decrease amount of parameter, count at least one in the setup parameter according to this increase and decrease amount increase and decrease conversion The frequency of setup parameter change DDS simultaneously, is counted by the side according to the conversion that has increased and decreased this at least one party Setup parameter thus, by once change, is not exported the above parasitism of predetermined level and change to The frequency setting parameter of clutter is compared with the situation of claim 11, just can change at a high speed each Setup parameter.
In the present invention, corresponding to should be from the data of the output frequency of second frequency synthesizer output As the address, in each data storage areas that its each address represents, can be from second frequency Synthesizer appears at the high spurious clutter in the DDS output, with the output corresponding to these data The frequency setting parameter of the DDS of second frequency synthesizer output, is frequently obtained and stored to frequency in advance Setup parameter is counted in the conversion of rate converter and second frequency synthesizer, should be from the second frequency synthesizer When the corresponding data of output frequency of output are imported as the address, the frequency corresponding to this address Setup parameter and conversion are counted setup parameter and are exported to respectively DDS, frequency changer and second frequency Synthesizer, thus, do not need to carry out the computing of each setup parameter in synthesizer inside and judge with And change processes, and becomes simple and make to consist of, and simultaneously, can seek to shorten for setting parameter Time. Its result just can especially accelerate the frequency switch speed of frequency synthesizer.

Claims (15)

1. frequency synthesizer comprises:
The first frequency synthesizer has Direct Digital synthesizer synchronous with reference clock and to export according to the frequency of frequency setting parameter;
Frequency changer, the output frequency and the output of counting the above-mentioned Direct Digital synthesizer of setup parameter conversion according to conversion;
The second frequency synthesizer is counted the output frequency of setup parameter conversion said frequencies converter and is also exported according to conversion,
It is characterized in that:
Can count setup parameter according to the conversion that setup parameter and above-mentioned second frequency synthesizer are counted in the conversion that the output frequency of above-mentioned second frequency synthesizer is set frequency setting parameter, the said frequencies converter of above-mentioned Direct Digital synthesizer.
2. frequency synthesizer according to claim 1 is characterized in that, further comprises:
Input unit, input is corresponding to should be from the data of the output frequency of second frequency synthesizer output;
The setup parameter arithmetic unit is counted in first conversion, obtains the conversion of above-mentioned second frequency synthesizer according to the above-mentioned data of above-mentioned input unit input and counts setup parameter;
The setup parameter arithmetic unit is counted in second conversion, counts conversion that the setup parameter arithmetic unit obtains according to the above-mentioned data of above-mentioned input unit input and above-mentioned first conversion and counts setup parameter and obtain the conversion of said frequencies converter and count setup parameter;
Frequency setting parameter arithmetic unit is counted conversion that the setup parameter arithmetic unit obtains according to above-mentioned data, above-mentioned first conversion of the input of above-mentioned input unit and is counted setup parameter and above-mentioned second conversion and count the conversion that the setup parameter arithmetic unit obtains and count the frequency setting parameter that setup parameter is obtained above-mentioned Direct Digital synthesizer;
Parameter setting apparatus is counted conversion that the setup parameter arithmetic unit obtains to above-mentioned first conversion and is counted setup parameter, above-mentioned second conversion and count conversion that the setup parameter arithmetic unit obtains and count the frequency setting parameter that setup parameter and said frequencies setup parameter arithmetic unit obtain and be individually set in above-mentioned second frequency synthesizer, said frequencies converter and the above-mentioned Direct Digital synthesizer.
3. frequency synthesizer according to claim 2 is characterized in that, further comprises:
The parameter decision device when frequency setting parameter arithmetic unit is obtained the frequency setting parameter, judges whether this frequency setting parameter has exported the spurious clutter more than the predetermined level from the Direct Digital synthesizer in the output band of second frequency synthesizer;
The parameter modification device, when being judged to be the frequency setting parameter by the above-mentioned parameter decision maker when having exported above-mentioned spurious clutter, the change conversion is counted setup parameter and frequency setting parameter and is exported to parameter setting apparatus, so that above-mentioned spurious clutter can not be included in the output band of second frequency synthesizer.
4. frequency synthesizer according to claim 3 is characterized in that, further comprises:
Storage device, store following determination information in advance: whether should be set in the spurious clutter of frequency setting parameter more than the second frequency synthesizer has been exported predetermined level the output that appears at the Direct Digital synthesizer in the Direct Digital synthesizer for each,
When the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, read above-mentioned determination information from above-mentioned storage device, and judge according to this determination information corresponding to the said frequencies setup parameter.
5. frequency synthesizer according to claim 3 is characterized in that, further comprises:
Storage device, store following determination information in advance: the frequency setting parameter of Direct Digital synthesizer as the address, in each data storage areas that its each address is represented as the said frequencies setup parameter of each address, in the output band of second frequency synthesizer, whether exported the spurious clutter more than the predetermined level from the Direct Digital synthesizer
When the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, the said frequencies setup parameter is carried out access as the address to above-mentioned storage device, and read above-mentioned determination information, judge according to this determination information.
6. frequency synthesizer according to claim 3 is characterized in that, further comprises:
Storage device, store following determination information in advance: whether exported the spurious clutter more than the predetermined level from the Direct Digital synthesizer, the upper pre-determined bit of the frequency setting parameter of its Direct Digital synthesizer is as the address, carry out the said frequencies setup parameter of upper pre-determined bit in the output band of second frequency synthesizer according to making each address in each data storage areas of representing in its each address
When the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, the upper pre-determined bit of said frequencies setup parameter is carried out access as the address to above-mentioned storage device, and read above-mentioned determination information, judge according to this determination information.
7. frequency synthesizer according to claim 3 is characterized in that, further comprises:
Storage device, the scope of the frequency setting parameter of the corresponding direct digital synthesizer when storing the Direct Digital synthesizer in advance and in the output band of second frequency synthesizer, exporting spurious clutter more than the predetermined level,
When the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, read the scope of said frequencies setup parameter from above-mentioned storage device, whether belong to the scope of this frequency setting parameter of reading by the frequency setting parameter, judge.
8. frequency synthesizer according to claim 3 is characterized in that, further comprises:
Storage device is stored the number of times of the spurious clutter more than the predetermined level that the Direct Digital synthesizer exports in advance in the output band of second frequency synthesizer,
When the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, read the number of times of above-mentioned spurious clutter from above-mentioned storage device, obtain spurious clutter frequency more than the predetermined level in the output that is included in above-mentioned Direct Digital synthesizer according to the number of times of this above-mentioned spurious clutter of reading and said frequencies setup parameter, by whether having exported this spurious clutter frequency more than predetermined level of obtaining, judge from the second frequency synthesizer.
9. frequency synthesizer according to claim 3, it is characterized in that, the parameter decision device is judged: the amplitude of variation at the output frequency of Direct Digital synthesizer is narrower, the scope of the frequency setting parameter of the above-mentioned Direct Digital synthesizer that the above spurious clutter of predetermined level occurs is roughly predetermined period and the above spurious clutter number of times of predetermined level that appears in the output of Direct Digital synthesizer is defined under the situation of specific times, whether whether the frequency setting parameter exported the spurious clutter more than the predetermined level from the Direct Digital synthesizer in the output band of second frequency synthesizer, in the case, obtain the predetermined period of the scope of said frequencies setup parameter according to above-mentioned specific number of times, whether belong to the scope of the said frequencies setup parameter of each this predetermined period of obtaining by the said frequencies setup parameter, judge.
10. frequency synthesizer according to claim 3 is characterized in that, further comprises:
Parameter adjustment controls, adjust corresponding Direct Digital synthesizer the frequency setting parameter so that the output frequency of Direct Digital synthesizer scan;
Storage device, storage in advance appear at the number of times of the above spurious clutter of predetermined level in the output of Direct Digital synthesizer,
When the parameter decision device judge this frequency setting parameter whether in the output band of second frequency synthesizer when the Direct Digital synthesizer has been exported the spurious clutter more than the predetermined level, obtain the scope of the spurious clutter number of times more than the predetermined level in the output that appears at above-mentioned Direct Digital synthesizer by the adjustment of above-mentioned parameter adjusting device, simultaneously, read the number of times of above-mentioned spurious clutter from above-mentioned storage device, whether belong to the scope of above-mentioned number of times by the number of times of this spurious clutter of reading, judge.
11. frequency synthesizer according to claim 3, it is characterized in that, count setup parameter and frequency setting parameter so that the spurious clutter more than the predetermined level can not be included in the output band of second frequency synthesizer the time in parameter modification device change conversion, at least one side that the conversion that makes the conversion of second frequency synthesizer count setup parameter and frequency changer is counted in the setup parameter increases and decreases with scheduled volume, simultaneously, count the frequency setting parameter that setup parameter changes the Direct Digital synthesizer according to the conversion that makes this at least one side's increase and decrease.
12. frequency synthesizer according to claim 3 is characterized in that, further comprises:
Storage device, the increase and decrease amount of at least one side in the setup parameter is counted in the conversion that setup parameter and frequency changer are counted in the conversion of storing the second frequency synthesizer in advance, the frequency setting parameter of setup parameter and above-mentioned Direct Digital synthesizer is counted in the conversion that setup parameter, frequency changer are counted in its conversion corresponding to the second frequency synthesizer, each frequency setting parameter can be from the spurious clutter more than the Direct Digital synthesizer output predetermined level in the output band of second frequency synthesizer
Change that setup parameter and frequency setting parameter are counted in above-mentioned conversion so that the spurious clutter more than the predetermined level can not be included in the output band of second frequency synthesizer the time at the parameter modification device, read corresponding to the conversion of second frequency synthesizer from above-mentioned storage device and to count setup parameter, the above-mentioned increase and decrease amount of the frequency setting parameter of setup parameter and above-mentioned Direct Digital synthesizer is counted in the conversion of said frequencies converter, at least one side who above-mentioned conversion is counted in the setup parameter according to this increase and decrease amount increases and decreases, simultaneously, count the frequency setting parameter that setup parameter changes the Direct Digital synthesizer according to the conversion that this at least one side is increased and decreased.
13. a frequency synthesizer is characterized in that, comprising:
The first frequency synthesizer has Direct Digital synthesizer synchronous with reference clock and to export according to the frequency of frequency setting parameter;
Frequency changer, the output frequency and the output of counting the above-mentioned Direct Digital synthesizer of setup parameter conversion according to conversion;
The second frequency synthesizer, the output frequency and the output of counting setup parameter conversion said frequencies converter according to conversion;
Input unit, as address input corresponding to should be from the data of the output frequency of second frequency synthesizer output;
Storage device, corresponding to should be from the data of the output frequency of above-mentioned second frequency synthesizer output as the address, the above spurious clutter of predetermined level that is not included in the output band of above-mentioned second frequency synthesizer in the output that appears at the Direct Digital synthesizer in each data storage areas of representing this each address, store the frequency setting parameter of above-mentioned second frequency synthesizer in advance with the above-mentioned Direct Digital synthesizer of above-mentioned output frequency output, the conversion of said frequencies converter is counted the conversion of setup parameter and above-mentioned second frequency synthesizer and is counted setup parameter, import by above-mentioned input unit under the situation of above-mentioned address, frequency setting parameter corresponding to the above-mentioned Direct Digital synthesizer of this address, the conversion that setup parameter and above-mentioned second frequency synthesizer are counted in the conversion of said frequencies converter is counted setup parameter and is exported to above-mentioned Direct Digital synthesizer respectively, said frequencies converter and above-mentioned second frequency synthesizer.
14. according to claim 2 or 13 described frequency synthesizers, it is characterized in that the first frequency synthesizer has variable frequency divider,, count setup parameter according to conversion the output frequency of Direct Digital synthesizer is carried out frequency division as frequency changer.
15. according to claim 1,2 or 13 described frequency synthesizers, it is characterized in that, the second frequency synthesizer is a phase-locked loop, at the output frequency of counting the above-mentioned first frequency synthesizer of setup parameter conversion according to conversion and when exporting, count according to above-mentioned conversion that setup parameter is exported this output frequency so that the frequency of variable frequency divider frequency division is consistent with the output frequency of above-mentioned first frequency synthesizer with should be from the output frequency of second frequency synthesizer output corresponding data
CN 97102497 1996-06-28 1997-02-24 Frequency synthesizing device Pending CN1169622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 97102497 CN1169622A (en) 1996-06-28 1997-02-24 Frequency synthesizing device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP169949/96 1996-06-28
CN 97102497 CN1169622A (en) 1996-06-28 1997-02-24 Frequency synthesizing device

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CN1169622A true CN1169622A (en) 1998-01-07

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CN 97102497 Pending CN1169622A (en) 1996-06-28 1997-02-24 Frequency synthesizing device

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847243B2 (en) 2000-07-21 2005-01-25 Nec Electronics Corporation Clock controlling method and circuit
CN101924552A (en) * 2009-06-12 2010-12-22 日本电波工业株式会社 Pll circuit
CN106797218A (en) * 2014-10-08 2017-05-31 日本电波工业株式会社 Frequency synthesizer

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847243B2 (en) 2000-07-21 2005-01-25 Nec Electronics Corporation Clock controlling method and circuit
US6888387B2 (en) 2000-07-21 2005-05-03 Nec Electronics Corporation Clock controlling method and circuit
US6900680B2 (en) 2000-07-21 2005-05-31 Nec Electronics Corporation Clock controlling method and circuit
US6965259B2 (en) 2000-07-21 2005-11-15 Nec Electronics Corporation Clock controlling method and circuit
US7034592B2 (en) 2000-07-21 2006-04-25 Nec Electronics Corporation Clock controlling method and circuit
CN101924552A (en) * 2009-06-12 2010-12-22 日本电波工业株式会社 Pll circuit
CN101924552B (en) * 2009-06-12 2013-08-07 日本电波工业株式会社 Pll circuit
CN106797218A (en) * 2014-10-08 2017-05-31 日本电波工业株式会社 Frequency synthesizer
CN106797218B (en) * 2014-10-08 2020-06-16 日本电波工业株式会社 Frequency synthesizer

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