CN116961446A

CN116961446A - Noise-suppressing power supply

Info

Publication number: CN116961446A
Application number: CN202210418372.0A
Authority: CN
Inventors: 詹子增
Original assignee: Acer Inc
Current assignee: Acer Inc
Priority date: 2022-04-20
Filing date: 2022-04-20
Publication date: 2023-10-27

Abstract

A noise-suppressing power supply, comprising: a first bridge rectifier, a second bridge rectifier, a coupling inductance element, a first power switch, a first output stage circuit, a switching circuit, a transformer, a second output stage circuit, and an auxiliary control circuit. The first bridge rectifier and the second bridge rectifier can generate a first rectifying potential and a second rectifying potential according to a first input potential and a second input potential. The coupled inductive element may receive a first rectified potential and a second rectified potential. The switching circuit can generate a control potential. The second output stage circuit can generate an output potential. The auxiliary control circuit includes a second power switch. The second power switch is coupled to the coupling inductance element and can be selectively enabled or disabled according to the control potential.

Description

Noise-suppressing power supply

Technical Field

The present invention relates to a power supply, and more particularly to a Noise suppressing power supply.

Background

In the conventional power supply, if the switching frequencies of the PFC (Power Factor Corrector, PFC) and the resonant LLC converter (Resonant LLC Converter) are close to each other, noise that can be easily distinguished by the human ear is easily generated, which results in poor user experience. In view of this, a completely new solution has to be proposed to overcome the dilemma faced by the prior art.

Disclosure of Invention

In a preferred embodiment, the present invention provides a power supply for suppressing noise, comprising: a first bridge rectifier for generating a first rectified potential according to a first input potential and a second input potential; a second bridge rectifier for generating a second rectified potential according to the first input potential and the second input potential; a coupling inductance element for receiving the first rectifying potential and the second rectifying potential; a first power switch selectively coupling the coupled inductive element to a ground potential according to a time Zhong Dianwei; a first output stage circuit coupled to the coupling inductance element and generating an internal potential; a switching circuit for receiving the internal potential and generating a switching potential and a control potential; a transformer including a main coil, a first secondary coil and a second secondary coil, wherein a leakage inductor and an exciting inductor are built in the transformer, and the main coil is coupled to the switching circuit via the leakage inductor; a resonant capacitor coupled to the excitation inductor; a second output stage circuit coupled to the first secondary winding and the second secondary winding and generating an output potential; and an auxiliary control circuit for generating the clock potential and comprising a second power switch coupled to the coupling inductance element and selectively enabling or disabling according to the control potential.

In some embodiments, the second power switch is enabled if a switching frequency of the switching potential falls within plus or minus 20kHz of a center frequency of the clock potential; otherwise the second power switch will be disabled.

In some embodiments, the first bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the first rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential and the cathode of the fourth diode is coupled to the second input node.

In some embodiments, the second bridge rectifier includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the first input node to receive the first input potential, and the cathode of the fifth diode is coupled to a second node to output the second rectified potential; a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the second input node to receive the second input potential, and the cathode of the sixth diode is coupled to the second node; a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the ground potential and the cathode of the seventh diode is coupled to the first input node; and an eighth diode having an anode and a cathode, wherein the anode of the eighth diode is coupled to the ground potential and the cathode of the eighth diode is coupled to the second input node.

In some embodiments, the coupled inductive element comprises: a first inductor having a first end and a second end, wherein the first end of the first inductor is coupled to the first node to receive the first rectified potential, and the second end of the first inductor is coupled to a third node; and a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the second node to receive the second rectified potential, and the second end of the second inductor is coupled to the third node; wherein the first inductor and the second inductor are coupled to each other.

In some embodiments, the first power switch comprises: the first transistor has a control terminal, a first terminal and a second terminal, wherein the control terminal of the first transistor is used for receiving the clock potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the third node.

In some embodiments, the first output stage circuit comprises: a ninth diode having an anode and a cathode, wherein the anode of the ninth diode is coupled to the third node, and the cathode of the ninth diode is coupled to a fourth node to output the internal potential; and a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the fourth node and the second end of the first capacitor is coupled to the ground potential.

In some embodiments, the switching circuit includes: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is for receiving the switching potential, the first terminal of the second transistor is coupled to a fifth node, and the second terminal of the second transistor is coupled to the fourth node for receiving the internal potential; a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is for receiving an inverse switching potential, the first terminal of the third transistor is coupled to the ground potential, and the second terminal of the third transistor is coupled to the fifth node; a resistor; and a first controller for generating the switching potential and the inverse switching potential, wherein the first controller generates the control potential according to the switching potential.

In some embodiments, the leakage inductor has a first end and a second end, the first end of the leakage inductor is coupled to the fifth node, the second end of the leakage inductor is coupled to a sixth node, the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the sixth node, the second end of the excitation inductor is coupled to a seventh node, the main winding has a first end and a second end, the first end of the main winding is coupled to the sixth node, the second end of the main winding is coupled to the seventh node, the resonant capacitor has a first end and a second end, the first end of the resonant capacitor is coupled to the seventh node, the first secondary winding has a first end and a second end, the first end of the first secondary winding is coupled to a eighth node, the first secondary winding is coupled to the first end, the first secondary winding is coupled to the first node, the second secondary winding is coupled to the first node, the first secondary winding is coupled to the first node, and the second secondary winding is coupled to the first node.

In some embodiments, the second output stage circuit includes: a twelfth diode having an anode and a cathode, wherein the anode of the tenth diode is coupled to the eighth node, and the cathode of the twelfth diode is coupled to an output node for outputting the output potential; an eleventh diode having an anode and a cathode, wherein the anode of the eleventh diode is coupled to the ninth node and the cathode of the eleventh diode is coupled to the output node; and a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the output node and the second end of the second capacitor is coupled to the common node.

In some embodiments, the auxiliary control circuit includes: a fourth transistor forming the second power switch and having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor is for receiving the clock potential, the first terminal of the fourth transistor is coupled to a tenth node, and the second terminal of the fourth transistor is coupled to the third node; a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is for receiving an adjustment potential, the first terminal of the fifth transistor is coupled to the ground potential, and the second terminal of the fifth transistor is coupled to the tenth node; and a second controller for generating the clock potential and receiving the control potential via the resistor, wherein the second controller further generates the adjustment potential according to the control potential.

Drawings

Fig. 1 is a schematic diagram showing a power supply according to an embodiment of the invention.

Fig. 2 is a schematic diagram showing a power supply according to an embodiment of the invention.

Fig. 3 is a graph showing a relationship between voltage gain and switching frequency of a power supply according to an embodiment of the invention.

Wherein reference numerals are as follows:

100, 200: power supply

110, 210: first bridge rectifier

120, 220: second bridge rectifier

130, 230: coupled inductance element

140, 240: first power switcher

150, 250: first output stage circuit

160, 260: switching circuit

170, 270: transformer

171, 271: main coil

172, 272: first auxiliary coil

173, 273: second auxiliary coil

180, 280: second output stage circuit

190, 290: auxiliary control circuit

192, 292: second power switcher

264: first controller

294: second controller

C1: first capacitor

C2: second capacitor

CR: resonant capacitor

D1: first diode

D2: second diode

D3: third diode

D4: fourth diode

D5: fifth diode

D6: sixth diode

D7: seventh diode

D8: eighth diode

D9: ninth diode

D10: twelfth polar tube

D11: eleventh diode

FC: center frequency

FH: upper frequency limit

FL: lower frequency limit

FV: frequency interval

FW: switching frequency

L1: first inductor

L2: second inductor

LM: exciting inductor

LR: leakage inductor

M1: first transistor

M2: second transistor

M3: third transistor

M4: fourth transistor

M5: fourth transistor

N1: first node

N2: second node

And N3: third node

N4: fourth node

N5: fifth node

N6: sixth node

N7: seventh node

N8: eighth node

N9: ninth node

N10: tenth node

NCM: common node

NIN1: first input node

NIN2: second input node

NOUT: output node

R1: resistor

VA: clock potential

VC: controlling potential

VIN1: a first input potential

VIN2: a second input potential

VN: internal potential

VOUT: output potential

VR1: a first rectifying potential

VR2: second rectifying potential

VSS: ground potential

VT: adjusting the potential

VW: switching potential

VWB: reverse switching potential

Detailed Description

The present invention will be described in more detail with reference to the drawings, wherein the invention is shown in the drawings.

Certain terms are used throughout the description and claims to refer to particular components. Those skilled in the art will appreciate that a hardware manufacturer may refer to the same element by different names. The description and claims do not take the form of an element differentiated by name, but rather by functional differences. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "substantially" means that within an acceptable error range, a person skilled in the art can solve the technical problem within a certain error range, and achieve the basic technical effect. In addition, the term "coupled" as used herein includes any direct or indirect electrical connection. Accordingly, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1 is a schematic diagram illustrating a power supply 100 according to an embodiment of the invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an integrally formed computer. As shown in fig. 1, the power supply 100 includes: a first bridge rectifier 110, a second bridge rectifier 120, a coupled inductive element 130, a first power switch 140, a first output stage 150, a switching circuit 160, a transformer 170, a resonant capacitor CR, a second output stage 180, and an auxiliary control circuit 190. It should be noted that although not shown in fig. 1, the power supply 100 may further include other elements, such as: a voltage stabilizer or (and) a negative feedback circuit.

The first bridge rectifier 110 can generate a first rectified voltage VR1 according to a first input voltage VIN1 and a second input voltage VIN 2. The first input potential VIN1 and the second input potential VIN2 can both be from an external input power source, wherein an ac voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN 2. For example, the frequency of the ac voltage may be about 50Hz or 60Hz, and the square root of the ac voltage may be from 90V to 264V, but is not limited thereto. The second bridge rectifier 120 generates a second rectified voltage VR2 according to the first input voltage VIN1 and the second input voltage VIN 2. The coupled inductive element 130 may receive the first rectified potential VR1 and the second rectified potential VR2. The first power switch 140 may selectively couple the coupling inductance element 130 to a ground potential VSS (e.g., 0V) according to a time Zhong Dianwei VA. For example, if the clock voltage VA is at a high logic level (e.g., logic "1"), the first power switch 140 can couple the coupling inductance element 130 to the ground voltage VSS (i.e., the first power switch 140 can approximate a short circuit path); conversely, if the clock voltage VA is at a low logic level (e.g., logic "0"), the first power switch 140 does not couple the coupling inductance element 130 to the ground voltage VSS (i.e., the first power switch 140 may approximate an open path). The first output stage 150 is coupled to the coupling inductor 130 and generates an internal potential VN. The internal potential VN may be considered as a boost potential. The switching circuit 160 receives the internal voltage VN and generates a switching voltage VW and a control voltage VC. The transformer 170 includes a primary winding 171, a first secondary winding 172, and a second secondary winding 173, wherein a leakage inductor LR and an excitation inductor LM are built into the transformer 170. The primary winding 171, the leakage inductor LR, and the excitation inductor LM may be disposed on the same side (e.g., primary side) of the transformer 170, and the first secondary winding 172 and the second secondary winding 173 may be disposed on opposite sides (e.g., secondary side) of the transformer 170, which may be isolated from the primary side. The primary winding 171 is coupled to the switching circuit 160 via the leakage inductor LR. The resonant capacitor CR is coupled to the excitation inductor LM. The second output stage 180 is coupled to the first secondary winding 172 and the second secondary winding 173, and generates an output voltage VOUT. For example, the output voltage VOUT may be a dc voltage, which may be between 18V and 20V, but is not limited thereto. The auxiliary control circuit 190 may generate the clock voltage VA and include a second power switch 192, wherein the second power switch 192 is coupled to the coupling inductance element 130 and selectively enabled or disabled according to the control voltage VC. For example, if the control voltage VC is at a high logic level, the second power switch 192 may be enabled; conversely, if the control voltage VC is at a low logic level, the second power switch 192 may be disabled. In some embodiments, if a switching frequency FW of the switching potential VW falls within plus or minus 20kHz of a center frequency FC of the clock potential VA, the second power switch 192 will be enabled; otherwise, the second power switch 192 will be disabled. It should be understood that the frequency range can be adjusted according to different requirements. According to the practical measurement result, the design of the present invention can effectively suppress the resonance noise generated by the power supply 100, so as to improve the experience of the user.

The following embodiments describe the detailed structure and operation of the power supply 100. It must be understood that these drawings and descriptions are only for the purpose of example and are not intended to limit the scope of the invention.

Fig. 2 is a schematic diagram showing a power supply 200 according to an embodiment of the invention. In the embodiment of fig. 2, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a first bridge rectifier 210, a second bridge rectifier 220, a coupling inductance element 230, a first power switch 240, a first output stage circuit 250, a switching circuit 260, a transformer 270, a resonant capacitor CR, a second output stage circuit 280, and an auxiliary control circuit 290. The first input node NIN1 and the second input node NIN2 of the power supply 200 can respectively receive the first input voltage VIN1 and the second input voltage VIN2 from an external input power source, and the output node NOUT of the power supply 200 can output an output voltage VOUT to an electronic device (not shown).

The first bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a first rectifying potential VR1. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The second bridge rectifier 220 includes a fifth diode D5, a sixth diode D6, a seventh diode D7, and an eighth diode D8. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the first input node NIN1, and the cathode of the fifth diode D5 is coupled to a second node N2 to output a second rectifying potential VR2. The sixth diode D6 has an anode and a cathode, wherein the anode of the sixth diode D6 is coupled to the second input node NIN2, and the cathode of the sixth diode D6 is coupled to the second node N2. The seventh diode D7 has an anode and a cathode, wherein the anode of the seventh diode D7 is coupled to the ground potential VSS, and the cathode of the seventh diode D7 is coupled to the first input node NIN1. The eighth diode D8 has an anode and a cathode, wherein the anode of the eighth diode D8 is coupled to the ground potential VSS, and the cathode of the eighth diode D8 is coupled to the second input node NIN2.

The coupling inductance element 230 includes a first inductor L1 and a second inductor L2. The first inductor L1 has a first end and a second end, wherein the first end of the first inductor L1 is coupled to the first node N1 to receive the first rectifying potential VR1, and the second end of the first inductor L1 is coupled to a third node N3. The second inductor L2 has a first end and a second end, wherein the first end of the second inductor L2 is coupled to the second node N2 to receive the second rectifying potential VR2, and the second end of the second inductor L2 is coupled to the third node N3. The first inductor L1 and the second inductor L2 are coupled to each other. For example, both the first inductor L1 and the second inductor L2 may be formed on the same core, but is not limited thereto.

The first power switch 240 includes a first transistor M1. The first transistor M1 may be an N-type mosfet. The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the first transistor M1 is for receiving a voltage of Zhong Dianwei VA, the first terminal of the first transistor M1 is coupled to the ground potential VSS, and the second terminal of the first transistor M1 is coupled to the third node N3. For example, the clock voltage VA can be maintained at a constant voltage when the power supply 200 is initialized, and a periodic clock waveform can be provided after the power supply 200 enters a normal use phase.

The first output stage 250 includes a ninth diode D9 and a first capacitor C1. The ninth diode D9 has an anode and a cathode, wherein the anode of the ninth diode D9 is coupled to the third node N3, and the cathode of the ninth diode D9 is coupled to a fourth node N4 to output an internal potential VN. The first capacitor C1 has a first end and a second end, wherein the first end of the first capacitor C1 is coupled to the fourth node N4, and the second end of the first capacitor C1 is coupled to the ground potential VSS.

The switching circuit 260 includes a second transistor M2, a third transistor M3, a resistor R1, and a first controller 264. The second transistor M2 and the third transistor M3 may each be an N-type mosfet. The first controller 264 may be implemented by an integrated circuit chip. The second transistor M2 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the second transistor M2 is for receiving a switching potential VW, the first terminal of the second transistor M2 is coupled to a fifth node N5, and the second terminal of the second transistor M2 is coupled to the fourth node N4 for receiving the internal potential VN. The third transistor M3 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the third transistor M3 is for receiving an inverted switching potential VWB, the first terminal of the third transistor M3 is coupled to the ground potential VSS, and the second terminal of the third transistor M3 is coupled to the fifth node N5. The first controller 264 may generate a switching potential VW and an inverted switching potential VWB, wherein the switching potential VW and the inverted switching potential VWB may have the same switching frequency FW and complementary logic levels. The first controller 264 further generates a control voltage VC according to the switching voltage VW. For example, the first controller 264 may include a frequency comparator (not shown). In some embodiments, if the switching frequency FW of the switching potential VW falls within plus or minus 20kHz of a center frequency FC of the clock potential VA, the control potential VC will be at a high logic level; conversely, if the switching frequency FW of the switching potential VW does not fall within the above range, the control potential VC will be at a low logic level. For example, the center frequency FC of the clock potential VA may be a constant. The first controller 264 further transmits the control potential VC to the auxiliary control circuit 290 via the resistor R1.

The transformer 270 includes a primary winding 271, a first secondary winding 272, and a second secondary winding 273, wherein the transformer 270 further includes a leakage inductor LR and an excitation inductor LM. Both leakage inductor LR and excitation inductor LM may be intrinsic components that are created by the manufacturing of transformer 270 and are not external stand-alone components. The leakage inductor LR, the main winding 271, and the excitation inductor LM may be located on the same side of the transformer 270, and the first sub-winding 272 and the second sub-winding 273 may be located on opposite sides of the transformer 270. The leakage inductor LR has a first end and a second end, wherein the first end of the leakage inductor LR is coupled to the fifth node N5, and the second end of the leakage inductor LR is coupled to a sixth node N6. The excitation inductor LM has a first end and a second end, wherein the first end of the excitation inductor LM is coupled to the sixth node N6, and the second end of the excitation inductor LM is coupled to a seventh node N7. The main coil 271 has a first end and a second end, wherein the first end of the main coil 271 is coupled to the sixth node N6, and the second end of the main coil 271 is coupled to the seventh node N7. The resonant capacitor CR has a first end and a second end, wherein the first end of the resonant capacitor CR is coupled to the seventh node N7, and the second end of the resonant capacitor CR is coupled to the ground potential VSS. The first secondary winding 272 has a first end and a second end, wherein the first end of the first secondary winding 272 is coupled to an eighth node N8, and the second end of the first secondary winding 272 is coupled to a common node NCM. For example, the common node NCM may be considered another ground potential, which may be the same or different from the aforementioned ground potential VSS. The second secondary winding 273 has a first end and a second end, wherein the first end of the second secondary winding 273 is coupled to the common node NCM and the second end of the second secondary winding 273 is coupled to a ninth node N9. It should be noted that the leakage inductor LR, the excitation inductor LM, and the resonant capacitor CR may together form an LLC resonant tank.

The second output stage 280 includes a twelfth diode D10, an eleventh diode D11, and a second capacitor C2. The twelfth diode D10 has an anode and a cathode, wherein the anode of the twelfth diode D10 is coupled to the eighth node N8, and the cathode of the tenth diode D10 is coupled to the output node NOUT. The eleventh diode D11 has an anode and a cathode, wherein the anode of the eleventh diode D11 is coupled to the ninth node N9, and the cathode of the eleventh diode D11 is coupled to the output node NOUT. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to the common node NCM.

The auxiliary control circuit 290 includes a fourth transistor M4, a fifth transistor M5, and a second controller 294. The fourth transistor M4 and the fifth transistor M5 may each be an N-type mosfet. The second controller 294 may be implemented by another integrated circuit chip. The fourth transistor M4 may form a second power switch 292 of the auxiliary control circuit 290. The fourth transistor M4 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the fourth transistor M4 is for receiving the clock voltage VA, the first terminal of the fourth transistor M4 is coupled to a tenth node N10, and the second terminal of the fourth transistor M4 is coupled to the third node N3. The fifth transistor M5 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the fifth transistor M5 is for receiving an adjustment potential VT, the first terminal of the fifth transistor M5 is coupled to the ground potential VSS, and the second terminal of the fifth transistor M5 is coupled to the tenth node N10. The second controller 294 may generate the clock potential VA and may receive the control potential VC via the resistor R1, wherein the second controller 294 may further generate the adjustment potential VT according to the control potential VC. For example, if the control voltage VC is at a high logic level, the second controller 294 generates an adjustment voltage VT at a high logic level to enable the fifth transistor M5 (while indirectly enabling the fourth transistor M4); conversely, if the control voltage VC is at a low logic level, the second controller 294 generates an adjustment voltage VT at a low logic level to disable the fifth transistor M5 (while indirectly disabling the fourth transistor M4). In other words, whether the fourth transistor M4 and the fifth transistor M5 are enabled is determined according to the comparison result of the switching frequency FW and the center frequency FC of the clock potential VA.

Fig. 3 is a graph showing a relationship between voltage gain and switching frequency of the power supply 200 according to an embodiment of the invention. The horizontal axis represents the switching frequency FW of the switching potential VW, while the vertical axis represents the voltage gain, which may be equal to the ratio of both the output potential VOUT and the internal potential VN. Generally, the first bridge rectifier 210, the second bridge rectifier 220, the coupling inductance element 230, the first power switch 240, the first output stage circuit 250, and the auxiliary control circuit 290 together form an improved power factor corrector (Power Factor Corrector, PFC); in addition, the switching circuit 260, the transformer 270, the resonant capacitor CR, and the second output stage 280 together form a resonant LLC converter (Resonant LLC Converter). If a difference between the switching frequency FW of the switching potential VW and the center frequency FC of the clock potential VA is between plus or minus 10kHz, the conventional power supply may generate noise perceived by human ears.

To suppress the aforementioned noise, some exemplary embodiments may set a lower frequency limit FL to the center frequency FC minus 20kHz, and may set an upper frequency limit FH to the center frequency FC plus 20kHz. If the switching frequency FW of the switching potential VW falls within a frequency range FV between the lower frequency limit FL and the upper frequency limit FH, the switching circuit 260 and the auxiliary control circuit 290 will enable the second power switch 292. Conversely, if the switching frequency FW of the switching potential VW does not fall within the frequency range FV, the switching circuit 260 and the auxiliary control circuit 290 disable the second power switch 292. Therefore, an auxiliary boost circuit formed by the second bridge rectifier 220, the second inductor L2, and the second power switch 292 can supplement the energy supplied to the resonant LLC converter in the frequency range FV. By reducing the voltage gain (e.g., to about 0) in the frequency range FV, the design not only maintains a stable output voltage VOUT, but also effectively eliminates the resonance noise of the power supply 200, which greatly improves the user experience.

In some embodiments, the component parameters of the power supply 200 may be as follows. The inductance of the first inductor L1 may be between 324 μh and 396 μh, and preferably may be about 360 μh. The inductance of the second inductor L2 may be between 324 μh and 396 μh, and preferably may be about 360 μh. The leakage inductor LR may have an inductance value between 37.8 muh and 46.2 muh, and preferably may be about 42 muh. The inductance of the excitation inductor LM may be between 594 muh and 726 muh, and preferably may be about 660 muh. The resistance of the resistor R1 may be between 99Ω and 101Ω, and preferably may be about 100deg.Ω. The capacitance of the resonant capacitor CR may be between 42.3nF and 51.7nF, preferably about 47nF. The capacitance of the first capacitor C1 may be between 1200 μF and 1800 μF, preferably about 1500 μF. The capacitance of the second capacitor C2 may be between 544 μF and 816 μF, preferably about 680 μF. The turns ratio of the primary winding 271 to the primary secondary winding 272 may be between 1 and 100, and preferably may be about 20. The turns ratio of the primary winding 271 to the secondary winding 273 may be between 1 and 100, and preferably may be about 20. The center frequency FC of the clock potential VA may be about 65kHz. The lower frequency limit FL may be about 45kHz. The upper frequency limit FH may be about 85kHz. The frequency range FV may be between about 45kHz and 85kHz. The above parameter ranges are derived from a plurality of experimental results, which help to minimize the resonance noise of the power supply 200.

The invention provides a novel power supply, which comprises a switching circuit and a corresponding auxiliary control circuit. According to the actual measurement result, the power supply with the design can effectively eliminate the non-ideal noise of the power supply, so that the power supply is very suitable for being applied to various devices.

It should be noted that the above-mentioned potential, current, resistance, inductance, capacitance, and other parameters are not limitations of the present invention. The designer can adjust these settings according to different needs. The power supply of the present invention is not limited to the states illustrated in fig. 1-3. The present invention may include only any one or more features of any one or more of the embodiments of fig. 1-3. In other words, not all of the illustrated features need be implemented in the power supply of the present invention at the same time. Although the embodiments of the present invention are exemplified by using mosfet, the present invention is not limited thereto, and those skilled in the art can use other kinds of transistors, such as: junction field effect transistors, or fin field effect transistors, and the like, without affecting the effect of the present invention.

Ordinal numbers such as "first," "second," "third," and the like in the description and in the claims are used for distinguishing between two different elements having the same name and not necessarily for describing a sequential order.

While the invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A noise-suppressing power supply, comprising:

a first bridge rectifier for generating a first rectified potential according to a first input potential and a second input potential;

a second bridge rectifier for generating a second rectified potential according to the first input potential and the second input potential;

a coupling inductance element for receiving the first rectifying potential and the second rectifying potential;

a first power switch selectively coupling the coupled inductive element to a ground potential according to a time Zhong Dianwei;

a first output stage circuit coupled to the coupling inductance element and generating an internal potential;

a switching circuit for receiving the internal potential and generating a switching potential and a control potential;

a transformer including a main coil, a first secondary coil and a second secondary coil, wherein a leakage inductor and an exciting inductor are built in the transformer, and the main coil is coupled to the switching circuit via the leakage inductor;

a resonant capacitor coupled to the excitation inductor;

a second output stage circuit coupled to the first secondary winding and the second secondary winding and generating an output potential; and

an auxiliary control circuit generates the clock potential and comprises a second power switch, wherein the second power switch is coupled to the coupling inductance element and selectively enables or disables according to the control potential.

2. The power supply of claim 1, wherein the second power switch is enabled if a switching frequency of the switching potential falls within plus or minus 20kHz of a center frequency of the clock potential; otherwise the second power switch will be disabled.

3. The power supply of claim 1, wherein the first bridge rectifier comprises:

a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the first rectified potential;

a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node;

a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential and the cathode of the third diode is coupled to the first input node; and

a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential and the cathode of the fourth diode is coupled to the second input node.

4. The power supply of claim 3, wherein the second bridge rectifier comprises:

a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the first input node to receive the first input potential, and the cathode of the fifth diode is coupled to a second node to output the second rectified potential;

a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the second input node to receive the second input potential, and the cathode of the sixth diode is coupled to the second node;

a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the ground potential and the cathode of the seventh diode is coupled to the first input node; and

an eighth diode having an anode and a cathode, wherein the anode of the eighth diode is coupled to the ground potential and the cathode of the eighth diode is coupled to the second input node.

5. The power supply of claim 4, wherein the coupled inductive element comprises:

a first inductor having a first end and a second end, wherein the first end of the first inductor is coupled to the first node to receive the first rectified potential, and the second end of the first inductor is coupled to a third node; and

a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the second node to receive the second rectified potential, and the second end of the second inductor is coupled to the third node;

wherein the first inductor and the second inductor are coupled to each other.

6. The power supply of claim 5, wherein the first power switch comprises:

the first transistor has a control terminal, a first terminal and a second terminal, wherein the control terminal of the first transistor is used for receiving the clock potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the third node.

7. The power supply of claim 6, wherein the first output stage circuit comprises:

a ninth diode having an anode and a cathode, wherein the anode of the ninth diode is coupled to the third node, and the cathode of the ninth diode is coupled to a fourth node to output the internal potential; and

a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the fourth node and the second end of the first capacitor is coupled to the ground potential.

8. The power supply of claim 7, wherein the switching circuit comprises:

a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is for receiving the switching potential, the first terminal of the second transistor is coupled to a fifth node, and the second terminal of the second transistor is coupled to the fourth node for receiving the internal potential;

a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is for receiving an inverse switching potential, the first terminal of the third transistor is coupled to the ground potential, and the second terminal of the third transistor is coupled to the fifth node;

a resistor; and

the first controller generates the switching potential and the inverse switching potential, wherein the first controller generates the control potential according to the switching potential.

9. The power supply of claim 8, wherein the leakage inductor has a first end and a second end, the first end of the leakage inductor is coupled to the fifth node, the second end of the leakage inductor is coupled to a sixth node, the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the sixth node, the second end of the excitation inductor is coupled to a seventh node, the main winding has a first end and a second end, the first end of the main winding is coupled to the sixth node, the second end of the main winding is coupled to the seventh node, the first end of the resonant capacitor is coupled to the seventh node, the second end of the resonant capacitor is coupled to the ground potential, the first secondary winding has a first end and a second end, the first end of the first secondary winding is coupled to an eighth node, the second end of the first secondary winding is coupled to a common node, the second secondary winding has a first end and a second end, the first end of the second secondary winding is coupled to the common node, and the second end of the second secondary winding is coupled to a ninth node.

10. The power supply of claim 9, wherein the second output stage circuit comprises:

a twelfth diode having an anode and a cathode, wherein the anode of the tenth diode is coupled to the eighth node, and the cathode of the twelfth diode is coupled to an output node for outputting the output potential;

an eleventh diode having an anode and a cathode, wherein the anode of the eleventh diode is coupled to the ninth node and the cathode of the eleventh diode is coupled to the output node; and

a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the output node and the second end of the second capacitor is coupled to the common node.

11. The power supply of claim 10, wherein the auxiliary control circuit comprises:

a fourth transistor forming the second power switch and having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor is for receiving the clock potential, the first terminal of the fourth transistor is coupled to a tenth node, and the second terminal of the fourth transistor is coupled to the third node;

a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is for receiving an adjustment potential, the first terminal of the fifth transistor is coupled to the ground potential, and the second terminal of the fifth transistor is coupled to the tenth node; and

and a second controller for generating the clock potential and receiving the control potential through the resistor, wherein the second controller further generates the adjustment potential according to the control potential.