CN116961446A - Noise suppressed power supply - Google Patents

Abstract

A noise-suppressing power supply, comprising: a first bridge rectifier, a second bridge rectifier, a coupling inductance element, a first power switch, a first output stage circuit, a switching circuit, a transformer, a second output stage circuit, and an auxiliary control circuit. The first bridge rectifier and the second bridge rectifier can generate a first rectifying potential and a second rectifying potential according to a first input potential and a second input potential. The coupled inductive element may receive a first rectified potential and a second rectified potential. The switching circuit can generate a control potential. The second output stage circuit can generate an output potential. The auxiliary control circuit includes a second power switch. The second power switch is coupled to the coupling inductance element and can be selectively enabled or disabled according to the control potential.

Description

Noise suppressed power supply

Technical field

The present invention relates to a power supply, and in particular to a power supply capable of suppressing noise.

Background technique

In traditional power supplies, if the switching frequencies of the power factor corrector (PFC) and the resonant LLC converter (Resonant LLC Converter) are close to each other, it is easy to produce signals that can be easily distinguished by the human ear. Noise, which results in a poor user experience. In view of this, it is necessary to propose a completely new solution to overcome the difficulties faced by previous technologies.

Contents of the invention

In a preferred embodiment, the present invention proposes a noise-suppressing power supply, including: a first bridge rectifier that generates a first rectified potential based on a first input potential and a second input potential; a first rectifier potential; A two-bridge rectifier generates a second rectified potential according to the first input potential and the second input potential; a coupled inductor element receives the first rectified potential and the second rectified potential; a first power switch, The coupling inductance element is selectively coupled to a ground potential according to a clock potential; a first output stage circuit is coupled to the coupling inductance element and generates an internal potential; a switching circuit receives the internal potential, and generates a switching potential and a control potential; a transformer includes a main coil, a first auxiliary coil, and a second auxiliary coil, wherein the transformer has a built-in leakage inductor and a magnetizing inductor, and the main coil is coupled to the switching circuit via the leakage inductor; a resonant capacitor is coupled to the exciting inductor; a second output stage circuit is coupled to the first secondary coil and the second secondary coil and generates a output potential; and an auxiliary control circuit that generates the clock potential and includes a second power switch, wherein the second power switch is coupled to the coupling inductance element and is selectively enabled according to the control potential Or disabled.

In some embodiments, if a switching frequency of the switching level falls within a range of plus or minus 20 kHz of a center frequency of the clock level, the second power switch will be enabled; otherwise, the second power switch will be disabled.

In some embodiments, the first bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the a first input potential, and the cathode of the first diode is coupled to a first node to output the first rectified potential; a second diode has an anode and a cathode, wherein the second diode The anode of the diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; a third diode has a an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential and the cathode of the third diode is coupled to the first input node; and a fourth diode , having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential, and the cathode of the fourth diode is coupled to the second input node.

In some embodiments, the second bridge rectifier includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the first input node to receive the a first input potential, and the cathode of the fifth diode is coupled to a second node to output the second rectified potential; a sixth diode has an anode and a cathode, wherein the sixth diode The anode of the diode is coupled to the second input node to receive the second input potential, and the cathode of the sixth diode is coupled to the second node; a seventh diode has a an anode and a cathode, wherein the anode of the seventh diode is coupled to the ground potential and the cathode of the seventh diode is coupled to the first input node; and an eighth diode , having an anode and a cathode, wherein the anode of the eighth diode is coupled to the ground potential, and the cathode of the eighth diode is coupled to the second input node.

In some embodiments, the coupled inductor element includes: a first inductor having a first terminal and a second terminal, wherein the first terminal of the first inductor is coupled to the first node to receive the first rectified potential, and the second end of the first inductor is coupled to a third node; and a second inductor has a first end and a second end, wherein the second inductor The first end of is coupled to the second node to receive the second rectified potential, and the second end of the second inductor is coupled to the third node; wherein the first inductor and the third The two inductors are coupled to each other.

In some embodiments, the first power switch includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the clock potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the third node.

In some embodiments, the first output stage circuit includes: a ninth diode having an anode and a cathode, wherein the anode of the ninth diode is coupled to the third node, and the The cathode of the nine-diode is coupled to a fourth node to output the internal potential; and a first capacitor has a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled is connected to the fourth node, and the second terminal of the first capacitor is coupled to the ground potential.

In some embodiments, the switching circuit includes: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used to receive the switching potential, the The first terminal of the second transistor is coupled to a fifth node, and the second terminal of the second transistor is coupled to the fourth node to receive the internal potential; a third transistor has a control terminal , a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive an inverted switching potential, the first terminal of the third transistor is coupled to the ground potential, and the The second terminal of the third transistor is coupled to the fifth node; a resistor; and a first controller to generate the switching potential and the inverted switching potential, wherein the first controller further generates the switching potential according to the switching potential. to generate the control potential.

In some embodiments, the leakage inductor has a first terminal and a second terminal, the first terminal of the leakage inductor is coupled to the fifth node, and the second terminal of the leakage inductor is coupled to to a sixth node, the exciting inductor has a first end and a second end, the first end of the exciting inductor is coupled to the sixth node, and the second end of the exciting inductor is coupled to to a seventh node, the main coil has a first end and a second end, the first end of the main coil is coupled to the sixth node, and the second end of the main coil is coupled to the The seventh node, the resonant capacitor has a first end and a second end, the first end of the resonant capacitor is coupled to the seventh node, and the second end of the resonant capacitor is coupled to the ground potential. , the first secondary coil has a first end and a second end, the first end of the first secondary coil is coupled to an eighth node, and the second end of the first secondary coil is coupled to a common node, the second secondary coil has a first end and a second end, the first end of the second secondary coil is coupled to the common node, and the second end of the second secondary coil is coupled to a ninth node.

In some embodiments, the second output stage circuit includes: a twelfth transistor having an anode and a cathode, wherein the anode of the twelfth transistor is coupled to the eighth node, and the The cathode of the dodeode is coupled to an output node to output the output potential; an eleventh diode has an anode and a cathode, wherein the anode of the eleventh diode is coupled to the ninth node, and the cathode of the eleventh diode is coupled to the output node; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor A terminal is coupled to the output node, and the second terminal of the second capacitor is coupled to the common node.

In some embodiments, the auxiliary control circuit includes: a fourth transistor forming the second power switch and having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor The terminal is used to receive the clock potential, the first terminal of the fourth transistor is coupled to a tenth node, and the second terminal of the fourth transistor is coupled to the third node; a fifth transistor , having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is used to receive an adjustment potential, and the first terminal of the fifth transistor is coupled to the ground potential. , and the second terminal of the fifth transistor is coupled to the tenth node; and a second controller generates the clock potential and receives the control potential through the resistor, wherein the second controller further The adjustment potential is generated based on the control potential.

Description of the drawings

FIG. 1 is a schematic diagram showing a power supply according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a power supply according to an embodiment of the present invention.

FIG. 3 is a diagram showing the relationship between voltage gain and switching frequency of a power supply according to an embodiment of the present invention.

Among them, the reference symbols are explained as follows:

100, 200: Power supply

110, 210: First bridge rectifier

120, 220: Second bridge rectifier

130, 230: Coupled inductance element

140, 240: First power switcher

150, 250: first output stage circuit

160, 260: switching circuit

170, 270: Transformer

171, 271: Main coil

172, 272: first secondary coil

173, 273: Second secondary coil

180, 280: Second output stage circuit

190, 290: Auxiliary control circuit

192, 292: Second power switch

264: First controller

294: Second controller

C1: first capacitor

C2: Second capacitor

CR: Resonant capacitor

D1: first diode

D2: Second diode

D3: The third diode

D4: The fourth diode

D5: fifth diode

D6: The sixth diode

D7: seventh diode

D8: The eighth diode

D9: Ninth diode

D10: Twelfth tube

D11: Eleventh diode

FC: center frequency

FH: frequency upper limit

FL: frequency lower limit

FV: frequency range

FW: switching frequency

L1: First inductor

L2: Second inductor

LM: Magnetizing inductor

LR: leakage inductor

M1: first transistor

M2: second transistor

M3: The third transistor

M4: The fourth transistor

M5: The fourth transistor

N1: first node

N2: second node

N3: The third node

N4: fourth node

N5: fifth node

N6: The sixth node

N7: The seventh node

N8: The eighth node

N9: Ninth node

N10: The tenth node

NCM: common node

NIN1: first input node

NIN2: second input node

NOUT: output node

R1: Resistor

VA: clock potential

VC: control potential

VIN1: first input potential

VIN2: second input potential

VN: internal potential

VOUT: output potential

VR1: first rectification potential

VR2: second rectification potential

VSS: ground potential

VT: adjust potential

VW: switching potential

VWB: reverse switching potential

Detailed ways

In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are cited below and described in detail with reference to the accompanying drawings.

Certain words are used in the description and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and the claims do not use differences in names as a means to distinguish components, but rather differences in functions of the components as a criterion for distinction. The words "include" and "include" mentioned throughout the description and claims are open-ended terms, and therefore should be interpreted to mean "include but not limited to." The word "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain error range. In addition, the word "coupling" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connections. Two devices.

FIG. 1 is a schematic diagram showing a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a notebook computer, or an all-in-one computer. As shown in Figure 1, the power supply 100 includes: a first bridge rectifier 110, a second bridge rectifier 120, a coupling inductor 130, a first power switch 140, a first output stage circuit 150, A switching circuit 160, a transformer 170, a resonant capacitor CR, a second output stage circuit 180, and an auxiliary control circuit 190. It should be noted that, although not shown in FIG. 1 , the power supply 100 may further include other components, such as a voltage regulator or/and a negative feedback circuit.

The first bridge rectifier 110 can generate a first rectified potential VR1 according to a first input potential VIN1 and a second input potential VIN2. Both the first input potential VIN1 and the second input potential VIN2 can come from an external input power supply, wherein an AC voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage may be about 50Hz or 60Hz, and the root mean square value of the AC voltage may be from 90V to 264V, but is not limited thereto. The second bridge rectifier 120 can generate a second rectified potential VR2 according to the first input potential VIN1 and the second input potential VIN2. The coupling inductance element 130 may receive the first rectified potential VR1 and the second rectified potential VR2. The first power switch 140 can selectively couple the coupling inductance element 130 to a ground potential VSS (eg, 0V) according to a clock potential VA. For example, if the clock potential VA is a high logic level (eg, logic “1”), the first power switch 140 can couple the coupling inductor 130 to the ground potential VSS (ie, the first power switch The switch 140 can be approximated as a short-circuit path); on the contrary, if the clock potential VA is a low logic level (for example: logic "0"), the first power switch 140 will not couple the coupling inductance element 130 to the ground potential VSS. (That is, the first power switch 140 may approximate an open path). The first output stage circuit 150 is coupled to the coupling inductor element 130 and can generate an internal potential VN. The internal potential VN can be regarded as a boosted potential. The switching circuit 160 can receive the internal potential VN and generate a switching potential VW and a control potential VC. The transformer 170 includes a main coil 171, a first auxiliary coil 172, and a second auxiliary coil 173. The transformer 170 has a built-in leakage inductor LR and a magnetizing inductor LM. The main coil 171, the leakage inductor LR, and the exciting inductor LM can all be located on the same side of the transformer 170 (for example, the primary side), while the first auxiliary coil 172 and the second auxiliary coil 173 can be located on opposite sides of the transformer 170. One side (for example: the secondary side, which can be isolated from the primary side). The main coil 171 is coupled to the switching circuit 160 via the leakage inductor LR. The resonant capacitor CR is coupled to the magnetizing inductor LM. The second output stage circuit 180 is coupled to the first secondary coil 172 and the second secondary coil 173 and can generate an output potential VOUT. For example, the output potential VOUT may be a DC potential, and its potential level may be between 18V and 20V, but is not limited thereto. The auxiliary control circuit 190 can generate the clock potential VA, and includes a second power switch 192, where the second power switch 192 is coupled to the coupling inductance element 130 and can selectively enable or disable according to the control potential VC. able. For example, if the control potential VC is at a high logic level, the second power switch 192 will be enabled; conversely, if the control potential VC is at a low logic level, the second power switch 192 will be disabled. In some embodiments, if a switching frequency FW of the switching potential VW falls within a range of plus or minus 20 kHz of a center frequency FC of the clock potential VA, the second power switch 192 will be enabled; otherwise, the second power switch 192 will be enabled. Switch 192 will be disabled. It must be understood that the aforementioned frequency range can also be adjusted according to different needs. According to actual measurement results, the design of the present invention can effectively suppress the resonance noise generated by the power supply 100, thereby improving the user's experience.

The following embodiments will introduce the detailed structure and operation mode of the power supply 100 . It must be understood that these drawings and descriptions are examples only and are not intended to limit the scope of the invention.

FIG. 2 is a schematic diagram showing a power supply 200 according to an embodiment of the present invention. In the embodiment of FIG. 2 , the power supply 200 has a first input node NIN1 , a second input node NIN2 , and an output node NOUT, and includes a first bridge rectifier 210 and a second bridge rectifier 220 , a coupling inductance element 230, a first power switch 240, a first output stage circuit 250, a switching circuit 260, a transformer 270, a resonant capacitor CR, a second output stage circuit 280, and an auxiliary control circuit 290. The first input node NIN1 and the second input node NIN2 of the power supply 200 can respectively receive the first input potential VIN1 and the second input potential VIN2 from an external input power source, and the output node NOUT of the power supply 200 can output an output potential. VOUT to an electronic device (not shown).

The first bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 To output a first rectified potential VR1. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to the first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a ground potential VSS, and the cathode of the third diode D3 is coupled to the first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to the ground potential VSS, and the cathode of the fourth diode D4 is coupled to the second input node NIN2.

The second bridge rectifier 220 includes a fifth diode D5, a sixth diode D6, a seventh diode D7, and an eighth diode D8. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the first input node NIN1, and the cathode of the fifth diode D5 is coupled to a second node N2 To output a second rectified potential VR2. The sixth diode D6 has an anode and a cathode, wherein the anode of the sixth diode D6 is coupled to the second input node NIN2, and the cathode of the sixth diode D6 is coupled to the second node N2. The seventh diode D7 has an anode and a cathode, wherein the anode of the seventh diode D7 is coupled to the ground potential VSS, and the cathode of the seventh diode D7 is coupled to the first input node NIN1. The eighth diode D8 has an anode and a cathode, wherein the anode of the eighth diode D8 is coupled to the ground potential VSS, and the cathode of the eighth diode D8 is coupled to the second input node NIN2.

The coupled inductor element 230 includes a first inductor L1 and a second inductor L2. The first inductor L1 has a first terminal and a second terminal, wherein the first terminal of the first inductor L1 is coupled to the first node N1 to receive the first rectified potential VR1, and the first terminal of the first inductor L1 The two terminals are coupled to a third node N3. The second inductor L2 has a first terminal and a second terminal, wherein the first terminal of the second inductor L2 is coupled to the second node N2 to receive the second rectified potential VR2, and the second terminal of the second inductor L2 The two terminals are coupled to the third node N3. The first inductor L1 and the second inductor L2 are coupled to each other. For example, the first inductor L1 and the second inductor L2 may be formed on the same core, but are not limited thereto.

The first power switch 240 includes a first transistor M1. The first transistor M1 may be an N-type metal oxide semiconductor field effect transistor. The first transistor M1 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the first transistor M1 is For receiving a clock potential VA, a first terminal of the first transistor M1 is coupled to the ground potential VSS, and a second terminal of the first transistor M1 is coupled to the third node N3. For example, the clock potential VA can be maintained at a fixed potential when the power supply 200 is initialized, and can provide a periodic clock waveform after the power supply 200 enters the normal use stage.

The first output stage circuit 250 includes a ninth diode D9 and a first capacitor C1. The ninth diode D9 has an anode and a cathode, wherein the anode of the ninth diode D9 is coupled to the third node N3, and the cathode of the ninth diode D9 is coupled to a fourth node N4. Output an internal potential VN. The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the fourth node N4, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS.

The switching circuit 260 includes a second transistor M2, a third transistor M3, a resistor R1, and a first controller 264. The second transistor M2 and the third transistor M3 may each be an N-type metal oxide semiconductor field effect transistor. The first controller 264 may be implemented by an integrated circuit chip. The second transistor M2 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the second transistor M2 is For receiving a switching potential VW, the first terminal of the second transistor M2 is coupled to a fifth node N5, and the second terminal of the second transistor M2 is coupled to the fourth node N4 to receive the internal potential VN. The third transistor M3 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the third transistor M3 is For receiving an inverted switching potential VWB, the first terminal of the third transistor M3 is coupled to the ground potential VSS, and the second terminal of the third transistor M3 is coupled to the fifth node N5. The first controller 264 may generate the switching potential VW and the inverted switching potential VWB, where the switching potential VW and the inverted switching potential VWB may have the same switching frequency FW and complementary logic levels. The first controller 264 can further generate a control potential VC according to the switching potential VW. For example, the first controller 264 may include a frequency comparator (not shown). In some embodiments, if the switching frequency FW of the switching potential VW falls within the range of plus or minus 20 kHz of a center frequency FC of the clock potential VA, the control potential VC will be a high logic level; conversely, if the switching frequency FW of the switching potential VW If the switching frequency FW does not fall within the aforementioned range, the control potential VC will be at a low logic level. For example, the center frequency FC of the clock potential VA can be a constant. The first controller 264 can further transmit the control potential VC to the auxiliary control circuit 290 through the resistor R1.

The transformer 270 includes a main coil 271, a first auxiliary coil 272, and a second auxiliary coil 273. The transformer 270 further has a built-in leakage inductor LR and a magnetizing inductor LM. Both the leakage inductor LR and the magnetizing inductor LM may be inherent components produced when the transformer 270 is manufactured, and are not external independent components. The leakage inductor LR, the main coil 271, and the exciting inductor LM can all be located on the same side of the transformer 270, while the first auxiliary coil 272 and the second auxiliary coil 273 can be located on opposite sides of the transformer 270. The leakage inductor LR has a first terminal and a second terminal, wherein the first terminal of the leakage inductor LR is coupled to the fifth node N5, and the second terminal of the leakage inductor LR is coupled to a sixth node N6. The exciting inductor LM has a first end and a second end, wherein the first end of the exciting inductor LM is coupled to the sixth node N6, and the second end of the exciting inductor LM is coupled to a seventh node. N7. The main coil 271 has a first end and a second end, wherein the first end of the main coil 271 is coupled to the sixth node N6, and the second end of the main coil 271 is coupled to the seventh node N7. The resonant capacitor CR has a first end and a second end, wherein the first end of the resonant capacitor CR is coupled to the seventh node N7, and the second end of the resonant capacitor CR is coupled to the ground potential VSS. The first secondary coil 272 has a first end and a second end, wherein the first end of the first secondary coil 272 is coupled to an eighth node N8, and the second end of the first secondary coil 272 is coupled to A common node NCM. For example, the common node NCM can be regarded as another ground potential, which can be the same as or different from the aforementioned ground potential VSS. The second secondary coil 273 has a first end and a second end, wherein the first end of the second secondary coil 273 is coupled to the common node NCM, and the second end of the second secondary coil 273 is coupled to a first end. Nine nodes N9. It must be noted that the leakage inductor LR, the magnetizing inductor LM, and the resonant capacitor CR may together form an LLC resonant tank.

The second output stage circuit 280 includes a twelfth diode D10, an eleventh diode D11, and a second capacitor C2. The twelfth tube D10 has an anode and a cathode, wherein the anode of the twelfth tube D10 is coupled to the eighth node N8, and the cathode of the twelfth tube D10 is coupled to the output node NOUT. The eleventh diode D11 has an anode and a cathode, wherein the anode of the eleventh diode D11 is coupled to the ninth node N9, and the cathode of the eleventh diode D11 is coupled to the output node NOUT . The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to the common node NCM.

The auxiliary control circuit 290 includes a fourth transistor M4, a fifth transistor M5, and a second controller 294. The fourth transistor M4 and the fifth transistor M5 may each be an N-type metal oxide semiconductor field effect transistor. The second controller 294 may be implemented by another integrated circuit chip. The fourth transistor M4 may form a second power switch 292 of the auxiliary control circuit 290 . The fourth transistor M4 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the fourth transistor M4 is For receiving the clock potential VA, the first terminal of the fourth transistor M4 is coupled to a tenth node N10, and the second terminal of the fourth transistor M4 is coupled to the third node N3. The fifth transistor M5 has a control terminal (for example: a gate), a first terminal (for example: a source), and a second terminal (for example: a drain), wherein the control terminal of the fifth transistor M5 is For receiving an adjustment potential VT, the first terminal of the fifth transistor M5 is coupled to the ground potential VSS, and the second terminal of the fifth transistor M5 is coupled to the tenth node N10. The second controller 294 can generate the clock potential VA, and can receive the control potential VC through the resistor R1, wherein the second controller 294 can further generate the adjustment potential VT according to the control potential VC. For example, if the control potential VC is a high logic level, the second controller 294 will generate a high logic level adjustment potential VT to enable the fifth transistor M5 (while indirectly enabling the fourth transistor M4); conversely, if If the control potential VC is a low logic level, the second controller 294 will generate a low logic level adjustment potential VT to disable the fifth transistor M5 (while indirectly disabling the fourth transistor M4). In other words, whether the fourth transistor M4 and the fifth transistor M5 are enabled is determined based on the comparison result between the switching frequency FW and the center frequency FC of the clock potential VA.

FIG. 3 is a diagram showing the relationship between voltage gain and switching frequency of the power supply 200 according to an embodiment of the present invention. The horizontal axis represents the switching frequency FW of the switching potential VW, and the vertical axis represents the voltage gain, which may be equal to the ratio of the output potential VOUT and the internal potential VN. Roughly speaking, the first bridge rectifier 210, the second bridge rectifier 220, the coupled inductor 230, the first power switch 240, the first output stage circuit 250, and the auxiliary control circuit 290 can together form an improved power Factor corrector (Power Factor Corrector, PFC); in addition, the switching circuit 260, the transformer 270, the resonant capacitor CR, and the second output stage circuit 280 can jointly form a resonant LLC converter (Resonant LLC Converter). If the difference between the switching frequency FW of the switching potential VW and the center frequency FC of the clock potential VA is between plus and minus 10 kHz, the conventional power supply may generate noise perceptible to human ears.

In order to suppress the aforementioned noise, some exemplary embodiments may set a lower frequency limit FL to the center frequency FC minus 20 kHz, and may set an upper frequency limit FH to the center frequency FC plus 20 kHz. If the switching frequency FW of the switching potential VW falls within a frequency interval FV between the lower frequency limit FL and the upper frequency limit FH, the switching circuit 260 and the auxiliary control circuit 290 will enable the second power switch 292 . On the contrary, if the switching frequency FW of the switching potential VW does not fall within the aforementioned frequency interval FV, the switching circuit 260 and the auxiliary control circuit 290 will disable the second power switch 292 . Therefore, an auxiliary boost circuit formed by the second bridge rectifier 220, the second inductor L2, and the second power switch 292 can supplementally provide energy to the resonant LLC converter within the aforementioned frequency range FV. By reducing the voltage gain in the aforementioned frequency range FV (for example, it drops to almost 0), this design can not only maintain a stable output potential VOUT, but also effectively eliminate the resonance noise of the power supply 200, which will greatly improve User experience.

In some embodiments, component parameters of the power supply 200 may be as follows. The inductance value of the first inductor L1 may be between 324 μH and 396 μH, preferably about 360 μH. The inductance value of the second inductor L2 may be between 324 μH and 396 μH, preferably about 360 μH. The inductance value of the leakage inductor LR can be between 37.8μH and 46.2μH, preferably about 42μH. The inductance value of the magnetizing inductor LM can be between 594μH and 726μH, preferably about 660μH. The resistance value of resistor R1 can be between 99Ω and 101Ω, preferably about 100Ω. The capacitance value of the resonant capacitor CR can be between 42.3nF and 51.7nF, preferably about 47nF. The capacitance value of the first capacitor C1 can be between 1200 μF and 1800 μF, preferably about 1500 μF. The capacitance value of the second capacitor C2 may be between 544 μF and 816 μF, preferably about 680 μF. The turns ratio of the main coil 271 to the first auxiliary coil 272 can be between 1 and 100, preferably about 20. The turns ratio of the main coil 271 to the second auxiliary coil 273 can be between 1 and 100, preferably about 20. The center frequency FC of the clock potential VA may be approximately 65 kHz. The lower frequency limit FL may be approximately 45kHz. The upper frequency limit FH may be approximately 85kHz. The frequency range FV can be approximately between 45kHz and 85kHz. The above parameter range is obtained based on the results of multiple experiments, which helps minimize the resonance noise of the power supply 200 .

The present invention proposes a novel power supply, which includes a switching circuit and a corresponding auxiliary control circuit. According to the actual measurement results, using the power supply designed as mentioned above can effectively eliminate the non-ideal noise of the power supply, so it is very suitable for use in various devices.

It is worth noting that the above-mentioned potential, current, resistance value, inductance value, capacitance value, and other component parameters are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The power supply of the present invention is not limited to the state illustrated in FIGS. 1 to 3 . The invention may simply include any one or more features of any one or more embodiments of Figures 1-3. In other words, not all the features shown in the figures need to be implemented in the power supply of the present invention at the same time. Although the embodiments of the present invention use metal oxide semiconductor field effect transistors as an example, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field effect transistors or fin type transistors. field effect transistors, etc., without affecting the effect of the present invention.

The ordinal numbers in this description and the claims, such as "first", "second", "third", etc., have no sequential relationship with each other. They are only used to distinguish two items with the same Different components of the name.

Although the preferred embodiments of the present invention are disclosed above, they are not intended to limit the scope of the present invention. Anyone skilled in the art can make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended claims.

Claims (11)

1. A noise-suppressing power supply, comprising:

a first bridge rectifier for generating a first rectified potential according to a first input potential and a second input potential;

a second bridge rectifier for generating a second rectified potential according to the first input potential and the second input potential;

a coupling inductance element for receiving the first rectifying potential and the second rectifying potential;

a first power switch selectively coupling the coupled inductive element to a ground potential according to a time Zhong Dianwei;

a first output stage circuit coupled to the coupling inductance element and generating an internal potential;

a switching circuit for receiving the internal potential and generating a switching potential and a control potential;

a transformer including a main coil, a first secondary coil and a second secondary coil, wherein a leakage inductor and an exciting inductor are built in the transformer, and the main coil is coupled to the switching circuit via the leakage inductor;

a resonant capacitor coupled to the excitation inductor;

a second output stage circuit coupled to the first secondary winding and the second secondary winding and generating an output potential; and

an auxiliary control circuit generates the clock potential and comprises a second power switch, wherein the second power switch is coupled to the coupling inductance element and selectively enables or disables according to the control potential.

2. The power supply of claim 1, wherein the second power switch is enabled if a switching frequency of the switching potential falls within plus or minus 20kHz of a center frequency of the clock potential; otherwise the second power switch will be disabled.

3. The power supply of claim 1, wherein the first bridge rectifier comprises:

a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the first rectified potential;

a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node;

a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to the ground potential and the cathode of the third diode is coupled to the first input node; and

a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential and the cathode of the fourth diode is coupled to the second input node.

4. The power supply of claim 3, wherein the second bridge rectifier comprises:

a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the first input node to receive the first input potential, and the cathode of the fifth diode is coupled to a second node to output the second rectified potential;

a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the second input node to receive the second input potential, and the cathode of the sixth diode is coupled to the second node;

a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the ground potential and the cathode of the seventh diode is coupled to the first input node; and

an eighth diode having an anode and a cathode, wherein the anode of the eighth diode is coupled to the ground potential and the cathode of the eighth diode is coupled to the second input node.

5. The power supply of claim 4, wherein the coupled inductive element comprises:

a first inductor having a first end and a second end, wherein the first end of the first inductor is coupled to the first node to receive the first rectified potential, and the second end of the first inductor is coupled to a third node; and

a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the second node to receive the second rectified potential, and the second end of the second inductor is coupled to the third node;

wherein the first inductor and the second inductor are coupled to each other.

6. The power supply of claim 5, wherein the first power switch comprises:

the first transistor has a control terminal, a first terminal and a second terminal, wherein the control terminal of the first transistor is used for receiving the clock potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the third node.

7. The power supply of claim 6, wherein the first output stage circuit comprises:

a ninth diode having an anode and a cathode, wherein the anode of the ninth diode is coupled to the third node, and the cathode of the ninth diode is coupled to a fourth node to output the internal potential; and

a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the fourth node and the second end of the first capacitor is coupled to the ground potential.

8. The power supply of claim 7, wherein the switching circuit comprises:

a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is for receiving the switching potential, the first terminal of the second transistor is coupled to a fifth node, and the second terminal of the second transistor is coupled to the fourth node for receiving the internal potential;

a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is for receiving an inverse switching potential, the first terminal of the third transistor is coupled to the ground potential, and the second terminal of the third transistor is coupled to the fifth node;

a resistor; and

the first controller generates the switching potential and the inverse switching potential, wherein the first controller generates the control potential according to the switching potential.

9. The power supply of claim 8, wherein the leakage inductor has a first end and a second end, the first end of the leakage inductor is coupled to the fifth node, the second end of the leakage inductor is coupled to a sixth node, the excitation inductor has a first end and a second end, the first end of the excitation inductor is coupled to the sixth node, the second end of the excitation inductor is coupled to a seventh node, the main winding has a first end and a second end, the first end of the main winding is coupled to the sixth node, the second end of the main winding is coupled to the seventh node, the first end of the resonant capacitor is coupled to the seventh node, the second end of the resonant capacitor is coupled to the ground potential, the first secondary winding has a first end and a second end, the first end of the first secondary winding is coupled to an eighth node, the second end of the first secondary winding is coupled to a common node, the second secondary winding has a first end and a second end, the first end of the second secondary winding is coupled to the common node, and the second end of the second secondary winding is coupled to a ninth node.

10. The power supply of claim 9, wherein the second output stage circuit comprises:

a twelfth diode having an anode and a cathode, wherein the anode of the tenth diode is coupled to the eighth node, and the cathode of the twelfth diode is coupled to an output node for outputting the output potential;

an eleventh diode having an anode and a cathode, wherein the anode of the eleventh diode is coupled to the ninth node and the cathode of the eleventh diode is coupled to the output node; and

a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the output node and the second end of the second capacitor is coupled to the common node.

11. The power supply of claim 10, wherein the auxiliary control circuit comprises:

a fourth transistor forming the second power switch and having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor is for receiving the clock potential, the first terminal of the fourth transistor is coupled to a tenth node, and the second terminal of the fourth transistor is coupled to the third node;

a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is for receiving an adjustment potential, the first terminal of the fifth transistor is coupled to the ground potential, and the second terminal of the fifth transistor is coupled to the tenth node; and

and a second controller for generating the clock potential and receiving the control potential through the resistor, wherein the second controller further generates the adjustment potential according to the control potential.